diff --git a/arch/.#make-manifest.toml b/arch/.#make-manifest.toml new file mode 120000 index 00000000..01962761 --- /dev/null +++ b/arch/.#make-manifest.toml @@ -0,0 +1 @@ +penguin@penguin-arch-home.68690:1602942911 \ No newline at end of file diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51g18a_flash.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51g18a_flash.ld new file mode 100644 index 00000000..06a01892 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51g18a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD51G18A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51g18a_sram.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51g18a_sram.ld new file mode 100644 index 00000000..d1ff26a0 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51g18a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD51G18A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51g19a_flash.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51g19a_flash.ld new file mode 100644 index 00000000..8a30999b --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51g19a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD51G19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51g19a_sram.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51g19a_sram.ld new file mode 100644 index 00000000..3e291a0e --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51g19a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD51G19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51j18a_flash.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51j18a_flash.ld new file mode 100644 index 00000000..2f976c5f --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51j18a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD51J18A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51j18a_sram.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51j18a_sram.ld new file mode 100644 index 00000000..19dc4365 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51j18a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD51J18A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51j19a_flash.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51j19a_flash.ld new file mode 100644 index 00000000..8937dddd --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51j19a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD51J19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51j19a_sram.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51j19a_sram.ld new file mode 100644 index 00000000..8b65580b --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51j19a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD51J19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51j20a_flash.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51j20a_flash.ld new file mode 100644 index 00000000..a1bcd966 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51j20a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD51J20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51j20a_sram.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51j20a_sram.ld new file mode 100644 index 00000000..b6babc2e --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51j20a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD51J20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51n19a_flash.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51n19a_flash.ld new file mode 100644 index 00000000..33ca24c6 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51n19a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD51N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51n19a_sram.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51n19a_sram.ld new file mode 100644 index 00000000..f968c773 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51n19a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD51N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51n20a_flash.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51n20a_flash.ld new file mode 100644 index 00000000..e37df547 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51n20a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD51N20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51n20a_sram.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51n20a_sram.ld new file mode 100644 index 00000000..aef65eef --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51n20a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD51N20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51p19a_flash.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51p19a_flash.ld new file mode 100644 index 00000000..63487e95 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51p19a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD51P19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51p19a_sram.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51p19a_sram.ld new file mode 100644 index 00000000..d77838ae --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51p19a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD51P19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51p20a_flash.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51p20a_flash.ld new file mode 100644 index 00000000..a989e023 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51p20a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD51P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/ld/samd51p20a_sram.ld b/arch/arm/SAMD51/SAMD51A/ld/samd51p20a_sram.ld new file mode 100644 index 00000000..0c2329f1 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/ld/samd51p20a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD51P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/component-version.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/component-version.h new file mode 100644 index 00000000..86854a45 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 3 +#define COMPONENT_VERSION_MINOR 3 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 30003 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 76 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "3.3" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2020-10-09 15:30:02" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/component/ac.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/ac.h new file mode 100644 index 00000000..7d88d301 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/ac.h @@ -0,0 +1,410 @@ +/** + * \brief Component description for AC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:45:00Z */ +#ifndef _SAMD51_AC_COMPONENT_H_ +#define _SAMD51_AC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AC */ +/* ************************************************************************** */ + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< (AC_CTRLA) Control A Reset Value */ + +#define AC_CTRLA_SWRST_Pos _U_(0) /**< (AC_CTRLA) Software Reset Position */ +#define AC_CTRLA_SWRST_Msk (_U_(0x1) << AC_CTRLA_SWRST_Pos) /**< (AC_CTRLA) Software Reset Mask */ +#define AC_CTRLA_SWRST(value) (AC_CTRLA_SWRST_Msk & ((value) << AC_CTRLA_SWRST_Pos)) +#define AC_CTRLA_ENABLE_Pos _U_(1) /**< (AC_CTRLA) Enable Position */ +#define AC_CTRLA_ENABLE_Msk (_U_(0x1) << AC_CTRLA_ENABLE_Pos) /**< (AC_CTRLA) Enable Mask */ +#define AC_CTRLA_ENABLE(value) (AC_CTRLA_ENABLE_Msk & ((value) << AC_CTRLA_ENABLE_Pos)) +#define AC_CTRLA_Msk _U_(0x03) /**< (AC_CTRLA) Register Mask */ + + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< (AC_CTRLB) Control B Reset Value */ + +#define AC_CTRLB_START0_Pos _U_(0) /**< (AC_CTRLB) Comparator 0 Start Comparison Position */ +#define AC_CTRLB_START0_Msk (_U_(0x1) << AC_CTRLB_START0_Pos) /**< (AC_CTRLB) Comparator 0 Start Comparison Mask */ +#define AC_CTRLB_START0(value) (AC_CTRLB_START0_Msk & ((value) << AC_CTRLB_START0_Pos)) +#define AC_CTRLB_START1_Pos _U_(1) /**< (AC_CTRLB) Comparator 1 Start Comparison Position */ +#define AC_CTRLB_START1_Msk (_U_(0x1) << AC_CTRLB_START1_Pos) /**< (AC_CTRLB) Comparator 1 Start Comparison Mask */ +#define AC_CTRLB_START1(value) (AC_CTRLB_START1_Msk & ((value) << AC_CTRLB_START1_Pos)) +#define AC_CTRLB_Msk _U_(0x03) /**< (AC_CTRLB) Register Mask */ + +#define AC_CTRLB_START_Pos _U_(0) /**< (AC_CTRLB Position) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) /**< (AC_CTRLB Mask) START */ +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#define AC_EVCTRL_RESETVALUE _U_(0x00) /**< (AC_EVCTRL) Event Control Reset Value */ + +#define AC_EVCTRL_COMPEO0_Pos _U_(0) /**< (AC_EVCTRL) Comparator 0 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO0_Msk (_U_(0x1) << AC_EVCTRL_COMPEO0_Pos) /**< (AC_EVCTRL) Comparator 0 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO0(value) (AC_EVCTRL_COMPEO0_Msk & ((value) << AC_EVCTRL_COMPEO0_Pos)) +#define AC_EVCTRL_COMPEO1_Pos _U_(1) /**< (AC_EVCTRL) Comparator 1 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO1_Msk (_U_(0x1) << AC_EVCTRL_COMPEO1_Pos) /**< (AC_EVCTRL) Comparator 1 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO1(value) (AC_EVCTRL_COMPEO1_Msk & ((value) << AC_EVCTRL_COMPEO1_Pos)) +#define AC_EVCTRL_WINEO0_Pos _U_(4) /**< (AC_EVCTRL) Window 0 Event Output Enable Position */ +#define AC_EVCTRL_WINEO0_Msk (_U_(0x1) << AC_EVCTRL_WINEO0_Pos) /**< (AC_EVCTRL) Window 0 Event Output Enable Mask */ +#define AC_EVCTRL_WINEO0(value) (AC_EVCTRL_WINEO0_Msk & ((value) << AC_EVCTRL_WINEO0_Pos)) +#define AC_EVCTRL_COMPEI0_Pos _U_(8) /**< (AC_EVCTRL) Comparator 0 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI0_Msk (_U_(0x1) << AC_EVCTRL_COMPEI0_Pos) /**< (AC_EVCTRL) Comparator 0 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI0(value) (AC_EVCTRL_COMPEI0_Msk & ((value) << AC_EVCTRL_COMPEI0_Pos)) +#define AC_EVCTRL_COMPEI1_Pos _U_(9) /**< (AC_EVCTRL) Comparator 1 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI1_Msk (_U_(0x1) << AC_EVCTRL_COMPEI1_Pos) /**< (AC_EVCTRL) Comparator 1 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI1(value) (AC_EVCTRL_COMPEI1_Msk & ((value) << AC_EVCTRL_COMPEI1_Pos)) +#define AC_EVCTRL_INVEI0_Pos _U_(12) /**< (AC_EVCTRL) Comparator 0 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI0_Msk (_U_(0x1) << AC_EVCTRL_INVEI0_Pos) /**< (AC_EVCTRL) Comparator 0 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI0(value) (AC_EVCTRL_INVEI0_Msk & ((value) << AC_EVCTRL_INVEI0_Pos)) +#define AC_EVCTRL_INVEI1_Pos _U_(13) /**< (AC_EVCTRL) Comparator 1 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI1_Msk (_U_(0x1) << AC_EVCTRL_INVEI1_Pos) /**< (AC_EVCTRL) Comparator 1 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI1(value) (AC_EVCTRL_INVEI1_Msk & ((value) << AC_EVCTRL_INVEI1_Pos)) +#define AC_EVCTRL_Msk _U_(0x3313) /**< (AC_EVCTRL) Register Mask */ + +#define AC_EVCTRL_COMPEO_Pos _U_(0) /**< (AC_EVCTRL Position) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) /**< (AC_EVCTRL Mask) COMPEO */ +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO_Pos _U_(4) /**< (AC_EVCTRL Position) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) /**< (AC_EVCTRL Mask) WINEO */ +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI_Pos _U_(8) /**< (AC_EVCTRL Position) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) /**< (AC_EVCTRL Mask) COMPEI */ +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI_Pos _U_(12) /**< (AC_EVCTRL Position) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) /**< (AC_EVCTRL Mask) INVEI */ +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< (AC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define AC_INTENCLR_COMP0_Pos _U_(0) /**< (AC_INTENCLR) Comparator 0 Interrupt Enable Position */ +#define AC_INTENCLR_COMP0_Msk (_U_(0x1) << AC_INTENCLR_COMP0_Pos) /**< (AC_INTENCLR) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP0(value) (AC_INTENCLR_COMP0_Msk & ((value) << AC_INTENCLR_COMP0_Pos)) +#define AC_INTENCLR_COMP1_Pos _U_(1) /**< (AC_INTENCLR) Comparator 1 Interrupt Enable Position */ +#define AC_INTENCLR_COMP1_Msk (_U_(0x1) << AC_INTENCLR_COMP1_Pos) /**< (AC_INTENCLR) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP1(value) (AC_INTENCLR_COMP1_Msk & ((value) << AC_INTENCLR_COMP1_Pos)) +#define AC_INTENCLR_WIN0_Pos _U_(4) /**< (AC_INTENCLR) Window 0 Interrupt Enable Position */ +#define AC_INTENCLR_WIN0_Msk (_U_(0x1) << AC_INTENCLR_WIN0_Pos) /**< (AC_INTENCLR) Window 0 Interrupt Enable Mask */ +#define AC_INTENCLR_WIN0(value) (AC_INTENCLR_WIN0_Msk & ((value) << AC_INTENCLR_WIN0_Pos)) +#define AC_INTENCLR_Msk _U_(0x13) /**< (AC_INTENCLR) Register Mask */ + +#define AC_INTENCLR_COMP_Pos _U_(0) /**< (AC_INTENCLR Position) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) /**< (AC_INTENCLR Mask) COMP */ +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN_Pos _U_(4) /**< (AC_INTENCLR Position) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) /**< (AC_INTENCLR Mask) WIN */ +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< (AC_INTENSET) Interrupt Enable Set Reset Value */ + +#define AC_INTENSET_COMP0_Pos _U_(0) /**< (AC_INTENSET) Comparator 0 Interrupt Enable Position */ +#define AC_INTENSET_COMP0_Msk (_U_(0x1) << AC_INTENSET_COMP0_Pos) /**< (AC_INTENSET) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENSET_COMP0(value) (AC_INTENSET_COMP0_Msk & ((value) << AC_INTENSET_COMP0_Pos)) +#define AC_INTENSET_COMP1_Pos _U_(1) /**< (AC_INTENSET) Comparator 1 Interrupt Enable Position */ +#define AC_INTENSET_COMP1_Msk (_U_(0x1) << AC_INTENSET_COMP1_Pos) /**< (AC_INTENSET) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENSET_COMP1(value) (AC_INTENSET_COMP1_Msk & ((value) << AC_INTENSET_COMP1_Pos)) +#define AC_INTENSET_WIN0_Pos _U_(4) /**< (AC_INTENSET) Window 0 Interrupt Enable Position */ +#define AC_INTENSET_WIN0_Msk (_U_(0x1) << AC_INTENSET_WIN0_Pos) /**< (AC_INTENSET) Window 0 Interrupt Enable Mask */ +#define AC_INTENSET_WIN0(value) (AC_INTENSET_WIN0_Msk & ((value) << AC_INTENSET_WIN0_Pos)) +#define AC_INTENSET_Msk _U_(0x13) /**< (AC_INTENSET) Register Mask */ + +#define AC_INTENSET_COMP_Pos _U_(0) /**< (AC_INTENSET Position) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) /**< (AC_INTENSET Mask) COMP */ +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN_Pos _U_(4) /**< (AC_INTENSET Position) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) /**< (AC_INTENSET Mask) WIN */ +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< (AC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define AC_INTFLAG_COMP0_Pos _U_(0) /**< (AC_INTFLAG) Comparator 0 Position */ +#define AC_INTFLAG_COMP0_Msk (_U_(0x1) << AC_INTFLAG_COMP0_Pos) /**< (AC_INTFLAG) Comparator 0 Mask */ +#define AC_INTFLAG_COMP0(value) (AC_INTFLAG_COMP0_Msk & ((value) << AC_INTFLAG_COMP0_Pos)) +#define AC_INTFLAG_COMP1_Pos _U_(1) /**< (AC_INTFLAG) Comparator 1 Position */ +#define AC_INTFLAG_COMP1_Msk (_U_(0x1) << AC_INTFLAG_COMP1_Pos) /**< (AC_INTFLAG) Comparator 1 Mask */ +#define AC_INTFLAG_COMP1(value) (AC_INTFLAG_COMP1_Msk & ((value) << AC_INTFLAG_COMP1_Pos)) +#define AC_INTFLAG_WIN0_Pos _U_(4) /**< (AC_INTFLAG) Window 0 Position */ +#define AC_INTFLAG_WIN0_Msk (_U_(0x1) << AC_INTFLAG_WIN0_Pos) /**< (AC_INTFLAG) Window 0 Mask */ +#define AC_INTFLAG_WIN0(value) (AC_INTFLAG_WIN0_Msk & ((value) << AC_INTFLAG_WIN0_Pos)) +#define AC_INTFLAG_Msk _U_(0x13) /**< (AC_INTFLAG) Register Mask */ + +#define AC_INTFLAG_COMP_Pos _U_(0) /**< (AC_INTFLAG Position) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) /**< (AC_INTFLAG Mask) COMP */ +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN_Pos _U_(4) /**< (AC_INTFLAG Position) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) /**< (AC_INTFLAG Mask) WIN */ +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) + +/* -------- AC_STATUSA : (AC Offset: 0x07) ( R/ 8) Status A -------- */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< (AC_STATUSA) Status A Reset Value */ + +#define AC_STATUSA_STATE0_Pos _U_(0) /**< (AC_STATUSA) Comparator 0 Current State Position */ +#define AC_STATUSA_STATE0_Msk (_U_(0x1) << AC_STATUSA_STATE0_Pos) /**< (AC_STATUSA) Comparator 0 Current State Mask */ +#define AC_STATUSA_STATE0(value) (AC_STATUSA_STATE0_Msk & ((value) << AC_STATUSA_STATE0_Pos)) +#define AC_STATUSA_STATE1_Pos _U_(1) /**< (AC_STATUSA) Comparator 1 Current State Position */ +#define AC_STATUSA_STATE1_Msk (_U_(0x1) << AC_STATUSA_STATE1_Pos) /**< (AC_STATUSA) Comparator 1 Current State Mask */ +#define AC_STATUSA_STATE1(value) (AC_STATUSA_STATE1_Msk & ((value) << AC_STATUSA_STATE1_Pos)) +#define AC_STATUSA_WSTATE0_Pos _U_(4) /**< (AC_STATUSA) Window 0 Current State Position */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Window 0 Current State Mask */ +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is above window Position */ +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is inside window Position */ +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is below window Position */ +#define AC_STATUSA_Msk _U_(0x33) /**< (AC_STATUSA) Register Mask */ + +#define AC_STATUSA_STATE_Pos _U_(0) /**< (AC_STATUSA Position) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) /**< (AC_STATUSA Mask) STATE */ +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) + +/* -------- AC_STATUSB : (AC Offset: 0x08) ( R/ 8) Status B -------- */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< (AC_STATUSB) Status B Reset Value */ + +#define AC_STATUSB_READY0_Pos _U_(0) /**< (AC_STATUSB) Comparator 0 Ready Position */ +#define AC_STATUSB_READY0_Msk (_U_(0x1) << AC_STATUSB_READY0_Pos) /**< (AC_STATUSB) Comparator 0 Ready Mask */ +#define AC_STATUSB_READY0(value) (AC_STATUSB_READY0_Msk & ((value) << AC_STATUSB_READY0_Pos)) +#define AC_STATUSB_READY1_Pos _U_(1) /**< (AC_STATUSB) Comparator 1 Ready Position */ +#define AC_STATUSB_READY1_Msk (_U_(0x1) << AC_STATUSB_READY1_Pos) /**< (AC_STATUSB) Comparator 1 Ready Mask */ +#define AC_STATUSB_READY1(value) (AC_STATUSB_READY1_Msk & ((value) << AC_STATUSB_READY1_Pos)) +#define AC_STATUSB_Msk _U_(0x03) /**< (AC_STATUSB) Register Mask */ + +#define AC_STATUSB_READY_Pos _U_(0) /**< (AC_STATUSB Position) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) /**< (AC_STATUSB Mask) READY */ +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< (AC_DBGCTRL) Debug Control Reset Value */ + +#define AC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (AC_DBGCTRL) Debug Run Position */ +#define AC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) /**< (AC_DBGCTRL) Debug Run Mask */ +#define AC_DBGCTRL_DBGRUN(value) (AC_DBGCTRL_DBGRUN_Msk & ((value) << AC_DBGCTRL_DBGRUN_Pos)) +#define AC_DBGCTRL_Msk _U_(0x01) /**< (AC_DBGCTRL) Register Mask */ + + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< (AC_WINCTRL) Window Control Reset Value */ + +#define AC_WINCTRL_WEN0_Pos _U_(0) /**< (AC_WINCTRL) Window 0 Mode Enable Position */ +#define AC_WINCTRL_WEN0_Msk (_U_(0x1) << AC_WINCTRL_WEN0_Pos) /**< (AC_WINCTRL) Window 0 Mode Enable Mask */ +#define AC_WINCTRL_WEN0(value) (AC_WINCTRL_WEN0_Msk & ((value) << AC_WINCTRL_WEN0_Pos)) +#define AC_WINCTRL_WINTSEL0_Pos _U_(1) /**< (AC_WINCTRL) Window 0 Interrupt Selection Position */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Window 0 Interrupt Selection Mask */ +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal above window Position */ +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal inside window Position */ +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal below window Position */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal outside window Position */ +#define AC_WINCTRL_Msk _U_(0x07) /**< (AC_WINCTRL) Register Mask */ + +#define AC_WINCTRL_WEN_Pos _U_(0) /**< (AC_WINCTRL Position) Window x Mode Enable */ +#define AC_WINCTRL_WEN_Msk (_U_(0x1) << AC_WINCTRL_WEN_Pos) /**< (AC_WINCTRL Mask) WEN */ +#define AC_WINCTRL_WEN(value) (AC_WINCTRL_WEN_Msk & ((value) << AC_WINCTRL_WEN_Pos)) + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< (AC_SCALER) Scaler n Reset Value */ + +#define AC_SCALER_VALUE_Pos _U_(0) /**< (AC_SCALER) Scaler Value Position */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) /**< (AC_SCALER) Scaler Value Mask */ +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_Msk _U_(0x3F) /**< (AC_SCALER) Register Mask */ + + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00) /**< (AC_COMPCTRL) Comparator Control n Reset Value */ + +#define AC_COMPCTRL_ENABLE_Pos _U_(1) /**< (AC_COMPCTRL) Enable Position */ +#define AC_COMPCTRL_ENABLE_Msk (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) /**< (AC_COMPCTRL) Enable Mask */ +#define AC_COMPCTRL_ENABLE(value) (AC_COMPCTRL_ENABLE_Msk & ((value) << AC_COMPCTRL_ENABLE_Pos)) +#define AC_COMPCTRL_SINGLE_Pos _U_(2) /**< (AC_COMPCTRL) Single-Shot Mode Position */ +#define AC_COMPCTRL_SINGLE_Msk (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) /**< (AC_COMPCTRL) Single-Shot Mode Mask */ +#define AC_COMPCTRL_SINGLE(value) (AC_COMPCTRL_SINGLE_Msk & ((value) << AC_COMPCTRL_SINGLE_Pos)) +#define AC_COMPCTRL_INTSEL_Pos _U_(3) /**< (AC_COMPCTRL) Interrupt Selection Position */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt Selection Mask */ +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output toggle Position */ +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output rising Position */ +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output falling Position */ +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) Position */ +#define AC_COMPCTRL_RUNSTDBY_Pos _U_(6) /**< (AC_COMPCTRL) Run in Standby Position */ +#define AC_COMPCTRL_RUNSTDBY_Msk (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) /**< (AC_COMPCTRL) Run in Standby Mask */ +#define AC_COMPCTRL_RUNSTDBY(value) (AC_COMPCTRL_RUNSTDBY_Msk & ((value) << AC_COMPCTRL_RUNSTDBY_Pos)) +#define AC_COMPCTRL_MUXNEG_Pos _U_(8) /**< (AC_COMPCTRL) Negative Input Mux Selection Position */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Negative Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Ground Position */ +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) VDD scaler Position */ +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Internal bandgap voltage Position */ +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) DAC output Position */ +#define AC_COMPCTRL_MUXPOS_Pos _U_(12) /**< (AC_COMPCTRL) Positive Input Mux Selection Position */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) Positive Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) VDD Scaler Position */ +#define AC_COMPCTRL_SWAP_Pos _U_(15) /**< (AC_COMPCTRL) Swap Inputs and Invert Position */ +#define AC_COMPCTRL_SWAP_Msk (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) /**< (AC_COMPCTRL) Swap Inputs and Invert Mask */ +#define AC_COMPCTRL_SWAP(value) (AC_COMPCTRL_SWAP_Msk & ((value) << AC_COMPCTRL_SWAP_Pos)) +#define AC_COMPCTRL_SPEED_Pos _U_(16) /**< (AC_COMPCTRL) Speed Selection Position */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) /**< (AC_COMPCTRL) Speed Selection Mask */ +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) /**< (AC_COMPCTRL) High speed Position */ +#define AC_COMPCTRL_HYSTEN_Pos _U_(19) /**< (AC_COMPCTRL) Hysteresis Enable Position */ +#define AC_COMPCTRL_HYSTEN_Msk (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) /**< (AC_COMPCTRL) Hysteresis Enable Mask */ +#define AC_COMPCTRL_HYSTEN(value) (AC_COMPCTRL_HYSTEN_Msk & ((value) << AC_COMPCTRL_HYSTEN_Pos)) +#define AC_COMPCTRL_HYST_Pos _U_(20) /**< (AC_COMPCTRL) Hysteresis Level Position */ +#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) Hysteresis Level Mask */ +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) +#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< (AC_COMPCTRL) 100mV */ +#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< (AC_COMPCTRL) 150mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 50mV Position */ +#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 100mV Position */ +#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 150mV Position */ +#define AC_COMPCTRL_FLEN_Pos _U_(24) /**< (AC_COMPCTRL) Filter Length Position */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) Filter Length Mask */ +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) No filtering Position */ +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) 3-bit majority function (2 of 3) Position */ +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) 5-bit majority function (3 of 5) Position */ +#define AC_COMPCTRL_OUT_Pos _U_(28) /**< (AC_COMPCTRL) Output Position */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) Output Mask */ +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_Msk _U_(0x373BF75E) /**< (AC_COMPCTRL) Register Mask */ + + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) ( R/ 32) Synchronization Busy -------- */ +#define AC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (AC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define AC_SYNCBUSY_SWRST_Pos _U_(0) /**< (AC_SYNCBUSY) Software Reset Synchronization Busy Position */ +#define AC_SYNCBUSY_SWRST_Msk (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) /**< (AC_SYNCBUSY) Software Reset Synchronization Busy Mask */ +#define AC_SYNCBUSY_SWRST(value) (AC_SYNCBUSY_SWRST_Msk & ((value) << AC_SYNCBUSY_SWRST_Pos)) +#define AC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (AC_SYNCBUSY) Enable Synchronization Busy Position */ +#define AC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) /**< (AC_SYNCBUSY) Enable Synchronization Busy Mask */ +#define AC_SYNCBUSY_ENABLE(value) (AC_SYNCBUSY_ENABLE_Msk & ((value) << AC_SYNCBUSY_ENABLE_Pos)) +#define AC_SYNCBUSY_WINCTRL_Pos _U_(2) /**< (AC_SYNCBUSY) WINCTRL Synchronization Busy Position */ +#define AC_SYNCBUSY_WINCTRL_Msk (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) /**< (AC_SYNCBUSY) WINCTRL Synchronization Busy Mask */ +#define AC_SYNCBUSY_WINCTRL(value) (AC_SYNCBUSY_WINCTRL_Msk & ((value) << AC_SYNCBUSY_WINCTRL_Pos)) +#define AC_SYNCBUSY_COMPCTRL0_Pos _U_(3) /**< (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL0_Msk (_U_(0x1) << AC_SYNCBUSY_COMPCTRL0_Pos) /**< (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL0(value) (AC_SYNCBUSY_COMPCTRL0_Msk & ((value) << AC_SYNCBUSY_COMPCTRL0_Pos)) +#define AC_SYNCBUSY_COMPCTRL1_Pos _U_(4) /**< (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL1_Msk (_U_(0x1) << AC_SYNCBUSY_COMPCTRL1_Pos) /**< (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL1(value) (AC_SYNCBUSY_COMPCTRL1_Msk & ((value) << AC_SYNCBUSY_COMPCTRL1_Pos)) +#define AC_SYNCBUSY_Msk _U_(0x0000001F) /**< (AC_SYNCBUSY) Register Mask */ + +#define AC_SYNCBUSY_COMPCTRL_Pos _U_(3) /**< (AC_SYNCBUSY Position) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) /**< (AC_SYNCBUSY Mask) COMPCTRL */ +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) + +/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ +#define AC_CALIB_RESETVALUE _U_(0x101) /**< (AC_CALIB) Calibration Reset Value */ + +#define AC_CALIB_BIAS0_Pos _U_(0) /**< (AC_CALIB) COMP0/1 Bias Scaling Position */ +#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) /**< (AC_CALIB) COMP0/1 Bias Scaling Mask */ +#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) +#define AC_CALIB_Msk _U_(0x0003) /**< (AC_CALIB) Register Mask */ + + +/** \brief AC register offsets definitions */ +#define AC_CTRLA_REG_OFST (0x00) /**< (AC_CTRLA) Control A Offset */ +#define AC_CTRLB_REG_OFST (0x01) /**< (AC_CTRLB) Control B Offset */ +#define AC_EVCTRL_REG_OFST (0x02) /**< (AC_EVCTRL) Event Control Offset */ +#define AC_INTENCLR_REG_OFST (0x04) /**< (AC_INTENCLR) Interrupt Enable Clear Offset */ +#define AC_INTENSET_REG_OFST (0x05) /**< (AC_INTENSET) Interrupt Enable Set Offset */ +#define AC_INTFLAG_REG_OFST (0x06) /**< (AC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define AC_STATUSA_REG_OFST (0x07) /**< (AC_STATUSA) Status A Offset */ +#define AC_STATUSB_REG_OFST (0x08) /**< (AC_STATUSB) Status B Offset */ +#define AC_DBGCTRL_REG_OFST (0x09) /**< (AC_DBGCTRL) Debug Control Offset */ +#define AC_WINCTRL_REG_OFST (0x0A) /**< (AC_WINCTRL) Window Control Offset */ +#define AC_SCALER_REG_OFST (0x0C) /**< (AC_SCALER) Scaler n Offset */ +#define AC_COMPCTRL_REG_OFST (0x10) /**< (AC_COMPCTRL) Comparator Control n Offset */ +#define AC_SYNCBUSY_REG_OFST (0x20) /**< (AC_SYNCBUSY) Synchronization Busy Offset */ +#define AC_CALIB_REG_OFST (0x24) /**< (AC_CALIB) Calibration Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AC register API structure */ +typedef struct +{ /* Analog Comparators */ + __IO uint8_t AC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __O uint8_t AC_CTRLB; /**< Offset: 0x01 ( /W 8) Control B */ + __IO uint16_t AC_EVCTRL; /**< Offset: 0x02 (R/W 16) Event Control */ + __IO uint8_t AC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t AC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t AC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t AC_STATUSA; /**< Offset: 0x07 (R/ 8) Status A */ + __I uint8_t AC_STATUSB; /**< Offset: 0x08 (R/ 8) Status B */ + __IO uint8_t AC_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug Control */ + __IO uint8_t AC_WINCTRL; /**< Offset: 0x0A (R/W 8) Window Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t AC_SCALER[2]; /**< Offset: 0x0C (R/W 8) Scaler n */ + __I uint8_t Reserved2[0x02]; + __IO uint32_t AC_COMPCTRL[2]; /**< Offset: 0x10 (R/W 32) Comparator Control n */ + __I uint8_t Reserved3[0x08]; + __I uint32_t AC_SYNCBUSY; /**< Offset: 0x20 (R/ 32) Synchronization Busy */ + __IO uint16_t AC_CALIB; /**< Offset: 0x24 (R/W 16) Calibration */ +} ac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMD51_AC_COMPONENT_H_ */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/component/adc.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/adc.h new file mode 100644 index 00000000..05e8db82 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/adc.h @@ -0,0 +1,649 @@ +/** + * \brief Component description for ADC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:45:00Z */ +#ifndef _SAMD51_ADC_COMPONENT_H_ +#define _SAMD51_ADC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ADC */ +/* ************************************************************************** */ + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ +#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< (ADC_CTRLA) Control A Reset Value */ + +#define ADC_CTRLA_SWRST_Pos _U_(0) /**< (ADC_CTRLA) Software Reset Position */ +#define ADC_CTRLA_SWRST_Msk (_U_(0x1) << ADC_CTRLA_SWRST_Pos) /**< (ADC_CTRLA) Software Reset Mask */ +#define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & ((value) << ADC_CTRLA_SWRST_Pos)) +#define ADC_CTRLA_ENABLE_Pos _U_(1) /**< (ADC_CTRLA) Enable Position */ +#define ADC_CTRLA_ENABLE_Msk (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) /**< (ADC_CTRLA) Enable Mask */ +#define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & ((value) << ADC_CTRLA_ENABLE_Pos)) +#define ADC_CTRLA_DUALSEL_Pos _U_(3) /**< (ADC_CTRLA) Dual Mode Trigger Selection Position */ +#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) Dual Mode Trigger Selection Mask */ +#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) +#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs Position */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 Position */ +#define ADC_CTRLA_SLAVEEN_Pos _U_(5) /**< (ADC_CTRLA) Slave Enable Position */ +#define ADC_CTRLA_SLAVEEN_Msk (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /**< (ADC_CTRLA) Slave Enable Mask */ +#define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & ((value) << ADC_CTRLA_SLAVEEN_Pos)) +#define ADC_CTRLA_RUNSTDBY_Pos _U_(6) /**< (ADC_CTRLA) Run in Standby Position */ +#define ADC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /**< (ADC_CTRLA) Run in Standby Mask */ +#define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & ((value) << ADC_CTRLA_RUNSTDBY_Pos)) +#define ADC_CTRLA_ONDEMAND_Pos _U_(7) /**< (ADC_CTRLA) On Demand Control Position */ +#define ADC_CTRLA_ONDEMAND_Msk (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /**< (ADC_CTRLA) On Demand Control Mask */ +#define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & ((value) << ADC_CTRLA_ONDEMAND_Pos)) +#define ADC_CTRLA_PRESCALER_Pos _U_(8) /**< (ADC_CTRLA) Prescaler Configuration Position */ +#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Prescaler Configuration Mask */ +#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) +#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< (ADC_CTRLA) Peripheral clock divided by 2 */ +#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< (ADC_CTRLA) Peripheral clock divided by 4 */ +#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< (ADC_CTRLA) Peripheral clock divided by 8 */ +#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< (ADC_CTRLA) Peripheral clock divided by 16 */ +#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< (ADC_CTRLA) Peripheral clock divided by 32 */ +#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< (ADC_CTRLA) Peripheral clock divided by 64 */ +#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< (ADC_CTRLA) Peripheral clock divided by 128 */ +#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< (ADC_CTRLA) Peripheral clock divided by 256 */ +#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 2 Position */ +#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 4 Position */ +#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 8 Position */ +#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 16 Position */ +#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 32 Position */ +#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 64 Position */ +#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 128 Position */ +#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 256 Position */ +#define ADC_CTRLA_R2R_Pos _U_(15) /**< (ADC_CTRLA) Rail to Rail Operation Enable Position */ +#define ADC_CTRLA_R2R_Msk (_U_(0x1) << ADC_CTRLA_R2R_Pos) /**< (ADC_CTRLA) Rail to Rail Operation Enable Mask */ +#define ADC_CTRLA_R2R(value) (ADC_CTRLA_R2R_Msk & ((value) << ADC_CTRLA_R2R_Pos)) +#define ADC_CTRLA_Msk _U_(0x87FB) /**< (ADC_CTRLA) Register Mask */ + + +/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< (ADC_EVCTRL) Event Control Reset Value */ + +#define ADC_EVCTRL_FLUSHEI_Pos _U_(0) /**< (ADC_EVCTRL) Flush Event Input Enable Position */ +#define ADC_EVCTRL_FLUSHEI_Msk (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /**< (ADC_EVCTRL) Flush Event Input Enable Mask */ +#define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & ((value) << ADC_EVCTRL_FLUSHEI_Pos)) +#define ADC_EVCTRL_STARTEI_Pos _U_(1) /**< (ADC_EVCTRL) Start Conversion Event Input Enable Position */ +#define ADC_EVCTRL_STARTEI_Msk (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) /**< (ADC_EVCTRL) Start Conversion Event Input Enable Mask */ +#define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & ((value) << ADC_EVCTRL_STARTEI_Pos)) +#define ADC_EVCTRL_FLUSHINV_Pos _U_(2) /**< (ADC_EVCTRL) Flush Event Invert Enable Position */ +#define ADC_EVCTRL_FLUSHINV_Msk (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /**< (ADC_EVCTRL) Flush Event Invert Enable Mask */ +#define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & ((value) << ADC_EVCTRL_FLUSHINV_Pos)) +#define ADC_EVCTRL_STARTINV_Pos _U_(3) /**< (ADC_EVCTRL) Start Conversion Event Invert Enable Position */ +#define ADC_EVCTRL_STARTINV_Msk (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) /**< (ADC_EVCTRL) Start Conversion Event Invert Enable Mask */ +#define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & ((value) << ADC_EVCTRL_STARTINV_Pos)) +#define ADC_EVCTRL_RESRDYEO_Pos _U_(4) /**< (ADC_EVCTRL) Result Ready Event Out Position */ +#define ADC_EVCTRL_RESRDYEO_Msk (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /**< (ADC_EVCTRL) Result Ready Event Out Mask */ +#define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & ((value) << ADC_EVCTRL_RESRDYEO_Pos)) +#define ADC_EVCTRL_WINMONEO_Pos _U_(5) /**< (ADC_EVCTRL) Window Monitor Event Out Position */ +#define ADC_EVCTRL_WINMONEO_Msk (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /**< (ADC_EVCTRL) Window Monitor Event Out Mask */ +#define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & ((value) << ADC_EVCTRL_WINMONEO_Pos)) +#define ADC_EVCTRL_Msk _U_(0x3F) /**< (ADC_EVCTRL) Register Mask */ + + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< (ADC_DBGCTRL) Debug Control Reset Value */ + +#define ADC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (ADC_DBGCTRL) Debug Run Position */ +#define ADC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /**< (ADC_DBGCTRL) Debug Run Mask */ +#define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & ((value) << ADC_DBGCTRL_DBGRUN_Pos)) +#define ADC_DBGCTRL_Msk _U_(0x01) /**< (ADC_DBGCTRL) Register Mask */ + + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x00) /**< (ADC_INPUTCTRL) Input Control Reset Value */ + +#define ADC_INPUTCTRL_MUXPOS_Pos _U_(0) /**< (ADC_INPUTCTRL) Positive Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Positive Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< (ADC_INPUTCTRL) ADC AIN20 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< (ADC_INPUTCTRL) ADC AIN21 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< (ADC_INPUTCTRL) ADC AIN22 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< (ADC_INPUTCTRL) ADC AIN23 Pin */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSP */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSC */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< (ADC_INPUTCTRL) PTC output (only on ADC0) */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN8 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN9 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN10 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN11 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN12 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN13 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN14 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN15 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN16 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN17 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN18 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN19 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN20 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN21 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN22 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN23 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled Core Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled I/O Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Bandgap Voltage Position */ +#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSP Position */ +#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSC Position */ +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) DAC Output Position */ +#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) PTC output (only on ADC0) Position */ +#define ADC_INPUTCTRL_DIFFMODE_Pos _U_(7) /**< (ADC_INPUTCTRL) Differential Mode Position */ +#define ADC_INPUTCTRL_DIFFMODE_Msk (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) /**< (ADC_INPUTCTRL) Differential Mode Mask */ +#define ADC_INPUTCTRL_DIFFMODE(value) (ADC_INPUTCTRL_DIFFMODE_Msk & ((value) << ADC_INPUTCTRL_DIFFMODE_Pos)) +#define ADC_INPUTCTRL_MUXNEG_Pos _U_(8) /**< (ADC_INPUTCTRL) Negative Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) Negative Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) Internal Ground Position */ +#define ADC_INPUTCTRL_DSEQSTOP_Pos _U_(15) /**< (ADC_INPUTCTRL) Stop DMA Sequencing Position */ +#define ADC_INPUTCTRL_DSEQSTOP_Msk (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) /**< (ADC_INPUTCTRL) Stop DMA Sequencing Mask */ +#define ADC_INPUTCTRL_DSEQSTOP(value) (ADC_INPUTCTRL_DSEQSTOP_Msk & ((value) << ADC_INPUTCTRL_DSEQSTOP_Pos)) +#define ADC_INPUTCTRL_Msk _U_(0x9F9F) /**< (ADC_INPUTCTRL) Register Mask */ + + +/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ +#define ADC_CTRLB_RESETVALUE _U_(0x00) /**< (ADC_CTRLB) Control B Reset Value */ + +#define ADC_CTRLB_LEFTADJ_Pos _U_(0) /**< (ADC_CTRLB) Left-Adjusted Result Position */ +#define ADC_CTRLB_LEFTADJ_Msk (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) /**< (ADC_CTRLB) Left-Adjusted Result Mask */ +#define ADC_CTRLB_LEFTADJ(value) (ADC_CTRLB_LEFTADJ_Msk & ((value) << ADC_CTRLB_LEFTADJ_Pos)) +#define ADC_CTRLB_FREERUN_Pos _U_(1) /**< (ADC_CTRLB) Free Running Mode Position */ +#define ADC_CTRLB_FREERUN_Msk (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) /**< (ADC_CTRLB) Free Running Mode Mask */ +#define ADC_CTRLB_FREERUN(value) (ADC_CTRLB_FREERUN_Msk & ((value) << ADC_CTRLB_FREERUN_Pos)) +#define ADC_CTRLB_CORREN_Pos _U_(2) /**< (ADC_CTRLB) Digital Correction Logic Enable Position */ +#define ADC_CTRLB_CORREN_Msk (_U_(0x1) << ADC_CTRLB_CORREN_Pos) /**< (ADC_CTRLB) Digital Correction Logic Enable Mask */ +#define ADC_CTRLB_CORREN(value) (ADC_CTRLB_CORREN_Msk & ((value) << ADC_CTRLB_CORREN_Pos)) +#define ADC_CTRLB_RESSEL_Pos _U_(3) /**< (ADC_CTRLB) Conversion Result Resolution Position */ +#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) Conversion Result Resolution Mask */ +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) +#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 12-bit result Position */ +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) For averaging mode output Position */ +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 10-bit result Position */ +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 8-bit result Position */ +#define ADC_CTRLB_WINMODE_Pos _U_(8) /**< (ADC_CTRLB) Window Monitor Mode Position */ +#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) Window Monitor Mode Mask */ +#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) +#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< (ADC_CTRLB) No window mode (default) */ +#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< (ADC_CTRLB) RESULT > WINLT */ +#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< (ADC_CTRLB) RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< (ADC_CTRLB) WINLT < RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) No window mode (default) Position */ +#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) RESULT > WINLT Position */ +#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) RESULT < WINUT Position */ +#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) WINLT < RESULT < WINUT Position */ +#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) !(WINLT < RESULT < WINUT) Position */ +#define ADC_CTRLB_WINSS_Pos _U_(11) /**< (ADC_CTRLB) Window Single Sample Position */ +#define ADC_CTRLB_WINSS_Msk (_U_(0x1) << ADC_CTRLB_WINSS_Pos) /**< (ADC_CTRLB) Window Single Sample Mask */ +#define ADC_CTRLB_WINSS(value) (ADC_CTRLB_WINSS_Msk & ((value) << ADC_CTRLB_WINSS_Pos)) +#define ADC_CTRLB_Msk _U_(0x0F1F) /**< (ADC_CTRLB) Register Mask */ + + +/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< (ADC_REFCTRL) Reference Control Reset Value */ + +#define ADC_REFCTRL_REFSEL_Pos _U_(0) /**< (ADC_REFCTRL) Reference Selection Position */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) Reference Selection Mask */ +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< (ADC_REFCTRL) External Reference A */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< (ADC_REFCTRL) External Reference B */ +#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< (ADC_REFCTRL) External Reference C (only on ADC1) */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) Internal Bandgap Reference Position */ +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) 1/2 VDDANA Position */ +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) VDDANA Position */ +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference A Position */ +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference B Position */ +#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference C (only on ADC1) Position */ +#define ADC_REFCTRL_REFCOMP_Pos _U_(7) /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */ +#define ADC_REFCTRL_REFCOMP_Msk (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */ +#define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & ((value) << ADC_REFCTRL_REFCOMP_Pos)) +#define ADC_REFCTRL_Msk _U_(0x8F) /**< (ADC_REFCTRL) Register Mask */ + + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< (ADC_AVGCTRL) Average Control Reset Value */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos _U_(0) /**< (ADC_AVGCTRL) Number of Samples to be Collected Position */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) Number of Samples to be Collected Mask */ +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1 sample Position */ +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 2 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 4 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 8 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 16 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 32 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 64 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 128 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 256 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 512 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1024 samples Position */ +#define ADC_AVGCTRL_ADJRES_Pos _U_(4) /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */ +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_Msk _U_(0x7F) /**< (ADC_AVGCTRL) Register Mask */ + + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< (ADC_SAMPCTRL) Sample Time Control Reset Value */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos _U_(0) /**< (ADC_SAMPCTRL) Sampling Time Length Position */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /**< (ADC_SAMPCTRL) Sampling Time Length Mask */ +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos _U_(7) /**< (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */ +#define ADC_SAMPCTRL_OFFCOMP_Msk (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /**< (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */ +#define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & ((value) << ADC_SAMPCTRL_OFFCOMP_Pos)) +#define ADC_SAMPCTRL_Msk _U_(0xBF) /**< (ADC_SAMPCTRL) Register Mask */ + + +/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ +#define ADC_WINLT_RESETVALUE _U_(0x00) /**< (ADC_WINLT) Window Monitor Lower Threshold Reset Value */ + +#define ADC_WINLT_WINLT_Pos _U_(0) /**< (ADC_WINLT) Window Lower Threshold Position */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) /**< (ADC_WINLT) Window Lower Threshold Mask */ +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_Msk _U_(0xFFFF) /**< (ADC_WINLT) Register Mask */ + + +/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ +#define ADC_WINUT_RESETVALUE _U_(0x00) /**< (ADC_WINUT) Window Monitor Upper Threshold Reset Value */ + +#define ADC_WINUT_WINUT_Pos _U_(0) /**< (ADC_WINUT) Window Upper Threshold Position */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) /**< (ADC_WINUT) Window Upper Threshold Mask */ +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_Msk _U_(0xFFFF) /**< (ADC_WINUT) Register Mask */ + + +/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ +#define ADC_GAINCORR_RESETVALUE _U_(0x00) /**< (ADC_GAINCORR) Gain Correction Reset Value */ + +#define ADC_GAINCORR_GAINCORR_Pos _U_(0) /**< (ADC_GAINCORR) Gain Correction Value Position */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /**< (ADC_GAINCORR) Gain Correction Value Mask */ +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_Msk _U_(0x0FFF) /**< (ADC_GAINCORR) Register Mask */ + + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x00) /**< (ADC_OFFSETCORR) Offset Correction Reset Value */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos _U_(0) /**< (ADC_OFFSETCORR) Offset Correction Value Position */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /**< (ADC_OFFSETCORR) Offset Correction Value Mask */ +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_Msk _U_(0x0FFF) /**< (ADC_OFFSETCORR) Register Mask */ + + +/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< (ADC_SWTRIG) Software Trigger Reset Value */ + +#define ADC_SWTRIG_FLUSH_Pos _U_(0) /**< (ADC_SWTRIG) ADC Conversion Flush Position */ +#define ADC_SWTRIG_FLUSH_Msk (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) /**< (ADC_SWTRIG) ADC Conversion Flush Mask */ +#define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & ((value) << ADC_SWTRIG_FLUSH_Pos)) +#define ADC_SWTRIG_START_Pos _U_(1) /**< (ADC_SWTRIG) Start ADC Conversion Position */ +#define ADC_SWTRIG_START_Msk (_U_(0x1) << ADC_SWTRIG_START_Pos) /**< (ADC_SWTRIG) Start ADC Conversion Mask */ +#define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & ((value) << ADC_SWTRIG_START_Pos)) +#define ADC_SWTRIG_Msk _U_(0x03) /**< (ADC_SWTRIG) Register Mask */ + + +/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< (ADC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define ADC_INTENCLR_RESRDY_Pos _U_(0) /**< (ADC_INTENCLR) Result Ready Interrupt Disable Position */ +#define ADC_INTENCLR_RESRDY_Msk (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) /**< (ADC_INTENCLR) Result Ready Interrupt Disable Mask */ +#define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & ((value) << ADC_INTENCLR_RESRDY_Pos)) +#define ADC_INTENCLR_OVERRUN_Pos _U_(1) /**< (ADC_INTENCLR) Overrun Interrupt Disable Position */ +#define ADC_INTENCLR_OVERRUN_Msk (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /**< (ADC_INTENCLR) Overrun Interrupt Disable Mask */ +#define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & ((value) << ADC_INTENCLR_OVERRUN_Pos)) +#define ADC_INTENCLR_WINMON_Pos _U_(2) /**< (ADC_INTENCLR) Window Monitor Interrupt Disable Position */ +#define ADC_INTENCLR_WINMON_Msk (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) /**< (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */ +#define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & ((value) << ADC_INTENCLR_WINMON_Pos)) +#define ADC_INTENCLR_Msk _U_(0x07) /**< (ADC_INTENCLR) Register Mask */ + + +/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< (ADC_INTENSET) Interrupt Enable Set Reset Value */ + +#define ADC_INTENSET_RESRDY_Pos _U_(0) /**< (ADC_INTENSET) Result Ready Interrupt Enable Position */ +#define ADC_INTENSET_RESRDY_Msk (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) /**< (ADC_INTENSET) Result Ready Interrupt Enable Mask */ +#define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & ((value) << ADC_INTENSET_RESRDY_Pos)) +#define ADC_INTENSET_OVERRUN_Pos _U_(1) /**< (ADC_INTENSET) Overrun Interrupt Enable Position */ +#define ADC_INTENSET_OVERRUN_Msk (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) /**< (ADC_INTENSET) Overrun Interrupt Enable Mask */ +#define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & ((value) << ADC_INTENSET_OVERRUN_Pos)) +#define ADC_INTENSET_WINMON_Pos _U_(2) /**< (ADC_INTENSET) Window Monitor Interrupt Enable Position */ +#define ADC_INTENSET_WINMON_Msk (_U_(0x1) << ADC_INTENSET_WINMON_Pos) /**< (ADC_INTENSET) Window Monitor Interrupt Enable Mask */ +#define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & ((value) << ADC_INTENSET_WINMON_Pos)) +#define ADC_INTENSET_Msk _U_(0x07) /**< (ADC_INTENSET) Register Mask */ + + +/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define ADC_INTFLAG_RESRDY_Pos _U_(0) /**< (ADC_INTFLAG) Result Ready Interrupt Flag Position */ +#define ADC_INTFLAG_RESRDY_Msk (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) /**< (ADC_INTFLAG) Result Ready Interrupt Flag Mask */ +#define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & ((value) << ADC_INTFLAG_RESRDY_Pos)) +#define ADC_INTFLAG_OVERRUN_Pos _U_(1) /**< (ADC_INTFLAG) Overrun Interrupt Flag Position */ +#define ADC_INTFLAG_OVERRUN_Msk (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /**< (ADC_INTFLAG) Overrun Interrupt Flag Mask */ +#define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & ((value) << ADC_INTFLAG_OVERRUN_Pos)) +#define ADC_INTFLAG_WINMON_Pos _U_(2) /**< (ADC_INTFLAG) Window Monitor Interrupt Flag Position */ +#define ADC_INTFLAG_WINMON_Msk (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) /**< (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */ +#define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & ((value) << ADC_INTFLAG_WINMON_Pos)) +#define ADC_INTFLAG_Msk _U_(0x07) /**< (ADC_INTFLAG) Register Mask */ + + +/* -------- ADC_STATUS : (ADC Offset: 0x2F) ( R/ 8) Status -------- */ +#define ADC_STATUS_RESETVALUE _U_(0x00) /**< (ADC_STATUS) Status Reset Value */ + +#define ADC_STATUS_ADCBUSY_Pos _U_(0) /**< (ADC_STATUS) ADC Busy Status Position */ +#define ADC_STATUS_ADCBUSY_Msk (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) /**< (ADC_STATUS) ADC Busy Status Mask */ +#define ADC_STATUS_ADCBUSY(value) (ADC_STATUS_ADCBUSY_Msk & ((value) << ADC_STATUS_ADCBUSY_Pos)) +#define ADC_STATUS_WCC_Pos _U_(2) /**< (ADC_STATUS) Window Comparator Counter Position */ +#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) /**< (ADC_STATUS) Window Comparator Counter Mask */ +#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) +#define ADC_STATUS_Msk _U_(0xFD) /**< (ADC_STATUS) Register Mask */ + + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) ( R/ 32) Synchronization Busy -------- */ +#define ADC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (ADC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define ADC_SYNCBUSY_SWRST_Pos _U_(0) /**< (ADC_SYNCBUSY) SWRST Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWRST_Msk (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /**< (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & ((value) << ADC_SYNCBUSY_SWRST_Pos)) +#define ADC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */ +#define ADC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /**< (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */ +#define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & ((value) << ADC_SYNCBUSY_ENABLE_Pos)) +#define ADC_SYNCBUSY_INPUTCTRL_Pos _U_(2) /**< (ADC_SYNCBUSY) Input Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_INPUTCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /**< (ADC_SYNCBUSY) Input Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & ((value) << ADC_SYNCBUSY_INPUTCTRL_Pos)) +#define ADC_SYNCBUSY_CTRLB_Pos _U_(3) /**< (ADC_SYNCBUSY) Control B Synchronization Busy Position */ +#define ADC_SYNCBUSY_CTRLB_Msk (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) /**< (ADC_SYNCBUSY) Control B Synchronization Busy Mask */ +#define ADC_SYNCBUSY_CTRLB(value) (ADC_SYNCBUSY_CTRLB_Msk & ((value) << ADC_SYNCBUSY_CTRLB_Pos)) +#define ADC_SYNCBUSY_REFCTRL_Pos _U_(4) /**< (ADC_SYNCBUSY) Reference Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_REFCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) /**< (ADC_SYNCBUSY) Reference Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_REFCTRL(value) (ADC_SYNCBUSY_REFCTRL_Msk & ((value) << ADC_SYNCBUSY_REFCTRL_Pos)) +#define ADC_SYNCBUSY_AVGCTRL_Pos _U_(5) /**< (ADC_SYNCBUSY) Average Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_AVGCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /**< (ADC_SYNCBUSY) Average Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & ((value) << ADC_SYNCBUSY_AVGCTRL_Pos)) +#define ADC_SYNCBUSY_SAMPCTRL_Pos _U_(6) /**< (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_SAMPCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /**< (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & ((value) << ADC_SYNCBUSY_SAMPCTRL_Pos)) +#define ADC_SYNCBUSY_WINLT_Pos _U_(7) /**< (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINLT_Msk (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /**< (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & ((value) << ADC_SYNCBUSY_WINLT_Pos)) +#define ADC_SYNCBUSY_WINUT_Pos _U_(8) /**< (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINUT_Msk (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /**< (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & ((value) << ADC_SYNCBUSY_WINUT_Pos)) +#define ADC_SYNCBUSY_GAINCORR_Pos _U_(9) /**< (ADC_SYNCBUSY) Gain Correction Synchronization Busy Position */ +#define ADC_SYNCBUSY_GAINCORR_Msk (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /**< (ADC_SYNCBUSY) Gain Correction Synchronization Busy Mask */ +#define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & ((value) << ADC_SYNCBUSY_GAINCORR_Pos)) +#define ADC_SYNCBUSY_OFFSETCORR_Pos _U_(10) /**< (ADC_SYNCBUSY) Offset Correction Synchronization Busy Position */ +#define ADC_SYNCBUSY_OFFSETCORR_Msk (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /**< (ADC_SYNCBUSY) Offset Correction Synchronization Busy Mask */ +#define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & ((value) << ADC_SYNCBUSY_OFFSETCORR_Pos)) +#define ADC_SYNCBUSY_SWTRIG_Pos _U_(11) /**< (ADC_SYNCBUSY) Software Trigger Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWTRIG_Msk (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /**< (ADC_SYNCBUSY) Software Trigger Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & ((value) << ADC_SYNCBUSY_SWTRIG_Pos)) +#define ADC_SYNCBUSY_Msk _U_(0x00000FFF) /**< (ADC_SYNCBUSY) Register Mask */ + + +/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ +#define ADC_DSEQDATA_RESETVALUE _U_(0x00) /**< (ADC_DSEQDATA) DMA Sequencial Data Reset Value */ + +#define ADC_DSEQDATA_DATA_Pos _U_(0) /**< (ADC_DSEQDATA) DMA Sequential Data Position */ +#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) /**< (ADC_DSEQDATA) DMA Sequential Data Mask */ +#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) +#define ADC_DSEQDATA_Msk _U_(0xFFFFFFFF) /**< (ADC_DSEQDATA) Register Mask */ + + +/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ +#define ADC_DSEQCTRL_RESETVALUE _U_(0x00) /**< (ADC_DSEQCTRL) DMA Sequential Control Reset Value */ + +#define ADC_DSEQCTRL_INPUTCTRL_Pos _U_(0) /**< (ADC_DSEQCTRL) Input Control Position */ +#define ADC_DSEQCTRL_INPUTCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) /**< (ADC_DSEQCTRL) Input Control Mask */ +#define ADC_DSEQCTRL_INPUTCTRL(value) (ADC_DSEQCTRL_INPUTCTRL_Msk & ((value) << ADC_DSEQCTRL_INPUTCTRL_Pos)) +#define ADC_DSEQCTRL_CTRLB_Pos _U_(1) /**< (ADC_DSEQCTRL) Control B Position */ +#define ADC_DSEQCTRL_CTRLB_Msk (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) /**< (ADC_DSEQCTRL) Control B Mask */ +#define ADC_DSEQCTRL_CTRLB(value) (ADC_DSEQCTRL_CTRLB_Msk & ((value) << ADC_DSEQCTRL_CTRLB_Pos)) +#define ADC_DSEQCTRL_REFCTRL_Pos _U_(2) /**< (ADC_DSEQCTRL) Reference Control Position */ +#define ADC_DSEQCTRL_REFCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) /**< (ADC_DSEQCTRL) Reference Control Mask */ +#define ADC_DSEQCTRL_REFCTRL(value) (ADC_DSEQCTRL_REFCTRL_Msk & ((value) << ADC_DSEQCTRL_REFCTRL_Pos)) +#define ADC_DSEQCTRL_AVGCTRL_Pos _U_(3) /**< (ADC_DSEQCTRL) Average Control Position */ +#define ADC_DSEQCTRL_AVGCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) /**< (ADC_DSEQCTRL) Average Control Mask */ +#define ADC_DSEQCTRL_AVGCTRL(value) (ADC_DSEQCTRL_AVGCTRL_Msk & ((value) << ADC_DSEQCTRL_AVGCTRL_Pos)) +#define ADC_DSEQCTRL_SAMPCTRL_Pos _U_(4) /**< (ADC_DSEQCTRL) Sampling Time Control Position */ +#define ADC_DSEQCTRL_SAMPCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) /**< (ADC_DSEQCTRL) Sampling Time Control Mask */ +#define ADC_DSEQCTRL_SAMPCTRL(value) (ADC_DSEQCTRL_SAMPCTRL_Msk & ((value) << ADC_DSEQCTRL_SAMPCTRL_Pos)) +#define ADC_DSEQCTRL_WINLT_Pos _U_(5) /**< (ADC_DSEQCTRL) Window Monitor Lower Threshold Position */ +#define ADC_DSEQCTRL_WINLT_Msk (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) /**< (ADC_DSEQCTRL) Window Monitor Lower Threshold Mask */ +#define ADC_DSEQCTRL_WINLT(value) (ADC_DSEQCTRL_WINLT_Msk & ((value) << ADC_DSEQCTRL_WINLT_Pos)) +#define ADC_DSEQCTRL_WINUT_Pos _U_(6) /**< (ADC_DSEQCTRL) Window Monitor Upper Threshold Position */ +#define ADC_DSEQCTRL_WINUT_Msk (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) /**< (ADC_DSEQCTRL) Window Monitor Upper Threshold Mask */ +#define ADC_DSEQCTRL_WINUT(value) (ADC_DSEQCTRL_WINUT_Msk & ((value) << ADC_DSEQCTRL_WINUT_Pos)) +#define ADC_DSEQCTRL_GAINCORR_Pos _U_(7) /**< (ADC_DSEQCTRL) Gain Correction Position */ +#define ADC_DSEQCTRL_GAINCORR_Msk (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) /**< (ADC_DSEQCTRL) Gain Correction Mask */ +#define ADC_DSEQCTRL_GAINCORR(value) (ADC_DSEQCTRL_GAINCORR_Msk & ((value) << ADC_DSEQCTRL_GAINCORR_Pos)) +#define ADC_DSEQCTRL_OFFSETCORR_Pos _U_(8) /**< (ADC_DSEQCTRL) Offset Correction Position */ +#define ADC_DSEQCTRL_OFFSETCORR_Msk (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) /**< (ADC_DSEQCTRL) Offset Correction Mask */ +#define ADC_DSEQCTRL_OFFSETCORR(value) (ADC_DSEQCTRL_OFFSETCORR_Msk & ((value) << ADC_DSEQCTRL_OFFSETCORR_Pos)) +#define ADC_DSEQCTRL_AUTOSTART_Pos _U_(31) /**< (ADC_DSEQCTRL) ADC Auto-Start Conversion Position */ +#define ADC_DSEQCTRL_AUTOSTART_Msk (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) /**< (ADC_DSEQCTRL) ADC Auto-Start Conversion Mask */ +#define ADC_DSEQCTRL_AUTOSTART(value) (ADC_DSEQCTRL_AUTOSTART_Msk & ((value) << ADC_DSEQCTRL_AUTOSTART_Pos)) +#define ADC_DSEQCTRL_Msk _U_(0x800001FF) /**< (ADC_DSEQCTRL) Register Mask */ + + +/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) ( R/ 32) DMA Sequencial Status -------- */ +#define ADC_DSEQSTAT_RESETVALUE _U_(0x00) /**< (ADC_DSEQSTAT) DMA Sequencial Status Reset Value */ + +#define ADC_DSEQSTAT_INPUTCTRL_Pos _U_(0) /**< (ADC_DSEQSTAT) Input Control Position */ +#define ADC_DSEQSTAT_INPUTCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) /**< (ADC_DSEQSTAT) Input Control Mask */ +#define ADC_DSEQSTAT_INPUTCTRL(value) (ADC_DSEQSTAT_INPUTCTRL_Msk & ((value) << ADC_DSEQSTAT_INPUTCTRL_Pos)) +#define ADC_DSEQSTAT_CTRLB_Pos _U_(1) /**< (ADC_DSEQSTAT) Control B Position */ +#define ADC_DSEQSTAT_CTRLB_Msk (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) /**< (ADC_DSEQSTAT) Control B Mask */ +#define ADC_DSEQSTAT_CTRLB(value) (ADC_DSEQSTAT_CTRLB_Msk & ((value) << ADC_DSEQSTAT_CTRLB_Pos)) +#define ADC_DSEQSTAT_REFCTRL_Pos _U_(2) /**< (ADC_DSEQSTAT) Reference Control Position */ +#define ADC_DSEQSTAT_REFCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) /**< (ADC_DSEQSTAT) Reference Control Mask */ +#define ADC_DSEQSTAT_REFCTRL(value) (ADC_DSEQSTAT_REFCTRL_Msk & ((value) << ADC_DSEQSTAT_REFCTRL_Pos)) +#define ADC_DSEQSTAT_AVGCTRL_Pos _U_(3) /**< (ADC_DSEQSTAT) Average Control Position */ +#define ADC_DSEQSTAT_AVGCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) /**< (ADC_DSEQSTAT) Average Control Mask */ +#define ADC_DSEQSTAT_AVGCTRL(value) (ADC_DSEQSTAT_AVGCTRL_Msk & ((value) << ADC_DSEQSTAT_AVGCTRL_Pos)) +#define ADC_DSEQSTAT_SAMPCTRL_Pos _U_(4) /**< (ADC_DSEQSTAT) Sampling Time Control Position */ +#define ADC_DSEQSTAT_SAMPCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) /**< (ADC_DSEQSTAT) Sampling Time Control Mask */ +#define ADC_DSEQSTAT_SAMPCTRL(value) (ADC_DSEQSTAT_SAMPCTRL_Msk & ((value) << ADC_DSEQSTAT_SAMPCTRL_Pos)) +#define ADC_DSEQSTAT_WINLT_Pos _U_(5) /**< (ADC_DSEQSTAT) Window Monitor Lower Threshold Position */ +#define ADC_DSEQSTAT_WINLT_Msk (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) /**< (ADC_DSEQSTAT) Window Monitor Lower Threshold Mask */ +#define ADC_DSEQSTAT_WINLT(value) (ADC_DSEQSTAT_WINLT_Msk & ((value) << ADC_DSEQSTAT_WINLT_Pos)) +#define ADC_DSEQSTAT_WINUT_Pos _U_(6) /**< (ADC_DSEQSTAT) Window Monitor Upper Threshold Position */ +#define ADC_DSEQSTAT_WINUT_Msk (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) /**< (ADC_DSEQSTAT) Window Monitor Upper Threshold Mask */ +#define ADC_DSEQSTAT_WINUT(value) (ADC_DSEQSTAT_WINUT_Msk & ((value) << ADC_DSEQSTAT_WINUT_Pos)) +#define ADC_DSEQSTAT_GAINCORR_Pos _U_(7) /**< (ADC_DSEQSTAT) Gain Correction Position */ +#define ADC_DSEQSTAT_GAINCORR_Msk (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) /**< (ADC_DSEQSTAT) Gain Correction Mask */ +#define ADC_DSEQSTAT_GAINCORR(value) (ADC_DSEQSTAT_GAINCORR_Msk & ((value) << ADC_DSEQSTAT_GAINCORR_Pos)) +#define ADC_DSEQSTAT_OFFSETCORR_Pos _U_(8) /**< (ADC_DSEQSTAT) Offset Correction Position */ +#define ADC_DSEQSTAT_OFFSETCORR_Msk (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) /**< (ADC_DSEQSTAT) Offset Correction Mask */ +#define ADC_DSEQSTAT_OFFSETCORR(value) (ADC_DSEQSTAT_OFFSETCORR_Msk & ((value) << ADC_DSEQSTAT_OFFSETCORR_Pos)) +#define ADC_DSEQSTAT_BUSY_Pos _U_(31) /**< (ADC_DSEQSTAT) DMA Sequencing Busy Position */ +#define ADC_DSEQSTAT_BUSY_Msk (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) /**< (ADC_DSEQSTAT) DMA Sequencing Busy Mask */ +#define ADC_DSEQSTAT_BUSY(value) (ADC_DSEQSTAT_BUSY_Msk & ((value) << ADC_DSEQSTAT_BUSY_Pos)) +#define ADC_DSEQSTAT_Msk _U_(0x800001FF) /**< (ADC_DSEQSTAT) Register Mask */ + + +/* -------- ADC_RESULT : (ADC Offset: 0x40) ( R/ 16) Result Conversion Value -------- */ +#define ADC_RESULT_RESETVALUE _U_(0x00) /**< (ADC_RESULT) Result Conversion Value Reset Value */ + +#define ADC_RESULT_RESULT_Pos _U_(0) /**< (ADC_RESULT) Result Conversion Value Position */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) /**< (ADC_RESULT) Result Conversion Value Mask */ +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_Msk _U_(0xFFFF) /**< (ADC_RESULT) Register Mask */ + + +/* -------- ADC_RESS : (ADC Offset: 0x44) ( R/ 16) Last Sample Result -------- */ +#define ADC_RESS_RESETVALUE _U_(0x00) /**< (ADC_RESS) Last Sample Result Reset Value */ + +#define ADC_RESS_RESS_Pos _U_(0) /**< (ADC_RESS) Last ADC conversion result Position */ +#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) /**< (ADC_RESS) Last ADC conversion result Mask */ +#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) +#define ADC_RESS_Msk _U_(0xFFFF) /**< (ADC_RESS) Register Mask */ + + +/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ +#define ADC_CALIB_RESETVALUE _U_(0x00) /**< (ADC_CALIB) Calibration Reset Value */ + +#define ADC_CALIB_BIASCOMP_Pos _U_(0) /**< (ADC_CALIB) Bias Comparator Scaling Position */ +#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) /**< (ADC_CALIB) Bias Comparator Scaling Mask */ +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASR2R_Pos _U_(4) /**< (ADC_CALIB) Bias R2R Ampli scaling Position */ +#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) /**< (ADC_CALIB) Bias R2R Ampli scaling Mask */ +#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos _U_(8) /**< (ADC_CALIB) Bias Reference Buffer Scaling Position */ +#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /**< (ADC_CALIB) Bias Reference Buffer Scaling Mask */ +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_Msk _U_(0x0777) /**< (ADC_CALIB) Register Mask */ + + +/** \brief ADC register offsets definitions */ +#define ADC_CTRLA_REG_OFST (0x00) /**< (ADC_CTRLA) Control A Offset */ +#define ADC_EVCTRL_REG_OFST (0x02) /**< (ADC_EVCTRL) Event Control Offset */ +#define ADC_DBGCTRL_REG_OFST (0x03) /**< (ADC_DBGCTRL) Debug Control Offset */ +#define ADC_INPUTCTRL_REG_OFST (0x04) /**< (ADC_INPUTCTRL) Input Control Offset */ +#define ADC_CTRLB_REG_OFST (0x06) /**< (ADC_CTRLB) Control B Offset */ +#define ADC_REFCTRL_REG_OFST (0x08) /**< (ADC_REFCTRL) Reference Control Offset */ +#define ADC_AVGCTRL_REG_OFST (0x0A) /**< (ADC_AVGCTRL) Average Control Offset */ +#define ADC_SAMPCTRL_REG_OFST (0x0B) /**< (ADC_SAMPCTRL) Sample Time Control Offset */ +#define ADC_WINLT_REG_OFST (0x0C) /**< (ADC_WINLT) Window Monitor Lower Threshold Offset */ +#define ADC_WINUT_REG_OFST (0x0E) /**< (ADC_WINUT) Window Monitor Upper Threshold Offset */ +#define ADC_GAINCORR_REG_OFST (0x10) /**< (ADC_GAINCORR) Gain Correction Offset */ +#define ADC_OFFSETCORR_REG_OFST (0x12) /**< (ADC_OFFSETCORR) Offset Correction Offset */ +#define ADC_SWTRIG_REG_OFST (0x14) /**< (ADC_SWTRIG) Software Trigger Offset */ +#define ADC_INTENCLR_REG_OFST (0x2C) /**< (ADC_INTENCLR) Interrupt Enable Clear Offset */ +#define ADC_INTENSET_REG_OFST (0x2D) /**< (ADC_INTENSET) Interrupt Enable Set Offset */ +#define ADC_INTFLAG_REG_OFST (0x2E) /**< (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define ADC_STATUS_REG_OFST (0x2F) /**< (ADC_STATUS) Status Offset */ +#define ADC_SYNCBUSY_REG_OFST (0x30) /**< (ADC_SYNCBUSY) Synchronization Busy Offset */ +#define ADC_DSEQDATA_REG_OFST (0x34) /**< (ADC_DSEQDATA) DMA Sequencial Data Offset */ +#define ADC_DSEQCTRL_REG_OFST (0x38) /**< (ADC_DSEQCTRL) DMA Sequential Control Offset */ +#define ADC_DSEQSTAT_REG_OFST (0x3C) /**< (ADC_DSEQSTAT) DMA Sequencial Status Offset */ +#define ADC_RESULT_REG_OFST (0x40) /**< (ADC_RESULT) Result Conversion Value Offset */ +#define ADC_RESS_REG_OFST (0x44) /**< (ADC_RESS) Last Sample Result Offset */ +#define ADC_CALIB_REG_OFST (0x48) /**< (ADC_CALIB) Calibration Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ADC register API structure */ +typedef struct +{ /* Analog Digital Converter */ + __IO uint16_t ADC_CTRLA; /**< Offset: 0x00 (R/W 16) Control A */ + __IO uint8_t ADC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ + __IO uint8_t ADC_DBGCTRL; /**< Offset: 0x03 (R/W 8) Debug Control */ + __IO uint16_t ADC_INPUTCTRL; /**< Offset: 0x04 (R/W 16) Input Control */ + __IO uint16_t ADC_CTRLB; /**< Offset: 0x06 (R/W 16) Control B */ + __IO uint8_t ADC_REFCTRL; /**< Offset: 0x08 (R/W 8) Reference Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t ADC_AVGCTRL; /**< Offset: 0x0A (R/W 8) Average Control */ + __IO uint8_t ADC_SAMPCTRL; /**< Offset: 0x0B (R/W 8) Sample Time Control */ + __IO uint16_t ADC_WINLT; /**< Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ + __IO uint16_t ADC_WINUT; /**< Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ + __IO uint16_t ADC_GAINCORR; /**< Offset: 0x10 (R/W 16) Gain Correction */ + __IO uint16_t ADC_OFFSETCORR; /**< Offset: 0x12 (R/W 16) Offset Correction */ + __IO uint8_t ADC_SWTRIG; /**< Offset: 0x14 (R/W 8) Software Trigger */ + __I uint8_t Reserved2[0x17]; + __IO uint8_t ADC_INTENCLR; /**< Offset: 0x2C (R/W 8) Interrupt Enable Clear */ + __IO uint8_t ADC_INTENSET; /**< Offset: 0x2D (R/W 8) Interrupt Enable Set */ + __IO uint8_t ADC_INTFLAG; /**< Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t ADC_STATUS; /**< Offset: 0x2F (R/ 8) Status */ + __I uint32_t ADC_SYNCBUSY; /**< Offset: 0x30 (R/ 32) Synchronization Busy */ + __O uint32_t ADC_DSEQDATA; /**< Offset: 0x34 ( /W 32) DMA Sequencial Data */ + __IO uint32_t ADC_DSEQCTRL; /**< Offset: 0x38 (R/W 32) DMA Sequential Control */ + __I uint32_t ADC_DSEQSTAT; /**< Offset: 0x3C (R/ 32) DMA Sequencial Status */ + __I uint16_t ADC_RESULT; /**< Offset: 0x40 (R/ 16) Result Conversion Value */ + __I uint8_t Reserved3[0x02]; + __I uint16_t ADC_RESS; /**< Offset: 0x44 (R/ 16) Last Sample Result */ + __I uint8_t Reserved4[0x02]; + __IO uint16_t ADC_CALIB; /**< Offset: 0x48 (R/W 16) Calibration */ +} adc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMD51_ADC_COMPONENT_H_ */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/component/aes.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/aes.h new file mode 100644 index 00000000..b274bfa6 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/aes.h @@ -0,0 +1,276 @@ +/** + * \brief Component description for AES + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:45:00Z */ +#ifndef _SAMD51_AES_COMPONENT_H_ +#define _SAMD51_AES_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AES */ +/* ************************************************************************** */ + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#define AES_CTRLA_RESETVALUE _U_(0x00) /**< (AES_CTRLA) Control A Reset Value */ + +#define AES_CTRLA_SWRST_Pos _U_(0) /**< (AES_CTRLA) Software Reset Position */ +#define AES_CTRLA_SWRST_Msk (_U_(0x1) << AES_CTRLA_SWRST_Pos) /**< (AES_CTRLA) Software Reset Mask */ +#define AES_CTRLA_SWRST(value) (AES_CTRLA_SWRST_Msk & ((value) << AES_CTRLA_SWRST_Pos)) +#define AES_CTRLA_ENABLE_Pos _U_(1) /**< (AES_CTRLA) Enable Position */ +#define AES_CTRLA_ENABLE_Msk (_U_(0x1) << AES_CTRLA_ENABLE_Pos) /**< (AES_CTRLA) Enable Mask */ +#define AES_CTRLA_ENABLE(value) (AES_CTRLA_ENABLE_Msk & ((value) << AES_CTRLA_ENABLE_Pos)) +#define AES_CTRLA_AESMODE_Pos _U_(2) /**< (AES_CTRLA) AES Modes of operation Position */ +#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) AES Modes of operation Mask */ +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) +#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< (AES_CTRLA) Electronic code book mode */ +#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< (AES_CTRLA) Cipher block chaining mode */ +#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< (AES_CTRLA) Output feedback mode */ +#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< (AES_CTRLA) Cipher feedback mode */ +#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< (AES_CTRLA) Counter mode */ +#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< (AES_CTRLA) CCM mode */ +#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< (AES_CTRLA) Galois counter mode */ +#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Electronic code book mode Position */ +#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher block chaining mode Position */ +#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Output feedback mode Position */ +#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher feedback mode Position */ +#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Counter mode Position */ +#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) CCM mode Position */ +#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Galois counter mode Position */ +#define AES_CTRLA_CFBS_Pos _U_(5) /**< (AES_CTRLA) Cipher Feedback Block Size Position */ +#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) Cipher Feedback Block Size Mask */ +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) +#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_KEYSIZE_Pos _U_(8) /**< (AES_CTRLA) Encryption Key Size Position */ +#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) Encryption Key Size Mask */ +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) +#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_CIPHER_Pos _U_(10) /**< (AES_CTRLA) Cipher Mode Position */ +#define AES_CTRLA_CIPHER_Msk (_U_(0x1) << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Cipher Mode Mask */ +#define AES_CTRLA_CIPHER(value) (AES_CTRLA_CIPHER_Msk & ((value) << AES_CTRLA_CIPHER_Pos)) +#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< (AES_CTRLA) Decryption */ +#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< (AES_CTRLA) Encryption */ +#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Decryption Position */ +#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Encryption Position */ +#define AES_CTRLA_STARTMODE_Pos _U_(11) /**< (AES_CTRLA) Start Mode Select Position */ +#define AES_CTRLA_STARTMODE_Msk (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Mode Select Mask */ +#define AES_CTRLA_STARTMODE(value) (AES_CTRLA_STARTMODE_Msk & ((value) << AES_CTRLA_STARTMODE_Pos)) +#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode */ +#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode */ +#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode Position */ +#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode Position */ +#define AES_CTRLA_LOD_Pos _U_(12) /**< (AES_CTRLA) Last Output Data Mode Position */ +#define AES_CTRLA_LOD_Msk (_U_(0x1) << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Last Output Data Mode Mask */ +#define AES_CTRLA_LOD(value) (AES_CTRLA_LOD_Msk & ((value) << AES_CTRLA_LOD_Pos)) +#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */ +#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start encryption in Last Output Data mode */ +#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) No effect Position */ +#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Start encryption in Last Output Data mode Position */ +#define AES_CTRLA_KEYGEN_Pos _U_(13) /**< (AES_CTRLA) Last Key Generation Position */ +#define AES_CTRLA_KEYGEN_Msk (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Last Key Generation Mask */ +#define AES_CTRLA_KEYGEN(value) (AES_CTRLA_KEYGEN_Msk & ((value) << AES_CTRLA_KEYGEN_Pos)) +#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */ +#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key */ +#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) No effect Position */ +#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key Position */ +#define AES_CTRLA_XORKEY_Pos _U_(14) /**< (AES_CTRLA) XOR Key Operation Position */ +#define AES_CTRLA_XORKEY_Msk (_U_(0x1) << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) XOR Key Operation Mask */ +#define AES_CTRLA_XORKEY(value) (AES_CTRLA_XORKEY_Msk & ((value) << AES_CTRLA_XORKEY_Pos)) +#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */ +#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ +#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) No effect Position */ +#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. Position */ +#define AES_CTRLA_CTYPE_Pos _U_(16) /**< (AES_CTRLA) Counter Measure Type Position */ +#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) /**< (AES_CTRLA) Counter Measure Type Mask */ +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) +#define AES_CTRLA_Msk _U_(0x000F7FFF) /**< (AES_CTRLA) Register Mask */ + + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#define AES_CTRLB_RESETVALUE _U_(0x00) /**< (AES_CTRLB) Control B Reset Value */ + +#define AES_CTRLB_START_Pos _U_(0) /**< (AES_CTRLB) Start Encryption/Decryption Position */ +#define AES_CTRLB_START_Msk (_U_(0x1) << AES_CTRLB_START_Pos) /**< (AES_CTRLB) Start Encryption/Decryption Mask */ +#define AES_CTRLB_START(value) (AES_CTRLB_START_Msk & ((value) << AES_CTRLB_START_Pos)) +#define AES_CTRLB_NEWMSG_Pos _U_(1) /**< (AES_CTRLB) New message Position */ +#define AES_CTRLB_NEWMSG_Msk (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) /**< (AES_CTRLB) New message Mask */ +#define AES_CTRLB_NEWMSG(value) (AES_CTRLB_NEWMSG_Msk & ((value) << AES_CTRLB_NEWMSG_Pos)) +#define AES_CTRLB_EOM_Pos _U_(2) /**< (AES_CTRLB) End of message Position */ +#define AES_CTRLB_EOM_Msk (_U_(0x1) << AES_CTRLB_EOM_Pos) /**< (AES_CTRLB) End of message Mask */ +#define AES_CTRLB_EOM(value) (AES_CTRLB_EOM_Msk & ((value) << AES_CTRLB_EOM_Pos)) +#define AES_CTRLB_GFMUL_Pos _U_(3) /**< (AES_CTRLB) GF Multiplication Position */ +#define AES_CTRLB_GFMUL_Msk (_U_(0x1) << AES_CTRLB_GFMUL_Pos) /**< (AES_CTRLB) GF Multiplication Mask */ +#define AES_CTRLB_GFMUL(value) (AES_CTRLB_GFMUL_Msk & ((value) << AES_CTRLB_GFMUL_Pos)) +#define AES_CTRLB_Msk _U_(0x0F) /**< (AES_CTRLB) Register Mask */ + + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< (AES_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define AES_INTENCLR_ENCCMP_Pos _U_(0) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Position */ +#define AES_INTENCLR_ENCCMP_Msk (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Mask */ +#define AES_INTENCLR_ENCCMP(value) (AES_INTENCLR_ENCCMP_Msk & ((value) << AES_INTENCLR_ENCCMP_Pos)) +#define AES_INTENCLR_GFMCMP_Pos _U_(1) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Position */ +#define AES_INTENCLR_GFMCMP_Msk (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Mask */ +#define AES_INTENCLR_GFMCMP(value) (AES_INTENCLR_GFMCMP_Msk & ((value) << AES_INTENCLR_GFMCMP_Pos)) +#define AES_INTENCLR_Msk _U_(0x03) /**< (AES_INTENCLR) Register Mask */ + + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#define AES_INTENSET_RESETVALUE _U_(0x00) /**< (AES_INTENSET) Interrupt Enable Set Reset Value */ + +#define AES_INTENSET_ENCCMP_Pos _U_(0) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Position */ +#define AES_INTENSET_ENCCMP_Msk (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Mask */ +#define AES_INTENSET_ENCCMP(value) (AES_INTENSET_ENCCMP_Msk & ((value) << AES_INTENSET_ENCCMP_Pos)) +#define AES_INTENSET_GFMCMP_Pos _U_(1) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Position */ +#define AES_INTENSET_GFMCMP_Msk (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Mask */ +#define AES_INTENSET_GFMCMP(value) (AES_INTENSET_GFMCMP_Msk & ((value) << AES_INTENSET_GFMCMP_Pos)) +#define AES_INTENSET_Msk _U_(0x03) /**< (AES_INTENSET) Register Mask */ + + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< (AES_INTFLAG) Interrupt Flag Status Reset Value */ + +#define AES_INTFLAG_ENCCMP_Pos _U_(0) /**< (AES_INTFLAG) Encryption Complete Position */ +#define AES_INTFLAG_ENCCMP_Msk (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) /**< (AES_INTFLAG) Encryption Complete Mask */ +#define AES_INTFLAG_ENCCMP(value) (AES_INTFLAG_ENCCMP_Msk & ((value) << AES_INTFLAG_ENCCMP_Pos)) +#define AES_INTFLAG_GFMCMP_Pos _U_(1) /**< (AES_INTFLAG) GF Multiplication Complete Position */ +#define AES_INTFLAG_GFMCMP_Msk (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) /**< (AES_INTFLAG) GF Multiplication Complete Mask */ +#define AES_INTFLAG_GFMCMP(value) (AES_INTFLAG_GFMCMP_Msk & ((value) << AES_INTFLAG_GFMCMP_Pos)) +#define AES_INTFLAG_Msk _U_(0x03) /**< (AES_INTFLAG) Register Mask */ + + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< (AES_DATABUFPTR) Data buffer pointer Reset Value */ + +#define AES_DATABUFPTR_INDATAPTR_Pos _U_(0) /**< (AES_DATABUFPTR) Input Data Pointer Position */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) /**< (AES_DATABUFPTR) Input Data Pointer Mask */ +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) +#define AES_DATABUFPTR_Msk _U_(0x03) /**< (AES_DATABUFPTR) Register Mask */ + + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ +#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< (AES_DBGCTRL) Debug control Reset Value */ + +#define AES_DBGCTRL_DBGRUN_Pos _U_(0) /**< (AES_DBGCTRL) Debug Run Position */ +#define AES_DBGCTRL_DBGRUN_Msk (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) /**< (AES_DBGCTRL) Debug Run Mask */ +#define AES_DBGCTRL_DBGRUN(value) (AES_DBGCTRL_DBGRUN_Msk & ((value) << AES_DBGCTRL_DBGRUN_Pos)) +#define AES_DBGCTRL_Msk _U_(0x01) /**< (AES_DBGCTRL) Register Mask */ + + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#define AES_KEYWORD_RESETVALUE _U_(0x00) /**< (AES_KEYWORD) Keyword n Reset Value */ + +#define AES_KEYWORD_Msk _U_(0x00000000) /**< (AES_KEYWORD) Register Mask */ + + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#define AES_INDATA_RESETVALUE _U_(0x00) /**< (AES_INDATA) Indata Reset Value */ + +#define AES_INDATA_Msk _U_(0x00000000) /**< (AES_INDATA) Register Mask */ + + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#define AES_INTVECTV_RESETVALUE _U_(0x00) /**< (AES_INTVECTV) Initialisation Vector n Reset Value */ + +#define AES_INTVECTV_Msk _U_(0x00000000) /**< (AES_INTVECTV) Register Mask */ + + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#define AES_HASHKEY_RESETVALUE _U_(0x00) /**< (AES_HASHKEY) Hash key n Reset Value */ + +#define AES_HASHKEY_Msk _U_(0x00000000) /**< (AES_HASHKEY) Register Mask */ + + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#define AES_GHASH_RESETVALUE _U_(0x00) /**< (AES_GHASH) Galois Hash n Reset Value */ + +#define AES_GHASH_Msk _U_(0x00000000) /**< (AES_GHASH) Register Mask */ + + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#define AES_CIPLEN_RESETVALUE _U_(0x00) /**< (AES_CIPLEN) Cipher Length Reset Value */ + +#define AES_CIPLEN_Msk _U_(0x00000000) /**< (AES_CIPLEN) Register Mask */ + + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#define AES_RANDSEED_RESETVALUE _U_(0x00) /**< (AES_RANDSEED) Random Seed Reset Value */ + +#define AES_RANDSEED_Msk _U_(0x00000000) /**< (AES_RANDSEED) Register Mask */ + + +/** \brief AES register offsets definitions */ +#define AES_CTRLA_REG_OFST (0x00) /**< (AES_CTRLA) Control A Offset */ +#define AES_CTRLB_REG_OFST (0x04) /**< (AES_CTRLB) Control B Offset */ +#define AES_INTENCLR_REG_OFST (0x05) /**< (AES_INTENCLR) Interrupt Enable Clear Offset */ +#define AES_INTENSET_REG_OFST (0x06) /**< (AES_INTENSET) Interrupt Enable Set Offset */ +#define AES_INTFLAG_REG_OFST (0x07) /**< (AES_INTFLAG) Interrupt Flag Status Offset */ +#define AES_DATABUFPTR_REG_OFST (0x08) /**< (AES_DATABUFPTR) Data buffer pointer Offset */ +#define AES_DBGCTRL_REG_OFST (0x09) /**< (AES_DBGCTRL) Debug control Offset */ +#define AES_KEYWORD_REG_OFST (0x0C) /**< (AES_KEYWORD) Keyword n Offset */ +#define AES_INDATA_REG_OFST (0x38) /**< (AES_INDATA) Indata Offset */ +#define AES_INTVECTV_REG_OFST (0x3C) /**< (AES_INTVECTV) Initialisation Vector n Offset */ +#define AES_HASHKEY_REG_OFST (0x5C) /**< (AES_HASHKEY) Hash key n Offset */ +#define AES_GHASH_REG_OFST (0x6C) /**< (AES_GHASH) Galois Hash n Offset */ +#define AES_CIPLEN_REG_OFST (0x80) /**< (AES_CIPLEN) Cipher Length Offset */ +#define AES_RANDSEED_REG_OFST (0x84) /**< (AES_RANDSEED) Random Seed Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AES register API structure */ +typedef struct +{ /* Advanced Encryption Standard */ + __IO uint32_t AES_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */ + __IO uint8_t AES_CTRLB; /**< Offset: 0x04 (R/W 8) Control B */ + __IO uint8_t AES_INTENCLR; /**< Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t AES_INTENSET; /**< Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO uint8_t AES_INTFLAG; /**< Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO uint8_t AES_DATABUFPTR; /**< Offset: 0x08 (R/W 8) Data buffer pointer */ + __IO uint8_t AES_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug control */ + __I uint8_t Reserved1[0x02]; + __O uint32_t AES_KEYWORD[8]; /**< Offset: 0x0C ( /W 32) Keyword n */ + __I uint8_t Reserved2[0x0C]; + __IO uint32_t AES_INDATA; /**< Offset: 0x38 (R/W 32) Indata */ + __O uint32_t AES_INTVECTV[4]; /**< Offset: 0x3C ( /W 32) Initialisation Vector n */ + __I uint8_t Reserved3[0x10]; + __IO uint32_t AES_HASHKEY[4]; /**< Offset: 0x5C (R/W 32) Hash key n */ + __IO uint32_t AES_GHASH[4]; /**< Offset: 0x6C (R/W 32) Galois Hash n */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t AES_CIPLEN; /**< Offset: 0x80 (R/W 32) Cipher Length */ + __IO uint32_t AES_RANDSEED; /**< Offset: 0x84 (R/W 32) Random Seed */ +} aes_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMD51_AES_COMPONENT_H_ */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/component/ccl.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/ccl.h new file mode 100644 index 00000000..894bd6f2 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/ccl.h @@ -0,0 +1,217 @@ +/** + * \brief Component description for CCL + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:45:00Z */ +#ifndef _SAMD51_CCL_COMPONENT_H_ +#define _SAMD51_CCL_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CCL */ +/* ************************************************************************** */ + +/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */ +#define CCL_CTRL_RESETVALUE _U_(0x00) /**< (CCL_CTRL) Control Reset Value */ + +#define CCL_CTRL_SWRST_Pos _U_(0) /**< (CCL_CTRL) Software Reset Position */ +#define CCL_CTRL_SWRST_Msk (_U_(0x1) << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) Software Reset Mask */ +#define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & ((value) << CCL_CTRL_SWRST_Pos)) +#define CCL_CTRL_SWRST_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) The peripheral is not reset */ +#define CCL_CTRL_SWRST_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) The peripheral is reset */ +#define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) The peripheral is not reset Position */ +#define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) The peripheral is reset Position */ +#define CCL_CTRL_ENABLE_Pos _U_(1) /**< (CCL_CTRL) Enable Position */ +#define CCL_CTRL_ENABLE_Msk (_U_(0x1) << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) Enable Mask */ +#define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & ((value) << CCL_CTRL_ENABLE_Pos)) +#define CCL_CTRL_ENABLE_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) The peripheral is disabled */ +#define CCL_CTRL_ENABLE_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) The peripheral is enabled */ +#define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) The peripheral is disabled Position */ +#define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) The peripheral is enabled Position */ +#define CCL_CTRL_RUNSTDBY_Pos _U_(6) /**< (CCL_CTRL) Run in Standby Position */ +#define CCL_CTRL_RUNSTDBY_Msk (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Run in Standby Mask */ +#define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & ((value) << CCL_CTRL_RUNSTDBY_Pos)) +#define CCL_CTRL_RUNSTDBY_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) Generic clock is not required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) Generic clock is required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Generic clock is not required in standby sleep mode Position */ +#define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Generic clock is required in standby sleep mode Position */ +#define CCL_CTRL_Msk _U_(0x43) /**< (CCL_CTRL) Register Mask */ + + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */ +#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< (CCL_SEQCTRL) SEQ Control x Reset Value */ + +#define CCL_SEQCTRL_SEQSEL_Pos _U_(0) /**< (CCL_SEQCTRL) Sequential Selection Position */ +#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) Sequential Selection Mask */ +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) Sequential logic is disabled Position */ +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) D flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) JK flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) D latch Position */ +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) RS latch Position */ +#define CCL_SEQCTRL_Msk _U_(0x0F) /**< (CCL_SEQCTRL) Register Mask */ + + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */ +#define CCL_LUTCTRL_RESETVALUE _U_(0x00) /**< (CCL_LUTCTRL) LUT Control x Reset Value */ + +#define CCL_LUTCTRL_ENABLE_Pos _U_(1) /**< (CCL_LUTCTRL) LUT Enable Position */ +#define CCL_LUTCTRL_ENABLE_Msk (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT Enable Mask */ +#define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & ((value) << CCL_LUTCTRL_ENABLE_Pos)) +#define CCL_LUTCTRL_ENABLE_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT block is disabled */ +#define CCL_LUTCTRL_ENABLE_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT block is enabled */ +#define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT block is disabled Position */ +#define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT block is enabled Position */ +#define CCL_LUTCTRL_FILTSEL_Pos _U_(4) /**< (CCL_LUTCTRL) Filter Selection Position */ +#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter Selection Mask */ +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter disabled Position */ +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Synchronizer enabled Position */ +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter enabled Position */ +#define CCL_LUTCTRL_EDGESEL_Pos _U_(7) /**< (CCL_LUTCTRL) Edge Selection Position */ +#define CCL_LUTCTRL_EDGESEL_Msk (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge Selection Mask */ +#define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & ((value) << CCL_LUTCTRL_EDGESEL_Pos)) +#define CCL_LUTCTRL_EDGESEL_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Edge detector is disabled */ +#define CCL_LUTCTRL_EDGESEL_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) Edge detector is enabled */ +#define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge detector is disabled Position */ +#define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge detector is enabled Position */ +#define CCL_LUTCTRL_INSEL0_Pos _U_(8) /**< (CCL_LUTCTRL) Input Selection 0 Position */ +#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Input Selection 0 Mask */ +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL1_Pos _U_(12) /**< (CCL_LUTCTRL) Input Selection 1 Position */ +#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Input Selection 1 Mask */ +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL2_Pos _U_(16) /**< (CCL_LUTCTRL) Input Selection 2 Position */ +#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Input Selection 2 Mask */ +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INVEI_Pos _U_(20) /**< (CCL_LUTCTRL) Inverted Event Input Enable Position */ +#define CCL_LUTCTRL_INVEI_Msk (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Inverted Event Input Enable Mask */ +#define CCL_LUTCTRL_INVEI(value) (CCL_LUTCTRL_INVEI_Msk & ((value) << CCL_LUTCTRL_INVEI_Pos)) +#define CCL_LUTCTRL_INVEI_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Incoming event is not inverted */ +#define CCL_LUTCTRL_INVEI_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) Incoming event is inverted */ +#define CCL_LUTCTRL_INVEI_DISABLE (CCL_LUTCTRL_INVEI_DISABLE_Val << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Incoming event is not inverted Position */ +#define CCL_LUTCTRL_INVEI_ENABLE (CCL_LUTCTRL_INVEI_ENABLE_Val << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Incoming event is inverted Position */ +#define CCL_LUTCTRL_LUTEI_Pos _U_(21) /**< (CCL_LUTCTRL) LUT Event Input Enable Position */ +#define CCL_LUTCTRL_LUTEI_Msk (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT Event Input Enable Mask */ +#define CCL_LUTCTRL_LUTEI(value) (CCL_LUTCTRL_LUTEI_Msk & ((value) << CCL_LUTCTRL_LUTEI_Pos)) +#define CCL_LUTCTRL_LUTEI_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT incoming event is disabled */ +#define CCL_LUTCTRL_LUTEI_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT incoming event is enabled */ +#define CCL_LUTCTRL_LUTEI_DISABLE (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT incoming event is disabled Position */ +#define CCL_LUTCTRL_LUTEI_ENABLE (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT incoming event is enabled Position */ +#define CCL_LUTCTRL_LUTEO_Pos _U_(22) /**< (CCL_LUTCTRL) LUT Event Output Enable Position */ +#define CCL_LUTCTRL_LUTEO_Msk (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT Event Output Enable Mask */ +#define CCL_LUTCTRL_LUTEO(value) (CCL_LUTCTRL_LUTEO_Msk & ((value) << CCL_LUTCTRL_LUTEO_Pos)) +#define CCL_LUTCTRL_LUTEO_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT event output is disabled */ +#define CCL_LUTCTRL_LUTEO_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT event output is enabled */ +#define CCL_LUTCTRL_LUTEO_DISABLE (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT event output is disabled Position */ +#define CCL_LUTCTRL_LUTEO_ENABLE (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT event output is enabled Position */ +#define CCL_LUTCTRL_TRUTH_Pos _U_(24) /**< (CCL_LUTCTRL) Truth Value Position */ +#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) /**< (CCL_LUTCTRL) Truth Value Mask */ +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_Msk _U_(0xFF7FFFB2) /**< (CCL_LUTCTRL) Register Mask */ + + +/** \brief CCL register offsets definitions */ +#define CCL_CTRL_REG_OFST (0x00) /**< (CCL_CTRL) Control Offset */ +#define CCL_SEQCTRL_REG_OFST (0x04) /**< (CCL_SEQCTRL) SEQ Control x Offset */ +#define CCL_LUTCTRL_REG_OFST (0x08) /**< (CCL_LUTCTRL) LUT Control x Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CCL register API structure */ +typedef struct +{ /* Configurable Custom Logic */ + __IO uint8_t CCL_CTRL; /**< Offset: 0x00 (R/W 8) Control */ + __I uint8_t Reserved1[0x03]; + __IO uint8_t CCL_SEQCTRL[2]; /**< Offset: 0x04 (R/W 8) SEQ Control x */ + __I uint8_t Reserved2[0x02]; + __IO uint32_t CCL_LUTCTRL[4]; /**< Offset: 0x08 (R/W 32) LUT Control x */ +} ccl_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMD51_CCL_COMPONENT_H_ */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/component/cmcc.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/cmcc.h new file mode 100644 index 00000000..eeb2125a --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/cmcc.h @@ -0,0 +1,247 @@ +/** + * \brief Component description for CMCC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:45:00Z */ +#ifndef _SAMD51_CMCC_COMPONENT_H_ +#define _SAMD51_CMCC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CMCC */ +/* ************************************************************************** */ + +/* -------- CMCC_TYPE : (CMCC Offset: 0x00) ( R/ 32) Cache Type Register -------- */ +#define CMCC_TYPE_RESETVALUE _U_(0x12D2) /**< (CMCC_TYPE) Cache Type Register Reset Value */ + +#define CMCC_TYPE_GCLK_Pos _U_(1) /**< (CMCC_TYPE) dynamic Clock Gating supported Position */ +#define CMCC_TYPE_GCLK_Msk (_U_(0x1) << CMCC_TYPE_GCLK_Pos) /**< (CMCC_TYPE) dynamic Clock Gating supported Mask */ +#define CMCC_TYPE_GCLK(value) (CMCC_TYPE_GCLK_Msk & ((value) << CMCC_TYPE_GCLK_Pos)) +#define CMCC_TYPE_RRP_Pos _U_(4) /**< (CMCC_TYPE) Round Robin Policy supported Position */ +#define CMCC_TYPE_RRP_Msk (_U_(0x1) << CMCC_TYPE_RRP_Pos) /**< (CMCC_TYPE) Round Robin Policy supported Mask */ +#define CMCC_TYPE_RRP(value) (CMCC_TYPE_RRP_Msk & ((value) << CMCC_TYPE_RRP_Pos)) +#define CMCC_TYPE_WAYNUM_Pos _U_(5) /**< (CMCC_TYPE) Number of Way Position */ +#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) Number of Way Mask */ +#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) +#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< (CMCC_TYPE) Direct Mapped Cache */ +#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< (CMCC_TYPE) 2-WAY set associative */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< (CMCC_TYPE) 4-WAY set associative */ +#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) Direct Mapped Cache Position */ +#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) 2-WAY set associative Position */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) 4-WAY set associative Position */ +#define CMCC_TYPE_LCKDOWN_Pos _U_(7) /**< (CMCC_TYPE) Lock Down supported Position */ +#define CMCC_TYPE_LCKDOWN_Msk (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) /**< (CMCC_TYPE) Lock Down supported Mask */ +#define CMCC_TYPE_LCKDOWN(value) (CMCC_TYPE_LCKDOWN_Msk & ((value) << CMCC_TYPE_LCKDOWN_Pos)) +#define CMCC_TYPE_CSIZE_Pos _U_(8) /**< (CMCC_TYPE) Cache Size Position */ +#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size Mask */ +#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) +#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< (CMCC_TYPE) Cache Size is 1 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< (CMCC_TYPE) Cache Size is 2 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< (CMCC_TYPE) Cache Size is 4 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< (CMCC_TYPE) Cache Size is 8 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< (CMCC_TYPE) Cache Size is 16 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< (CMCC_TYPE) Cache Size is 32 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< (CMCC_TYPE) Cache Size is 64 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 1 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 2 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 4 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 8 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 16 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 32 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 64 KB Position */ +#define CMCC_TYPE_CLSIZE_Pos _U_(11) /**< (CMCC_TYPE) Cache Line Size Position */ +#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size Mask */ +#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) +#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< (CMCC_TYPE) Cache Line Size is 4 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< (CMCC_TYPE) Cache Line Size is 8 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< (CMCC_TYPE) Cache Line Size is 16 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< (CMCC_TYPE) Cache Line Size is 32 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< (CMCC_TYPE) Cache Line Size is 64 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< (CMCC_TYPE) Cache Line Size is 128 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 4 bytes Position */ +#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 8 bytes Position */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 16 bytes Position */ +#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 32 bytes Position */ +#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 64 bytes Position */ +#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 128 bytes Position */ +#define CMCC_TYPE_Msk _U_(0x00003FF2) /**< (CMCC_TYPE) Register Mask */ + + +/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ +#define CMCC_CFG_RESETVALUE _U_(0x20) /**< (CMCC_CFG) Cache Configuration Register Reset Value */ + +#define CMCC_CFG_ICDIS_Pos _U_(1) /**< (CMCC_CFG) Instruction Cache Disable Position */ +#define CMCC_CFG_ICDIS_Msk (_U_(0x1) << CMCC_CFG_ICDIS_Pos) /**< (CMCC_CFG) Instruction Cache Disable Mask */ +#define CMCC_CFG_ICDIS(value) (CMCC_CFG_ICDIS_Msk & ((value) << CMCC_CFG_ICDIS_Pos)) +#define CMCC_CFG_DCDIS_Pos _U_(2) /**< (CMCC_CFG) Data Cache Disable Position */ +#define CMCC_CFG_DCDIS_Msk (_U_(0x1) << CMCC_CFG_DCDIS_Pos) /**< (CMCC_CFG) Data Cache Disable Mask */ +#define CMCC_CFG_DCDIS(value) (CMCC_CFG_DCDIS_Msk & ((value) << CMCC_CFG_DCDIS_Pos)) +#define CMCC_CFG_CSIZESW_Pos _U_(4) /**< (CMCC_CFG) Cache size configured by software Position */ +#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) Cache size configured by software Mask */ +#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< (CMCC_CFG) The Cache Size is configured to 1KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< (CMCC_CFG) The Cache Size is configured to 2KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< (CMCC_CFG) The Cache Size is configured to 4KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< (CMCC_CFG) The Cache Size is configured to 8KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< (CMCC_CFG) The Cache Size is configured to 16KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< (CMCC_CFG) The Cache Size is configured to 32KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< (CMCC_CFG) The Cache Size is configured to 64KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 1KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 2KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 4KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 8KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 16KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 32KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 64KB Position */ +#define CMCC_CFG_Msk _U_(0x00000076) /**< (CMCC_CFG) Register Mask */ + + +/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ +#define CMCC_CTRL_RESETVALUE _U_(0x00) /**< (CMCC_CTRL) Cache Control Register Reset Value */ + +#define CMCC_CTRL_CEN_Pos _U_(0) /**< (CMCC_CTRL) Cache Controller Enable Position */ +#define CMCC_CTRL_CEN_Msk (_U_(0x1) << CMCC_CTRL_CEN_Pos) /**< (CMCC_CTRL) Cache Controller Enable Mask */ +#define CMCC_CTRL_CEN(value) (CMCC_CTRL_CEN_Msk & ((value) << CMCC_CTRL_CEN_Pos)) +#define CMCC_CTRL_Msk _U_(0x00000001) /**< (CMCC_CTRL) Register Mask */ + + +/* -------- CMCC_SR : (CMCC Offset: 0x0C) ( R/ 32) Cache Status Register -------- */ +#define CMCC_SR_RESETVALUE _U_(0x00) /**< (CMCC_SR) Cache Status Register Reset Value */ + +#define CMCC_SR_CSTS_Pos _U_(0) /**< (CMCC_SR) Cache Controller Status Position */ +#define CMCC_SR_CSTS_Msk (_U_(0x1) << CMCC_SR_CSTS_Pos) /**< (CMCC_SR) Cache Controller Status Mask */ +#define CMCC_SR_CSTS(value) (CMCC_SR_CSTS_Msk & ((value) << CMCC_SR_CSTS_Pos)) +#define CMCC_SR_Msk _U_(0x00000001) /**< (CMCC_SR) Register Mask */ + + +/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ +#define CMCC_LCKWAY_RESETVALUE _U_(0x00) /**< (CMCC_LCKWAY) Cache Lock per Way Register Reset Value */ + +#define CMCC_LCKWAY_LCKWAY_Pos _U_(0) /**< (CMCC_LCKWAY) Lockdown way Register Position */ +#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) /**< (CMCC_LCKWAY) Lockdown way Register Mask */ +#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) +#define CMCC_LCKWAY_Msk _U_(0x0000000F) /**< (CMCC_LCKWAY) Register Mask */ + + +/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ +#define CMCC_MAINT0_RESETVALUE _U_(0x00) /**< (CMCC_MAINT0) Cache Maintenance Register 0 Reset Value */ + +#define CMCC_MAINT0_INVALL_Pos _U_(0) /**< (CMCC_MAINT0) Cache Controller invalidate All Position */ +#define CMCC_MAINT0_INVALL_Msk (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) /**< (CMCC_MAINT0) Cache Controller invalidate All Mask */ +#define CMCC_MAINT0_INVALL(value) (CMCC_MAINT0_INVALL_Msk & ((value) << CMCC_MAINT0_INVALL_Pos)) +#define CMCC_MAINT0_Msk _U_(0x00000001) /**< (CMCC_MAINT0) Register Mask */ + + +/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ +#define CMCC_MAINT1_RESETVALUE _U_(0x00) /**< (CMCC_MAINT1) Cache Maintenance Register 1 Reset Value */ + +#define CMCC_MAINT1_INDEX_Pos _U_(4) /**< (CMCC_MAINT1) Invalidate Index Position */ +#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) /**< (CMCC_MAINT1) Invalidate Index Mask */ +#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) +#define CMCC_MAINT1_WAY_Pos _U_(28) /**< (CMCC_MAINT1) Invalidate Way Position */ +#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Invalidate Way Mask */ +#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) +#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< (CMCC_MAINT1) Way 0 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< (CMCC_MAINT1) Way 1 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< (CMCC_MAINT1) Way 2 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< (CMCC_MAINT1) Way 3 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 0 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 1 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 2 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 3 is selection for index invalidation Position */ +#define CMCC_MAINT1_Msk _U_(0xF0000FF0) /**< (CMCC_MAINT1) Register Mask */ + + +/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ +#define CMCC_MCFG_RESETVALUE _U_(0x00) /**< (CMCC_MCFG) Cache Monitor Configuration Register Reset Value */ + +#define CMCC_MCFG_MODE_Pos _U_(0) /**< (CMCC_MCFG) Cache Controller Monitor Counter Mode Position */ +#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Cache Controller Monitor Counter Mode Mask */ +#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) +#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< (CMCC_MCFG) Cycle counter */ +#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< (CMCC_MCFG) Instruction hit counter */ +#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< (CMCC_MCFG) Data hit counter */ +#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Cycle counter Position */ +#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Instruction hit counter Position */ +#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Data hit counter Position */ +#define CMCC_MCFG_Msk _U_(0x00000003) /**< (CMCC_MCFG) Register Mask */ + + +/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ +#define CMCC_MEN_RESETVALUE _U_(0x00) /**< (CMCC_MEN) Cache Monitor Enable Register Reset Value */ + +#define CMCC_MEN_MENABLE_Pos _U_(0) /**< (CMCC_MEN) Cache Controller Monitor Enable Position */ +#define CMCC_MEN_MENABLE_Msk (_U_(0x1) << CMCC_MEN_MENABLE_Pos) /**< (CMCC_MEN) Cache Controller Monitor Enable Mask */ +#define CMCC_MEN_MENABLE(value) (CMCC_MEN_MENABLE_Msk & ((value) << CMCC_MEN_MENABLE_Pos)) +#define CMCC_MEN_Msk _U_(0x00000001) /**< (CMCC_MEN) Register Mask */ + + +/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ +#define CMCC_MCTRL_RESETVALUE _U_(0x00) /**< (CMCC_MCTRL) Cache Monitor Control Register Reset Value */ + +#define CMCC_MCTRL_SWRST_Pos _U_(0) /**< (CMCC_MCTRL) Cache Controller Software Reset Position */ +#define CMCC_MCTRL_SWRST_Msk (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) /**< (CMCC_MCTRL) Cache Controller Software Reset Mask */ +#define CMCC_MCTRL_SWRST(value) (CMCC_MCTRL_SWRST_Msk & ((value) << CMCC_MCTRL_SWRST_Pos)) +#define CMCC_MCTRL_Msk _U_(0x00000001) /**< (CMCC_MCTRL) Register Mask */ + + +/* -------- CMCC_MSR : (CMCC Offset: 0x34) ( R/ 32) Cache Monitor Status Register -------- */ +#define CMCC_MSR_RESETVALUE _U_(0x00) /**< (CMCC_MSR) Cache Monitor Status Register Reset Value */ + +#define CMCC_MSR_EVENT_CNT_Pos _U_(0) /**< (CMCC_MSR) Monitor Event Counter Position */ +#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) /**< (CMCC_MSR) Monitor Event Counter Mask */ +#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) +#define CMCC_MSR_Msk _U_(0xFFFFFFFF) /**< (CMCC_MSR) Register Mask */ + + +/** \brief CMCC register offsets definitions */ +#define CMCC_TYPE_REG_OFST (0x00) /**< (CMCC_TYPE) Cache Type Register Offset */ +#define CMCC_CFG_REG_OFST (0x04) /**< (CMCC_CFG) Cache Configuration Register Offset */ +#define CMCC_CTRL_REG_OFST (0x08) /**< (CMCC_CTRL) Cache Control Register Offset */ +#define CMCC_SR_REG_OFST (0x0C) /**< (CMCC_SR) Cache Status Register Offset */ +#define CMCC_LCKWAY_REG_OFST (0x10) /**< (CMCC_LCKWAY) Cache Lock per Way Register Offset */ +#define CMCC_MAINT0_REG_OFST (0x20) /**< (CMCC_MAINT0) Cache Maintenance Register 0 Offset */ +#define CMCC_MAINT1_REG_OFST (0x24) /**< (CMCC_MAINT1) Cache Maintenance Register 1 Offset */ +#define CMCC_MCFG_REG_OFST (0x28) /**< (CMCC_MCFG) Cache Monitor Configuration Register Offset */ +#define CMCC_MEN_REG_OFST (0x2C) /**< (CMCC_MEN) Cache Monitor Enable Register Offset */ +#define CMCC_MCTRL_REG_OFST (0x30) /**< (CMCC_MCTRL) Cache Monitor Control Register Offset */ +#define CMCC_MSR_REG_OFST (0x34) /**< (CMCC_MSR) Cache Monitor Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CMCC register API structure */ +typedef struct +{ /* Cortex M Cache Controller */ + __I uint32_t CMCC_TYPE; /**< Offset: 0x00 (R/ 32) Cache Type Register */ + __IO uint32_t CMCC_CFG; /**< Offset: 0x04 (R/W 32) Cache Configuration Register */ + __O uint32_t CMCC_CTRL; /**< Offset: 0x08 ( /W 32) Cache Control Register */ + __I uint32_t CMCC_SR; /**< Offset: 0x0C (R/ 32) Cache Status Register */ + __IO uint32_t CMCC_LCKWAY; /**< Offset: 0x10 (R/W 32) Cache Lock per Way Register */ + __I uint8_t Reserved1[0x0C]; + __O uint32_t CMCC_MAINT0; /**< Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ + __O uint32_t CMCC_MAINT1; /**< Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ + __IO uint32_t CMCC_MCFG; /**< Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ + __IO uint32_t CMCC_MEN; /**< Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ + __O uint32_t CMCC_MCTRL; /**< Offset: 0x30 ( /W 32) Cache Monitor Control Register */ + __I uint32_t CMCC_MSR; /**< Offset: 0x34 (R/ 32) Cache Monitor Status Register */ +} cmcc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMD51_CMCC_COMPONENT_H_ */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/component/dac.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/dac.h new file mode 100644 index 00000000..740fe7af --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/dac.h @@ -0,0 +1,439 @@ +/** + * \brief Component description for DAC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:45:00Z */ +#ifndef _SAMD51_DAC_COMPONENT_H_ +#define _SAMD51_DAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DAC */ +/* ************************************************************************** */ + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< (DAC_CTRLA) Control A Reset Value */ + +#define DAC_CTRLA_SWRST_Pos _U_(0) /**< (DAC_CTRLA) Software Reset Position */ +#define DAC_CTRLA_SWRST_Msk (_U_(0x1) << DAC_CTRLA_SWRST_Pos) /**< (DAC_CTRLA) Software Reset Mask */ +#define DAC_CTRLA_SWRST(value) (DAC_CTRLA_SWRST_Msk & ((value) << DAC_CTRLA_SWRST_Pos)) +#define DAC_CTRLA_ENABLE_Pos _U_(1) /**< (DAC_CTRLA) Enable DAC Controller Position */ +#define DAC_CTRLA_ENABLE_Msk (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) /**< (DAC_CTRLA) Enable DAC Controller Mask */ +#define DAC_CTRLA_ENABLE(value) (DAC_CTRLA_ENABLE_Msk & ((value) << DAC_CTRLA_ENABLE_Pos)) +#define DAC_CTRLA_Msk _U_(0x03) /**< (DAC_CTRLA) Register Mask */ + + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< (DAC_CTRLB) Control B Reset Value */ + +#define DAC_CTRLB_DIFF_Pos _U_(0) /**< (DAC_CTRLB) Differential mode enable Position */ +#define DAC_CTRLB_DIFF_Msk (_U_(0x1) << DAC_CTRLB_DIFF_Pos) /**< (DAC_CTRLB) Differential mode enable Mask */ +#define DAC_CTRLB_DIFF(value) (DAC_CTRLB_DIFF_Msk & ((value) << DAC_CTRLB_DIFF_Pos)) +#define DAC_CTRLB_REFSEL_Pos _U_(1) /**< (DAC_CTRLB) Reference Selection for DAC0/1 Position */ +#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Reference Selection for DAC0/1 Mask */ +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< (DAC_CTRLB) External reference unbuffered */ +#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< (DAC_CTRLB) Analog supply */ +#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< (DAC_CTRLB) External reference buffered */ +#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< (DAC_CTRLB) Internal bandgap reference */ +#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) External reference unbuffered Position */ +#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Analog supply Position */ +#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) External reference buffered Position */ +#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Internal bandgap reference Position */ +#define DAC_CTRLB_Msk _U_(0x07) /**< (DAC_CTRLB) Register Mask */ + + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< (DAC_EVCTRL) Event Control Reset Value */ + +#define DAC_EVCTRL_STARTEI0_Pos _U_(0) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 0 Position */ +#define DAC_EVCTRL_STARTEI0_Msk (_U_(0x1) << DAC_EVCTRL_STARTEI0_Pos) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 0 Mask */ +#define DAC_EVCTRL_STARTEI0(value) (DAC_EVCTRL_STARTEI0_Msk & ((value) << DAC_EVCTRL_STARTEI0_Pos)) +#define DAC_EVCTRL_STARTEI1_Pos _U_(1) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 1 Position */ +#define DAC_EVCTRL_STARTEI1_Msk (_U_(0x1) << DAC_EVCTRL_STARTEI1_Pos) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 1 Mask */ +#define DAC_EVCTRL_STARTEI1(value) (DAC_EVCTRL_STARTEI1_Msk & ((value) << DAC_EVCTRL_STARTEI1_Pos)) +#define DAC_EVCTRL_EMPTYEO0_Pos _U_(2) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Position */ +#define DAC_EVCTRL_EMPTYEO0_Msk (_U_(0x1) << DAC_EVCTRL_EMPTYEO0_Pos) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Mask */ +#define DAC_EVCTRL_EMPTYEO0(value) (DAC_EVCTRL_EMPTYEO0_Msk & ((value) << DAC_EVCTRL_EMPTYEO0_Pos)) +#define DAC_EVCTRL_EMPTYEO1_Pos _U_(3) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Position */ +#define DAC_EVCTRL_EMPTYEO1_Msk (_U_(0x1) << DAC_EVCTRL_EMPTYEO1_Pos) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Mask */ +#define DAC_EVCTRL_EMPTYEO1(value) (DAC_EVCTRL_EMPTYEO1_Msk & ((value) << DAC_EVCTRL_EMPTYEO1_Pos)) +#define DAC_EVCTRL_INVEI0_Pos _U_(4) /**< (DAC_EVCTRL) Enable Invertion of DAC 0 input event Position */ +#define DAC_EVCTRL_INVEI0_Msk (_U_(0x1) << DAC_EVCTRL_INVEI0_Pos) /**< (DAC_EVCTRL) Enable Invertion of DAC 0 input event Mask */ +#define DAC_EVCTRL_INVEI0(value) (DAC_EVCTRL_INVEI0_Msk & ((value) << DAC_EVCTRL_INVEI0_Pos)) +#define DAC_EVCTRL_INVEI1_Pos _U_(5) /**< (DAC_EVCTRL) Enable Invertion of DAC 1 input event Position */ +#define DAC_EVCTRL_INVEI1_Msk (_U_(0x1) << DAC_EVCTRL_INVEI1_Pos) /**< (DAC_EVCTRL) Enable Invertion of DAC 1 input event Mask */ +#define DAC_EVCTRL_INVEI1(value) (DAC_EVCTRL_INVEI1_Msk & ((value) << DAC_EVCTRL_INVEI1_Pos)) +#define DAC_EVCTRL_RESRDYEO0_Pos _U_(6) /**< (DAC_EVCTRL) Result Ready Event Output 0 Position */ +#define DAC_EVCTRL_RESRDYEO0_Msk (_U_(0x1) << DAC_EVCTRL_RESRDYEO0_Pos) /**< (DAC_EVCTRL) Result Ready Event Output 0 Mask */ +#define DAC_EVCTRL_RESRDYEO0(value) (DAC_EVCTRL_RESRDYEO0_Msk & ((value) << DAC_EVCTRL_RESRDYEO0_Pos)) +#define DAC_EVCTRL_RESRDYEO1_Pos _U_(7) /**< (DAC_EVCTRL) Result Ready Event Output 1 Position */ +#define DAC_EVCTRL_RESRDYEO1_Msk (_U_(0x1) << DAC_EVCTRL_RESRDYEO1_Pos) /**< (DAC_EVCTRL) Result Ready Event Output 1 Mask */ +#define DAC_EVCTRL_RESRDYEO1(value) (DAC_EVCTRL_RESRDYEO1_Msk & ((value) << DAC_EVCTRL_RESRDYEO1_Pos)) +#define DAC_EVCTRL_Msk _U_(0xFF) /**< (DAC_EVCTRL) Register Mask */ + +#define DAC_EVCTRL_STARTEI_Pos _U_(0) /**< (DAC_EVCTRL Position) Start Conversion Event Input DAC x */ +#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) /**< (DAC_EVCTRL Mask) STARTEI */ +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) +#define DAC_EVCTRL_EMPTYEO_Pos _U_(2) /**< (DAC_EVCTRL Position) Data Buffer Empty Event Output DAC x */ +#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) /**< (DAC_EVCTRL Mask) EMPTYEO */ +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) +#define DAC_EVCTRL_INVEI_Pos _U_(4) /**< (DAC_EVCTRL Position) Enable Invertion of DAC x input event */ +#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) /**< (DAC_EVCTRL Mask) INVEI */ +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) +#define DAC_EVCTRL_RESRDYEO_Pos _U_(6) /**< (DAC_EVCTRL Position) Result Ready Event Output x */ +#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) /**< (DAC_EVCTRL Mask) RESRDYEO */ +#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< (DAC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define DAC_INTENCLR_UNDERRUN0_Pos _U_(0) /**< (DAC_INTENCLR) Underrun 0 Interrupt Enable Position */ +#define DAC_INTENCLR_UNDERRUN0_Msk (_U_(0x1) << DAC_INTENCLR_UNDERRUN0_Pos) /**< (DAC_INTENCLR) Underrun 0 Interrupt Enable Mask */ +#define DAC_INTENCLR_UNDERRUN0(value) (DAC_INTENCLR_UNDERRUN0_Msk & ((value) << DAC_INTENCLR_UNDERRUN0_Pos)) +#define DAC_INTENCLR_UNDERRUN1_Pos _U_(1) /**< (DAC_INTENCLR) Underrun 1 Interrupt Enable Position */ +#define DAC_INTENCLR_UNDERRUN1_Msk (_U_(0x1) << DAC_INTENCLR_UNDERRUN1_Pos) /**< (DAC_INTENCLR) Underrun 1 Interrupt Enable Mask */ +#define DAC_INTENCLR_UNDERRUN1(value) (DAC_INTENCLR_UNDERRUN1_Msk & ((value) << DAC_INTENCLR_UNDERRUN1_Pos)) +#define DAC_INTENCLR_EMPTY0_Pos _U_(2) /**< (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Position */ +#define DAC_INTENCLR_EMPTY0_Msk (_U_(0x1) << DAC_INTENCLR_EMPTY0_Pos) /**< (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Mask */ +#define DAC_INTENCLR_EMPTY0(value) (DAC_INTENCLR_EMPTY0_Msk & ((value) << DAC_INTENCLR_EMPTY0_Pos)) +#define DAC_INTENCLR_EMPTY1_Pos _U_(3) /**< (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Position */ +#define DAC_INTENCLR_EMPTY1_Msk (_U_(0x1) << DAC_INTENCLR_EMPTY1_Pos) /**< (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Mask */ +#define DAC_INTENCLR_EMPTY1(value) (DAC_INTENCLR_EMPTY1_Msk & ((value) << DAC_INTENCLR_EMPTY1_Pos)) +#define DAC_INTENCLR_RESRDY0_Pos _U_(4) /**< (DAC_INTENCLR) Result 0 Ready Interrupt Enable Position */ +#define DAC_INTENCLR_RESRDY0_Msk (_U_(0x1) << DAC_INTENCLR_RESRDY0_Pos) /**< (DAC_INTENCLR) Result 0 Ready Interrupt Enable Mask */ +#define DAC_INTENCLR_RESRDY0(value) (DAC_INTENCLR_RESRDY0_Msk & ((value) << DAC_INTENCLR_RESRDY0_Pos)) +#define DAC_INTENCLR_RESRDY1_Pos _U_(5) /**< (DAC_INTENCLR) Result 1 Ready Interrupt Enable Position */ +#define DAC_INTENCLR_RESRDY1_Msk (_U_(0x1) << DAC_INTENCLR_RESRDY1_Pos) /**< (DAC_INTENCLR) Result 1 Ready Interrupt Enable Mask */ +#define DAC_INTENCLR_RESRDY1(value) (DAC_INTENCLR_RESRDY1_Msk & ((value) << DAC_INTENCLR_RESRDY1_Pos)) +#define DAC_INTENCLR_OVERRUN0_Pos _U_(6) /**< (DAC_INTENCLR) Overrun 0 Interrupt Enable Position */ +#define DAC_INTENCLR_OVERRUN0_Msk (_U_(0x1) << DAC_INTENCLR_OVERRUN0_Pos) /**< (DAC_INTENCLR) Overrun 0 Interrupt Enable Mask */ +#define DAC_INTENCLR_OVERRUN0(value) (DAC_INTENCLR_OVERRUN0_Msk & ((value) << DAC_INTENCLR_OVERRUN0_Pos)) +#define DAC_INTENCLR_OVERRUN1_Pos _U_(7) /**< (DAC_INTENCLR) Overrun 1 Interrupt Enable Position */ +#define DAC_INTENCLR_OVERRUN1_Msk (_U_(0x1) << DAC_INTENCLR_OVERRUN1_Pos) /**< (DAC_INTENCLR) Overrun 1 Interrupt Enable Mask */ +#define DAC_INTENCLR_OVERRUN1(value) (DAC_INTENCLR_OVERRUN1_Msk & ((value) << DAC_INTENCLR_OVERRUN1_Pos)) +#define DAC_INTENCLR_Msk _U_(0xFF) /**< (DAC_INTENCLR) Register Mask */ + +#define DAC_INTENCLR_UNDERRUN_Pos _U_(0) /**< (DAC_INTENCLR Position) Underrun x Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) /**< (DAC_INTENCLR Mask) UNDERRUN */ +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) +#define DAC_INTENCLR_EMPTY_Pos _U_(2) /**< (DAC_INTENCLR Position) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) /**< (DAC_INTENCLR Mask) EMPTY */ +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) +#define DAC_INTENCLR_RESRDY_Pos _U_(4) /**< (DAC_INTENCLR Position) Result x Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) /**< (DAC_INTENCLR Mask) RESRDY */ +#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) +#define DAC_INTENCLR_OVERRUN_Pos _U_(6) /**< (DAC_INTENCLR Position) Overrun x Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) /**< (DAC_INTENCLR Mask) OVERRUN */ +#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< (DAC_INTENSET) Interrupt Enable Set Reset Value */ + +#define DAC_INTENSET_UNDERRUN0_Pos _U_(0) /**< (DAC_INTENSET) Underrun 0 Interrupt Enable Position */ +#define DAC_INTENSET_UNDERRUN0_Msk (_U_(0x1) << DAC_INTENSET_UNDERRUN0_Pos) /**< (DAC_INTENSET) Underrun 0 Interrupt Enable Mask */ +#define DAC_INTENSET_UNDERRUN0(value) (DAC_INTENSET_UNDERRUN0_Msk & ((value) << DAC_INTENSET_UNDERRUN0_Pos)) +#define DAC_INTENSET_UNDERRUN1_Pos _U_(1) /**< (DAC_INTENSET) Underrun 1 Interrupt Enable Position */ +#define DAC_INTENSET_UNDERRUN1_Msk (_U_(0x1) << DAC_INTENSET_UNDERRUN1_Pos) /**< (DAC_INTENSET) Underrun 1 Interrupt Enable Mask */ +#define DAC_INTENSET_UNDERRUN1(value) (DAC_INTENSET_UNDERRUN1_Msk & ((value) << DAC_INTENSET_UNDERRUN1_Pos)) +#define DAC_INTENSET_EMPTY0_Pos _U_(2) /**< (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Position */ +#define DAC_INTENSET_EMPTY0_Msk (_U_(0x1) << DAC_INTENSET_EMPTY0_Pos) /**< (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Mask */ +#define DAC_INTENSET_EMPTY0(value) (DAC_INTENSET_EMPTY0_Msk & ((value) << DAC_INTENSET_EMPTY0_Pos)) +#define DAC_INTENSET_EMPTY1_Pos _U_(3) /**< (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Position */ +#define DAC_INTENSET_EMPTY1_Msk (_U_(0x1) << DAC_INTENSET_EMPTY1_Pos) /**< (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Mask */ +#define DAC_INTENSET_EMPTY1(value) (DAC_INTENSET_EMPTY1_Msk & ((value) << DAC_INTENSET_EMPTY1_Pos)) +#define DAC_INTENSET_RESRDY0_Pos _U_(4) /**< (DAC_INTENSET) Result 0 Ready Interrupt Enable Position */ +#define DAC_INTENSET_RESRDY0_Msk (_U_(0x1) << DAC_INTENSET_RESRDY0_Pos) /**< (DAC_INTENSET) Result 0 Ready Interrupt Enable Mask */ +#define DAC_INTENSET_RESRDY0(value) (DAC_INTENSET_RESRDY0_Msk & ((value) << DAC_INTENSET_RESRDY0_Pos)) +#define DAC_INTENSET_RESRDY1_Pos _U_(5) /**< (DAC_INTENSET) Result 1 Ready Interrupt Enable Position */ +#define DAC_INTENSET_RESRDY1_Msk (_U_(0x1) << DAC_INTENSET_RESRDY1_Pos) /**< (DAC_INTENSET) Result 1 Ready Interrupt Enable Mask */ +#define DAC_INTENSET_RESRDY1(value) (DAC_INTENSET_RESRDY1_Msk & ((value) << DAC_INTENSET_RESRDY1_Pos)) +#define DAC_INTENSET_OVERRUN0_Pos _U_(6) /**< (DAC_INTENSET) Overrun 0 Interrupt Enable Position */ +#define DAC_INTENSET_OVERRUN0_Msk (_U_(0x1) << DAC_INTENSET_OVERRUN0_Pos) /**< (DAC_INTENSET) Overrun 0 Interrupt Enable Mask */ +#define DAC_INTENSET_OVERRUN0(value) (DAC_INTENSET_OVERRUN0_Msk & ((value) << DAC_INTENSET_OVERRUN0_Pos)) +#define DAC_INTENSET_OVERRUN1_Pos _U_(7) /**< (DAC_INTENSET) Overrun 1 Interrupt Enable Position */ +#define DAC_INTENSET_OVERRUN1_Msk (_U_(0x1) << DAC_INTENSET_OVERRUN1_Pos) /**< (DAC_INTENSET) Overrun 1 Interrupt Enable Mask */ +#define DAC_INTENSET_OVERRUN1(value) (DAC_INTENSET_OVERRUN1_Msk & ((value) << DAC_INTENSET_OVERRUN1_Pos)) +#define DAC_INTENSET_Msk _U_(0xFF) /**< (DAC_INTENSET) Register Mask */ + +#define DAC_INTENSET_UNDERRUN_Pos _U_(0) /**< (DAC_INTENSET Position) Underrun x Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) /**< (DAC_INTENSET Mask) UNDERRUN */ +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) +#define DAC_INTENSET_EMPTY_Pos _U_(2) /**< (DAC_INTENSET Position) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) /**< (DAC_INTENSET Mask) EMPTY */ +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) +#define DAC_INTENSET_RESRDY_Pos _U_(4) /**< (DAC_INTENSET Position) Result x Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) /**< (DAC_INTENSET Mask) RESRDY */ +#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) +#define DAC_INTENSET_OVERRUN_Pos _U_(6) /**< (DAC_INTENSET Position) Overrun x Interrupt Enable */ +#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) /**< (DAC_INTENSET Mask) OVERRUN */ +#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< (DAC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define DAC_INTFLAG_UNDERRUN0_Pos _U_(0) /**< (DAC_INTFLAG) Result 0 Underrun Position */ +#define DAC_INTFLAG_UNDERRUN0_Msk (_U_(0x1) << DAC_INTFLAG_UNDERRUN0_Pos) /**< (DAC_INTFLAG) Result 0 Underrun Mask */ +#define DAC_INTFLAG_UNDERRUN0(value) (DAC_INTFLAG_UNDERRUN0_Msk & ((value) << DAC_INTFLAG_UNDERRUN0_Pos)) +#define DAC_INTFLAG_UNDERRUN1_Pos _U_(1) /**< (DAC_INTFLAG) Result 1 Underrun Position */ +#define DAC_INTFLAG_UNDERRUN1_Msk (_U_(0x1) << DAC_INTFLAG_UNDERRUN1_Pos) /**< (DAC_INTFLAG) Result 1 Underrun Mask */ +#define DAC_INTFLAG_UNDERRUN1(value) (DAC_INTFLAG_UNDERRUN1_Msk & ((value) << DAC_INTFLAG_UNDERRUN1_Pos)) +#define DAC_INTFLAG_EMPTY0_Pos _U_(2) /**< (DAC_INTFLAG) Data Buffer 0 Empty Position */ +#define DAC_INTFLAG_EMPTY0_Msk (_U_(0x1) << DAC_INTFLAG_EMPTY0_Pos) /**< (DAC_INTFLAG) Data Buffer 0 Empty Mask */ +#define DAC_INTFLAG_EMPTY0(value) (DAC_INTFLAG_EMPTY0_Msk & ((value) << DAC_INTFLAG_EMPTY0_Pos)) +#define DAC_INTFLAG_EMPTY1_Pos _U_(3) /**< (DAC_INTFLAG) Data Buffer 1 Empty Position */ +#define DAC_INTFLAG_EMPTY1_Msk (_U_(0x1) << DAC_INTFLAG_EMPTY1_Pos) /**< (DAC_INTFLAG) Data Buffer 1 Empty Mask */ +#define DAC_INTFLAG_EMPTY1(value) (DAC_INTFLAG_EMPTY1_Msk & ((value) << DAC_INTFLAG_EMPTY1_Pos)) +#define DAC_INTFLAG_RESRDY0_Pos _U_(4) /**< (DAC_INTFLAG) Result 0 Ready Position */ +#define DAC_INTFLAG_RESRDY0_Msk (_U_(0x1) << DAC_INTFLAG_RESRDY0_Pos) /**< (DAC_INTFLAG) Result 0 Ready Mask */ +#define DAC_INTFLAG_RESRDY0(value) (DAC_INTFLAG_RESRDY0_Msk & ((value) << DAC_INTFLAG_RESRDY0_Pos)) +#define DAC_INTFLAG_RESRDY1_Pos _U_(5) /**< (DAC_INTFLAG) Result 1 Ready Position */ +#define DAC_INTFLAG_RESRDY1_Msk (_U_(0x1) << DAC_INTFLAG_RESRDY1_Pos) /**< (DAC_INTFLAG) Result 1 Ready Mask */ +#define DAC_INTFLAG_RESRDY1(value) (DAC_INTFLAG_RESRDY1_Msk & ((value) << DAC_INTFLAG_RESRDY1_Pos)) +#define DAC_INTFLAG_OVERRUN0_Pos _U_(6) /**< (DAC_INTFLAG) Result 0 Overrun Position */ +#define DAC_INTFLAG_OVERRUN0_Msk (_U_(0x1) << DAC_INTFLAG_OVERRUN0_Pos) /**< (DAC_INTFLAG) Result 0 Overrun Mask */ +#define DAC_INTFLAG_OVERRUN0(value) (DAC_INTFLAG_OVERRUN0_Msk & ((value) << DAC_INTFLAG_OVERRUN0_Pos)) +#define DAC_INTFLAG_OVERRUN1_Pos _U_(7) /**< (DAC_INTFLAG) Result 1 Overrun Position */ +#define DAC_INTFLAG_OVERRUN1_Msk (_U_(0x1) << DAC_INTFLAG_OVERRUN1_Pos) /**< (DAC_INTFLAG) Result 1 Overrun Mask */ +#define DAC_INTFLAG_OVERRUN1(value) (DAC_INTFLAG_OVERRUN1_Msk & ((value) << DAC_INTFLAG_OVERRUN1_Pos)) +#define DAC_INTFLAG_Msk _U_(0xFF) /**< (DAC_INTFLAG) Register Mask */ + +#define DAC_INTFLAG_UNDERRUN_Pos _U_(0) /**< (DAC_INTFLAG Position) Result x Underrun */ +#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) /**< (DAC_INTFLAG Mask) UNDERRUN */ +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) +#define DAC_INTFLAG_EMPTY_Pos _U_(2) /**< (DAC_INTFLAG Position) Data Buffer x Empty */ +#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) /**< (DAC_INTFLAG Mask) EMPTY */ +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) +#define DAC_INTFLAG_RESRDY_Pos _U_(4) /**< (DAC_INTFLAG Position) Result x Ready */ +#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) /**< (DAC_INTFLAG Mask) RESRDY */ +#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) +#define DAC_INTFLAG_OVERRUN_Pos _U_(6) /**< (DAC_INTFLAG Position) Result x Overrun */ +#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) /**< (DAC_INTFLAG Mask) OVERRUN */ +#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) + +/* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */ +#define DAC_STATUS_RESETVALUE _U_(0x00) /**< (DAC_STATUS) Status Reset Value */ + +#define DAC_STATUS_READY0_Pos _U_(0) /**< (DAC_STATUS) DAC 0 Startup Ready Position */ +#define DAC_STATUS_READY0_Msk (_U_(0x1) << DAC_STATUS_READY0_Pos) /**< (DAC_STATUS) DAC 0 Startup Ready Mask */ +#define DAC_STATUS_READY0(value) (DAC_STATUS_READY0_Msk & ((value) << DAC_STATUS_READY0_Pos)) +#define DAC_STATUS_READY1_Pos _U_(1) /**< (DAC_STATUS) DAC 1 Startup Ready Position */ +#define DAC_STATUS_READY1_Msk (_U_(0x1) << DAC_STATUS_READY1_Pos) /**< (DAC_STATUS) DAC 1 Startup Ready Mask */ +#define DAC_STATUS_READY1(value) (DAC_STATUS_READY1_Msk & ((value) << DAC_STATUS_READY1_Pos)) +#define DAC_STATUS_EOC0_Pos _U_(2) /**< (DAC_STATUS) DAC 0 End of Conversion Position */ +#define DAC_STATUS_EOC0_Msk (_U_(0x1) << DAC_STATUS_EOC0_Pos) /**< (DAC_STATUS) DAC 0 End of Conversion Mask */ +#define DAC_STATUS_EOC0(value) (DAC_STATUS_EOC0_Msk & ((value) << DAC_STATUS_EOC0_Pos)) +#define DAC_STATUS_EOC1_Pos _U_(3) /**< (DAC_STATUS) DAC 1 End of Conversion Position */ +#define DAC_STATUS_EOC1_Msk (_U_(0x1) << DAC_STATUS_EOC1_Pos) /**< (DAC_STATUS) DAC 1 End of Conversion Mask */ +#define DAC_STATUS_EOC1(value) (DAC_STATUS_EOC1_Msk & ((value) << DAC_STATUS_EOC1_Pos)) +#define DAC_STATUS_Msk _U_(0x0F) /**< (DAC_STATUS) Register Mask */ + +#define DAC_STATUS_READY_Pos _U_(0) /**< (DAC_STATUS Position) DAC x Startup Ready */ +#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) /**< (DAC_STATUS Mask) READY */ +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) +#define DAC_STATUS_EOC_Pos _U_(2) /**< (DAC_STATUS Position) DAC x End of Conversion */ +#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) /**< (DAC_STATUS Mask) EOC */ +#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) ( R/ 32) Synchronization Busy -------- */ +#define DAC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (DAC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define DAC_SYNCBUSY_SWRST_Pos _U_(0) /**< (DAC_SYNCBUSY) Software Reset Position */ +#define DAC_SYNCBUSY_SWRST_Msk (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) /**< (DAC_SYNCBUSY) Software Reset Mask */ +#define DAC_SYNCBUSY_SWRST(value) (DAC_SYNCBUSY_SWRST_Msk & ((value) << DAC_SYNCBUSY_SWRST_Pos)) +#define DAC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (DAC_SYNCBUSY) DAC Enable Status Position */ +#define DAC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) /**< (DAC_SYNCBUSY) DAC Enable Status Mask */ +#define DAC_SYNCBUSY_ENABLE(value) (DAC_SYNCBUSY_ENABLE_Msk & ((value) << DAC_SYNCBUSY_ENABLE_Pos)) +#define DAC_SYNCBUSY_DATA0_Pos _U_(2) /**< (DAC_SYNCBUSY) Data DAC 0 Position */ +#define DAC_SYNCBUSY_DATA0_Msk (_U_(0x1) << DAC_SYNCBUSY_DATA0_Pos) /**< (DAC_SYNCBUSY) Data DAC 0 Mask */ +#define DAC_SYNCBUSY_DATA0(value) (DAC_SYNCBUSY_DATA0_Msk & ((value) << DAC_SYNCBUSY_DATA0_Pos)) +#define DAC_SYNCBUSY_DATA1_Pos _U_(3) /**< (DAC_SYNCBUSY) Data DAC 1 Position */ +#define DAC_SYNCBUSY_DATA1_Msk (_U_(0x1) << DAC_SYNCBUSY_DATA1_Pos) /**< (DAC_SYNCBUSY) Data DAC 1 Mask */ +#define DAC_SYNCBUSY_DATA1(value) (DAC_SYNCBUSY_DATA1_Msk & ((value) << DAC_SYNCBUSY_DATA1_Pos)) +#define DAC_SYNCBUSY_DATABUF0_Pos _U_(4) /**< (DAC_SYNCBUSY) Data Buffer DAC 0 Position */ +#define DAC_SYNCBUSY_DATABUF0_Msk (_U_(0x1) << DAC_SYNCBUSY_DATABUF0_Pos) /**< (DAC_SYNCBUSY) Data Buffer DAC 0 Mask */ +#define DAC_SYNCBUSY_DATABUF0(value) (DAC_SYNCBUSY_DATABUF0_Msk & ((value) << DAC_SYNCBUSY_DATABUF0_Pos)) +#define DAC_SYNCBUSY_DATABUF1_Pos _U_(5) /**< (DAC_SYNCBUSY) Data Buffer DAC 1 Position */ +#define DAC_SYNCBUSY_DATABUF1_Msk (_U_(0x1) << DAC_SYNCBUSY_DATABUF1_Pos) /**< (DAC_SYNCBUSY) Data Buffer DAC 1 Mask */ +#define DAC_SYNCBUSY_DATABUF1(value) (DAC_SYNCBUSY_DATABUF1_Msk & ((value) << DAC_SYNCBUSY_DATABUF1_Pos)) +#define DAC_SYNCBUSY_Msk _U_(0x0000003F) /**< (DAC_SYNCBUSY) Register Mask */ + +#define DAC_SYNCBUSY_DATA_Pos _U_(2) /**< (DAC_SYNCBUSY Position) Data DAC x */ +#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) /**< (DAC_SYNCBUSY Mask) DATA */ +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) +#define DAC_SYNCBUSY_DATABUF_Pos _U_(4) /**< (DAC_SYNCBUSY Position) Data Buffer DAC x */ +#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) /**< (DAC_SYNCBUSY Mask) DATABUF */ +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) + +/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ +#define DAC_DACCTRL_RESETVALUE _U_(0x00) /**< (DAC_DACCTRL) DAC n Control Reset Value */ + +#define DAC_DACCTRL_LEFTADJ_Pos _U_(0) /**< (DAC_DACCTRL) Left Adjusted Data Position */ +#define DAC_DACCTRL_LEFTADJ_Msk (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) /**< (DAC_DACCTRL) Left Adjusted Data Mask */ +#define DAC_DACCTRL_LEFTADJ(value) (DAC_DACCTRL_LEFTADJ_Msk & ((value) << DAC_DACCTRL_LEFTADJ_Pos)) +#define DAC_DACCTRL_ENABLE_Pos _U_(1) /**< (DAC_DACCTRL) Enable DAC0 Position */ +#define DAC_DACCTRL_ENABLE_Msk (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) /**< (DAC_DACCTRL) Enable DAC0 Mask */ +#define DAC_DACCTRL_ENABLE(value) (DAC_DACCTRL_ENABLE_Msk & ((value) << DAC_DACCTRL_ENABLE_Pos)) +#define DAC_DACCTRL_CCTRL_Pos _U_(2) /**< (DAC_DACCTRL) Current Control Position */ +#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) Current Control Mask */ +#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) +#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< (DAC_DACCTRL) 100kSPS */ +#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< (DAC_DACCTRL) 500kSPS */ +#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< (DAC_DACCTRL) 1MSPS */ +#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 100kSPS Position */ +#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 500kSPS Position */ +#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 1MSPS Position */ +#define DAC_DACCTRL_FEXT_Pos _U_(5) /**< (DAC_DACCTRL) Standalone Filter Position */ +#define DAC_DACCTRL_FEXT_Msk (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) /**< (DAC_DACCTRL) Standalone Filter Mask */ +#define DAC_DACCTRL_FEXT(value) (DAC_DACCTRL_FEXT_Msk & ((value) << DAC_DACCTRL_FEXT_Pos)) +#define DAC_DACCTRL_RUNSTDBY_Pos _U_(6) /**< (DAC_DACCTRL) Run in Standby Position */ +#define DAC_DACCTRL_RUNSTDBY_Msk (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) /**< (DAC_DACCTRL) Run in Standby Mask */ +#define DAC_DACCTRL_RUNSTDBY(value) (DAC_DACCTRL_RUNSTDBY_Msk & ((value) << DAC_DACCTRL_RUNSTDBY_Pos)) +#define DAC_DACCTRL_DITHER_Pos _U_(7) /**< (DAC_DACCTRL) Dithering Mode Position */ +#define DAC_DACCTRL_DITHER_Msk (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) /**< (DAC_DACCTRL) Dithering Mode Mask */ +#define DAC_DACCTRL_DITHER(value) (DAC_DACCTRL_DITHER_Msk & ((value) << DAC_DACCTRL_DITHER_Pos)) +#define DAC_DACCTRL_REFRESH_Pos _U_(8) /**< (DAC_DACCTRL) Refresh period Position */ +#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh period Mask */ +#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) +#define DAC_DACCTRL_REFRESH_REFRESH_0_Val _U_(0x0) /**< (DAC_DACCTRL) Do not Refresh */ +#define DAC_DACCTRL_REFRESH_REFRESH_1_Val _U_(0x1) /**< (DAC_DACCTRL) Refresh every 30 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_2_Val _U_(0x2) /**< (DAC_DACCTRL) Refresh every 60 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_3_Val _U_(0x3) /**< (DAC_DACCTRL) Refresh every 90 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_4_Val _U_(0x4) /**< (DAC_DACCTRL) Refresh every 120 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_5_Val _U_(0x5) /**< (DAC_DACCTRL) Refresh every 150 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_6_Val _U_(0x6) /**< (DAC_DACCTRL) Refresh every 180 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_7_Val _U_(0x7) /**< (DAC_DACCTRL) Refresh every 210 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_8_Val _U_(0x8) /**< (DAC_DACCTRL) Refresh every 240 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_9_Val _U_(0x9) /**< (DAC_DACCTRL) Refresh every 270 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_10_Val _U_(0xA) /**< (DAC_DACCTRL) Refresh every 300 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_11_Val _U_(0xB) /**< (DAC_DACCTRL) Refresh every 330 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_12_Val _U_(0xC) /**< (DAC_DACCTRL) Refresh every 360 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_13_Val _U_(0xD) /**< (DAC_DACCTRL) Refresh every 390 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_14_Val _U_(0xE) /**< (DAC_DACCTRL) Refresh every 420 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_15_Val _U_(0xF) /**< (DAC_DACCTRL) Refresh every 450 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_0 (DAC_DACCTRL_REFRESH_REFRESH_0_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Do not Refresh Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_1 (DAC_DACCTRL_REFRESH_REFRESH_1_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 30 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_2 (DAC_DACCTRL_REFRESH_REFRESH_2_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 60 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_3 (DAC_DACCTRL_REFRESH_REFRESH_3_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 90 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_4 (DAC_DACCTRL_REFRESH_REFRESH_4_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 120 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_5 (DAC_DACCTRL_REFRESH_REFRESH_5_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 150 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_6 (DAC_DACCTRL_REFRESH_REFRESH_6_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 180 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_7 (DAC_DACCTRL_REFRESH_REFRESH_7_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 210 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_8 (DAC_DACCTRL_REFRESH_REFRESH_8_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 240 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_9 (DAC_DACCTRL_REFRESH_REFRESH_9_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 270 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_10 (DAC_DACCTRL_REFRESH_REFRESH_10_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 300 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_11 (DAC_DACCTRL_REFRESH_REFRESH_11_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 330 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_12 (DAC_DACCTRL_REFRESH_REFRESH_12_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 360 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_13 (DAC_DACCTRL_REFRESH_REFRESH_13_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 390 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_14 (DAC_DACCTRL_REFRESH_REFRESH_14_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 420 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_15 (DAC_DACCTRL_REFRESH_REFRESH_15_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 450 us Position */ +#define DAC_DACCTRL_OSR_Pos _U_(13) /**< (DAC_DACCTRL) Sampling Rate Position */ +#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) Sampling Rate Mask */ +#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) +#define DAC_DACCTRL_OSR_OSR_1_Val _U_(0x0) /**< (DAC_DACCTRL) No Over Sampling */ +#define DAC_DACCTRL_OSR_OSR_2_Val _U_(0x1) /**< (DAC_DACCTRL) 2x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_4_Val _U_(0x2) /**< (DAC_DACCTRL) 4x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_8_Val _U_(0x3) /**< (DAC_DACCTRL) 8x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_16_Val _U_(0x4) /**< (DAC_DACCTRL) 16x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_32_Val _U_(0x5) /**< (DAC_DACCTRL) 32x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_1 (DAC_DACCTRL_OSR_OSR_1_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) No Over Sampling Position */ +#define DAC_DACCTRL_OSR_OSR_2 (DAC_DACCTRL_OSR_OSR_2_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 2x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_4 (DAC_DACCTRL_OSR_OSR_4_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 4x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_8 (DAC_DACCTRL_OSR_OSR_8_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 8x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_16 (DAC_DACCTRL_OSR_OSR_16_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 16x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_32 (DAC_DACCTRL_OSR_OSR_32_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 32x Over Sampling Ratio Position */ +#define DAC_DACCTRL_Msk _U_(0xEFEF) /**< (DAC_DACCTRL) Register Mask */ + + +/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ +#define DAC_DATA_RESETVALUE _U_(0x00) /**< (DAC_DATA) DAC n Data Reset Value */ + +#define DAC_DATA_DATA_Pos _U_(0) /**< (DAC_DATA) DAC0 Data Position */ +#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) /**< (DAC_DATA) DAC0 Data Mask */ +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_Msk _U_(0xFFFF) /**< (DAC_DATA) Register Mask */ + + +/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ +#define DAC_DATABUF_RESETVALUE _U_(0x00) /**< (DAC_DATABUF) DAC n Data Buffer Reset Value */ + +#define DAC_DATABUF_DATABUF_Pos _U_(0) /**< (DAC_DATABUF) DAC0 Data Buffer Position */ +#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) /**< (DAC_DATABUF) DAC0 Data Buffer Mask */ +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_Msk _U_(0xFFFF) /**< (DAC_DATABUF) Register Mask */ + + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ +#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< (DAC_DBGCTRL) Debug Control Reset Value */ + +#define DAC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (DAC_DBGCTRL) Debug Run Position */ +#define DAC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) /**< (DAC_DBGCTRL) Debug Run Mask */ +#define DAC_DBGCTRL_DBGRUN(value) (DAC_DBGCTRL_DBGRUN_Msk & ((value) << DAC_DBGCTRL_DBGRUN_Pos)) +#define DAC_DBGCTRL_Msk _U_(0x01) /**< (DAC_DBGCTRL) Register Mask */ + + +/* -------- DAC_RESULT : (DAC Offset: 0x1C) ( R/ 16) Filter Result -------- */ +#define DAC_RESULT_RESETVALUE _U_(0x00) /**< (DAC_RESULT) Filter Result Reset Value */ + +#define DAC_RESULT_RESULT_Pos _U_(0) /**< (DAC_RESULT) Filter Result Position */ +#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) /**< (DAC_RESULT) Filter Result Mask */ +#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) +#define DAC_RESULT_Msk _U_(0xFFFF) /**< (DAC_RESULT) Register Mask */ + + +/** \brief DAC register offsets definitions */ +#define DAC_CTRLA_REG_OFST (0x00) /**< (DAC_CTRLA) Control A Offset */ +#define DAC_CTRLB_REG_OFST (0x01) /**< (DAC_CTRLB) Control B Offset */ +#define DAC_EVCTRL_REG_OFST (0x02) /**< (DAC_EVCTRL) Event Control Offset */ +#define DAC_INTENCLR_REG_OFST (0x04) /**< (DAC_INTENCLR) Interrupt Enable Clear Offset */ +#define DAC_INTENSET_REG_OFST (0x05) /**< (DAC_INTENSET) Interrupt Enable Set Offset */ +#define DAC_INTFLAG_REG_OFST (0x06) /**< (DAC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define DAC_STATUS_REG_OFST (0x07) /**< (DAC_STATUS) Status Offset */ +#define DAC_SYNCBUSY_REG_OFST (0x08) /**< (DAC_SYNCBUSY) Synchronization Busy Offset */ +#define DAC_DACCTRL_REG_OFST (0x0C) /**< (DAC_DACCTRL) DAC n Control Offset */ +#define DAC_DATA_REG_OFST (0x10) /**< (DAC_DATA) DAC n Data Offset */ +#define DAC_DATABUF_REG_OFST (0x14) /**< (DAC_DATABUF) DAC n Data Buffer Offset */ +#define DAC_DBGCTRL_REG_OFST (0x18) /**< (DAC_DBGCTRL) Debug Control Offset */ +#define DAC_RESULT_REG_OFST (0x1C) /**< (DAC_RESULT) Filter Result Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DAC register API structure */ +typedef struct +{ /* Digital-to-Analog Converter */ + __IO uint8_t DAC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __IO uint8_t DAC_CTRLB; /**< Offset: 0x01 (R/W 8) Control B */ + __IO uint8_t DAC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t DAC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t DAC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t DAC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t DAC_STATUS; /**< Offset: 0x07 (R/ 8) Status */ + __I uint32_t DAC_SYNCBUSY; /**< Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO uint16_t DAC_DACCTRL[2]; /**< Offset: 0x0C (R/W 16) DAC n Control */ + __O uint16_t DAC_DATA[2]; /**< Offset: 0x10 ( /W 16) DAC n Data */ + __O uint16_t DAC_DATABUF[2]; /**< Offset: 0x14 ( /W 16) DAC n Data Buffer */ + __IO uint8_t DAC_DBGCTRL; /**< Offset: 0x18 (R/W 8) Debug Control */ + __I uint8_t Reserved2[0x03]; + __I uint16_t DAC_RESULT[2]; /**< Offset: 0x1C (R/ 16) Filter Result */ +} dac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMD51_DAC_COMPONENT_H_ */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/component/dmac.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/dmac.h new file mode 100644 index 00000000..733001bd --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/component/dmac.h @@ -0,0 +1,1125 @@ +/** + * \brief Component description for DMAC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:45:00Z */ +#ifndef _SAMD51_DMAC_COMPONENT_H_ +#define _SAMD51_DMAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DMAC */ +/* ************************************************************************** */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#define DMAC_BTCTRL_RESETVALUE _U_(0x00) /**< (DMAC_BTCTRL) Block Transfer Control Reset Value */ + +#define DMAC_BTCTRL_VALID_Pos _U_(0) /**< (DMAC_BTCTRL) Descriptor Valid Position */ +#define DMAC_BTCTRL_VALID_Msk (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) /**< (DMAC_BTCTRL) Descriptor Valid Mask */ +#define DMAC_BTCTRL_VALID(value) (DMAC_BTCTRL_VALID_Msk & ((value) << DMAC_BTCTRL_VALID_Pos)) +#define DMAC_BTCTRL_EVOSEL_Pos _U_(1) /**< (DMAC_BTCTRL) Block Event Output Selection Position */ +#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Block Event Output Selection Mask */ +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< (DMAC_BTCTRL) Block event strobe */ +#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< (DMAC_BTCTRL) Burst event strobe */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Event generation disabled Position */ +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Block event strobe Position */ +#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Burst event strobe Position */ +#define DMAC_BTCTRL_BLOCKACT_Pos _U_(3) /**< (DMAC_BTCTRL) Block Action Position */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Block Action Mask */ +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction Position */ +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt Position */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Channel suspend operation is completed Position */ +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Both channel suspend operation and block interrupt Position */ +#define DMAC_BTCTRL_BEATSIZE_Pos _U_(8) /**< (DMAC_BTCTRL) Beat Size Position */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) Beat Size Mask */ +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 8-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 16-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 32-bit bus transfer Position */ +#define DMAC_BTCTRL_SRCINC_Pos _U_(10) /**< (DMAC_BTCTRL) Source Address Increment Enable Position */ +#define DMAC_BTCTRL_SRCINC_Msk (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) /**< (DMAC_BTCTRL) Source Address Increment Enable Mask */ +#define DMAC_BTCTRL_SRCINC(value) (DMAC_BTCTRL_SRCINC_Msk & ((value) << DMAC_BTCTRL_SRCINC_Pos)) +#define DMAC_BTCTRL_DSTINC_Pos _U_(11) /**< (DMAC_BTCTRL) Destination Address Increment Enable Position */ +#define DMAC_BTCTRL_DSTINC_Msk (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) /**< (DMAC_BTCTRL) Destination Address Increment Enable Mask */ +#define DMAC_BTCTRL_DSTINC(value) (DMAC_BTCTRL_DSTINC_Msk & ((value) << DMAC_BTCTRL_DSTINC_Pos)) +#define DMAC_BTCTRL_STEPSEL_Pos _U_(12) /**< (DMAC_BTCTRL) Step Selection Position */ +#define DMAC_BTCTRL_STEPSEL_Msk (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step Selection Mask */ +#define DMAC_BTCTRL_STEPSEL(value) (DMAC_BTCTRL_STEPSEL_Msk & ((value) << DMAC_BTCTRL_STEPSEL_Pos)) +#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step size settings apply to the destination address Position */ +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step size settings apply to the source address Position */ +#define DMAC_BTCTRL_STEPSIZE_Pos _U_(13) /**< (DMAC_BTCTRL) Address Increment Step Size Position */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Address Increment Step Size Mask */ +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) +#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< (DMAC_BTCTRL) Next ADDR = ADDR + (1< +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAMD51G18A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + + PERIPH_MAX_IRQn = 135 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pvReserved84; + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pvReserved101; + void* pvReserved102; + void* pvReserved103; + void* pvReserved104; + void* pvReserved105; + void* pvReserved106; + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pvReserved111; + void* pvReserved112; + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pvReserved128; + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAMD51G18A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G18A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAMD51G18A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAMD51G18A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51G18A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51G18A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +#include "pio/samd51g18a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 512) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAMD51G18A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X60060308) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAMD51G18A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAMD51G18A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAMD51G18A definitions */ + + +#endif /* _SAMD51G18A_H_ */ + diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51g19a.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51g19a.h new file mode 100644 index 00000000..fcd6823b --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51g19a.h @@ -0,0 +1,973 @@ +/** + * \brief Header file for ATSAMD51G19A + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:44:39Z */ +#ifndef _SAMD51G19A_H_ +#define _SAMD51G19A_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAMD51G19A_definitions SAMD51G19A definitions + This file defines all structures and symbols for SAMD51G19A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAMD51G19A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + + PERIPH_MAX_IRQn = 135 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pvReserved84; + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pvReserved101; + void* pvReserved102; + void* pvReserved103; + void* pvReserved104; + void* pvReserved105; + void* pvReserved106; + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pvReserved111; + void* pvReserved112; + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pvReserved128; + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAMD51G19A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G19A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAMD51G19A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAMD51G19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51G19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51G19A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +#include "pio/samd51g19a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 1024) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00030000) /* 192kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAMD51G19A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X60060307) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAMD51G19A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAMD51G19A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAMD51G19A definitions */ + + +#endif /* _SAMD51G19A_H_ */ + diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51j18a.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51j18a.h new file mode 100644 index 00000000..ea849b3a --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51j18a.h @@ -0,0 +1,1033 @@ +/** + * \brief Header file for ATSAMD51J18A + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:44:43Z */ +#ifndef _SAMD51J18A_H_ +#define _SAMD51J18A_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAMD51J18A_definitions SAMD51J18A definitions + This file defines all structures and symbols for SAMD51J18A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAMD51J18A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + + PERIPH_MAX_IRQn = 135 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pvReserved84; + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAMD51J18A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J18A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAMD51J18A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ +#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ +#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAMD51J18A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51J18A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ +#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51J18A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +#include "pio/samd51j18a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 512) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAMD51J18A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X60060306) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAMD51J18A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAMD51J18A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAMD51J18A definitions */ + + +#endif /* _SAMD51J18A_H_ */ + diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51j19a.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51j19a.h new file mode 100644 index 00000000..03084920 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51j19a.h @@ -0,0 +1,1033 @@ +/** + * \brief Header file for ATSAMD51J19A + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:44:46Z */ +#ifndef _SAMD51J19A_H_ +#define _SAMD51J19A_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAMD51J19A_definitions SAMD51J19A definitions + This file defines all structures and symbols for SAMD51J19A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAMD51J19A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + + PERIPH_MAX_IRQn = 135 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pvReserved84; + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAMD51J19A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J19A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAMD51J19A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ +#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ +#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAMD51J19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51J19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ +#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51J19A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +#include "pio/samd51j19a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 1024) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00030000) /* 192kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAMD51J19A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X60060305) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAMD51J19A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAMD51J19A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAMD51J19A definitions */ + + +#endif /* _SAMD51J19A_H_ */ + diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51j20a.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51j20a.h new file mode 100644 index 00000000..99ad5ad1 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51j20a.h @@ -0,0 +1,1033 @@ +/** + * \brief Header file for ATSAMD51J20A + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:44:50Z */ +#ifndef _SAMD51J20A_H_ +#define _SAMD51J20A_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAMD51J20A_definitions SAMD51J20A definitions + This file defines all structures and symbols for SAMD51J20A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAMD51J20A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + + PERIPH_MAX_IRQn = 135 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pvReserved84; + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAMD51J20A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J20A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAMD51J20A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ +#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ +#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAMD51J20A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51J20A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ +#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51J20A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +#include "pio/samd51j20a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 2048) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAMD51J20A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X60060304) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAMD51J20A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAMD51J20A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAMD51J20A definitions */ + + +#endif /* _SAMD51J20A_H_ */ + diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51n19a.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51n19a.h new file mode 100644 index 00000000..813b46b3 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51n19a.h @@ -0,0 +1,1080 @@ +/** + * \brief Header file for ATSAMD51N19A + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:44:52Z */ +#ifndef _SAMD51N19A_H_ +#define _SAMD51N19A_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAMD51N19A_definitions SAMD51N19A definitions + This file defines all structures and symbols for SAMD51N19A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAMD51N19A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pvReserved84; + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAMD51N19A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51N19A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAMD51N19A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ +#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ +#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ +#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ +#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ +#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ +#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAMD51N19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51N19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ +#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ +#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ +#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51N19A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +#include "pio/samd51n19a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 1024) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00030000) /* 192kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAMD51N19A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X60060303) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAMD51N19A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAMD51N19A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAMD51N19A definitions */ + + +#endif /* _SAMD51N19A_H_ */ + diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51n20a.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51n20a.h new file mode 100644 index 00000000..c57ebee2 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51n20a.h @@ -0,0 +1,1080 @@ +/** + * \brief Header file for ATSAMD51N20A + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:44:55Z */ +#ifndef _SAMD51N20A_H_ +#define _SAMD51N20A_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAMD51N20A_definitions SAMD51N20A definitions + This file defines all structures and symbols for SAMD51N20A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAMD51N20A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pvReserved84; + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAMD51N20A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51N20A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAMD51N20A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ +#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ +#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ +#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ +#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ +#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ +#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAMD51N20A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51N20A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ +#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ +#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ +#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51N20A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +#include "pio/samd51n20a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 2048) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAMD51N20A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X60060302) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAMD51N20A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAMD51N20A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAMD51N20A definitions */ + + +#endif /* _SAMD51N20A_H_ */ + diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51p19a.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51p19a.h new file mode 100644 index 00000000..5560db31 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51p19a.h @@ -0,0 +1,1080 @@ +/** + * \brief Header file for ATSAMD51P19A + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:44:57Z */ +#ifndef _SAMD51P19A_H_ +#define _SAMD51P19A_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAMD51P19A_definitions SAMD51P19A definitions + This file defines all structures and symbols for SAMD51P19A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAMD51P19A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pvReserved84; + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAMD51P19A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P19A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAMD51P19A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ +#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ +#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ +#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ +#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ +#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ +#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAMD51P19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51P19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ +#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ +#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ +#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51P19A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +#include "pio/samd51p19a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 1024) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00030000) /* 192kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAMD51P19A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X60060301) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAMD51P19A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAMD51P19A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAMD51P19A definitions */ + + +#endif /* _SAMD51P19A_H_ */ + diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51p20a.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51p20a.h new file mode 100644 index 00000000..567dcc7f --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/samd51p20a.h @@ -0,0 +1,1080 @@ +/** + * \brief Header file for ATSAMD51P20A + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-09-28T13:45:00Z */ +#ifndef _SAMD51P20A_H_ +#define _SAMD51P20A_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAMD51P20A_definitions SAMD51P20A definitions + This file defines all structures and symbols for SAMD51P20A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAMD51P20A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pvReserved84; + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAMD51P20A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P20A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAMD51P20A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ +#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ +#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ +#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ +#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ +#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ +#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAMD51P20A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51P20A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ +#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ +#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ +#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAMD51P20A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +#include "pio/samd51p20a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 2048) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAMD51P20A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X60060300) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAMD51P20A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAMD51P20A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAMD51P20A definitions */ + + +#endif /* _SAMD51P20A_H_ */ + diff --git a/arch/arm/SAMD51/SAMD51A/mcu/inc/system_samd51.h b/arch/arm/SAMD51/SAMD51A/mcu/inc/system_samd51.h new file mode 100644 index 00000000..a6f268d6 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/inc/system_samd51.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon device startup + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SYSTEM_SAMD51_H_INCLUDED_ +#define _SYSTEM_SAMD51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_SAMD51_H_INCLUDED */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51g18a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51g18a.c new file mode 100644 index 00000000..3e72f9ed --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51g18a.c @@ -0,0 +1,385 @@ +/** + * \file + * + * \brief GCC startup file for ATSAMD51G18A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51g18a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pvReserved71 = (void*) (0UL), /* 71 Reserved */ + .pvReserved72 = (void*) (0UL), /* 72 Reserved */ + .pvReserved73 = (void*) (0UL), /* 73 Reserved */ + .pvReserved74 = (void*) (0UL), /* 74 Reserved */ + .pvReserved75 = (void*) (0UL), /* 75 Reserved */ + .pvReserved76 = (void*) (0UL), /* 76 Reserved */ + .pvReserved77 = (void*) (0UL), /* 77 Reserved */ + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pvReserved101 = (void*) (0UL), /* 101 Reserved */ + .pvReserved102 = (void*) (0UL), /* 102 Reserved */ + .pvReserved103 = (void*) (0UL), /* 103 Reserved */ + .pvReserved104 = (void*) (0UL), /* 104 Reserved */ + .pvReserved105 = (void*) (0UL), /* 105 Reserved */ + .pvReserved106 = (void*) (0UL), /* 106 Reserved */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pvReserved111 = (void*) (0UL), /* 111 Reserved */ + .pvReserved112 = (void*) (0UL), /* 112 Reserved */ + .pvReserved113 = (void*) (0UL), /* 113 Reserved */ + .pvReserved114 = (void*) (0UL), /* 114 Reserved */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pvReserved128 = (void*) (0UL), /* 128 Reserved */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler /* 135 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51g19a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51g19a.c new file mode 100644 index 00000000..779645d7 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51g19a.c @@ -0,0 +1,385 @@ +/** + * \file + * + * \brief GCC startup file for ATSAMD51G19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51g19a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pvReserved71 = (void*) (0UL), /* 71 Reserved */ + .pvReserved72 = (void*) (0UL), /* 72 Reserved */ + .pvReserved73 = (void*) (0UL), /* 73 Reserved */ + .pvReserved74 = (void*) (0UL), /* 74 Reserved */ + .pvReserved75 = (void*) (0UL), /* 75 Reserved */ + .pvReserved76 = (void*) (0UL), /* 76 Reserved */ + .pvReserved77 = (void*) (0UL), /* 77 Reserved */ + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pvReserved101 = (void*) (0UL), /* 101 Reserved */ + .pvReserved102 = (void*) (0UL), /* 102 Reserved */ + .pvReserved103 = (void*) (0UL), /* 103 Reserved */ + .pvReserved104 = (void*) (0UL), /* 104 Reserved */ + .pvReserved105 = (void*) (0UL), /* 105 Reserved */ + .pvReserved106 = (void*) (0UL), /* 106 Reserved */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pvReserved111 = (void*) (0UL), /* 111 Reserved */ + .pvReserved112 = (void*) (0UL), /* 112 Reserved */ + .pvReserved113 = (void*) (0UL), /* 113 Reserved */ + .pvReserved114 = (void*) (0UL), /* 114 Reserved */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pvReserved128 = (void*) (0UL), /* 128 Reserved */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler /* 135 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j18a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j18a.c new file mode 100644 index 00000000..f1f630a8 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j18a.c @@ -0,0 +1,394 @@ +/** + * \file + * + * \brief GCC startup file for ATSAMD51J18A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51j18a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pvReserved71 = (void*) (0UL), /* 71 Reserved */ + .pvReserved72 = (void*) (0UL), /* 72 Reserved */ + .pvReserved73 = (void*) (0UL), /* 73 Reserved */ + .pvReserved74 = (void*) (0UL), /* 74 Reserved */ + .pvReserved75 = (void*) (0UL), /* 75 Reserved */ + .pvReserved76 = (void*) (0UL), /* 76 Reserved */ + .pvReserved77 = (void*) (0UL), /* 77 Reserved */ + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ + .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ + .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ + .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ + .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ + .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ + .pvReserved113 = (void*) (0UL), /* 113 Reserved */ + .pvReserved114 = (void*) (0UL), /* 114 Reserved */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler /* 135 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j19a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j19a.c new file mode 100644 index 00000000..9c7349df --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j19a.c @@ -0,0 +1,394 @@ +/** + * \file + * + * \brief GCC startup file for ATSAMD51J19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51j19a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pvReserved71 = (void*) (0UL), /* 71 Reserved */ + .pvReserved72 = (void*) (0UL), /* 72 Reserved */ + .pvReserved73 = (void*) (0UL), /* 73 Reserved */ + .pvReserved74 = (void*) (0UL), /* 74 Reserved */ + .pvReserved75 = (void*) (0UL), /* 75 Reserved */ + .pvReserved76 = (void*) (0UL), /* 76 Reserved */ + .pvReserved77 = (void*) (0UL), /* 77 Reserved */ + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ + .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ + .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ + .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ + .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ + .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ + .pvReserved113 = (void*) (0UL), /* 113 Reserved */ + .pvReserved114 = (void*) (0UL), /* 114 Reserved */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler /* 135 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j20a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j20a.c new file mode 100644 index 00000000..9a571d75 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j20a.c @@ -0,0 +1,394 @@ +/** + * \file + * + * \brief GCC startup file for ATSAMD51J20A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51j20a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pvReserved71 = (void*) (0UL), /* 71 Reserved */ + .pvReserved72 = (void*) (0UL), /* 72 Reserved */ + .pvReserved73 = (void*) (0UL), /* 73 Reserved */ + .pvReserved74 = (void*) (0UL), /* 74 Reserved */ + .pvReserved75 = (void*) (0UL), /* 75 Reserved */ + .pvReserved76 = (void*) (0UL), /* 76 Reserved */ + .pvReserved77 = (void*) (0UL), /* 77 Reserved */ + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ + .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ + .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ + .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ + .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ + .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ + .pvReserved113 = (void*) (0UL), /* 113 Reserved */ + .pvReserved114 = (void*) (0UL), /* 114 Reserved */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler /* 135 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51n19a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51n19a.c new file mode 100644 index 00000000..616fb53c --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51n19a.c @@ -0,0 +1,406 @@ +/** + * \file + * + * \brief GCC startup file for ATSAMD51N19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51n19a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ + .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ + .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ + .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ + .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ + .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ + .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ + .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ + .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ + .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ + .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ + .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ + .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ + .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51n20a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51n20a.c new file mode 100644 index 00000000..c5695e52 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51n20a.c @@ -0,0 +1,406 @@ +/** + * \file + * + * \brief GCC startup file for ATSAMD51N20A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51n20a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ + .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ + .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ + .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ + .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ + .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ + .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ + .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ + .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ + .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ + .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ + .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ + .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ + .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51p19a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51p19a.c new file mode 100644 index 00000000..dd355034 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51p19a.c @@ -0,0 +1,406 @@ +/** + * \file + * + * \brief GCC startup file for ATSAMD51P19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51p19a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ + .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ + .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ + .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ + .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ + .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ + .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ + .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ + .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ + .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ + .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ + .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ + .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ + .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51p20a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51p20a.c new file mode 100644 index 00000000..ca848dee --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51p20a.c @@ -0,0 +1,406 @@ +/** + * \file + * + * \brief GCC startup file for ATSAMD51P20A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51p20a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ + .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ + .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ + .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ + .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ + .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ + .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ + .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ + .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ + .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ + .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ + .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ + .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ + .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51g18a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51g18a.c new file mode 100644 index 00000000..b09f44c9 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51g18a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAMD51G18A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51g18a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51g19a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51g19a.c new file mode 100644 index 00000000..bc7b5990 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51g19a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAMD51G19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51g19a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j18a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j18a.c new file mode 100644 index 00000000..c1e3bfff --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j18a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAMD51J18A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51j18a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j19a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j19a.c new file mode 100644 index 00000000..55503563 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j19a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAMD51J19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51j19a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j20a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j20a.c new file mode 100644 index 00000000..b05b73f2 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j20a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAMD51J20A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51j20a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51n19a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51n19a.c new file mode 100644 index 00000000..98a92553 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51n19a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAMD51N19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51n19a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51n20a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51n20a.c new file mode 100644 index 00000000..6f1ad769 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51n20a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAMD51N20A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51n20a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51p19a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51p19a.c new file mode 100644 index 00000000..6502ec39 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51p19a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAMD51P19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51p19a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51p20a.c b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51p20a.c new file mode 100644 index 00000000..b9811624 --- /dev/null +++ b/arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51p20a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAMD51P20A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "samd51p20a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME54/ld/same54n19a_flash.ld b/arch/arm/SAME54/ld/same54n19a_flash.ld new file mode 100644 index 00000000..33b8ed9c --- /dev/null +++ b/arch/arm/SAME54/ld/same54n19a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAME54N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAME54/ld/same54n19a_sram.ld b/arch/arm/SAME54/ld/same54n19a_sram.ld new file mode 100644 index 00000000..c770c7c6 --- /dev/null +++ b/arch/arm/SAME54/ld/same54n19a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAME54N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAME54/ld/same54n20a_flash.ld b/arch/arm/SAME54/ld/same54n20a_flash.ld new file mode 100644 index 00000000..b6a797bb --- /dev/null +++ b/arch/arm/SAME54/ld/same54n20a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAME54N20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAME54/ld/same54n20a_sram.ld b/arch/arm/SAME54/ld/same54n20a_sram.ld new file mode 100644 index 00000000..340af27a --- /dev/null +++ b/arch/arm/SAME54/ld/same54n20a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAME54N20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAME54/ld/same54p19a_flash.ld b/arch/arm/SAME54/ld/same54p19a_flash.ld new file mode 100644 index 00000000..f60307a3 --- /dev/null +++ b/arch/arm/SAME54/ld/same54p19a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAME54P19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAME54/ld/same54p19a_sram.ld b/arch/arm/SAME54/ld/same54p19a_sram.ld new file mode 100644 index 00000000..9c45843b --- /dev/null +++ b/arch/arm/SAME54/ld/same54p19a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAME54P19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAME54/ld/same54p20a_flash.ld b/arch/arm/SAME54/ld/same54p20a_flash.ld new file mode 100644 index 00000000..6b9660b8 --- /dev/null +++ b/arch/arm/SAME54/ld/same54p20a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAME54/ld/same54p20a_sram.ld b/arch/arm/SAME54/ld/same54p20a_sram.ld new file mode 100644 index 00000000..646b1bd0 --- /dev/null +++ b/arch/arm/SAME54/ld/same54p20a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/SAME54/mcu/inc/component-version.h b/arch/arm/SAME54/mcu/inc/component-version.h new file mode 100644 index 00000000..672dd5ee --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 3 +#define COMPONENT_VERSION_MINOR 3 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 30003 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 64 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "3.3" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2020-04-28 23:52:31" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/arch/arm/SAME54/mcu/inc/component/ac.h b/arch/arm/SAME54/mcu/inc/component/ac.h new file mode 100644 index 00000000..417aad88 --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/component/ac.h @@ -0,0 +1,410 @@ +/** + * \brief Component description for AC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-12T17:27:04Z */ +#ifndef _SAME54_AC_COMPONENT_H_ +#define _SAME54_AC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AC */ +/* ************************************************************************** */ + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< (AC_CTRLA) Control A Reset Value */ + +#define AC_CTRLA_SWRST_Pos _U_(0) /**< (AC_CTRLA) Software Reset Position */ +#define AC_CTRLA_SWRST_Msk (_U_(0x1) << AC_CTRLA_SWRST_Pos) /**< (AC_CTRLA) Software Reset Mask */ +#define AC_CTRLA_SWRST(value) (AC_CTRLA_SWRST_Msk & ((value) << AC_CTRLA_SWRST_Pos)) +#define AC_CTRLA_ENABLE_Pos _U_(1) /**< (AC_CTRLA) Enable Position */ +#define AC_CTRLA_ENABLE_Msk (_U_(0x1) << AC_CTRLA_ENABLE_Pos) /**< (AC_CTRLA) Enable Mask */ +#define AC_CTRLA_ENABLE(value) (AC_CTRLA_ENABLE_Msk & ((value) << AC_CTRLA_ENABLE_Pos)) +#define AC_CTRLA_Msk _U_(0x03) /**< (AC_CTRLA) Register Mask */ + + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< (AC_CTRLB) Control B Reset Value */ + +#define AC_CTRLB_START0_Pos _U_(0) /**< (AC_CTRLB) Comparator 0 Start Comparison Position */ +#define AC_CTRLB_START0_Msk (_U_(0x1) << AC_CTRLB_START0_Pos) /**< (AC_CTRLB) Comparator 0 Start Comparison Mask */ +#define AC_CTRLB_START0(value) (AC_CTRLB_START0_Msk & ((value) << AC_CTRLB_START0_Pos)) +#define AC_CTRLB_START1_Pos _U_(1) /**< (AC_CTRLB) Comparator 1 Start Comparison Position */ +#define AC_CTRLB_START1_Msk (_U_(0x1) << AC_CTRLB_START1_Pos) /**< (AC_CTRLB) Comparator 1 Start Comparison Mask */ +#define AC_CTRLB_START1(value) (AC_CTRLB_START1_Msk & ((value) << AC_CTRLB_START1_Pos)) +#define AC_CTRLB_Msk _U_(0x03) /**< (AC_CTRLB) Register Mask */ + +#define AC_CTRLB_START_Pos _U_(0) /**< (AC_CTRLB Position) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) /**< (AC_CTRLB Mask) START */ +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#define AC_EVCTRL_RESETVALUE _U_(0x00) /**< (AC_EVCTRL) Event Control Reset Value */ + +#define AC_EVCTRL_COMPEO0_Pos _U_(0) /**< (AC_EVCTRL) Comparator 0 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO0_Msk (_U_(0x1) << AC_EVCTRL_COMPEO0_Pos) /**< (AC_EVCTRL) Comparator 0 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO0(value) (AC_EVCTRL_COMPEO0_Msk & ((value) << AC_EVCTRL_COMPEO0_Pos)) +#define AC_EVCTRL_COMPEO1_Pos _U_(1) /**< (AC_EVCTRL) Comparator 1 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO1_Msk (_U_(0x1) << AC_EVCTRL_COMPEO1_Pos) /**< (AC_EVCTRL) Comparator 1 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO1(value) (AC_EVCTRL_COMPEO1_Msk & ((value) << AC_EVCTRL_COMPEO1_Pos)) +#define AC_EVCTRL_WINEO0_Pos _U_(4) /**< (AC_EVCTRL) Window 0 Event Output Enable Position */ +#define AC_EVCTRL_WINEO0_Msk (_U_(0x1) << AC_EVCTRL_WINEO0_Pos) /**< (AC_EVCTRL) Window 0 Event Output Enable Mask */ +#define AC_EVCTRL_WINEO0(value) (AC_EVCTRL_WINEO0_Msk & ((value) << AC_EVCTRL_WINEO0_Pos)) +#define AC_EVCTRL_COMPEI0_Pos _U_(8) /**< (AC_EVCTRL) Comparator 0 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI0_Msk (_U_(0x1) << AC_EVCTRL_COMPEI0_Pos) /**< (AC_EVCTRL) Comparator 0 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI0(value) (AC_EVCTRL_COMPEI0_Msk & ((value) << AC_EVCTRL_COMPEI0_Pos)) +#define AC_EVCTRL_COMPEI1_Pos _U_(9) /**< (AC_EVCTRL) Comparator 1 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI1_Msk (_U_(0x1) << AC_EVCTRL_COMPEI1_Pos) /**< (AC_EVCTRL) Comparator 1 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI1(value) (AC_EVCTRL_COMPEI1_Msk & ((value) << AC_EVCTRL_COMPEI1_Pos)) +#define AC_EVCTRL_INVEI0_Pos _U_(12) /**< (AC_EVCTRL) Comparator 0 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI0_Msk (_U_(0x1) << AC_EVCTRL_INVEI0_Pos) /**< (AC_EVCTRL) Comparator 0 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI0(value) (AC_EVCTRL_INVEI0_Msk & ((value) << AC_EVCTRL_INVEI0_Pos)) +#define AC_EVCTRL_INVEI1_Pos _U_(13) /**< (AC_EVCTRL) Comparator 1 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI1_Msk (_U_(0x1) << AC_EVCTRL_INVEI1_Pos) /**< (AC_EVCTRL) Comparator 1 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI1(value) (AC_EVCTRL_INVEI1_Msk & ((value) << AC_EVCTRL_INVEI1_Pos)) +#define AC_EVCTRL_Msk _U_(0x3313) /**< (AC_EVCTRL) Register Mask */ + +#define AC_EVCTRL_COMPEO_Pos _U_(0) /**< (AC_EVCTRL Position) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) /**< (AC_EVCTRL Mask) COMPEO */ +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO_Pos _U_(4) /**< (AC_EVCTRL Position) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) /**< (AC_EVCTRL Mask) WINEO */ +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI_Pos _U_(8) /**< (AC_EVCTRL Position) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) /**< (AC_EVCTRL Mask) COMPEI */ +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI_Pos _U_(12) /**< (AC_EVCTRL Position) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) /**< (AC_EVCTRL Mask) INVEI */ +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< (AC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define AC_INTENCLR_COMP0_Pos _U_(0) /**< (AC_INTENCLR) Comparator 0 Interrupt Enable Position */ +#define AC_INTENCLR_COMP0_Msk (_U_(0x1) << AC_INTENCLR_COMP0_Pos) /**< (AC_INTENCLR) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP0(value) (AC_INTENCLR_COMP0_Msk & ((value) << AC_INTENCLR_COMP0_Pos)) +#define AC_INTENCLR_COMP1_Pos _U_(1) /**< (AC_INTENCLR) Comparator 1 Interrupt Enable Position */ +#define AC_INTENCLR_COMP1_Msk (_U_(0x1) << AC_INTENCLR_COMP1_Pos) /**< (AC_INTENCLR) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP1(value) (AC_INTENCLR_COMP1_Msk & ((value) << AC_INTENCLR_COMP1_Pos)) +#define AC_INTENCLR_WIN0_Pos _U_(4) /**< (AC_INTENCLR) Window 0 Interrupt Enable Position */ +#define AC_INTENCLR_WIN0_Msk (_U_(0x1) << AC_INTENCLR_WIN0_Pos) /**< (AC_INTENCLR) Window 0 Interrupt Enable Mask */ +#define AC_INTENCLR_WIN0(value) (AC_INTENCLR_WIN0_Msk & ((value) << AC_INTENCLR_WIN0_Pos)) +#define AC_INTENCLR_Msk _U_(0x13) /**< (AC_INTENCLR) Register Mask */ + +#define AC_INTENCLR_COMP_Pos _U_(0) /**< (AC_INTENCLR Position) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) /**< (AC_INTENCLR Mask) COMP */ +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN_Pos _U_(4) /**< (AC_INTENCLR Position) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) /**< (AC_INTENCLR Mask) WIN */ +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< (AC_INTENSET) Interrupt Enable Set Reset Value */ + +#define AC_INTENSET_COMP0_Pos _U_(0) /**< (AC_INTENSET) Comparator 0 Interrupt Enable Position */ +#define AC_INTENSET_COMP0_Msk (_U_(0x1) << AC_INTENSET_COMP0_Pos) /**< (AC_INTENSET) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENSET_COMP0(value) (AC_INTENSET_COMP0_Msk & ((value) << AC_INTENSET_COMP0_Pos)) +#define AC_INTENSET_COMP1_Pos _U_(1) /**< (AC_INTENSET) Comparator 1 Interrupt Enable Position */ +#define AC_INTENSET_COMP1_Msk (_U_(0x1) << AC_INTENSET_COMP1_Pos) /**< (AC_INTENSET) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENSET_COMP1(value) (AC_INTENSET_COMP1_Msk & ((value) << AC_INTENSET_COMP1_Pos)) +#define AC_INTENSET_WIN0_Pos _U_(4) /**< (AC_INTENSET) Window 0 Interrupt Enable Position */ +#define AC_INTENSET_WIN0_Msk (_U_(0x1) << AC_INTENSET_WIN0_Pos) /**< (AC_INTENSET) Window 0 Interrupt Enable Mask */ +#define AC_INTENSET_WIN0(value) (AC_INTENSET_WIN0_Msk & ((value) << AC_INTENSET_WIN0_Pos)) +#define AC_INTENSET_Msk _U_(0x13) /**< (AC_INTENSET) Register Mask */ + +#define AC_INTENSET_COMP_Pos _U_(0) /**< (AC_INTENSET Position) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) /**< (AC_INTENSET Mask) COMP */ +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN_Pos _U_(4) /**< (AC_INTENSET Position) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) /**< (AC_INTENSET Mask) WIN */ +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< (AC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define AC_INTFLAG_COMP0_Pos _U_(0) /**< (AC_INTFLAG) Comparator 0 Position */ +#define AC_INTFLAG_COMP0_Msk (_U_(0x1) << AC_INTFLAG_COMP0_Pos) /**< (AC_INTFLAG) Comparator 0 Mask */ +#define AC_INTFLAG_COMP0(value) (AC_INTFLAG_COMP0_Msk & ((value) << AC_INTFLAG_COMP0_Pos)) +#define AC_INTFLAG_COMP1_Pos _U_(1) /**< (AC_INTFLAG) Comparator 1 Position */ +#define AC_INTFLAG_COMP1_Msk (_U_(0x1) << AC_INTFLAG_COMP1_Pos) /**< (AC_INTFLAG) Comparator 1 Mask */ +#define AC_INTFLAG_COMP1(value) (AC_INTFLAG_COMP1_Msk & ((value) << AC_INTFLAG_COMP1_Pos)) +#define AC_INTFLAG_WIN0_Pos _U_(4) /**< (AC_INTFLAG) Window 0 Position */ +#define AC_INTFLAG_WIN0_Msk (_U_(0x1) << AC_INTFLAG_WIN0_Pos) /**< (AC_INTFLAG) Window 0 Mask */ +#define AC_INTFLAG_WIN0(value) (AC_INTFLAG_WIN0_Msk & ((value) << AC_INTFLAG_WIN0_Pos)) +#define AC_INTFLAG_Msk _U_(0x13) /**< (AC_INTFLAG) Register Mask */ + +#define AC_INTFLAG_COMP_Pos _U_(0) /**< (AC_INTFLAG Position) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) /**< (AC_INTFLAG Mask) COMP */ +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN_Pos _U_(4) /**< (AC_INTFLAG Position) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) /**< (AC_INTFLAG Mask) WIN */ +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) + +/* -------- AC_STATUSA : (AC Offset: 0x07) ( R/ 8) Status A -------- */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< (AC_STATUSA) Status A Reset Value */ + +#define AC_STATUSA_STATE0_Pos _U_(0) /**< (AC_STATUSA) Comparator 0 Current State Position */ +#define AC_STATUSA_STATE0_Msk (_U_(0x1) << AC_STATUSA_STATE0_Pos) /**< (AC_STATUSA) Comparator 0 Current State Mask */ +#define AC_STATUSA_STATE0(value) (AC_STATUSA_STATE0_Msk & ((value) << AC_STATUSA_STATE0_Pos)) +#define AC_STATUSA_STATE1_Pos _U_(1) /**< (AC_STATUSA) Comparator 1 Current State Position */ +#define AC_STATUSA_STATE1_Msk (_U_(0x1) << AC_STATUSA_STATE1_Pos) /**< (AC_STATUSA) Comparator 1 Current State Mask */ +#define AC_STATUSA_STATE1(value) (AC_STATUSA_STATE1_Msk & ((value) << AC_STATUSA_STATE1_Pos)) +#define AC_STATUSA_WSTATE0_Pos _U_(4) /**< (AC_STATUSA) Window 0 Current State Position */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Window 0 Current State Mask */ +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is above window Position */ +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is inside window Position */ +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is below window Position */ +#define AC_STATUSA_Msk _U_(0x33) /**< (AC_STATUSA) Register Mask */ + +#define AC_STATUSA_STATE_Pos _U_(0) /**< (AC_STATUSA Position) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) /**< (AC_STATUSA Mask) STATE */ +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) + +/* -------- AC_STATUSB : (AC Offset: 0x08) ( R/ 8) Status B -------- */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< (AC_STATUSB) Status B Reset Value */ + +#define AC_STATUSB_READY0_Pos _U_(0) /**< (AC_STATUSB) Comparator 0 Ready Position */ +#define AC_STATUSB_READY0_Msk (_U_(0x1) << AC_STATUSB_READY0_Pos) /**< (AC_STATUSB) Comparator 0 Ready Mask */ +#define AC_STATUSB_READY0(value) (AC_STATUSB_READY0_Msk & ((value) << AC_STATUSB_READY0_Pos)) +#define AC_STATUSB_READY1_Pos _U_(1) /**< (AC_STATUSB) Comparator 1 Ready Position */ +#define AC_STATUSB_READY1_Msk (_U_(0x1) << AC_STATUSB_READY1_Pos) /**< (AC_STATUSB) Comparator 1 Ready Mask */ +#define AC_STATUSB_READY1(value) (AC_STATUSB_READY1_Msk & ((value) << AC_STATUSB_READY1_Pos)) +#define AC_STATUSB_Msk _U_(0x03) /**< (AC_STATUSB) Register Mask */ + +#define AC_STATUSB_READY_Pos _U_(0) /**< (AC_STATUSB Position) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) /**< (AC_STATUSB Mask) READY */ +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< (AC_DBGCTRL) Debug Control Reset Value */ + +#define AC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (AC_DBGCTRL) Debug Run Position */ +#define AC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) /**< (AC_DBGCTRL) Debug Run Mask */ +#define AC_DBGCTRL_DBGRUN(value) (AC_DBGCTRL_DBGRUN_Msk & ((value) << AC_DBGCTRL_DBGRUN_Pos)) +#define AC_DBGCTRL_Msk _U_(0x01) /**< (AC_DBGCTRL) Register Mask */ + + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< (AC_WINCTRL) Window Control Reset Value */ + +#define AC_WINCTRL_WEN0_Pos _U_(0) /**< (AC_WINCTRL) Window 0 Mode Enable Position */ +#define AC_WINCTRL_WEN0_Msk (_U_(0x1) << AC_WINCTRL_WEN0_Pos) /**< (AC_WINCTRL) Window 0 Mode Enable Mask */ +#define AC_WINCTRL_WEN0(value) (AC_WINCTRL_WEN0_Msk & ((value) << AC_WINCTRL_WEN0_Pos)) +#define AC_WINCTRL_WINTSEL0_Pos _U_(1) /**< (AC_WINCTRL) Window 0 Interrupt Selection Position */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Window 0 Interrupt Selection Mask */ +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal above window Position */ +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal inside window Position */ +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal below window Position */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal outside window Position */ +#define AC_WINCTRL_Msk _U_(0x07) /**< (AC_WINCTRL) Register Mask */ + +#define AC_WINCTRL_WEN_Pos _U_(0) /**< (AC_WINCTRL Position) Window x Mode Enable */ +#define AC_WINCTRL_WEN_Msk (_U_(0x1) << AC_WINCTRL_WEN_Pos) /**< (AC_WINCTRL Mask) WEN */ +#define AC_WINCTRL_WEN(value) (AC_WINCTRL_WEN_Msk & ((value) << AC_WINCTRL_WEN_Pos)) + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< (AC_SCALER) Scaler n Reset Value */ + +#define AC_SCALER_VALUE_Pos _U_(0) /**< (AC_SCALER) Scaler Value Position */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) /**< (AC_SCALER) Scaler Value Mask */ +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_Msk _U_(0x3F) /**< (AC_SCALER) Register Mask */ + + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00) /**< (AC_COMPCTRL) Comparator Control n Reset Value */ + +#define AC_COMPCTRL_ENABLE_Pos _U_(1) /**< (AC_COMPCTRL) Enable Position */ +#define AC_COMPCTRL_ENABLE_Msk (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) /**< (AC_COMPCTRL) Enable Mask */ +#define AC_COMPCTRL_ENABLE(value) (AC_COMPCTRL_ENABLE_Msk & ((value) << AC_COMPCTRL_ENABLE_Pos)) +#define AC_COMPCTRL_SINGLE_Pos _U_(2) /**< (AC_COMPCTRL) Single-Shot Mode Position */ +#define AC_COMPCTRL_SINGLE_Msk (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) /**< (AC_COMPCTRL) Single-Shot Mode Mask */ +#define AC_COMPCTRL_SINGLE(value) (AC_COMPCTRL_SINGLE_Msk & ((value) << AC_COMPCTRL_SINGLE_Pos)) +#define AC_COMPCTRL_INTSEL_Pos _U_(3) /**< (AC_COMPCTRL) Interrupt Selection Position */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt Selection Mask */ +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output toggle Position */ +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output rising Position */ +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output falling Position */ +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) Position */ +#define AC_COMPCTRL_RUNSTDBY_Pos _U_(6) /**< (AC_COMPCTRL) Run in Standby Position */ +#define AC_COMPCTRL_RUNSTDBY_Msk (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) /**< (AC_COMPCTRL) Run in Standby Mask */ +#define AC_COMPCTRL_RUNSTDBY(value) (AC_COMPCTRL_RUNSTDBY_Msk & ((value) << AC_COMPCTRL_RUNSTDBY_Pos)) +#define AC_COMPCTRL_MUXNEG_Pos _U_(8) /**< (AC_COMPCTRL) Negative Input Mux Selection Position */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Negative Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Ground Position */ +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) VDD scaler Position */ +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Internal bandgap voltage Position */ +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) DAC output Position */ +#define AC_COMPCTRL_MUXPOS_Pos _U_(12) /**< (AC_COMPCTRL) Positive Input Mux Selection Position */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) Positive Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) VDD Scaler Position */ +#define AC_COMPCTRL_SWAP_Pos _U_(15) /**< (AC_COMPCTRL) Swap Inputs and Invert Position */ +#define AC_COMPCTRL_SWAP_Msk (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) /**< (AC_COMPCTRL) Swap Inputs and Invert Mask */ +#define AC_COMPCTRL_SWAP(value) (AC_COMPCTRL_SWAP_Msk & ((value) << AC_COMPCTRL_SWAP_Pos)) +#define AC_COMPCTRL_SPEED_Pos _U_(16) /**< (AC_COMPCTRL) Speed Selection Position */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) /**< (AC_COMPCTRL) Speed Selection Mask */ +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) /**< (AC_COMPCTRL) High speed Position */ +#define AC_COMPCTRL_HYSTEN_Pos _U_(19) /**< (AC_COMPCTRL) Hysteresis Enable Position */ +#define AC_COMPCTRL_HYSTEN_Msk (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) /**< (AC_COMPCTRL) Hysteresis Enable Mask */ +#define AC_COMPCTRL_HYSTEN(value) (AC_COMPCTRL_HYSTEN_Msk & ((value) << AC_COMPCTRL_HYSTEN_Pos)) +#define AC_COMPCTRL_HYST_Pos _U_(20) /**< (AC_COMPCTRL) Hysteresis Level Position */ +#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) Hysteresis Level Mask */ +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) +#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< (AC_COMPCTRL) 100mV */ +#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< (AC_COMPCTRL) 150mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 50mV Position */ +#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 100mV Position */ +#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 150mV Position */ +#define AC_COMPCTRL_FLEN_Pos _U_(24) /**< (AC_COMPCTRL) Filter Length Position */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) Filter Length Mask */ +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) No filtering Position */ +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) 3-bit majority function (2 of 3) Position */ +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) 5-bit majority function (3 of 5) Position */ +#define AC_COMPCTRL_OUT_Pos _U_(28) /**< (AC_COMPCTRL) Output Position */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) Output Mask */ +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_Msk _U_(0x373BF75E) /**< (AC_COMPCTRL) Register Mask */ + + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) ( R/ 32) Synchronization Busy -------- */ +#define AC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (AC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define AC_SYNCBUSY_SWRST_Pos _U_(0) /**< (AC_SYNCBUSY) Software Reset Synchronization Busy Position */ +#define AC_SYNCBUSY_SWRST_Msk (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) /**< (AC_SYNCBUSY) Software Reset Synchronization Busy Mask */ +#define AC_SYNCBUSY_SWRST(value) (AC_SYNCBUSY_SWRST_Msk & ((value) << AC_SYNCBUSY_SWRST_Pos)) +#define AC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (AC_SYNCBUSY) Enable Synchronization Busy Position */ +#define AC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) /**< (AC_SYNCBUSY) Enable Synchronization Busy Mask */ +#define AC_SYNCBUSY_ENABLE(value) (AC_SYNCBUSY_ENABLE_Msk & ((value) << AC_SYNCBUSY_ENABLE_Pos)) +#define AC_SYNCBUSY_WINCTRL_Pos _U_(2) /**< (AC_SYNCBUSY) WINCTRL Synchronization Busy Position */ +#define AC_SYNCBUSY_WINCTRL_Msk (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) /**< (AC_SYNCBUSY) WINCTRL Synchronization Busy Mask */ +#define AC_SYNCBUSY_WINCTRL(value) (AC_SYNCBUSY_WINCTRL_Msk & ((value) << AC_SYNCBUSY_WINCTRL_Pos)) +#define AC_SYNCBUSY_COMPCTRL0_Pos _U_(3) /**< (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL0_Msk (_U_(0x1) << AC_SYNCBUSY_COMPCTRL0_Pos) /**< (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL0(value) (AC_SYNCBUSY_COMPCTRL0_Msk & ((value) << AC_SYNCBUSY_COMPCTRL0_Pos)) +#define AC_SYNCBUSY_COMPCTRL1_Pos _U_(4) /**< (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL1_Msk (_U_(0x1) << AC_SYNCBUSY_COMPCTRL1_Pos) /**< (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL1(value) (AC_SYNCBUSY_COMPCTRL1_Msk & ((value) << AC_SYNCBUSY_COMPCTRL1_Pos)) +#define AC_SYNCBUSY_Msk _U_(0x0000001F) /**< (AC_SYNCBUSY) Register Mask */ + +#define AC_SYNCBUSY_COMPCTRL_Pos _U_(3) /**< (AC_SYNCBUSY Position) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) /**< (AC_SYNCBUSY Mask) COMPCTRL */ +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) + +/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ +#define AC_CALIB_RESETVALUE _U_(0x101) /**< (AC_CALIB) Calibration Reset Value */ + +#define AC_CALIB_BIAS0_Pos _U_(0) /**< (AC_CALIB) COMP0/1 Bias Scaling Position */ +#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) /**< (AC_CALIB) COMP0/1 Bias Scaling Mask */ +#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) +#define AC_CALIB_Msk _U_(0x0003) /**< (AC_CALIB) Register Mask */ + + +/** \brief AC register offsets definitions */ +#define AC_CTRLA_REG_OFST (0x00) /**< (AC_CTRLA) Control A Offset */ +#define AC_CTRLB_REG_OFST (0x01) /**< (AC_CTRLB) Control B Offset */ +#define AC_EVCTRL_REG_OFST (0x02) /**< (AC_EVCTRL) Event Control Offset */ +#define AC_INTENCLR_REG_OFST (0x04) /**< (AC_INTENCLR) Interrupt Enable Clear Offset */ +#define AC_INTENSET_REG_OFST (0x05) /**< (AC_INTENSET) Interrupt Enable Set Offset */ +#define AC_INTFLAG_REG_OFST (0x06) /**< (AC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define AC_STATUSA_REG_OFST (0x07) /**< (AC_STATUSA) Status A Offset */ +#define AC_STATUSB_REG_OFST (0x08) /**< (AC_STATUSB) Status B Offset */ +#define AC_DBGCTRL_REG_OFST (0x09) /**< (AC_DBGCTRL) Debug Control Offset */ +#define AC_WINCTRL_REG_OFST (0x0A) /**< (AC_WINCTRL) Window Control Offset */ +#define AC_SCALER_REG_OFST (0x0C) /**< (AC_SCALER) Scaler n Offset */ +#define AC_COMPCTRL_REG_OFST (0x10) /**< (AC_COMPCTRL) Comparator Control n Offset */ +#define AC_SYNCBUSY_REG_OFST (0x20) /**< (AC_SYNCBUSY) Synchronization Busy Offset */ +#define AC_CALIB_REG_OFST (0x24) /**< (AC_CALIB) Calibration Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AC register API structure */ +typedef struct +{ /* Analog Comparators */ + __IO uint8_t AC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __O uint8_t AC_CTRLB; /**< Offset: 0x01 ( /W 8) Control B */ + __IO uint16_t AC_EVCTRL; /**< Offset: 0x02 (R/W 16) Event Control */ + __IO uint8_t AC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t AC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t AC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t AC_STATUSA; /**< Offset: 0x07 (R/ 8) Status A */ + __I uint8_t AC_STATUSB; /**< Offset: 0x08 (R/ 8) Status B */ + __IO uint8_t AC_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug Control */ + __IO uint8_t AC_WINCTRL; /**< Offset: 0x0A (R/W 8) Window Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t AC_SCALER[2]; /**< Offset: 0x0C (R/W 8) Scaler n */ + __I uint8_t Reserved2[0x02]; + __IO uint32_t AC_COMPCTRL[2]; /**< Offset: 0x10 (R/W 32) Comparator Control n */ + __I uint8_t Reserved3[0x08]; + __I uint32_t AC_SYNCBUSY; /**< Offset: 0x20 (R/ 32) Synchronization Busy */ + __IO uint16_t AC_CALIB; /**< Offset: 0x24 (R/W 16) Calibration */ +} ac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_AC_COMPONENT_H_ */ diff --git a/arch/arm/SAME54/mcu/inc/component/adc.h b/arch/arm/SAME54/mcu/inc/component/adc.h new file mode 100644 index 00000000..cb78fd2a --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/component/adc.h @@ -0,0 +1,649 @@ +/** + * \brief Component description for ADC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-12T17:27:04Z */ +#ifndef _SAME54_ADC_COMPONENT_H_ +#define _SAME54_ADC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ADC */ +/* ************************************************************************** */ + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ +#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< (ADC_CTRLA) Control A Reset Value */ + +#define ADC_CTRLA_SWRST_Pos _U_(0) /**< (ADC_CTRLA) Software Reset Position */ +#define ADC_CTRLA_SWRST_Msk (_U_(0x1) << ADC_CTRLA_SWRST_Pos) /**< (ADC_CTRLA) Software Reset Mask */ +#define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & ((value) << ADC_CTRLA_SWRST_Pos)) +#define ADC_CTRLA_ENABLE_Pos _U_(1) /**< (ADC_CTRLA) Enable Position */ +#define ADC_CTRLA_ENABLE_Msk (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) /**< (ADC_CTRLA) Enable Mask */ +#define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & ((value) << ADC_CTRLA_ENABLE_Pos)) +#define ADC_CTRLA_DUALSEL_Pos _U_(3) /**< (ADC_CTRLA) Dual Mode Trigger Selection Position */ +#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) Dual Mode Trigger Selection Mask */ +#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) +#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs Position */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 Position */ +#define ADC_CTRLA_SLAVEEN_Pos _U_(5) /**< (ADC_CTRLA) Slave Enable Position */ +#define ADC_CTRLA_SLAVEEN_Msk (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /**< (ADC_CTRLA) Slave Enable Mask */ +#define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & ((value) << ADC_CTRLA_SLAVEEN_Pos)) +#define ADC_CTRLA_RUNSTDBY_Pos _U_(6) /**< (ADC_CTRLA) Run in Standby Position */ +#define ADC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /**< (ADC_CTRLA) Run in Standby Mask */ +#define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & ((value) << ADC_CTRLA_RUNSTDBY_Pos)) +#define ADC_CTRLA_ONDEMAND_Pos _U_(7) /**< (ADC_CTRLA) On Demand Control Position */ +#define ADC_CTRLA_ONDEMAND_Msk (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /**< (ADC_CTRLA) On Demand Control Mask */ +#define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & ((value) << ADC_CTRLA_ONDEMAND_Pos)) +#define ADC_CTRLA_PRESCALER_Pos _U_(8) /**< (ADC_CTRLA) Prescaler Configuration Position */ +#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Prescaler Configuration Mask */ +#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) +#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< (ADC_CTRLA) Peripheral clock divided by 2 */ +#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< (ADC_CTRLA) Peripheral clock divided by 4 */ +#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< (ADC_CTRLA) Peripheral clock divided by 8 */ +#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< (ADC_CTRLA) Peripheral clock divided by 16 */ +#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< (ADC_CTRLA) Peripheral clock divided by 32 */ +#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< (ADC_CTRLA) Peripheral clock divided by 64 */ +#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< (ADC_CTRLA) Peripheral clock divided by 128 */ +#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< (ADC_CTRLA) Peripheral clock divided by 256 */ +#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 2 Position */ +#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 4 Position */ +#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 8 Position */ +#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 16 Position */ +#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 32 Position */ +#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 64 Position */ +#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 128 Position */ +#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 256 Position */ +#define ADC_CTRLA_R2R_Pos _U_(15) /**< (ADC_CTRLA) Rail to Rail Operation Enable Position */ +#define ADC_CTRLA_R2R_Msk (_U_(0x1) << ADC_CTRLA_R2R_Pos) /**< (ADC_CTRLA) Rail to Rail Operation Enable Mask */ +#define ADC_CTRLA_R2R(value) (ADC_CTRLA_R2R_Msk & ((value) << ADC_CTRLA_R2R_Pos)) +#define ADC_CTRLA_Msk _U_(0x87FB) /**< (ADC_CTRLA) Register Mask */ + + +/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< (ADC_EVCTRL) Event Control Reset Value */ + +#define ADC_EVCTRL_FLUSHEI_Pos _U_(0) /**< (ADC_EVCTRL) Flush Event Input Enable Position */ +#define ADC_EVCTRL_FLUSHEI_Msk (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /**< (ADC_EVCTRL) Flush Event Input Enable Mask */ +#define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & ((value) << ADC_EVCTRL_FLUSHEI_Pos)) +#define ADC_EVCTRL_STARTEI_Pos _U_(1) /**< (ADC_EVCTRL) Start Conversion Event Input Enable Position */ +#define ADC_EVCTRL_STARTEI_Msk (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) /**< (ADC_EVCTRL) Start Conversion Event Input Enable Mask */ +#define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & ((value) << ADC_EVCTRL_STARTEI_Pos)) +#define ADC_EVCTRL_FLUSHINV_Pos _U_(2) /**< (ADC_EVCTRL) Flush Event Invert Enable Position */ +#define ADC_EVCTRL_FLUSHINV_Msk (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /**< (ADC_EVCTRL) Flush Event Invert Enable Mask */ +#define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & ((value) << ADC_EVCTRL_FLUSHINV_Pos)) +#define ADC_EVCTRL_STARTINV_Pos _U_(3) /**< (ADC_EVCTRL) Start Conversion Event Invert Enable Position */ +#define ADC_EVCTRL_STARTINV_Msk (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) /**< (ADC_EVCTRL) Start Conversion Event Invert Enable Mask */ +#define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & ((value) << ADC_EVCTRL_STARTINV_Pos)) +#define ADC_EVCTRL_RESRDYEO_Pos _U_(4) /**< (ADC_EVCTRL) Result Ready Event Out Position */ +#define ADC_EVCTRL_RESRDYEO_Msk (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /**< (ADC_EVCTRL) Result Ready Event Out Mask */ +#define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & ((value) << ADC_EVCTRL_RESRDYEO_Pos)) +#define ADC_EVCTRL_WINMONEO_Pos _U_(5) /**< (ADC_EVCTRL) Window Monitor Event Out Position */ +#define ADC_EVCTRL_WINMONEO_Msk (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /**< (ADC_EVCTRL) Window Monitor Event Out Mask */ +#define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & ((value) << ADC_EVCTRL_WINMONEO_Pos)) +#define ADC_EVCTRL_Msk _U_(0x3F) /**< (ADC_EVCTRL) Register Mask */ + + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< (ADC_DBGCTRL) Debug Control Reset Value */ + +#define ADC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (ADC_DBGCTRL) Debug Run Position */ +#define ADC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /**< (ADC_DBGCTRL) Debug Run Mask */ +#define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & ((value) << ADC_DBGCTRL_DBGRUN_Pos)) +#define ADC_DBGCTRL_Msk _U_(0x01) /**< (ADC_DBGCTRL) Register Mask */ + + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x00) /**< (ADC_INPUTCTRL) Input Control Reset Value */ + +#define ADC_INPUTCTRL_MUXPOS_Pos _U_(0) /**< (ADC_INPUTCTRL) Positive Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Positive Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< (ADC_INPUTCTRL) ADC AIN20 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< (ADC_INPUTCTRL) ADC AIN21 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< (ADC_INPUTCTRL) ADC AIN22 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< (ADC_INPUTCTRL) ADC AIN23 Pin */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSP */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSC */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< (ADC_INPUTCTRL) PTC output (only on ADC0) */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN8 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN9 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN10 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN11 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN12 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN13 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN14 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN15 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN16 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN17 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN18 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN19 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN20 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN21 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN22 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN23 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled Core Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled I/O Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Bandgap Voltage Position */ +#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSP Position */ +#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSC Position */ +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) DAC Output Position */ +#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) PTC output (only on ADC0) Position */ +#define ADC_INPUTCTRL_DIFFMODE_Pos _U_(7) /**< (ADC_INPUTCTRL) Differential Mode Position */ +#define ADC_INPUTCTRL_DIFFMODE_Msk (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) /**< (ADC_INPUTCTRL) Differential Mode Mask */ +#define ADC_INPUTCTRL_DIFFMODE(value) (ADC_INPUTCTRL_DIFFMODE_Msk & ((value) << ADC_INPUTCTRL_DIFFMODE_Pos)) +#define ADC_INPUTCTRL_MUXNEG_Pos _U_(8) /**< (ADC_INPUTCTRL) Negative Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) Negative Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) Internal Ground Position */ +#define ADC_INPUTCTRL_DSEQSTOP_Pos _U_(15) /**< (ADC_INPUTCTRL) Stop DMA Sequencing Position */ +#define ADC_INPUTCTRL_DSEQSTOP_Msk (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) /**< (ADC_INPUTCTRL) Stop DMA Sequencing Mask */ +#define ADC_INPUTCTRL_DSEQSTOP(value) (ADC_INPUTCTRL_DSEQSTOP_Msk & ((value) << ADC_INPUTCTRL_DSEQSTOP_Pos)) +#define ADC_INPUTCTRL_Msk _U_(0x9F9F) /**< (ADC_INPUTCTRL) Register Mask */ + + +/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ +#define ADC_CTRLB_RESETVALUE _U_(0x00) /**< (ADC_CTRLB) Control B Reset Value */ + +#define ADC_CTRLB_LEFTADJ_Pos _U_(0) /**< (ADC_CTRLB) Left-Adjusted Result Position */ +#define ADC_CTRLB_LEFTADJ_Msk (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) /**< (ADC_CTRLB) Left-Adjusted Result Mask */ +#define ADC_CTRLB_LEFTADJ(value) (ADC_CTRLB_LEFTADJ_Msk & ((value) << ADC_CTRLB_LEFTADJ_Pos)) +#define ADC_CTRLB_FREERUN_Pos _U_(1) /**< (ADC_CTRLB) Free Running Mode Position */ +#define ADC_CTRLB_FREERUN_Msk (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) /**< (ADC_CTRLB) Free Running Mode Mask */ +#define ADC_CTRLB_FREERUN(value) (ADC_CTRLB_FREERUN_Msk & ((value) << ADC_CTRLB_FREERUN_Pos)) +#define ADC_CTRLB_CORREN_Pos _U_(2) /**< (ADC_CTRLB) Digital Correction Logic Enable Position */ +#define ADC_CTRLB_CORREN_Msk (_U_(0x1) << ADC_CTRLB_CORREN_Pos) /**< (ADC_CTRLB) Digital Correction Logic Enable Mask */ +#define ADC_CTRLB_CORREN(value) (ADC_CTRLB_CORREN_Msk & ((value) << ADC_CTRLB_CORREN_Pos)) +#define ADC_CTRLB_RESSEL_Pos _U_(3) /**< (ADC_CTRLB) Conversion Result Resolution Position */ +#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) Conversion Result Resolution Mask */ +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) +#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 12-bit result Position */ +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) For averaging mode output Position */ +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 10-bit result Position */ +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 8-bit result Position */ +#define ADC_CTRLB_WINMODE_Pos _U_(8) /**< (ADC_CTRLB) Window Monitor Mode Position */ +#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) Window Monitor Mode Mask */ +#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) +#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< (ADC_CTRLB) No window mode (default) */ +#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< (ADC_CTRLB) RESULT > WINLT */ +#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< (ADC_CTRLB) RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< (ADC_CTRLB) WINLT < RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) No window mode (default) Position */ +#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) RESULT > WINLT Position */ +#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) RESULT < WINUT Position */ +#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) WINLT < RESULT < WINUT Position */ +#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) !(WINLT < RESULT < WINUT) Position */ +#define ADC_CTRLB_WINSS_Pos _U_(11) /**< (ADC_CTRLB) Window Single Sample Position */ +#define ADC_CTRLB_WINSS_Msk (_U_(0x1) << ADC_CTRLB_WINSS_Pos) /**< (ADC_CTRLB) Window Single Sample Mask */ +#define ADC_CTRLB_WINSS(value) (ADC_CTRLB_WINSS_Msk & ((value) << ADC_CTRLB_WINSS_Pos)) +#define ADC_CTRLB_Msk _U_(0x0F1F) /**< (ADC_CTRLB) Register Mask */ + + +/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< (ADC_REFCTRL) Reference Control Reset Value */ + +#define ADC_REFCTRL_REFSEL_Pos _U_(0) /**< (ADC_REFCTRL) Reference Selection Position */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) Reference Selection Mask */ +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< (ADC_REFCTRL) External Reference A */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< (ADC_REFCTRL) External Reference B */ +#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< (ADC_REFCTRL) External Reference C (only on ADC1) */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) Internal Bandgap Reference Position */ +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) 1/2 VDDANA Position */ +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) VDDANA Position */ +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference A Position */ +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference B Position */ +#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference C (only on ADC1) Position */ +#define ADC_REFCTRL_REFCOMP_Pos _U_(7) /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */ +#define ADC_REFCTRL_REFCOMP_Msk (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */ +#define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & ((value) << ADC_REFCTRL_REFCOMP_Pos)) +#define ADC_REFCTRL_Msk _U_(0x8F) /**< (ADC_REFCTRL) Register Mask */ + + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< (ADC_AVGCTRL) Average Control Reset Value */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos _U_(0) /**< (ADC_AVGCTRL) Number of Samples to be Collected Position */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) Number of Samples to be Collected Mask */ +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1 sample Position */ +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 2 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 4 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 8 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 16 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 32 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 64 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 128 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 256 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 512 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1024 samples Position */ +#define ADC_AVGCTRL_ADJRES_Pos _U_(4) /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */ +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_Msk _U_(0x7F) /**< (ADC_AVGCTRL) Register Mask */ + + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< (ADC_SAMPCTRL) Sample Time Control Reset Value */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos _U_(0) /**< (ADC_SAMPCTRL) Sampling Time Length Position */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /**< (ADC_SAMPCTRL) Sampling Time Length Mask */ +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos _U_(7) /**< (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */ +#define ADC_SAMPCTRL_OFFCOMP_Msk (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /**< (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */ +#define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & ((value) << ADC_SAMPCTRL_OFFCOMP_Pos)) +#define ADC_SAMPCTRL_Msk _U_(0xBF) /**< (ADC_SAMPCTRL) Register Mask */ + + +/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ +#define ADC_WINLT_RESETVALUE _U_(0x00) /**< (ADC_WINLT) Window Monitor Lower Threshold Reset Value */ + +#define ADC_WINLT_WINLT_Pos _U_(0) /**< (ADC_WINLT) Window Lower Threshold Position */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) /**< (ADC_WINLT) Window Lower Threshold Mask */ +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_Msk _U_(0xFFFF) /**< (ADC_WINLT) Register Mask */ + + +/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ +#define ADC_WINUT_RESETVALUE _U_(0x00) /**< (ADC_WINUT) Window Monitor Upper Threshold Reset Value */ + +#define ADC_WINUT_WINUT_Pos _U_(0) /**< (ADC_WINUT) Window Upper Threshold Position */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) /**< (ADC_WINUT) Window Upper Threshold Mask */ +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_Msk _U_(0xFFFF) /**< (ADC_WINUT) Register Mask */ + + +/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ +#define ADC_GAINCORR_RESETVALUE _U_(0x00) /**< (ADC_GAINCORR) Gain Correction Reset Value */ + +#define ADC_GAINCORR_GAINCORR_Pos _U_(0) /**< (ADC_GAINCORR) Gain Correction Value Position */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /**< (ADC_GAINCORR) Gain Correction Value Mask */ +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_Msk _U_(0x0FFF) /**< (ADC_GAINCORR) Register Mask */ + + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x00) /**< (ADC_OFFSETCORR) Offset Correction Reset Value */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos _U_(0) /**< (ADC_OFFSETCORR) Offset Correction Value Position */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /**< (ADC_OFFSETCORR) Offset Correction Value Mask */ +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_Msk _U_(0x0FFF) /**< (ADC_OFFSETCORR) Register Mask */ + + +/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< (ADC_SWTRIG) Software Trigger Reset Value */ + +#define ADC_SWTRIG_FLUSH_Pos _U_(0) /**< (ADC_SWTRIG) ADC Conversion Flush Position */ +#define ADC_SWTRIG_FLUSH_Msk (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) /**< (ADC_SWTRIG) ADC Conversion Flush Mask */ +#define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & ((value) << ADC_SWTRIG_FLUSH_Pos)) +#define ADC_SWTRIG_START_Pos _U_(1) /**< (ADC_SWTRIG) Start ADC Conversion Position */ +#define ADC_SWTRIG_START_Msk (_U_(0x1) << ADC_SWTRIG_START_Pos) /**< (ADC_SWTRIG) Start ADC Conversion Mask */ +#define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & ((value) << ADC_SWTRIG_START_Pos)) +#define ADC_SWTRIG_Msk _U_(0x03) /**< (ADC_SWTRIG) Register Mask */ + + +/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< (ADC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define ADC_INTENCLR_RESRDY_Pos _U_(0) /**< (ADC_INTENCLR) Result Ready Interrupt Disable Position */ +#define ADC_INTENCLR_RESRDY_Msk (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) /**< (ADC_INTENCLR) Result Ready Interrupt Disable Mask */ +#define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & ((value) << ADC_INTENCLR_RESRDY_Pos)) +#define ADC_INTENCLR_OVERRUN_Pos _U_(1) /**< (ADC_INTENCLR) Overrun Interrupt Disable Position */ +#define ADC_INTENCLR_OVERRUN_Msk (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /**< (ADC_INTENCLR) Overrun Interrupt Disable Mask */ +#define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & ((value) << ADC_INTENCLR_OVERRUN_Pos)) +#define ADC_INTENCLR_WINMON_Pos _U_(2) /**< (ADC_INTENCLR) Window Monitor Interrupt Disable Position */ +#define ADC_INTENCLR_WINMON_Msk (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) /**< (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */ +#define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & ((value) << ADC_INTENCLR_WINMON_Pos)) +#define ADC_INTENCLR_Msk _U_(0x07) /**< (ADC_INTENCLR) Register Mask */ + + +/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< (ADC_INTENSET) Interrupt Enable Set Reset Value */ + +#define ADC_INTENSET_RESRDY_Pos _U_(0) /**< (ADC_INTENSET) Result Ready Interrupt Enable Position */ +#define ADC_INTENSET_RESRDY_Msk (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) /**< (ADC_INTENSET) Result Ready Interrupt Enable Mask */ +#define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & ((value) << ADC_INTENSET_RESRDY_Pos)) +#define ADC_INTENSET_OVERRUN_Pos _U_(1) /**< (ADC_INTENSET) Overrun Interrupt Enable Position */ +#define ADC_INTENSET_OVERRUN_Msk (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) /**< (ADC_INTENSET) Overrun Interrupt Enable Mask */ +#define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & ((value) << ADC_INTENSET_OVERRUN_Pos)) +#define ADC_INTENSET_WINMON_Pos _U_(2) /**< (ADC_INTENSET) Window Monitor Interrupt Enable Position */ +#define ADC_INTENSET_WINMON_Msk (_U_(0x1) << ADC_INTENSET_WINMON_Pos) /**< (ADC_INTENSET) Window Monitor Interrupt Enable Mask */ +#define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & ((value) << ADC_INTENSET_WINMON_Pos)) +#define ADC_INTENSET_Msk _U_(0x07) /**< (ADC_INTENSET) Register Mask */ + + +/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define ADC_INTFLAG_RESRDY_Pos _U_(0) /**< (ADC_INTFLAG) Result Ready Interrupt Flag Position */ +#define ADC_INTFLAG_RESRDY_Msk (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) /**< (ADC_INTFLAG) Result Ready Interrupt Flag Mask */ +#define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & ((value) << ADC_INTFLAG_RESRDY_Pos)) +#define ADC_INTFLAG_OVERRUN_Pos _U_(1) /**< (ADC_INTFLAG) Overrun Interrupt Flag Position */ +#define ADC_INTFLAG_OVERRUN_Msk (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /**< (ADC_INTFLAG) Overrun Interrupt Flag Mask */ +#define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & ((value) << ADC_INTFLAG_OVERRUN_Pos)) +#define ADC_INTFLAG_WINMON_Pos _U_(2) /**< (ADC_INTFLAG) Window Monitor Interrupt Flag Position */ +#define ADC_INTFLAG_WINMON_Msk (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) /**< (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */ +#define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & ((value) << ADC_INTFLAG_WINMON_Pos)) +#define ADC_INTFLAG_Msk _U_(0x07) /**< (ADC_INTFLAG) Register Mask */ + + +/* -------- ADC_STATUS : (ADC Offset: 0x2F) ( R/ 8) Status -------- */ +#define ADC_STATUS_RESETVALUE _U_(0x00) /**< (ADC_STATUS) Status Reset Value */ + +#define ADC_STATUS_ADCBUSY_Pos _U_(0) /**< (ADC_STATUS) ADC Busy Status Position */ +#define ADC_STATUS_ADCBUSY_Msk (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) /**< (ADC_STATUS) ADC Busy Status Mask */ +#define ADC_STATUS_ADCBUSY(value) (ADC_STATUS_ADCBUSY_Msk & ((value) << ADC_STATUS_ADCBUSY_Pos)) +#define ADC_STATUS_WCC_Pos _U_(2) /**< (ADC_STATUS) Window Comparator Counter Position */ +#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) /**< (ADC_STATUS) Window Comparator Counter Mask */ +#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) +#define ADC_STATUS_Msk _U_(0xFD) /**< (ADC_STATUS) Register Mask */ + + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) ( R/ 32) Synchronization Busy -------- */ +#define ADC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (ADC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define ADC_SYNCBUSY_SWRST_Pos _U_(0) /**< (ADC_SYNCBUSY) SWRST Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWRST_Msk (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /**< (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & ((value) << ADC_SYNCBUSY_SWRST_Pos)) +#define ADC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */ +#define ADC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /**< (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */ +#define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & ((value) << ADC_SYNCBUSY_ENABLE_Pos)) +#define ADC_SYNCBUSY_INPUTCTRL_Pos _U_(2) /**< (ADC_SYNCBUSY) Input Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_INPUTCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /**< (ADC_SYNCBUSY) Input Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & ((value) << ADC_SYNCBUSY_INPUTCTRL_Pos)) +#define ADC_SYNCBUSY_CTRLB_Pos _U_(3) /**< (ADC_SYNCBUSY) Control B Synchronization Busy Position */ +#define ADC_SYNCBUSY_CTRLB_Msk (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) /**< (ADC_SYNCBUSY) Control B Synchronization Busy Mask */ +#define ADC_SYNCBUSY_CTRLB(value) (ADC_SYNCBUSY_CTRLB_Msk & ((value) << ADC_SYNCBUSY_CTRLB_Pos)) +#define ADC_SYNCBUSY_REFCTRL_Pos _U_(4) /**< (ADC_SYNCBUSY) Reference Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_REFCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) /**< (ADC_SYNCBUSY) Reference Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_REFCTRL(value) (ADC_SYNCBUSY_REFCTRL_Msk & ((value) << ADC_SYNCBUSY_REFCTRL_Pos)) +#define ADC_SYNCBUSY_AVGCTRL_Pos _U_(5) /**< (ADC_SYNCBUSY) Average Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_AVGCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /**< (ADC_SYNCBUSY) Average Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & ((value) << ADC_SYNCBUSY_AVGCTRL_Pos)) +#define ADC_SYNCBUSY_SAMPCTRL_Pos _U_(6) /**< (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_SAMPCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /**< (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & ((value) << ADC_SYNCBUSY_SAMPCTRL_Pos)) +#define ADC_SYNCBUSY_WINLT_Pos _U_(7) /**< (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINLT_Msk (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /**< (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & ((value) << ADC_SYNCBUSY_WINLT_Pos)) +#define ADC_SYNCBUSY_WINUT_Pos _U_(8) /**< (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINUT_Msk (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /**< (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & ((value) << ADC_SYNCBUSY_WINUT_Pos)) +#define ADC_SYNCBUSY_GAINCORR_Pos _U_(9) /**< (ADC_SYNCBUSY) Gain Correction Synchronization Busy Position */ +#define ADC_SYNCBUSY_GAINCORR_Msk (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /**< (ADC_SYNCBUSY) Gain Correction Synchronization Busy Mask */ +#define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & ((value) << ADC_SYNCBUSY_GAINCORR_Pos)) +#define ADC_SYNCBUSY_OFFSETCORR_Pos _U_(10) /**< (ADC_SYNCBUSY) Offset Correction Synchronization Busy Position */ +#define ADC_SYNCBUSY_OFFSETCORR_Msk (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /**< (ADC_SYNCBUSY) Offset Correction Synchronization Busy Mask */ +#define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & ((value) << ADC_SYNCBUSY_OFFSETCORR_Pos)) +#define ADC_SYNCBUSY_SWTRIG_Pos _U_(11) /**< (ADC_SYNCBUSY) Software Trigger Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWTRIG_Msk (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /**< (ADC_SYNCBUSY) Software Trigger Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & ((value) << ADC_SYNCBUSY_SWTRIG_Pos)) +#define ADC_SYNCBUSY_Msk _U_(0x00000FFF) /**< (ADC_SYNCBUSY) Register Mask */ + + +/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ +#define ADC_DSEQDATA_RESETVALUE _U_(0x00) /**< (ADC_DSEQDATA) DMA Sequencial Data Reset Value */ + +#define ADC_DSEQDATA_DATA_Pos _U_(0) /**< (ADC_DSEQDATA) DMA Sequential Data Position */ +#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) /**< (ADC_DSEQDATA) DMA Sequential Data Mask */ +#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) +#define ADC_DSEQDATA_Msk _U_(0xFFFFFFFF) /**< (ADC_DSEQDATA) Register Mask */ + + +/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ +#define ADC_DSEQCTRL_RESETVALUE _U_(0x00) /**< (ADC_DSEQCTRL) DMA Sequential Control Reset Value */ + +#define ADC_DSEQCTRL_INPUTCTRL_Pos _U_(0) /**< (ADC_DSEQCTRL) Input Control Position */ +#define ADC_DSEQCTRL_INPUTCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) /**< (ADC_DSEQCTRL) Input Control Mask */ +#define ADC_DSEQCTRL_INPUTCTRL(value) (ADC_DSEQCTRL_INPUTCTRL_Msk & ((value) << ADC_DSEQCTRL_INPUTCTRL_Pos)) +#define ADC_DSEQCTRL_CTRLB_Pos _U_(1) /**< (ADC_DSEQCTRL) Control B Position */ +#define ADC_DSEQCTRL_CTRLB_Msk (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) /**< (ADC_DSEQCTRL) Control B Mask */ +#define ADC_DSEQCTRL_CTRLB(value) (ADC_DSEQCTRL_CTRLB_Msk & ((value) << ADC_DSEQCTRL_CTRLB_Pos)) +#define ADC_DSEQCTRL_REFCTRL_Pos _U_(2) /**< (ADC_DSEQCTRL) Reference Control Position */ +#define ADC_DSEQCTRL_REFCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) /**< (ADC_DSEQCTRL) Reference Control Mask */ +#define ADC_DSEQCTRL_REFCTRL(value) (ADC_DSEQCTRL_REFCTRL_Msk & ((value) << ADC_DSEQCTRL_REFCTRL_Pos)) +#define ADC_DSEQCTRL_AVGCTRL_Pos _U_(3) /**< (ADC_DSEQCTRL) Average Control Position */ +#define ADC_DSEQCTRL_AVGCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) /**< (ADC_DSEQCTRL) Average Control Mask */ +#define ADC_DSEQCTRL_AVGCTRL(value) (ADC_DSEQCTRL_AVGCTRL_Msk & ((value) << ADC_DSEQCTRL_AVGCTRL_Pos)) +#define ADC_DSEQCTRL_SAMPCTRL_Pos _U_(4) /**< (ADC_DSEQCTRL) Sampling Time Control Position */ +#define ADC_DSEQCTRL_SAMPCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) /**< (ADC_DSEQCTRL) Sampling Time Control Mask */ +#define ADC_DSEQCTRL_SAMPCTRL(value) (ADC_DSEQCTRL_SAMPCTRL_Msk & ((value) << ADC_DSEQCTRL_SAMPCTRL_Pos)) +#define ADC_DSEQCTRL_WINLT_Pos _U_(5) /**< (ADC_DSEQCTRL) Window Monitor Lower Threshold Position */ +#define ADC_DSEQCTRL_WINLT_Msk (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) /**< (ADC_DSEQCTRL) Window Monitor Lower Threshold Mask */ +#define ADC_DSEQCTRL_WINLT(value) (ADC_DSEQCTRL_WINLT_Msk & ((value) << ADC_DSEQCTRL_WINLT_Pos)) +#define ADC_DSEQCTRL_WINUT_Pos _U_(6) /**< (ADC_DSEQCTRL) Window Monitor Upper Threshold Position */ +#define ADC_DSEQCTRL_WINUT_Msk (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) /**< (ADC_DSEQCTRL) Window Monitor Upper Threshold Mask */ +#define ADC_DSEQCTRL_WINUT(value) (ADC_DSEQCTRL_WINUT_Msk & ((value) << ADC_DSEQCTRL_WINUT_Pos)) +#define ADC_DSEQCTRL_GAINCORR_Pos _U_(7) /**< (ADC_DSEQCTRL) Gain Correction Position */ +#define ADC_DSEQCTRL_GAINCORR_Msk (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) /**< (ADC_DSEQCTRL) Gain Correction Mask */ +#define ADC_DSEQCTRL_GAINCORR(value) (ADC_DSEQCTRL_GAINCORR_Msk & ((value) << ADC_DSEQCTRL_GAINCORR_Pos)) +#define ADC_DSEQCTRL_OFFSETCORR_Pos _U_(8) /**< (ADC_DSEQCTRL) Offset Correction Position */ +#define ADC_DSEQCTRL_OFFSETCORR_Msk (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) /**< (ADC_DSEQCTRL) Offset Correction Mask */ +#define ADC_DSEQCTRL_OFFSETCORR(value) (ADC_DSEQCTRL_OFFSETCORR_Msk & ((value) << ADC_DSEQCTRL_OFFSETCORR_Pos)) +#define ADC_DSEQCTRL_AUTOSTART_Pos _U_(31) /**< (ADC_DSEQCTRL) ADC Auto-Start Conversion Position */ +#define ADC_DSEQCTRL_AUTOSTART_Msk (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) /**< (ADC_DSEQCTRL) ADC Auto-Start Conversion Mask */ +#define ADC_DSEQCTRL_AUTOSTART(value) (ADC_DSEQCTRL_AUTOSTART_Msk & ((value) << ADC_DSEQCTRL_AUTOSTART_Pos)) +#define ADC_DSEQCTRL_Msk _U_(0x800001FF) /**< (ADC_DSEQCTRL) Register Mask */ + + +/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) ( R/ 32) DMA Sequencial Status -------- */ +#define ADC_DSEQSTAT_RESETVALUE _U_(0x00) /**< (ADC_DSEQSTAT) DMA Sequencial Status Reset Value */ + +#define ADC_DSEQSTAT_INPUTCTRL_Pos _U_(0) /**< (ADC_DSEQSTAT) Input Control Position */ +#define ADC_DSEQSTAT_INPUTCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) /**< (ADC_DSEQSTAT) Input Control Mask */ +#define ADC_DSEQSTAT_INPUTCTRL(value) (ADC_DSEQSTAT_INPUTCTRL_Msk & ((value) << ADC_DSEQSTAT_INPUTCTRL_Pos)) +#define ADC_DSEQSTAT_CTRLB_Pos _U_(1) /**< (ADC_DSEQSTAT) Control B Position */ +#define ADC_DSEQSTAT_CTRLB_Msk (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) /**< (ADC_DSEQSTAT) Control B Mask */ +#define ADC_DSEQSTAT_CTRLB(value) (ADC_DSEQSTAT_CTRLB_Msk & ((value) << ADC_DSEQSTAT_CTRLB_Pos)) +#define ADC_DSEQSTAT_REFCTRL_Pos _U_(2) /**< (ADC_DSEQSTAT) Reference Control Position */ +#define ADC_DSEQSTAT_REFCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) /**< (ADC_DSEQSTAT) Reference Control Mask */ +#define ADC_DSEQSTAT_REFCTRL(value) (ADC_DSEQSTAT_REFCTRL_Msk & ((value) << ADC_DSEQSTAT_REFCTRL_Pos)) +#define ADC_DSEQSTAT_AVGCTRL_Pos _U_(3) /**< (ADC_DSEQSTAT) Average Control Position */ +#define ADC_DSEQSTAT_AVGCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) /**< (ADC_DSEQSTAT) Average Control Mask */ +#define ADC_DSEQSTAT_AVGCTRL(value) (ADC_DSEQSTAT_AVGCTRL_Msk & ((value) << ADC_DSEQSTAT_AVGCTRL_Pos)) +#define ADC_DSEQSTAT_SAMPCTRL_Pos _U_(4) /**< (ADC_DSEQSTAT) Sampling Time Control Position */ +#define ADC_DSEQSTAT_SAMPCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) /**< (ADC_DSEQSTAT) Sampling Time Control Mask */ +#define ADC_DSEQSTAT_SAMPCTRL(value) (ADC_DSEQSTAT_SAMPCTRL_Msk & ((value) << ADC_DSEQSTAT_SAMPCTRL_Pos)) +#define ADC_DSEQSTAT_WINLT_Pos _U_(5) /**< (ADC_DSEQSTAT) Window Monitor Lower Threshold Position */ +#define ADC_DSEQSTAT_WINLT_Msk (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) /**< (ADC_DSEQSTAT) Window Monitor Lower Threshold Mask */ +#define ADC_DSEQSTAT_WINLT(value) (ADC_DSEQSTAT_WINLT_Msk & ((value) << ADC_DSEQSTAT_WINLT_Pos)) +#define ADC_DSEQSTAT_WINUT_Pos _U_(6) /**< (ADC_DSEQSTAT) Window Monitor Upper Threshold Position */ +#define ADC_DSEQSTAT_WINUT_Msk (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) /**< (ADC_DSEQSTAT) Window Monitor Upper Threshold Mask */ +#define ADC_DSEQSTAT_WINUT(value) (ADC_DSEQSTAT_WINUT_Msk & ((value) << ADC_DSEQSTAT_WINUT_Pos)) +#define ADC_DSEQSTAT_GAINCORR_Pos _U_(7) /**< (ADC_DSEQSTAT) Gain Correction Position */ +#define ADC_DSEQSTAT_GAINCORR_Msk (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) /**< (ADC_DSEQSTAT) Gain Correction Mask */ +#define ADC_DSEQSTAT_GAINCORR(value) (ADC_DSEQSTAT_GAINCORR_Msk & ((value) << ADC_DSEQSTAT_GAINCORR_Pos)) +#define ADC_DSEQSTAT_OFFSETCORR_Pos _U_(8) /**< (ADC_DSEQSTAT) Offset Correction Position */ +#define ADC_DSEQSTAT_OFFSETCORR_Msk (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) /**< (ADC_DSEQSTAT) Offset Correction Mask */ +#define ADC_DSEQSTAT_OFFSETCORR(value) (ADC_DSEQSTAT_OFFSETCORR_Msk & ((value) << ADC_DSEQSTAT_OFFSETCORR_Pos)) +#define ADC_DSEQSTAT_BUSY_Pos _U_(31) /**< (ADC_DSEQSTAT) DMA Sequencing Busy Position */ +#define ADC_DSEQSTAT_BUSY_Msk (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) /**< (ADC_DSEQSTAT) DMA Sequencing Busy Mask */ +#define ADC_DSEQSTAT_BUSY(value) (ADC_DSEQSTAT_BUSY_Msk & ((value) << ADC_DSEQSTAT_BUSY_Pos)) +#define ADC_DSEQSTAT_Msk _U_(0x800001FF) /**< (ADC_DSEQSTAT) Register Mask */ + + +/* -------- ADC_RESULT : (ADC Offset: 0x40) ( R/ 16) Result Conversion Value -------- */ +#define ADC_RESULT_RESETVALUE _U_(0x00) /**< (ADC_RESULT) Result Conversion Value Reset Value */ + +#define ADC_RESULT_RESULT_Pos _U_(0) /**< (ADC_RESULT) Result Conversion Value Position */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) /**< (ADC_RESULT) Result Conversion Value Mask */ +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_Msk _U_(0xFFFF) /**< (ADC_RESULT) Register Mask */ + + +/* -------- ADC_RESS : (ADC Offset: 0x44) ( R/ 16) Last Sample Result -------- */ +#define ADC_RESS_RESETVALUE _U_(0x00) /**< (ADC_RESS) Last Sample Result Reset Value */ + +#define ADC_RESS_RESS_Pos _U_(0) /**< (ADC_RESS) Last ADC conversion result Position */ +#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) /**< (ADC_RESS) Last ADC conversion result Mask */ +#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) +#define ADC_RESS_Msk _U_(0xFFFF) /**< (ADC_RESS) Register Mask */ + + +/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ +#define ADC_CALIB_RESETVALUE _U_(0x00) /**< (ADC_CALIB) Calibration Reset Value */ + +#define ADC_CALIB_BIASCOMP_Pos _U_(0) /**< (ADC_CALIB) Bias Comparator Scaling Position */ +#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) /**< (ADC_CALIB) Bias Comparator Scaling Mask */ +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASR2R_Pos _U_(4) /**< (ADC_CALIB) Bias R2R Ampli scaling Position */ +#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) /**< (ADC_CALIB) Bias R2R Ampli scaling Mask */ +#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos _U_(8) /**< (ADC_CALIB) Bias Reference Buffer Scaling Position */ +#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /**< (ADC_CALIB) Bias Reference Buffer Scaling Mask */ +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_Msk _U_(0x0777) /**< (ADC_CALIB) Register Mask */ + + +/** \brief ADC register offsets definitions */ +#define ADC_CTRLA_REG_OFST (0x00) /**< (ADC_CTRLA) Control A Offset */ +#define ADC_EVCTRL_REG_OFST (0x02) /**< (ADC_EVCTRL) Event Control Offset */ +#define ADC_DBGCTRL_REG_OFST (0x03) /**< (ADC_DBGCTRL) Debug Control Offset */ +#define ADC_INPUTCTRL_REG_OFST (0x04) /**< (ADC_INPUTCTRL) Input Control Offset */ +#define ADC_CTRLB_REG_OFST (0x06) /**< (ADC_CTRLB) Control B Offset */ +#define ADC_REFCTRL_REG_OFST (0x08) /**< (ADC_REFCTRL) Reference Control Offset */ +#define ADC_AVGCTRL_REG_OFST (0x0A) /**< (ADC_AVGCTRL) Average Control Offset */ +#define ADC_SAMPCTRL_REG_OFST (0x0B) /**< (ADC_SAMPCTRL) Sample Time Control Offset */ +#define ADC_WINLT_REG_OFST (0x0C) /**< (ADC_WINLT) Window Monitor Lower Threshold Offset */ +#define ADC_WINUT_REG_OFST (0x0E) /**< (ADC_WINUT) Window Monitor Upper Threshold Offset */ +#define ADC_GAINCORR_REG_OFST (0x10) /**< (ADC_GAINCORR) Gain Correction Offset */ +#define ADC_OFFSETCORR_REG_OFST (0x12) /**< (ADC_OFFSETCORR) Offset Correction Offset */ +#define ADC_SWTRIG_REG_OFST (0x14) /**< (ADC_SWTRIG) Software Trigger Offset */ +#define ADC_INTENCLR_REG_OFST (0x2C) /**< (ADC_INTENCLR) Interrupt Enable Clear Offset */ +#define ADC_INTENSET_REG_OFST (0x2D) /**< (ADC_INTENSET) Interrupt Enable Set Offset */ +#define ADC_INTFLAG_REG_OFST (0x2E) /**< (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define ADC_STATUS_REG_OFST (0x2F) /**< (ADC_STATUS) Status Offset */ +#define ADC_SYNCBUSY_REG_OFST (0x30) /**< (ADC_SYNCBUSY) Synchronization Busy Offset */ +#define ADC_DSEQDATA_REG_OFST (0x34) /**< (ADC_DSEQDATA) DMA Sequencial Data Offset */ +#define ADC_DSEQCTRL_REG_OFST (0x38) /**< (ADC_DSEQCTRL) DMA Sequential Control Offset */ +#define ADC_DSEQSTAT_REG_OFST (0x3C) /**< (ADC_DSEQSTAT) DMA Sequencial Status Offset */ +#define ADC_RESULT_REG_OFST (0x40) /**< (ADC_RESULT) Result Conversion Value Offset */ +#define ADC_RESS_REG_OFST (0x44) /**< (ADC_RESS) Last Sample Result Offset */ +#define ADC_CALIB_REG_OFST (0x48) /**< (ADC_CALIB) Calibration Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ADC register API structure */ +typedef struct +{ /* Analog Digital Converter */ + __IO uint16_t ADC_CTRLA; /**< Offset: 0x00 (R/W 16) Control A */ + __IO uint8_t ADC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ + __IO uint8_t ADC_DBGCTRL; /**< Offset: 0x03 (R/W 8) Debug Control */ + __IO uint16_t ADC_INPUTCTRL; /**< Offset: 0x04 (R/W 16) Input Control */ + __IO uint16_t ADC_CTRLB; /**< Offset: 0x06 (R/W 16) Control B */ + __IO uint8_t ADC_REFCTRL; /**< Offset: 0x08 (R/W 8) Reference Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t ADC_AVGCTRL; /**< Offset: 0x0A (R/W 8) Average Control */ + __IO uint8_t ADC_SAMPCTRL; /**< Offset: 0x0B (R/W 8) Sample Time Control */ + __IO uint16_t ADC_WINLT; /**< Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ + __IO uint16_t ADC_WINUT; /**< Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ + __IO uint16_t ADC_GAINCORR; /**< Offset: 0x10 (R/W 16) Gain Correction */ + __IO uint16_t ADC_OFFSETCORR; /**< Offset: 0x12 (R/W 16) Offset Correction */ + __IO uint8_t ADC_SWTRIG; /**< Offset: 0x14 (R/W 8) Software Trigger */ + __I uint8_t Reserved2[0x17]; + __IO uint8_t ADC_INTENCLR; /**< Offset: 0x2C (R/W 8) Interrupt Enable Clear */ + __IO uint8_t ADC_INTENSET; /**< Offset: 0x2D (R/W 8) Interrupt Enable Set */ + __IO uint8_t ADC_INTFLAG; /**< Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t ADC_STATUS; /**< Offset: 0x2F (R/ 8) Status */ + __I uint32_t ADC_SYNCBUSY; /**< Offset: 0x30 (R/ 32) Synchronization Busy */ + __O uint32_t ADC_DSEQDATA; /**< Offset: 0x34 ( /W 32) DMA Sequencial Data */ + __IO uint32_t ADC_DSEQCTRL; /**< Offset: 0x38 (R/W 32) DMA Sequential Control */ + __I uint32_t ADC_DSEQSTAT; /**< Offset: 0x3C (R/ 32) DMA Sequencial Status */ + __I uint16_t ADC_RESULT; /**< Offset: 0x40 (R/ 16) Result Conversion Value */ + __I uint8_t Reserved3[0x02]; + __I uint16_t ADC_RESS; /**< Offset: 0x44 (R/ 16) Last Sample Result */ + __I uint8_t Reserved4[0x02]; + __IO uint16_t ADC_CALIB; /**< Offset: 0x48 (R/W 16) Calibration */ +} adc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_ADC_COMPONENT_H_ */ diff --git a/arch/arm/SAME54/mcu/inc/component/aes.h b/arch/arm/SAME54/mcu/inc/component/aes.h new file mode 100644 index 00000000..ed46fe47 --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/component/aes.h @@ -0,0 +1,276 @@ +/** + * \brief Component description for AES + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-12T17:27:04Z */ +#ifndef _SAME54_AES_COMPONENT_H_ +#define _SAME54_AES_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AES */ +/* ************************************************************************** */ + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#define AES_CTRLA_RESETVALUE _U_(0x00) /**< (AES_CTRLA) Control A Reset Value */ + +#define AES_CTRLA_SWRST_Pos _U_(0) /**< (AES_CTRLA) Software Reset Position */ +#define AES_CTRLA_SWRST_Msk (_U_(0x1) << AES_CTRLA_SWRST_Pos) /**< (AES_CTRLA) Software Reset Mask */ +#define AES_CTRLA_SWRST(value) (AES_CTRLA_SWRST_Msk & ((value) << AES_CTRLA_SWRST_Pos)) +#define AES_CTRLA_ENABLE_Pos _U_(1) /**< (AES_CTRLA) Enable Position */ +#define AES_CTRLA_ENABLE_Msk (_U_(0x1) << AES_CTRLA_ENABLE_Pos) /**< (AES_CTRLA) Enable Mask */ +#define AES_CTRLA_ENABLE(value) (AES_CTRLA_ENABLE_Msk & ((value) << AES_CTRLA_ENABLE_Pos)) +#define AES_CTRLA_AESMODE_Pos _U_(2) /**< (AES_CTRLA) AES Modes of operation Position */ +#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) AES Modes of operation Mask */ +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) +#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< (AES_CTRLA) Electronic code book mode */ +#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< (AES_CTRLA) Cipher block chaining mode */ +#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< (AES_CTRLA) Output feedback mode */ +#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< (AES_CTRLA) Cipher feedback mode */ +#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< (AES_CTRLA) Counter mode */ +#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< (AES_CTRLA) CCM mode */ +#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< (AES_CTRLA) Galois counter mode */ +#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Electronic code book mode Position */ +#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher block chaining mode Position */ +#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Output feedback mode Position */ +#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher feedback mode Position */ +#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Counter mode Position */ +#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) CCM mode Position */ +#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Galois counter mode Position */ +#define AES_CTRLA_CFBS_Pos _U_(5) /**< (AES_CTRLA) Cipher Feedback Block Size Position */ +#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) Cipher Feedback Block Size Mask */ +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) +#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_KEYSIZE_Pos _U_(8) /**< (AES_CTRLA) Encryption Key Size Position */ +#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) Encryption Key Size Mask */ +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) +#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_CIPHER_Pos _U_(10) /**< (AES_CTRLA) Cipher Mode Position */ +#define AES_CTRLA_CIPHER_Msk (_U_(0x1) << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Cipher Mode Mask */ +#define AES_CTRLA_CIPHER(value) (AES_CTRLA_CIPHER_Msk & ((value) << AES_CTRLA_CIPHER_Pos)) +#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< (AES_CTRLA) Decryption */ +#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< (AES_CTRLA) Encryption */ +#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Decryption Position */ +#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Encryption Position */ +#define AES_CTRLA_STARTMODE_Pos _U_(11) /**< (AES_CTRLA) Start Mode Select Position */ +#define AES_CTRLA_STARTMODE_Msk (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Mode Select Mask */ +#define AES_CTRLA_STARTMODE(value) (AES_CTRLA_STARTMODE_Msk & ((value) << AES_CTRLA_STARTMODE_Pos)) +#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode */ +#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode */ +#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode Position */ +#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode Position */ +#define AES_CTRLA_LOD_Pos _U_(12) /**< (AES_CTRLA) Last Output Data Mode Position */ +#define AES_CTRLA_LOD_Msk (_U_(0x1) << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Last Output Data Mode Mask */ +#define AES_CTRLA_LOD(value) (AES_CTRLA_LOD_Msk & ((value) << AES_CTRLA_LOD_Pos)) +#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */ +#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start encryption in Last Output Data mode */ +#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) No effect Position */ +#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Start encryption in Last Output Data mode Position */ +#define AES_CTRLA_KEYGEN_Pos _U_(13) /**< (AES_CTRLA) Last Key Generation Position */ +#define AES_CTRLA_KEYGEN_Msk (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Last Key Generation Mask */ +#define AES_CTRLA_KEYGEN(value) (AES_CTRLA_KEYGEN_Msk & ((value) << AES_CTRLA_KEYGEN_Pos)) +#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */ +#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key */ +#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) No effect Position */ +#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key Position */ +#define AES_CTRLA_XORKEY_Pos _U_(14) /**< (AES_CTRLA) XOR Key Operation Position */ +#define AES_CTRLA_XORKEY_Msk (_U_(0x1) << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) XOR Key Operation Mask */ +#define AES_CTRLA_XORKEY(value) (AES_CTRLA_XORKEY_Msk & ((value) << AES_CTRLA_XORKEY_Pos)) +#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */ +#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ +#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) No effect Position */ +#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. Position */ +#define AES_CTRLA_CTYPE_Pos _U_(16) /**< (AES_CTRLA) Counter Measure Type Position */ +#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) /**< (AES_CTRLA) Counter Measure Type Mask */ +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) +#define AES_CTRLA_Msk _U_(0x000F7FFF) /**< (AES_CTRLA) Register Mask */ + + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#define AES_CTRLB_RESETVALUE _U_(0x00) /**< (AES_CTRLB) Control B Reset Value */ + +#define AES_CTRLB_START_Pos _U_(0) /**< (AES_CTRLB) Start Encryption/Decryption Position */ +#define AES_CTRLB_START_Msk (_U_(0x1) << AES_CTRLB_START_Pos) /**< (AES_CTRLB) Start Encryption/Decryption Mask */ +#define AES_CTRLB_START(value) (AES_CTRLB_START_Msk & ((value) << AES_CTRLB_START_Pos)) +#define AES_CTRLB_NEWMSG_Pos _U_(1) /**< (AES_CTRLB) New message Position */ +#define AES_CTRLB_NEWMSG_Msk (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) /**< (AES_CTRLB) New message Mask */ +#define AES_CTRLB_NEWMSG(value) (AES_CTRLB_NEWMSG_Msk & ((value) << AES_CTRLB_NEWMSG_Pos)) +#define AES_CTRLB_EOM_Pos _U_(2) /**< (AES_CTRLB) End of message Position */ +#define AES_CTRLB_EOM_Msk (_U_(0x1) << AES_CTRLB_EOM_Pos) /**< (AES_CTRLB) End of message Mask */ +#define AES_CTRLB_EOM(value) (AES_CTRLB_EOM_Msk & ((value) << AES_CTRLB_EOM_Pos)) +#define AES_CTRLB_GFMUL_Pos _U_(3) /**< (AES_CTRLB) GF Multiplication Position */ +#define AES_CTRLB_GFMUL_Msk (_U_(0x1) << AES_CTRLB_GFMUL_Pos) /**< (AES_CTRLB) GF Multiplication Mask */ +#define AES_CTRLB_GFMUL(value) (AES_CTRLB_GFMUL_Msk & ((value) << AES_CTRLB_GFMUL_Pos)) +#define AES_CTRLB_Msk _U_(0x0F) /**< (AES_CTRLB) Register Mask */ + + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< (AES_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define AES_INTENCLR_ENCCMP_Pos _U_(0) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Position */ +#define AES_INTENCLR_ENCCMP_Msk (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Mask */ +#define AES_INTENCLR_ENCCMP(value) (AES_INTENCLR_ENCCMP_Msk & ((value) << AES_INTENCLR_ENCCMP_Pos)) +#define AES_INTENCLR_GFMCMP_Pos _U_(1) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Position */ +#define AES_INTENCLR_GFMCMP_Msk (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Mask */ +#define AES_INTENCLR_GFMCMP(value) (AES_INTENCLR_GFMCMP_Msk & ((value) << AES_INTENCLR_GFMCMP_Pos)) +#define AES_INTENCLR_Msk _U_(0x03) /**< (AES_INTENCLR) Register Mask */ + + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#define AES_INTENSET_RESETVALUE _U_(0x00) /**< (AES_INTENSET) Interrupt Enable Set Reset Value */ + +#define AES_INTENSET_ENCCMP_Pos _U_(0) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Position */ +#define AES_INTENSET_ENCCMP_Msk (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Mask */ +#define AES_INTENSET_ENCCMP(value) (AES_INTENSET_ENCCMP_Msk & ((value) << AES_INTENSET_ENCCMP_Pos)) +#define AES_INTENSET_GFMCMP_Pos _U_(1) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Position */ +#define AES_INTENSET_GFMCMP_Msk (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Mask */ +#define AES_INTENSET_GFMCMP(value) (AES_INTENSET_GFMCMP_Msk & ((value) << AES_INTENSET_GFMCMP_Pos)) +#define AES_INTENSET_Msk _U_(0x03) /**< (AES_INTENSET) Register Mask */ + + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< (AES_INTFLAG) Interrupt Flag Status Reset Value */ + +#define AES_INTFLAG_ENCCMP_Pos _U_(0) /**< (AES_INTFLAG) Encryption Complete Position */ +#define AES_INTFLAG_ENCCMP_Msk (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) /**< (AES_INTFLAG) Encryption Complete Mask */ +#define AES_INTFLAG_ENCCMP(value) (AES_INTFLAG_ENCCMP_Msk & ((value) << AES_INTFLAG_ENCCMP_Pos)) +#define AES_INTFLAG_GFMCMP_Pos _U_(1) /**< (AES_INTFLAG) GF Multiplication Complete Position */ +#define AES_INTFLAG_GFMCMP_Msk (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) /**< (AES_INTFLAG) GF Multiplication Complete Mask */ +#define AES_INTFLAG_GFMCMP(value) (AES_INTFLAG_GFMCMP_Msk & ((value) << AES_INTFLAG_GFMCMP_Pos)) +#define AES_INTFLAG_Msk _U_(0x03) /**< (AES_INTFLAG) Register Mask */ + + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< (AES_DATABUFPTR) Data buffer pointer Reset Value */ + +#define AES_DATABUFPTR_INDATAPTR_Pos _U_(0) /**< (AES_DATABUFPTR) Input Data Pointer Position */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) /**< (AES_DATABUFPTR) Input Data Pointer Mask */ +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) +#define AES_DATABUFPTR_Msk _U_(0x03) /**< (AES_DATABUFPTR) Register Mask */ + + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ +#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< (AES_DBGCTRL) Debug control Reset Value */ + +#define AES_DBGCTRL_DBGRUN_Pos _U_(0) /**< (AES_DBGCTRL) Debug Run Position */ +#define AES_DBGCTRL_DBGRUN_Msk (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) /**< (AES_DBGCTRL) Debug Run Mask */ +#define AES_DBGCTRL_DBGRUN(value) (AES_DBGCTRL_DBGRUN_Msk & ((value) << AES_DBGCTRL_DBGRUN_Pos)) +#define AES_DBGCTRL_Msk _U_(0x01) /**< (AES_DBGCTRL) Register Mask */ + + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#define AES_KEYWORD_RESETVALUE _U_(0x00) /**< (AES_KEYWORD) Keyword n Reset Value */ + +#define AES_KEYWORD_Msk _U_(0x00000000) /**< (AES_KEYWORD) Register Mask */ + + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#define AES_INDATA_RESETVALUE _U_(0x00) /**< (AES_INDATA) Indata Reset Value */ + +#define AES_INDATA_Msk _U_(0x00000000) /**< (AES_INDATA) Register Mask */ + + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#define AES_INTVECTV_RESETVALUE _U_(0x00) /**< (AES_INTVECTV) Initialisation Vector n Reset Value */ + +#define AES_INTVECTV_Msk _U_(0x00000000) /**< (AES_INTVECTV) Register Mask */ + + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#define AES_HASHKEY_RESETVALUE _U_(0x00) /**< (AES_HASHKEY) Hash key n Reset Value */ + +#define AES_HASHKEY_Msk _U_(0x00000000) /**< (AES_HASHKEY) Register Mask */ + + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#define AES_GHASH_RESETVALUE _U_(0x00) /**< (AES_GHASH) Galois Hash n Reset Value */ + +#define AES_GHASH_Msk _U_(0x00000000) /**< (AES_GHASH) Register Mask */ + + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#define AES_CIPLEN_RESETVALUE _U_(0x00) /**< (AES_CIPLEN) Cipher Length Reset Value */ + +#define AES_CIPLEN_Msk _U_(0x00000000) /**< (AES_CIPLEN) Register Mask */ + + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#define AES_RANDSEED_RESETVALUE _U_(0x00) /**< (AES_RANDSEED) Random Seed Reset Value */ + +#define AES_RANDSEED_Msk _U_(0x00000000) /**< (AES_RANDSEED) Register Mask */ + + +/** \brief AES register offsets definitions */ +#define AES_CTRLA_REG_OFST (0x00) /**< (AES_CTRLA) Control A Offset */ +#define AES_CTRLB_REG_OFST (0x04) /**< (AES_CTRLB) Control B Offset */ +#define AES_INTENCLR_REG_OFST (0x05) /**< (AES_INTENCLR) Interrupt Enable Clear Offset */ +#define AES_INTENSET_REG_OFST (0x06) /**< (AES_INTENSET) Interrupt Enable Set Offset */ +#define AES_INTFLAG_REG_OFST (0x07) /**< (AES_INTFLAG) Interrupt Flag Status Offset */ +#define AES_DATABUFPTR_REG_OFST (0x08) /**< (AES_DATABUFPTR) Data buffer pointer Offset */ +#define AES_DBGCTRL_REG_OFST (0x09) /**< (AES_DBGCTRL) Debug control Offset */ +#define AES_KEYWORD_REG_OFST (0x0C) /**< (AES_KEYWORD) Keyword n Offset */ +#define AES_INDATA_REG_OFST (0x38) /**< (AES_INDATA) Indata Offset */ +#define AES_INTVECTV_REG_OFST (0x3C) /**< (AES_INTVECTV) Initialisation Vector n Offset */ +#define AES_HASHKEY_REG_OFST (0x5C) /**< (AES_HASHKEY) Hash key n Offset */ +#define AES_GHASH_REG_OFST (0x6C) /**< (AES_GHASH) Galois Hash n Offset */ +#define AES_CIPLEN_REG_OFST (0x80) /**< (AES_CIPLEN) Cipher Length Offset */ +#define AES_RANDSEED_REG_OFST (0x84) /**< (AES_RANDSEED) Random Seed Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AES register API structure */ +typedef struct +{ /* Advanced Encryption Standard */ + __IO uint32_t AES_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */ + __IO uint8_t AES_CTRLB; /**< Offset: 0x04 (R/W 8) Control B */ + __IO uint8_t AES_INTENCLR; /**< Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t AES_INTENSET; /**< Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO uint8_t AES_INTFLAG; /**< Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO uint8_t AES_DATABUFPTR; /**< Offset: 0x08 (R/W 8) Data buffer pointer */ + __IO uint8_t AES_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug control */ + __I uint8_t Reserved1[0x02]; + __O uint32_t AES_KEYWORD[8]; /**< Offset: 0x0C ( /W 32) Keyword n */ + __I uint8_t Reserved2[0x0C]; + __IO uint32_t AES_INDATA; /**< Offset: 0x38 (R/W 32) Indata */ + __O uint32_t AES_INTVECTV[4]; /**< Offset: 0x3C ( /W 32) Initialisation Vector n */ + __I uint8_t Reserved3[0x10]; + __IO uint32_t AES_HASHKEY[4]; /**< Offset: 0x5C (R/W 32) Hash key n */ + __IO uint32_t AES_GHASH[4]; /**< Offset: 0x6C (R/W 32) Galois Hash n */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t AES_CIPLEN; /**< Offset: 0x80 (R/W 32) Cipher Length */ + __IO uint32_t AES_RANDSEED; /**< Offset: 0x84 (R/W 32) Random Seed */ +} aes_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_AES_COMPONENT_H_ */ diff --git a/arch/arm/SAME54/mcu/inc/component/can.h b/arch/arm/SAME54/mcu/inc/component/can.h new file mode 100644 index 00000000..970b5f37 --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/component/can.h @@ -0,0 +1,2527 @@ +/** + * \brief Component description for CAN + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-12T17:27:04Z */ +#ifndef _SAME54_CAN_COMPONENT_H_ +#define _SAME54_CAN_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CAN */ +/* ************************************************************************** */ + +/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#define CAN_RXBE_0_ID_Pos _U_(0) /**< (CAN_RXBE_0) Identifier Position */ +#define CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) /**< (CAN_RXBE_0) Identifier Mask */ +#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos)) +#define CAN_RXBE_0_RTR_Pos _U_(29) /**< (CAN_RXBE_0) Remote Transmission Request Position */ +#define CAN_RXBE_0_RTR_Msk (_U_(0x1) << CAN_RXBE_0_RTR_Pos) /**< (CAN_RXBE_0) Remote Transmission Request Mask */ +#define CAN_RXBE_0_RTR(value) (CAN_RXBE_0_RTR_Msk & ((value) << CAN_RXBE_0_RTR_Pos)) +#define CAN_RXBE_0_XTD_Pos _U_(30) /**< (CAN_RXBE_0) Extended Identifier Position */ +#define CAN_RXBE_0_XTD_Msk (_U_(0x1) << CAN_RXBE_0_XTD_Pos) /**< (CAN_RXBE_0) Extended Identifier Mask */ +#define CAN_RXBE_0_XTD(value) (CAN_RXBE_0_XTD_Msk & ((value) << CAN_RXBE_0_XTD_Pos)) +#define CAN_RXBE_0_ESI_Pos _U_(31) /**< (CAN_RXBE_0) Error State Indicator Position */ +#define CAN_RXBE_0_ESI_Msk (_U_(0x1) << CAN_RXBE_0_ESI_Pos) /**< (CAN_RXBE_0) Error State Indicator Mask */ +#define CAN_RXBE_0_ESI(value) (CAN_RXBE_0_ESI_Msk & ((value) << CAN_RXBE_0_ESI_Pos)) +#define CAN_RXBE_0_Msk _U_(0xFFFFFFFF) /**< (CAN_RXBE_0) Register Mask */ + + +/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#define CAN_RXBE_1_RXTS_Pos _U_(0) /**< (CAN_RXBE_1) Rx Timestamp Position */ +#define CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) /**< (CAN_RXBE_1) Rx Timestamp Mask */ +#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos)) +#define CAN_RXBE_1_DLC_Pos _U_(16) /**< (CAN_RXBE_1) Data Length Code Position */ +#define CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos) /**< (CAN_RXBE_1) Data Length Code Mask */ +#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos)) +#define CAN_RXBE_1_BRS_Pos _U_(20) /**< (CAN_RXBE_1) Bit Rate Switch Position */ +#define CAN_RXBE_1_BRS_Msk (_U_(0x1) << CAN_RXBE_1_BRS_Pos) /**< (CAN_RXBE_1) Bit Rate Switch Mask */ +#define CAN_RXBE_1_BRS(value) (CAN_RXBE_1_BRS_Msk & ((value) << CAN_RXBE_1_BRS_Pos)) +#define CAN_RXBE_1_FDF_Pos _U_(21) /**< (CAN_RXBE_1) FD Format Position */ +#define CAN_RXBE_1_FDF_Msk (_U_(0x1) << CAN_RXBE_1_FDF_Pos) /**< (CAN_RXBE_1) FD Format Mask */ +#define CAN_RXBE_1_FDF(value) (CAN_RXBE_1_FDF_Msk & ((value) << CAN_RXBE_1_FDF_Pos)) +#define CAN_RXBE_1_FIDX_Pos _U_(24) /**< (CAN_RXBE_1) Filter Index Position */ +#define CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos) /**< (CAN_RXBE_1) Filter Index Mask */ +#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos)) +#define CAN_RXBE_1_ANMF_Pos _U_(31) /**< (CAN_RXBE_1) Accepted Non-matching Frame Position */ +#define CAN_RXBE_1_ANMF_Msk (_U_(0x1) << CAN_RXBE_1_ANMF_Pos) /**< (CAN_RXBE_1) Accepted Non-matching Frame Mask */ +#define CAN_RXBE_1_ANMF(value) (CAN_RXBE_1_ANMF_Msk & ((value) << CAN_RXBE_1_ANMF_Pos)) +#define CAN_RXBE_1_Msk _U_(0xFF3FFFFF) /**< (CAN_RXBE_1) Register Mask */ + + +/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#define CAN_RXBE_DATA_DB0_Pos _U_(0) /**< (CAN_RXBE_DATA) Data Byte 0 Position */ +#define CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos) /**< (CAN_RXBE_DATA) Data Byte 0 Mask */ +#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos)) +#define CAN_RXBE_DATA_DB1_Pos _U_(8) /**< (CAN_RXBE_DATA) Data Byte 1 Position */ +#define CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos) /**< (CAN_RXBE_DATA) Data Byte 1 Mask */ +#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos)) +#define CAN_RXBE_DATA_DB2_Pos _U_(16) /**< (CAN_RXBE_DATA) Data Byte 2 Position */ +#define CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos) /**< (CAN_RXBE_DATA) Data Byte 2 Mask */ +#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos)) +#define CAN_RXBE_DATA_DB3_Pos _U_(24) /**< (CAN_RXBE_DATA) Data Byte 3 Position */ +#define CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos) /**< (CAN_RXBE_DATA) Data Byte 3 Mask */ +#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos)) +#define CAN_RXBE_DATA_Msk _U_(0xFFFFFFFF) /**< (CAN_RXBE_DATA) Register Mask */ + + +/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#define CAN_RXF0E_0_ID_Pos _U_(0) /**< (CAN_RXF0E_0) Identifier Position */ +#define CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) /**< (CAN_RXF0E_0) Identifier Mask */ +#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos)) +#define CAN_RXF0E_0_RTR_Pos _U_(29) /**< (CAN_RXF0E_0) Remote Transmission Request Position */ +#define CAN_RXF0E_0_RTR_Msk (_U_(0x1) << CAN_RXF0E_0_RTR_Pos) /**< (CAN_RXF0E_0) Remote Transmission Request Mask */ +#define CAN_RXF0E_0_RTR(value) (CAN_RXF0E_0_RTR_Msk & ((value) << CAN_RXF0E_0_RTR_Pos)) +#define CAN_RXF0E_0_XTD_Pos _U_(30) /**< (CAN_RXF0E_0) Extended Identifier Position */ +#define CAN_RXF0E_0_XTD_Msk (_U_(0x1) << CAN_RXF0E_0_XTD_Pos) /**< (CAN_RXF0E_0) Extended Identifier Mask */ +#define CAN_RXF0E_0_XTD(value) (CAN_RXF0E_0_XTD_Msk & ((value) << CAN_RXF0E_0_XTD_Pos)) +#define CAN_RXF0E_0_ESI_Pos _U_(31) /**< (CAN_RXF0E_0) Error State Indicator Position */ +#define CAN_RXF0E_0_ESI_Msk (_U_(0x1) << CAN_RXF0E_0_ESI_Pos) /**< (CAN_RXF0E_0) Error State Indicator Mask */ +#define CAN_RXF0E_0_ESI(value) (CAN_RXF0E_0_ESI_Msk & ((value) << CAN_RXF0E_0_ESI_Pos)) +#define CAN_RXF0E_0_Msk _U_(0xFFFFFFFF) /**< (CAN_RXF0E_0) Register Mask */ + + +/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#define CAN_RXF0E_1_RXTS_Pos _U_(0) /**< (CAN_RXF0E_1) Rx Timestamp Position */ +#define CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) /**< (CAN_RXF0E_1) Rx Timestamp Mask */ +#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos)) +#define CAN_RXF0E_1_DLC_Pos _U_(16) /**< (CAN_RXF0E_1) Data Length Code Position */ +#define CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos) /**< (CAN_RXF0E_1) Data Length Code Mask */ +#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos)) +#define CAN_RXF0E_1_BRS_Pos _U_(20) /**< (CAN_RXF0E_1) Bit Rate Switch Position */ +#define CAN_RXF0E_1_BRS_Msk (_U_(0x1) << CAN_RXF0E_1_BRS_Pos) /**< (CAN_RXF0E_1) Bit Rate Switch Mask */ +#define CAN_RXF0E_1_BRS(value) (CAN_RXF0E_1_BRS_Msk & ((value) << CAN_RXF0E_1_BRS_Pos)) +#define CAN_RXF0E_1_FDF_Pos _U_(21) /**< (CAN_RXF0E_1) FD Format Position */ +#define CAN_RXF0E_1_FDF_Msk (_U_(0x1) << CAN_RXF0E_1_FDF_Pos) /**< (CAN_RXF0E_1) FD Format Mask */ +#define CAN_RXF0E_1_FDF(value) (CAN_RXF0E_1_FDF_Msk & ((value) << CAN_RXF0E_1_FDF_Pos)) +#define CAN_RXF0E_1_FIDX_Pos _U_(24) /**< (CAN_RXF0E_1) Filter Index Position */ +#define CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos) /**< (CAN_RXF0E_1) Filter Index Mask */ +#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos)) +#define CAN_RXF0E_1_ANMF_Pos _U_(31) /**< (CAN_RXF0E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF0E_1_ANMF_Msk (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos) /**< (CAN_RXF0E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF0E_1_ANMF(value) (CAN_RXF0E_1_ANMF_Msk & ((value) << CAN_RXF0E_1_ANMF_Pos)) +#define CAN_RXF0E_1_Msk _U_(0xFF3FFFFF) /**< (CAN_RXF0E_1) Register Mask */ + + +/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#define CAN_RXF0E_DATA_DB0_Pos _U_(0) /**< (CAN_RXF0E_DATA) Data Byte 0 Position */ +#define CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) /**< (CAN_RXF0E_DATA) Data Byte 0 Mask */ +#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos)) +#define CAN_RXF0E_DATA_DB1_Pos _U_(8) /**< (CAN_RXF0E_DATA) Data Byte 1 Position */ +#define CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) /**< (CAN_RXF0E_DATA) Data Byte 1 Mask */ +#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos)) +#define CAN_RXF0E_DATA_DB2_Pos _U_(16) /**< (CAN_RXF0E_DATA) Data Byte 2 Position */ +#define CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) /**< (CAN_RXF0E_DATA) Data Byte 2 Mask */ +#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos)) +#define CAN_RXF0E_DATA_DB3_Pos _U_(24) /**< (CAN_RXF0E_DATA) Data Byte 3 Position */ +#define CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) /**< (CAN_RXF0E_DATA) Data Byte 3 Mask */ +#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos)) +#define CAN_RXF0E_DATA_Msk _U_(0xFFFFFFFF) /**< (CAN_RXF0E_DATA) Register Mask */ + + +/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#define CAN_RXF1E_0_ID_Pos _U_(0) /**< (CAN_RXF1E_0) Identifier Position */ +#define CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) /**< (CAN_RXF1E_0) Identifier Mask */ +#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos)) +#define CAN_RXF1E_0_RTR_Pos _U_(29) /**< (CAN_RXF1E_0) Remote Transmission Request Position */ +#define CAN_RXF1E_0_RTR_Msk (_U_(0x1) << CAN_RXF1E_0_RTR_Pos) /**< (CAN_RXF1E_0) Remote Transmission Request Mask */ +#define CAN_RXF1E_0_RTR(value) (CAN_RXF1E_0_RTR_Msk & ((value) << CAN_RXF1E_0_RTR_Pos)) +#define CAN_RXF1E_0_XTD_Pos _U_(30) /**< (CAN_RXF1E_0) Extended Identifier Position */ +#define CAN_RXF1E_0_XTD_Msk (_U_(0x1) << CAN_RXF1E_0_XTD_Pos) /**< (CAN_RXF1E_0) Extended Identifier Mask */ +#define CAN_RXF1E_0_XTD(value) (CAN_RXF1E_0_XTD_Msk & ((value) << CAN_RXF1E_0_XTD_Pos)) +#define CAN_RXF1E_0_ESI_Pos _U_(31) /**< (CAN_RXF1E_0) Error State Indicator Position */ +#define CAN_RXF1E_0_ESI_Msk (_U_(0x1) << CAN_RXF1E_0_ESI_Pos) /**< (CAN_RXF1E_0) Error State Indicator Mask */ +#define CAN_RXF1E_0_ESI(value) (CAN_RXF1E_0_ESI_Msk & ((value) << CAN_RXF1E_0_ESI_Pos)) +#define CAN_RXF1E_0_Msk _U_(0xFFFFFFFF) /**< (CAN_RXF1E_0) Register Mask */ + + +/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#define CAN_RXF1E_1_RXTS_Pos _U_(0) /**< (CAN_RXF1E_1) Rx Timestamp Position */ +#define CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) /**< (CAN_RXF1E_1) Rx Timestamp Mask */ +#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos)) +#define CAN_RXF1E_1_DLC_Pos _U_(16) /**< (CAN_RXF1E_1) Data Length Code Position */ +#define CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos) /**< (CAN_RXF1E_1) Data Length Code Mask */ +#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos)) +#define CAN_RXF1E_1_BRS_Pos _U_(20) /**< (CAN_RXF1E_1) Bit Rate Switch Position */ +#define CAN_RXF1E_1_BRS_Msk (_U_(0x1) << CAN_RXF1E_1_BRS_Pos) /**< (CAN_RXF1E_1) Bit Rate Switch Mask */ +#define CAN_RXF1E_1_BRS(value) (CAN_RXF1E_1_BRS_Msk & ((value) << CAN_RXF1E_1_BRS_Pos)) +#define CAN_RXF1E_1_FDF_Pos _U_(21) /**< (CAN_RXF1E_1) FD Format Position */ +#define CAN_RXF1E_1_FDF_Msk (_U_(0x1) << CAN_RXF1E_1_FDF_Pos) /**< (CAN_RXF1E_1) FD Format Mask */ +#define CAN_RXF1E_1_FDF(value) (CAN_RXF1E_1_FDF_Msk & ((value) << CAN_RXF1E_1_FDF_Pos)) +#define CAN_RXF1E_1_FIDX_Pos _U_(24) /**< (CAN_RXF1E_1) Filter Index Position */ +#define CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos) /**< (CAN_RXF1E_1) Filter Index Mask */ +#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos)) +#define CAN_RXF1E_1_ANMF_Pos _U_(31) /**< (CAN_RXF1E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF1E_1_ANMF_Msk (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos) /**< (CAN_RXF1E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF1E_1_ANMF(value) (CAN_RXF1E_1_ANMF_Msk & ((value) << CAN_RXF1E_1_ANMF_Pos)) +#define CAN_RXF1E_1_Msk _U_(0xFF3FFFFF) /**< (CAN_RXF1E_1) Register Mask */ + + +/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#define CAN_RXF1E_DATA_DB0_Pos _U_(0) /**< (CAN_RXF1E_DATA) Data Byte 0 Position */ +#define CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) /**< (CAN_RXF1E_DATA) Data Byte 0 Mask */ +#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos)) +#define CAN_RXF1E_DATA_DB1_Pos _U_(8) /**< (CAN_RXF1E_DATA) Data Byte 1 Position */ +#define CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) /**< (CAN_RXF1E_DATA) Data Byte 1 Mask */ +#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos)) +#define CAN_RXF1E_DATA_DB2_Pos _U_(16) /**< (CAN_RXF1E_DATA) Data Byte 2 Position */ +#define CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) /**< (CAN_RXF1E_DATA) Data Byte 2 Mask */ +#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos)) +#define CAN_RXF1E_DATA_DB3_Pos _U_(24) /**< (CAN_RXF1E_DATA) Data Byte 3 Position */ +#define CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) /**< (CAN_RXF1E_DATA) Data Byte 3 Mask */ +#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos)) +#define CAN_RXF1E_DATA_Msk _U_(0xFFFFFFFF) /**< (CAN_RXF1E_DATA) Register Mask */ + + +/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#define CAN_TXBE_0_ID_Pos _U_(0) /**< (CAN_TXBE_0) Identifier Position */ +#define CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) /**< (CAN_TXBE_0) Identifier Mask */ +#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos)) +#define CAN_TXBE_0_RTR_Pos _U_(29) /**< (CAN_TXBE_0) Remote Transmission Request Position */ +#define CAN_TXBE_0_RTR_Msk (_U_(0x1) << CAN_TXBE_0_RTR_Pos) /**< (CAN_TXBE_0) Remote Transmission Request Mask */ +#define CAN_TXBE_0_RTR(value) (CAN_TXBE_0_RTR_Msk & ((value) << CAN_TXBE_0_RTR_Pos)) +#define CAN_TXBE_0_XTD_Pos _U_(30) /**< (CAN_TXBE_0) Extended Identifier Position */ +#define CAN_TXBE_0_XTD_Msk (_U_(0x1) << CAN_TXBE_0_XTD_Pos) /**< (CAN_TXBE_0) Extended Identifier Mask */ +#define CAN_TXBE_0_XTD(value) (CAN_TXBE_0_XTD_Msk & ((value) << CAN_TXBE_0_XTD_Pos)) +#define CAN_TXBE_0_ESI_Pos _U_(31) /**< (CAN_TXBE_0) Error State Indicator Position */ +#define CAN_TXBE_0_ESI_Msk (_U_(0x1) << CAN_TXBE_0_ESI_Pos) /**< (CAN_TXBE_0) Error State Indicator Mask */ +#define CAN_TXBE_0_ESI(value) (CAN_TXBE_0_ESI_Msk & ((value) << CAN_TXBE_0_ESI_Pos)) +#define CAN_TXBE_0_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBE_0) Register Mask */ + + +/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#define CAN_TXBE_1_DLC_Pos _U_(16) /**< (CAN_TXBE_1) Data Length Code Position */ +#define CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos) /**< (CAN_TXBE_1) Data Length Code Mask */ +#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos)) +#define CAN_TXBE_1_BRS_Pos _U_(20) /**< (CAN_TXBE_1) Bit Rate Switch Position */ +#define CAN_TXBE_1_BRS_Msk (_U_(0x1) << CAN_TXBE_1_BRS_Pos) /**< (CAN_TXBE_1) Bit Rate Switch Mask */ +#define CAN_TXBE_1_BRS(value) (CAN_TXBE_1_BRS_Msk & ((value) << CAN_TXBE_1_BRS_Pos)) +#define CAN_TXBE_1_FDF_Pos _U_(21) /**< (CAN_TXBE_1) FD Format Position */ +#define CAN_TXBE_1_FDF_Msk (_U_(0x1) << CAN_TXBE_1_FDF_Pos) /**< (CAN_TXBE_1) FD Format Mask */ +#define CAN_TXBE_1_FDF(value) (CAN_TXBE_1_FDF_Msk & ((value) << CAN_TXBE_1_FDF_Pos)) +#define CAN_TXBE_1_EFC_Pos _U_(23) /**< (CAN_TXBE_1) Event FIFO Control Position */ +#define CAN_TXBE_1_EFC_Msk (_U_(0x1) << CAN_TXBE_1_EFC_Pos) /**< (CAN_TXBE_1) Event FIFO Control Mask */ +#define CAN_TXBE_1_EFC(value) (CAN_TXBE_1_EFC_Msk & ((value) << CAN_TXBE_1_EFC_Pos)) +#define CAN_TXBE_1_MM_Pos _U_(24) /**< (CAN_TXBE_1) Message Marker Position */ +#define CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos) /**< (CAN_TXBE_1) Message Marker Mask */ +#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos)) +#define CAN_TXBE_1_Msk _U_(0xFFBF0000) /**< (CAN_TXBE_1) Register Mask */ + + +/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#define CAN_TXBE_DATA_DB0_Pos _U_(0) /**< (CAN_TXBE_DATA) Data Byte 0 Position */ +#define CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos) /**< (CAN_TXBE_DATA) Data Byte 0 Mask */ +#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos)) +#define CAN_TXBE_DATA_DB1_Pos _U_(8) /**< (CAN_TXBE_DATA) Data Byte 1 Position */ +#define CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos) /**< (CAN_TXBE_DATA) Data Byte 1 Mask */ +#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos)) +#define CAN_TXBE_DATA_DB2_Pos _U_(16) /**< (CAN_TXBE_DATA) Data Byte 2 Position */ +#define CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos) /**< (CAN_TXBE_DATA) Data Byte 2 Mask */ +#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos)) +#define CAN_TXBE_DATA_DB3_Pos _U_(24) /**< (CAN_TXBE_DATA) Data Byte 3 Position */ +#define CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos) /**< (CAN_TXBE_DATA) Data Byte 3 Mask */ +#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos)) +#define CAN_TXBE_DATA_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBE_DATA) Register Mask */ + + +/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#define CAN_TXEFE_0_ID_Pos _U_(0) /**< (CAN_TXEFE_0) Identifier Position */ +#define CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) /**< (CAN_TXEFE_0) Identifier Mask */ +#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos)) +#define CAN_TXEFE_0_RTR_Pos _U_(29) /**< (CAN_TXEFE_0) Remote Transmission Request Position */ +#define CAN_TXEFE_0_RTR_Msk (_U_(0x1) << CAN_TXEFE_0_RTR_Pos) /**< (CAN_TXEFE_0) Remote Transmission Request Mask */ +#define CAN_TXEFE_0_RTR(value) (CAN_TXEFE_0_RTR_Msk & ((value) << CAN_TXEFE_0_RTR_Pos)) +#define CAN_TXEFE_0_XTD_Pos _U_(30) /**< (CAN_TXEFE_0) Extended Identifier Position */ +#define CAN_TXEFE_0_XTD_Msk (_U_(0x1) << CAN_TXEFE_0_XTD_Pos) /**< (CAN_TXEFE_0) Extended Identifier Mask */ +#define CAN_TXEFE_0_XTD(value) (CAN_TXEFE_0_XTD_Msk & ((value) << CAN_TXEFE_0_XTD_Pos)) +#define CAN_TXEFE_0_ESI_Pos _U_(31) /**< (CAN_TXEFE_0) Error State Indicator Position */ +#define CAN_TXEFE_0_ESI_Msk (_U_(0x1) << CAN_TXEFE_0_ESI_Pos) /**< (CAN_TXEFE_0) Error State Indicator Mask */ +#define CAN_TXEFE_0_ESI(value) (CAN_TXEFE_0_ESI_Msk & ((value) << CAN_TXEFE_0_ESI_Pos)) +#define CAN_TXEFE_0_Msk _U_(0xFFFFFFFF) /**< (CAN_TXEFE_0) Register Mask */ + + +/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#define CAN_TXEFE_1_TXTS_Pos _U_(0) /**< (CAN_TXEFE_1) Tx Timestamp Position */ +#define CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) /**< (CAN_TXEFE_1) Tx Timestamp Mask */ +#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos)) +#define CAN_TXEFE_1_DLC_Pos _U_(16) /**< (CAN_TXEFE_1) Data Length Code Position */ +#define CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos) /**< (CAN_TXEFE_1) Data Length Code Mask */ +#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos)) +#define CAN_TXEFE_1_BRS_Pos _U_(20) /**< (CAN_TXEFE_1) Bit Rate Switch Position */ +#define CAN_TXEFE_1_BRS_Msk (_U_(0x1) << CAN_TXEFE_1_BRS_Pos) /**< (CAN_TXEFE_1) Bit Rate Switch Mask */ +#define CAN_TXEFE_1_BRS(value) (CAN_TXEFE_1_BRS_Msk & ((value) << CAN_TXEFE_1_BRS_Pos)) +#define CAN_TXEFE_1_FDF_Pos _U_(21) /**< (CAN_TXEFE_1) FD Format Position */ +#define CAN_TXEFE_1_FDF_Msk (_U_(0x1) << CAN_TXEFE_1_FDF_Pos) /**< (CAN_TXEFE_1) FD Format Mask */ +#define CAN_TXEFE_1_FDF(value) (CAN_TXEFE_1_FDF_Msk & ((value) << CAN_TXEFE_1_FDF_Pos)) +#define CAN_TXEFE_1_ET_Pos _U_(22) /**< (CAN_TXEFE_1) Event Type Position */ +#define CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos) /**< (CAN_TXEFE_1) Event Type Mask */ +#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos)) +#define CAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< (CAN_TXEFE_1) Tx event */ +#define CAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< (CAN_TXEFE_1) Transmission in spite of cancellation */ +#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) /**< (CAN_TXEFE_1) Tx event Position */ +#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) /**< (CAN_TXEFE_1) Transmission in spite of cancellation Position */ +#define CAN_TXEFE_1_MM_Pos _U_(24) /**< (CAN_TXEFE_1) Message Marker Position */ +#define CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos) /**< (CAN_TXEFE_1) Message Marker Mask */ +#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos)) +#define CAN_TXEFE_1_Msk _U_(0xFFFFFFFF) /**< (CAN_TXEFE_1) Register Mask */ + + +/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ +#define CAN_SIDFE_0_SFID2_Pos _U_(0) /**< (CAN_SIDFE_0) Standard Filter ID 2 Position */ +#define CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) /**< (CAN_SIDFE_0) Standard Filter ID 2 Mask */ +#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos)) +#define CAN_SIDFE_0_SFID1_Pos _U_(16) /**< (CAN_SIDFE_0) Standard Filter ID 1 Position */ +#define CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) /**< (CAN_SIDFE_0) Standard Filter ID 1 Mask */ +#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos)) +#define CAN_SIDFE_0_SFEC_Pos _U_(27) /**< (CAN_SIDFE_0) Standard Filter Element Configuration Position */ +#define CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Standard Filter Element Configuration Mask */ +#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos)) +#define CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< (CAN_SIDFE_0) Disable filter element */ +#define CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< (CAN_SIDFE_0) Reject ID if filter match */ +#define CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< (CAN_SIDFE_0) Set priority if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< (CAN_SIDFE_0) Store into Rx Buffer */ +#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Disable filter element Position */ +#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Reject ID if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Set priority if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Store into Rx Buffer Position */ +#define CAN_SIDFE_0_SFT_Pos _U_(30) /**< (CAN_SIDFE_0) Standard Filter Type Position */ +#define CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos) /**< (CAN_SIDFE_0) Standard Filter Type Mask */ +#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos)) +#define CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ +#define CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< (CAN_SIDFE_0) Classic filter */ +#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) /**< (CAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ +#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) /**< (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 Position */ +#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) /**< (CAN_SIDFE_0) Classic filter Position */ +#define CAN_SIDFE_0_Msk _U_(0xFFFF07FF) /**< (CAN_SIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#define CAN_XIDFE_0_EFID1_Pos _U_(0) /**< (CAN_XIDFE_0) Extended Filter ID 1 Position */ +#define CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) /**< (CAN_XIDFE_0) Extended Filter ID 1 Mask */ +#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos)) +#define CAN_XIDFE_0_EFEC_Pos _U_(29) /**< (CAN_XIDFE_0) Extended Filter Element Configuration Position */ +#define CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Extended Filter Element Configuration Mask */ +#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos)) +#define CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< (CAN_XIDFE_0) Disable filter element */ +#define CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< (CAN_XIDFE_0) Reject ID if filter match */ +#define CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< (CAN_XIDFE_0) Set priority if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< (CAN_XIDFE_0) Store into Rx Buffer */ +#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Disable filter element Position */ +#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Reject ID if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Set priority if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Store into Rx Buffer Position */ +#define CAN_XIDFE_0_Msk _U_(0xFFFFFFFF) /**< (CAN_XIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#define CAN_XIDFE_1_EFID2_Pos _U_(0) /**< (CAN_XIDFE_1) Extended Filter ID 2 Position */ +#define CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) /**< (CAN_XIDFE_1) Extended Filter ID 2 Mask */ +#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos)) +#define CAN_XIDFE_1_EFT_Pos _U_(30) /**< (CAN_XIDFE_1) Extended Filter Type Position */ +#define CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos) /**< (CAN_XIDFE_1) Extended Filter Type Mask */ +#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos)) +#define CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) /**< (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< (CAN_XIDFE_1) Classic filter */ +#define CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) /**< (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) /**< (CAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ +#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) /**< (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ +#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) /**< (CAN_XIDFE_1) Classic filter Position */ +#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) /**< (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ +#define CAN_XIDFE_1_Msk _U_(0xDFFFFFFF) /**< (CAN_XIDFE_1) Register Mask */ + + +/* -------- CAN_CREL : (CAN Offset: 0x00) ( R/ 32) Core Release -------- */ +#define CAN_CREL_RESETVALUE _U_(0x32100000) /**< (CAN_CREL) Core Release Reset Value */ + +#define CAN_CREL_SUBSTEP_Pos _U_(20) /**< (CAN_CREL) Sub-step of Core Release Position */ +#define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos) /**< (CAN_CREL) Sub-step of Core Release Mask */ +#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos)) +#define CAN_CREL_STEP_Pos _U_(24) /**< (CAN_CREL) Step of Core Release Position */ +#define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos) /**< (CAN_CREL) Step of Core Release Mask */ +#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos)) +#define CAN_CREL_REL_Pos _U_(28) /**< (CAN_CREL) Core Release Position */ +#define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos) /**< (CAN_CREL) Core Release Mask */ +#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos)) +#define CAN_CREL_Msk _U_(0xFFF00000) /**< (CAN_CREL) Register Mask */ + + +/* -------- CAN_ENDN : (CAN Offset: 0x04) ( R/ 32) Endian -------- */ +#define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< (CAN_ENDN) Endian Reset Value */ + +#define CAN_ENDN_ETV_Pos _U_(0) /**< (CAN_ENDN) Endianness Test Value Position */ +#define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) /**< (CAN_ENDN) Endianness Test Value Mask */ +#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos)) +#define CAN_ENDN_Msk _U_(0xFFFFFFFF) /**< (CAN_ENDN) Register Mask */ + + +/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ +#define CAN_MRCFG_RESETVALUE _U_(0x02) /**< (CAN_MRCFG) Message RAM Configuration Reset Value */ + +#define CAN_MRCFG_QOS_Pos _U_(0) /**< (CAN_MRCFG) Quality of Service Position */ +#define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos) /**< (CAN_MRCFG) Quality of Service Mask */ +#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos)) +#define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< (CAN_MRCFG) Background (no sensitive operation) */ +#define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< (CAN_MRCFG) Sensitive Bandwidth */ +#define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< (CAN_MRCFG) Sensitive Latency */ +#define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< (CAN_MRCFG) Critical Latency */ +#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) /**< (CAN_MRCFG) Background (no sensitive operation) Position */ +#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) /**< (CAN_MRCFG) Sensitive Bandwidth Position */ +#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) /**< (CAN_MRCFG) Sensitive Latency Position */ +#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) /**< (CAN_MRCFG) Critical Latency Position */ +#define CAN_MRCFG_Msk _U_(0x00000003) /**< (CAN_MRCFG) Register Mask */ + + +/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ +#define CAN_DBTP_RESETVALUE _U_(0xA33) /**< (CAN_DBTP) Fast Bit Timing and Prescaler Reset Value */ + +#define CAN_DBTP_DSJW_Pos _U_(0) /**< (CAN_DBTP) Data (Re)Synchronization Jump Width Position */ +#define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos) /**< (CAN_DBTP) Data (Re)Synchronization Jump Width Mask */ +#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos)) +#define CAN_DBTP_DTSEG2_Pos _U_(4) /**< (CAN_DBTP) Data time segment after sample point Position */ +#define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos) /**< (CAN_DBTP) Data time segment after sample point Mask */ +#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos)) +#define CAN_DBTP_DTSEG1_Pos _U_(8) /**< (CAN_DBTP) Data time segment before sample point Position */ +#define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos) /**< (CAN_DBTP) Data time segment before sample point Mask */ +#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos)) +#define CAN_DBTP_DBRP_Pos _U_(16) /**< (CAN_DBTP) Data Baud Rate Prescaler Position */ +#define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos) /**< (CAN_DBTP) Data Baud Rate Prescaler Mask */ +#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos)) +#define CAN_DBTP_TDC_Pos _U_(23) /**< (CAN_DBTP) Tranceiver Delay Compensation Position */ +#define CAN_DBTP_TDC_Msk (_U_(0x1) << CAN_DBTP_TDC_Pos) /**< (CAN_DBTP) Tranceiver Delay Compensation Mask */ +#define CAN_DBTP_TDC(value) (CAN_DBTP_TDC_Msk & ((value) << CAN_DBTP_TDC_Pos)) +#define CAN_DBTP_Msk _U_(0x009F1FFF) /**< (CAN_DBTP) Register Mask */ + + +/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ +#define CAN_TEST_RESETVALUE _U_(0x00) /**< (CAN_TEST) Test Reset Value */ + +#define CAN_TEST_LBCK_Pos _U_(4) /**< (CAN_TEST) Loop Back Mode Position */ +#define CAN_TEST_LBCK_Msk (_U_(0x1) << CAN_TEST_LBCK_Pos) /**< (CAN_TEST) Loop Back Mode Mask */ +#define CAN_TEST_LBCK(value) (CAN_TEST_LBCK_Msk & ((value) << CAN_TEST_LBCK_Pos)) +#define CAN_TEST_TX_Pos _U_(5) /**< (CAN_TEST) Control of Transmit Pin Position */ +#define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos) /**< (CAN_TEST) Control of Transmit Pin Mask */ +#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos)) +#define CAN_TEST_TX_CORE_Val _U_(0x0) /**< (CAN_TEST) TX controlled by CAN core */ +#define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< (CAN_TEST) TX monitoring sample point */ +#define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< (CAN_TEST) Dominant (0) level at pin CAN_TX */ +#define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< (CAN_TEST) Recessive (1) level at pin CAN_TX */ +#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) /**< (CAN_TEST) TX controlled by CAN core Position */ +#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) /**< (CAN_TEST) TX monitoring sample point Position */ +#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) /**< (CAN_TEST) Dominant (0) level at pin CAN_TX Position */ +#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) /**< (CAN_TEST) Recessive (1) level at pin CAN_TX Position */ +#define CAN_TEST_RX_Pos _U_(7) /**< (CAN_TEST) Receive Pin Position */ +#define CAN_TEST_RX_Msk (_U_(0x1) << CAN_TEST_RX_Pos) /**< (CAN_TEST) Receive Pin Mask */ +#define CAN_TEST_RX(value) (CAN_TEST_RX_Msk & ((value) << CAN_TEST_RX_Pos)) +#define CAN_TEST_Msk _U_(0x000000F0) /**< (CAN_TEST) Register Mask */ + + +/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ +#define CAN_RWD_RESETVALUE _U_(0x00) /**< (CAN_RWD) RAM Watchdog Reset Value */ + +#define CAN_RWD_WDC_Pos _U_(0) /**< (CAN_RWD) Watchdog Configuration Position */ +#define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos) /**< (CAN_RWD) Watchdog Configuration Mask */ +#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos)) +#define CAN_RWD_WDV_Pos _U_(8) /**< (CAN_RWD) Watchdog Value Position */ +#define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos) /**< (CAN_RWD) Watchdog Value Mask */ +#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos)) +#define CAN_RWD_Msk _U_(0x0000FFFF) /**< (CAN_RWD) Register Mask */ + + +/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ +#define CAN_CCCR_RESETVALUE _U_(0x01) /**< (CAN_CCCR) CC Control Reset Value */ + +#define CAN_CCCR_INIT_Pos _U_(0) /**< (CAN_CCCR) Initialization Position */ +#define CAN_CCCR_INIT_Msk (_U_(0x1) << CAN_CCCR_INIT_Pos) /**< (CAN_CCCR) Initialization Mask */ +#define CAN_CCCR_INIT(value) (CAN_CCCR_INIT_Msk & ((value) << CAN_CCCR_INIT_Pos)) +#define CAN_CCCR_CCE_Pos _U_(1) /**< (CAN_CCCR) Configuration Change Enable Position */ +#define CAN_CCCR_CCE_Msk (_U_(0x1) << CAN_CCCR_CCE_Pos) /**< (CAN_CCCR) Configuration Change Enable Mask */ +#define CAN_CCCR_CCE(value) (CAN_CCCR_CCE_Msk & ((value) << CAN_CCCR_CCE_Pos)) +#define CAN_CCCR_ASM_Pos _U_(2) /**< (CAN_CCCR) ASM Restricted Operation Mode Position */ +#define CAN_CCCR_ASM_Msk (_U_(0x1) << CAN_CCCR_ASM_Pos) /**< (CAN_CCCR) ASM Restricted Operation Mode Mask */ +#define CAN_CCCR_ASM(value) (CAN_CCCR_ASM_Msk & ((value) << CAN_CCCR_ASM_Pos)) +#define CAN_CCCR_CSA_Pos _U_(3) /**< (CAN_CCCR) Clock Stop Acknowledge Position */ +#define CAN_CCCR_CSA_Msk (_U_(0x1) << CAN_CCCR_CSA_Pos) /**< (CAN_CCCR) Clock Stop Acknowledge Mask */ +#define CAN_CCCR_CSA(value) (CAN_CCCR_CSA_Msk & ((value) << CAN_CCCR_CSA_Pos)) +#define CAN_CCCR_CSR_Pos _U_(4) /**< (CAN_CCCR) Clock Stop Request Position */ +#define CAN_CCCR_CSR_Msk (_U_(0x1) << CAN_CCCR_CSR_Pos) /**< (CAN_CCCR) Clock Stop Request Mask */ +#define CAN_CCCR_CSR(value) (CAN_CCCR_CSR_Msk & ((value) << CAN_CCCR_CSR_Pos)) +#define CAN_CCCR_MON_Pos _U_(5) /**< (CAN_CCCR) Bus Monitoring Mode Position */ +#define CAN_CCCR_MON_Msk (_U_(0x1) << CAN_CCCR_MON_Pos) /**< (CAN_CCCR) Bus Monitoring Mode Mask */ +#define CAN_CCCR_MON(value) (CAN_CCCR_MON_Msk & ((value) << CAN_CCCR_MON_Pos)) +#define CAN_CCCR_DAR_Pos _U_(6) /**< (CAN_CCCR) Disable Automatic Retransmission Position */ +#define CAN_CCCR_DAR_Msk (_U_(0x1) << CAN_CCCR_DAR_Pos) /**< (CAN_CCCR) Disable Automatic Retransmission Mask */ +#define CAN_CCCR_DAR(value) (CAN_CCCR_DAR_Msk & ((value) << CAN_CCCR_DAR_Pos)) +#define CAN_CCCR_TEST_Pos _U_(7) /**< (CAN_CCCR) Test Mode Enable Position */ +#define CAN_CCCR_TEST_Msk (_U_(0x1) << CAN_CCCR_TEST_Pos) /**< (CAN_CCCR) Test Mode Enable Mask */ +#define CAN_CCCR_TEST(value) (CAN_CCCR_TEST_Msk & ((value) << CAN_CCCR_TEST_Pos)) +#define CAN_CCCR_FDOE_Pos _U_(8) /**< (CAN_CCCR) FD Operation Enable Position */ +#define CAN_CCCR_FDOE_Msk (_U_(0x1) << CAN_CCCR_FDOE_Pos) /**< (CAN_CCCR) FD Operation Enable Mask */ +#define CAN_CCCR_FDOE(value) (CAN_CCCR_FDOE_Msk & ((value) << CAN_CCCR_FDOE_Pos)) +#define CAN_CCCR_BRSE_Pos _U_(9) /**< (CAN_CCCR) Bit Rate Switch Enable Position */ +#define CAN_CCCR_BRSE_Msk (_U_(0x1) << CAN_CCCR_BRSE_Pos) /**< (CAN_CCCR) Bit Rate Switch Enable Mask */ +#define CAN_CCCR_BRSE(value) (CAN_CCCR_BRSE_Msk & ((value) << CAN_CCCR_BRSE_Pos)) +#define CAN_CCCR_PXHD_Pos _U_(12) /**< (CAN_CCCR) Protocol Exception Handling Disable Position */ +#define CAN_CCCR_PXHD_Msk (_U_(0x1) << CAN_CCCR_PXHD_Pos) /**< (CAN_CCCR) Protocol Exception Handling Disable Mask */ +#define CAN_CCCR_PXHD(value) (CAN_CCCR_PXHD_Msk & ((value) << CAN_CCCR_PXHD_Pos)) +#define CAN_CCCR_EFBI_Pos _U_(13) /**< (CAN_CCCR) Edge Filtering during Bus Integration Position */ +#define CAN_CCCR_EFBI_Msk (_U_(0x1) << CAN_CCCR_EFBI_Pos) /**< (CAN_CCCR) Edge Filtering during Bus Integration Mask */ +#define CAN_CCCR_EFBI(value) (CAN_CCCR_EFBI_Msk & ((value) << CAN_CCCR_EFBI_Pos)) +#define CAN_CCCR_TXP_Pos _U_(14) /**< (CAN_CCCR) Transmit Pause Position */ +#define CAN_CCCR_TXP_Msk (_U_(0x1) << CAN_CCCR_TXP_Pos) /**< (CAN_CCCR) Transmit Pause Mask */ +#define CAN_CCCR_TXP(value) (CAN_CCCR_TXP_Msk & ((value) << CAN_CCCR_TXP_Pos)) +#define CAN_CCCR_NISO_Pos _U_(15) /**< (CAN_CCCR) Non ISO Operation Position */ +#define CAN_CCCR_NISO_Msk (_U_(0x1) << CAN_CCCR_NISO_Pos) /**< (CAN_CCCR) Non ISO Operation Mask */ +#define CAN_CCCR_NISO(value) (CAN_CCCR_NISO_Msk & ((value) << CAN_CCCR_NISO_Pos)) +#define CAN_CCCR_Msk _U_(0x0000F3FF) /**< (CAN_CCCR) Register Mask */ + + +/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ +#define CAN_NBTP_RESETVALUE _U_(0x6000A03) /**< (CAN_NBTP) Nominal Bit Timing and Prescaler Reset Value */ + +#define CAN_NBTP_NTSEG2_Pos _U_(0) /**< (CAN_NBTP) Nominal Time segment after sample point Position */ +#define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos) /**< (CAN_NBTP) Nominal Time segment after sample point Mask */ +#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos)) +#define CAN_NBTP_NTSEG1_Pos _U_(8) /**< (CAN_NBTP) Nominal Time segment before sample point Position */ +#define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos) /**< (CAN_NBTP) Nominal Time segment before sample point Mask */ +#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos)) +#define CAN_NBTP_NBRP_Pos _U_(16) /**< (CAN_NBTP) Nominal Baud Rate Prescaler Position */ +#define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos) /**< (CAN_NBTP) Nominal Baud Rate Prescaler Mask */ +#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos)) +#define CAN_NBTP_NSJW_Pos _U_(25) /**< (CAN_NBTP) Nominal (Re)Synchronization Jump Width Position */ +#define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos) /**< (CAN_NBTP) Nominal (Re)Synchronization Jump Width Mask */ +#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos)) +#define CAN_NBTP_Msk _U_(0xFFFFFF7F) /**< (CAN_NBTP) Register Mask */ + + +/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ +#define CAN_TSCC_RESETVALUE _U_(0x00) /**< (CAN_TSCC) Timestamp Counter Configuration Reset Value */ + +#define CAN_TSCC_TSS_Pos _U_(0) /**< (CAN_TSCC) Timestamp Select Position */ +#define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos) /**< (CAN_TSCC) Timestamp Select Mask */ +#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos)) +#define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< (CAN_TSCC) Timestamp counter value always 0x0000 */ +#define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< (CAN_TSCC) Timestamp counter value incremented by TCP */ +#define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< (CAN_TSCC) External timestamp counter value used */ +#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) /**< (CAN_TSCC) Timestamp counter value always 0x0000 Position */ +#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) /**< (CAN_TSCC) Timestamp counter value incremented by TCP Position */ +#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) /**< (CAN_TSCC) External timestamp counter value used Position */ +#define CAN_TSCC_TCP_Pos _U_(16) /**< (CAN_TSCC) Timestamp Counter Prescaler Position */ +#define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos) /**< (CAN_TSCC) Timestamp Counter Prescaler Mask */ +#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos)) +#define CAN_TSCC_Msk _U_(0x000F0003) /**< (CAN_TSCC) Register Mask */ + + +/* -------- CAN_TSCV : (CAN Offset: 0x24) ( R/ 32) Timestamp Counter Value -------- */ +#define CAN_TSCV_RESETVALUE _U_(0x00) /**< (CAN_TSCV) Timestamp Counter Value Reset Value */ + +#define CAN_TSCV_TSC_Pos _U_(0) /**< (CAN_TSCV) Timestamp Counter Position */ +#define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos) /**< (CAN_TSCV) Timestamp Counter Mask */ +#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos)) +#define CAN_TSCV_Msk _U_(0x0000FFFF) /**< (CAN_TSCV) Register Mask */ + + +/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ +#define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< (CAN_TOCC) Timeout Counter Configuration Reset Value */ + +#define CAN_TOCC_ETOC_Pos _U_(0) /**< (CAN_TOCC) Enable Timeout Counter Position */ +#define CAN_TOCC_ETOC_Msk (_U_(0x1) << CAN_TOCC_ETOC_Pos) /**< (CAN_TOCC) Enable Timeout Counter Mask */ +#define CAN_TOCC_ETOC(value) (CAN_TOCC_ETOC_Msk & ((value) << CAN_TOCC_ETOC_Pos)) +#define CAN_TOCC_TOS_Pos _U_(1) /**< (CAN_TOCC) Timeout Select Position */ +#define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos) /**< (CAN_TOCC) Timeout Select Mask */ +#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos)) +#define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< (CAN_TOCC) Continuout operation */ +#define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< (CAN_TOCC) Timeout controlled by TX Event FIFO */ +#define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ +#define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ +#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) /**< (CAN_TOCC) Continuout operation Position */ +#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) /**< (CAN_TOCC) Timeout controlled by TX Event FIFO Position */ +#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) /**< (CAN_TOCC) Timeout controlled by Rx FIFO 0 Position */ +#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) /**< (CAN_TOCC) Timeout controlled by Rx FIFO 1 Position */ +#define CAN_TOCC_TOP_Pos _U_(16) /**< (CAN_TOCC) Timeout Period Position */ +#define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos) /**< (CAN_TOCC) Timeout Period Mask */ +#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos)) +#define CAN_TOCC_Msk _U_(0xFFFF0007) /**< (CAN_TOCC) Register Mask */ + + +/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ +#define CAN_TOCV_RESETVALUE _U_(0xFFFF) /**< (CAN_TOCV) Timeout Counter Value Reset Value */ + +#define CAN_TOCV_TOC_Pos _U_(0) /**< (CAN_TOCV) Timeout Counter Position */ +#define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos) /**< (CAN_TOCV) Timeout Counter Mask */ +#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos)) +#define CAN_TOCV_Msk _U_(0x0000FFFF) /**< (CAN_TOCV) Register Mask */ + + +/* -------- CAN_ECR : (CAN Offset: 0x40) ( R/ 32) Error Counter -------- */ +#define CAN_ECR_RESETVALUE _U_(0x00) /**< (CAN_ECR) Error Counter Reset Value */ + +#define CAN_ECR_TEC_Pos _U_(0) /**< (CAN_ECR) Transmit Error Counter Position */ +#define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos) /**< (CAN_ECR) Transmit Error Counter Mask */ +#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos)) +#define CAN_ECR_REC_Pos _U_(8) /**< (CAN_ECR) Receive Error Counter Position */ +#define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos) /**< (CAN_ECR) Receive Error Counter Mask */ +#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos)) +#define CAN_ECR_RP_Pos _U_(15) /**< (CAN_ECR) Receive Error Passive Position */ +#define CAN_ECR_RP_Msk (_U_(0x1) << CAN_ECR_RP_Pos) /**< (CAN_ECR) Receive Error Passive Mask */ +#define CAN_ECR_RP(value) (CAN_ECR_RP_Msk & ((value) << CAN_ECR_RP_Pos)) +#define CAN_ECR_CEL_Pos _U_(16) /**< (CAN_ECR) CAN Error Logging Position */ +#define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos) /**< (CAN_ECR) CAN Error Logging Mask */ +#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos)) +#define CAN_ECR_Msk _U_(0x00FFFFFF) /**< (CAN_ECR) Register Mask */ + + +/* -------- CAN_PSR : (CAN Offset: 0x44) ( R/ 32) Protocol Status -------- */ +#define CAN_PSR_RESETVALUE _U_(0x707) /**< (CAN_PSR) Protocol Status Reset Value */ + +#define CAN_PSR_LEC_Pos _U_(0) /**< (CAN_PSR) Last Error Code Position */ +#define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Last Error Code Mask */ +#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos)) +#define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< (CAN_PSR) No Error */ +#define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< (CAN_PSR) Stuff Error */ +#define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< (CAN_PSR) Form Error */ +#define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< (CAN_PSR) Ack Error */ +#define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< (CAN_PSR) Bit1 Error */ +#define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< (CAN_PSR) Bit0 Error */ +#define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< (CAN_PSR) CRC Error */ +#define CAN_PSR_LEC_NC_Val _U_(0x7) /**< (CAN_PSR) No Change */ +#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) No Error Position */ +#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Form Error Position */ +#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Ack Error Position */ +#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) CRC Error Position */ +#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) No Change Position */ +#define CAN_PSR_ACT_Pos _U_(3) /**< (CAN_PSR) Activity Position */ +#define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos) /**< (CAN_PSR) Activity Mask */ +#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos)) +#define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< (CAN_PSR) Node is synchronizing on CAN communication */ +#define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< (CAN_PSR) Node is neither receiver nor transmitter */ +#define CAN_PSR_ACT_RX_Val _U_(0x2) /**< (CAN_PSR) Node is operating as receiver */ +#define CAN_PSR_ACT_TX_Val _U_(0x3) /**< (CAN_PSR) Node is operating as transmitter */ +#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) /**< (CAN_PSR) Node is synchronizing on CAN communication Position */ +#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) /**< (CAN_PSR) Node is neither receiver nor transmitter Position */ +#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) /**< (CAN_PSR) Node is operating as receiver Position */ +#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) /**< (CAN_PSR) Node is operating as transmitter Position */ +#define CAN_PSR_EP_Pos _U_(5) /**< (CAN_PSR) Error Passive Position */ +#define CAN_PSR_EP_Msk (_U_(0x1) << CAN_PSR_EP_Pos) /**< (CAN_PSR) Error Passive Mask */ +#define CAN_PSR_EP(value) (CAN_PSR_EP_Msk & ((value) << CAN_PSR_EP_Pos)) +#define CAN_PSR_EW_Pos _U_(6) /**< (CAN_PSR) Warning Status Position */ +#define CAN_PSR_EW_Msk (_U_(0x1) << CAN_PSR_EW_Pos) /**< (CAN_PSR) Warning Status Mask */ +#define CAN_PSR_EW(value) (CAN_PSR_EW_Msk & ((value) << CAN_PSR_EW_Pos)) +#define CAN_PSR_BO_Pos _U_(7) /**< (CAN_PSR) Bus_Off Status Position */ +#define CAN_PSR_BO_Msk (_U_(0x1) << CAN_PSR_BO_Pos) /**< (CAN_PSR) Bus_Off Status Mask */ +#define CAN_PSR_BO(value) (CAN_PSR_BO_Msk & ((value) << CAN_PSR_BO_Pos)) +#define CAN_PSR_DLEC_Pos _U_(8) /**< (CAN_PSR) Data Phase Last Error Code Position */ +#define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Data Phase Last Error Code Mask */ +#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos)) +#define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< (CAN_PSR) No Error */ +#define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< (CAN_PSR) Stuff Error */ +#define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< (CAN_PSR) Form Error */ +#define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< (CAN_PSR) Ack Error */ +#define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< (CAN_PSR) Bit1 Error */ +#define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< (CAN_PSR) Bit0 Error */ +#define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< (CAN_PSR) CRC Error */ +#define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< (CAN_PSR) No Change */ +#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) No Error Position */ +#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Form Error Position */ +#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Ack Error Position */ +#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) CRC Error Position */ +#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) No Change Position */ +#define CAN_PSR_RESI_Pos _U_(11) /**< (CAN_PSR) ESI flag of last received CAN FD Message Position */ +#define CAN_PSR_RESI_Msk (_U_(0x1) << CAN_PSR_RESI_Pos) /**< (CAN_PSR) ESI flag of last received CAN FD Message Mask */ +#define CAN_PSR_RESI(value) (CAN_PSR_RESI_Msk & ((value) << CAN_PSR_RESI_Pos)) +#define CAN_PSR_RBRS_Pos _U_(12) /**< (CAN_PSR) BRS flag of last received CAN FD Message Position */ +#define CAN_PSR_RBRS_Msk (_U_(0x1) << CAN_PSR_RBRS_Pos) /**< (CAN_PSR) BRS flag of last received CAN FD Message Mask */ +#define CAN_PSR_RBRS(value) (CAN_PSR_RBRS_Msk & ((value) << CAN_PSR_RBRS_Pos)) +#define CAN_PSR_RFDF_Pos _U_(13) /**< (CAN_PSR) Received a CAN FD Message Position */ +#define CAN_PSR_RFDF_Msk (_U_(0x1) << CAN_PSR_RFDF_Pos) /**< (CAN_PSR) Received a CAN FD Message Mask */ +#define CAN_PSR_RFDF(value) (CAN_PSR_RFDF_Msk & ((value) << CAN_PSR_RFDF_Pos)) +#define CAN_PSR_PXE_Pos _U_(14) /**< (CAN_PSR) Protocol Exception Event Position */ +#define CAN_PSR_PXE_Msk (_U_(0x1) << CAN_PSR_PXE_Pos) /**< (CAN_PSR) Protocol Exception Event Mask */ +#define CAN_PSR_PXE(value) (CAN_PSR_PXE_Msk & ((value) << CAN_PSR_PXE_Pos)) +#define CAN_PSR_TDCV_Pos _U_(16) /**< (CAN_PSR) Transmitter Delay Compensation Value Position */ +#define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos) /**< (CAN_PSR) Transmitter Delay Compensation Value Mask */ +#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos)) +#define CAN_PSR_Msk _U_(0x007F7FFF) /**< (CAN_PSR) Register Mask */ + + +/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_TDCR_RESETVALUE _U_(0x00) /**< (CAN_TDCR) Extended ID Filter Configuration Reset Value */ + +#define CAN_TDCR_TDCF_Pos _U_(0) /**< (CAN_TDCR) Transmitter Delay Compensation Filter Length Position */ +#define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos) /**< (CAN_TDCR) Transmitter Delay Compensation Filter Length Mask */ +#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos)) +#define CAN_TDCR_TDCO_Pos _U_(8) /**< (CAN_TDCR) Transmitter Delay Compensation Offset Position */ +#define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos) /**< (CAN_TDCR) Transmitter Delay Compensation Offset Mask */ +#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos)) +#define CAN_TDCR_Msk _U_(0x00007F7F) /**< (CAN_TDCR) Register Mask */ + + +/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ +#define CAN_IR_RESETVALUE _U_(0x00) /**< (CAN_IR) Interrupt Reset Value */ + +#define CAN_IR_RF0N_Pos _U_(0) /**< (CAN_IR) Rx FIFO 0 New Message Position */ +#define CAN_IR_RF0N_Msk (_U_(0x1) << CAN_IR_RF0N_Pos) /**< (CAN_IR) Rx FIFO 0 New Message Mask */ +#define CAN_IR_RF0N(value) (CAN_IR_RF0N_Msk & ((value) << CAN_IR_RF0N_Pos)) +#define CAN_IR_RF0W_Pos _U_(1) /**< (CAN_IR) Rx FIFO 0 Watermark Reached Position */ +#define CAN_IR_RF0W_Msk (_U_(0x1) << CAN_IR_RF0W_Pos) /**< (CAN_IR) Rx FIFO 0 Watermark Reached Mask */ +#define CAN_IR_RF0W(value) (CAN_IR_RF0W_Msk & ((value) << CAN_IR_RF0W_Pos)) +#define CAN_IR_RF0F_Pos _U_(2) /**< (CAN_IR) Rx FIFO 0 Full Position */ +#define CAN_IR_RF0F_Msk (_U_(0x1) << CAN_IR_RF0F_Pos) /**< (CAN_IR) Rx FIFO 0 Full Mask */ +#define CAN_IR_RF0F(value) (CAN_IR_RF0F_Msk & ((value) << CAN_IR_RF0F_Pos)) +#define CAN_IR_RF0L_Pos _U_(3) /**< (CAN_IR) Rx FIFO 0 Message Lost Position */ +#define CAN_IR_RF0L_Msk (_U_(0x1) << CAN_IR_RF0L_Pos) /**< (CAN_IR) Rx FIFO 0 Message Lost Mask */ +#define CAN_IR_RF0L(value) (CAN_IR_RF0L_Msk & ((value) << CAN_IR_RF0L_Pos)) +#define CAN_IR_RF1N_Pos _U_(4) /**< (CAN_IR) Rx FIFO 1 New Message Position */ +#define CAN_IR_RF1N_Msk (_U_(0x1) << CAN_IR_RF1N_Pos) /**< (CAN_IR) Rx FIFO 1 New Message Mask */ +#define CAN_IR_RF1N(value) (CAN_IR_RF1N_Msk & ((value) << CAN_IR_RF1N_Pos)) +#define CAN_IR_RF1W_Pos _U_(5) /**< (CAN_IR) Rx FIFO 1 Watermark Reached Position */ +#define CAN_IR_RF1W_Msk (_U_(0x1) << CAN_IR_RF1W_Pos) /**< (CAN_IR) Rx FIFO 1 Watermark Reached Mask */ +#define CAN_IR_RF1W(value) (CAN_IR_RF1W_Msk & ((value) << CAN_IR_RF1W_Pos)) +#define CAN_IR_RF1F_Pos _U_(6) /**< (CAN_IR) Rx FIFO 1 FIFO Full Position */ +#define CAN_IR_RF1F_Msk (_U_(0x1) << CAN_IR_RF1F_Pos) /**< (CAN_IR) Rx FIFO 1 FIFO Full Mask */ +#define CAN_IR_RF1F(value) (CAN_IR_RF1F_Msk & ((value) << CAN_IR_RF1F_Pos)) +#define CAN_IR_RF1L_Pos _U_(7) /**< (CAN_IR) Rx FIFO 1 Message Lost Position */ +#define CAN_IR_RF1L_Msk (_U_(0x1) << CAN_IR_RF1L_Pos) /**< (CAN_IR) Rx FIFO 1 Message Lost Mask */ +#define CAN_IR_RF1L(value) (CAN_IR_RF1L_Msk & ((value) << CAN_IR_RF1L_Pos)) +#define CAN_IR_HPM_Pos _U_(8) /**< (CAN_IR) High Priority Message Position */ +#define CAN_IR_HPM_Msk (_U_(0x1) << CAN_IR_HPM_Pos) /**< (CAN_IR) High Priority Message Mask */ +#define CAN_IR_HPM(value) (CAN_IR_HPM_Msk & ((value) << CAN_IR_HPM_Pos)) +#define CAN_IR_TC_Pos _U_(9) /**< (CAN_IR) Timestamp Completed Position */ +#define CAN_IR_TC_Msk (_U_(0x1) << CAN_IR_TC_Pos) /**< (CAN_IR) Timestamp Completed Mask */ +#define CAN_IR_TC(value) (CAN_IR_TC_Msk & ((value) << CAN_IR_TC_Pos)) +#define CAN_IR_TCF_Pos _U_(10) /**< (CAN_IR) Transmission Cancellation Finished Position */ +#define CAN_IR_TCF_Msk (_U_(0x1) << CAN_IR_TCF_Pos) /**< (CAN_IR) Transmission Cancellation Finished Mask */ +#define CAN_IR_TCF(value) (CAN_IR_TCF_Msk & ((value) << CAN_IR_TCF_Pos)) +#define CAN_IR_TFE_Pos _U_(11) /**< (CAN_IR) Tx FIFO Empty Position */ +#define CAN_IR_TFE_Msk (_U_(0x1) << CAN_IR_TFE_Pos) /**< (CAN_IR) Tx FIFO Empty Mask */ +#define CAN_IR_TFE(value) (CAN_IR_TFE_Msk & ((value) << CAN_IR_TFE_Pos)) +#define CAN_IR_TEFN_Pos _U_(12) /**< (CAN_IR) Tx Event FIFO New Entry Position */ +#define CAN_IR_TEFN_Msk (_U_(0x1) << CAN_IR_TEFN_Pos) /**< (CAN_IR) Tx Event FIFO New Entry Mask */ +#define CAN_IR_TEFN(value) (CAN_IR_TEFN_Msk & ((value) << CAN_IR_TEFN_Pos)) +#define CAN_IR_TEFW_Pos _U_(13) /**< (CAN_IR) Tx Event FIFO Watermark Reached Position */ +#define CAN_IR_TEFW_Msk (_U_(0x1) << CAN_IR_TEFW_Pos) /**< (CAN_IR) Tx Event FIFO Watermark Reached Mask */ +#define CAN_IR_TEFW(value) (CAN_IR_TEFW_Msk & ((value) << CAN_IR_TEFW_Pos)) +#define CAN_IR_TEFF_Pos _U_(14) /**< (CAN_IR) Tx Event FIFO Full Position */ +#define CAN_IR_TEFF_Msk (_U_(0x1) << CAN_IR_TEFF_Pos) /**< (CAN_IR) Tx Event FIFO Full Mask */ +#define CAN_IR_TEFF(value) (CAN_IR_TEFF_Msk & ((value) << CAN_IR_TEFF_Pos)) +#define CAN_IR_TEFL_Pos _U_(15) /**< (CAN_IR) Tx Event FIFO Element Lost Position */ +#define CAN_IR_TEFL_Msk (_U_(0x1) << CAN_IR_TEFL_Pos) /**< (CAN_IR) Tx Event FIFO Element Lost Mask */ +#define CAN_IR_TEFL(value) (CAN_IR_TEFL_Msk & ((value) << CAN_IR_TEFL_Pos)) +#define CAN_IR_TSW_Pos _U_(16) /**< (CAN_IR) Timestamp Wraparound Position */ +#define CAN_IR_TSW_Msk (_U_(0x1) << CAN_IR_TSW_Pos) /**< (CAN_IR) Timestamp Wraparound Mask */ +#define CAN_IR_TSW(value) (CAN_IR_TSW_Msk & ((value) << CAN_IR_TSW_Pos)) +#define CAN_IR_MRAF_Pos _U_(17) /**< (CAN_IR) Message RAM Access Failure Position */ +#define CAN_IR_MRAF_Msk (_U_(0x1) << CAN_IR_MRAF_Pos) /**< (CAN_IR) Message RAM Access Failure Mask */ +#define CAN_IR_MRAF(value) (CAN_IR_MRAF_Msk & ((value) << CAN_IR_MRAF_Pos)) +#define CAN_IR_TOO_Pos _U_(18) /**< (CAN_IR) Timeout Occurred Position */ +#define CAN_IR_TOO_Msk (_U_(0x1) << CAN_IR_TOO_Pos) /**< (CAN_IR) Timeout Occurred Mask */ +#define CAN_IR_TOO(value) (CAN_IR_TOO_Msk & ((value) << CAN_IR_TOO_Pos)) +#define CAN_IR_DRX_Pos _U_(19) /**< (CAN_IR) Message stored to Dedicated Rx Buffer Position */ +#define CAN_IR_DRX_Msk (_U_(0x1) << CAN_IR_DRX_Pos) /**< (CAN_IR) Message stored to Dedicated Rx Buffer Mask */ +#define CAN_IR_DRX(value) (CAN_IR_DRX_Msk & ((value) << CAN_IR_DRX_Pos)) +#define CAN_IR_BEC_Pos _U_(20) /**< (CAN_IR) Bit Error Corrected Position */ +#define CAN_IR_BEC_Msk (_U_(0x1) << CAN_IR_BEC_Pos) /**< (CAN_IR) Bit Error Corrected Mask */ +#define CAN_IR_BEC(value) (CAN_IR_BEC_Msk & ((value) << CAN_IR_BEC_Pos)) +#define CAN_IR_BEU_Pos _U_(21) /**< (CAN_IR) Bit Error Uncorrected Position */ +#define CAN_IR_BEU_Msk (_U_(0x1) << CAN_IR_BEU_Pos) /**< (CAN_IR) Bit Error Uncorrected Mask */ +#define CAN_IR_BEU(value) (CAN_IR_BEU_Msk & ((value) << CAN_IR_BEU_Pos)) +#define CAN_IR_ELO_Pos _U_(22) /**< (CAN_IR) Error Logging Overflow Position */ +#define CAN_IR_ELO_Msk (_U_(0x1) << CAN_IR_ELO_Pos) /**< (CAN_IR) Error Logging Overflow Mask */ +#define CAN_IR_ELO(value) (CAN_IR_ELO_Msk & ((value) << CAN_IR_ELO_Pos)) +#define CAN_IR_EP_Pos _U_(23) /**< (CAN_IR) Error Passive Position */ +#define CAN_IR_EP_Msk (_U_(0x1) << CAN_IR_EP_Pos) /**< (CAN_IR) Error Passive Mask */ +#define CAN_IR_EP(value) (CAN_IR_EP_Msk & ((value) << CAN_IR_EP_Pos)) +#define CAN_IR_EW_Pos _U_(24) /**< (CAN_IR) Warning Status Position */ +#define CAN_IR_EW_Msk (_U_(0x1) << CAN_IR_EW_Pos) /**< (CAN_IR) Warning Status Mask */ +#define CAN_IR_EW(value) (CAN_IR_EW_Msk & ((value) << CAN_IR_EW_Pos)) +#define CAN_IR_BO_Pos _U_(25) /**< (CAN_IR) Bus_Off Status Position */ +#define CAN_IR_BO_Msk (_U_(0x1) << CAN_IR_BO_Pos) /**< (CAN_IR) Bus_Off Status Mask */ +#define CAN_IR_BO(value) (CAN_IR_BO_Msk & ((value) << CAN_IR_BO_Pos)) +#define CAN_IR_WDI_Pos _U_(26) /**< (CAN_IR) Watchdog Interrupt Position */ +#define CAN_IR_WDI_Msk (_U_(0x1) << CAN_IR_WDI_Pos) /**< (CAN_IR) Watchdog Interrupt Mask */ +#define CAN_IR_WDI(value) (CAN_IR_WDI_Msk & ((value) << CAN_IR_WDI_Pos)) +#define CAN_IR_PEA_Pos _U_(27) /**< (CAN_IR) Protocol Error in Arbitration Phase Position */ +#define CAN_IR_PEA_Msk (_U_(0x1) << CAN_IR_PEA_Pos) /**< (CAN_IR) Protocol Error in Arbitration Phase Mask */ +#define CAN_IR_PEA(value) (CAN_IR_PEA_Msk & ((value) << CAN_IR_PEA_Pos)) +#define CAN_IR_PED_Pos _U_(28) /**< (CAN_IR) Protocol Error in Data Phase Position */ +#define CAN_IR_PED_Msk (_U_(0x1) << CAN_IR_PED_Pos) /**< (CAN_IR) Protocol Error in Data Phase Mask */ +#define CAN_IR_PED(value) (CAN_IR_PED_Msk & ((value) << CAN_IR_PED_Pos)) +#define CAN_IR_ARA_Pos _U_(29) /**< (CAN_IR) Access to Reserved Address Position */ +#define CAN_IR_ARA_Msk (_U_(0x1) << CAN_IR_ARA_Pos) /**< (CAN_IR) Access to Reserved Address Mask */ +#define CAN_IR_ARA(value) (CAN_IR_ARA_Msk & ((value) << CAN_IR_ARA_Pos)) +#define CAN_IR_Msk _U_(0x3FFFFFFF) /**< (CAN_IR) Register Mask */ + + +/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ +#define CAN_IE_RESETVALUE _U_(0x00) /**< (CAN_IE) Interrupt Enable Reset Value */ + +#define CAN_IE_RF0NE_Pos _U_(0) /**< (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Position */ +#define CAN_IE_RF0NE_Msk (_U_(0x1) << CAN_IE_RF0NE_Pos) /**< (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Mask */ +#define CAN_IE_RF0NE(value) (CAN_IE_RF0NE_Msk & ((value) << CAN_IE_RF0NE_Pos)) +#define CAN_IE_RF0WE_Pos _U_(1) /**< (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF0WE_Msk (_U_(0x1) << CAN_IE_RF0WE_Pos) /**< (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF0WE(value) (CAN_IE_RF0WE_Msk & ((value) << CAN_IE_RF0WE_Pos)) +#define CAN_IE_RF0FE_Pos _U_(2) /**< (CAN_IE) Rx FIFO 0 Full Interrupt Enable Position */ +#define CAN_IE_RF0FE_Msk (_U_(0x1) << CAN_IE_RF0FE_Pos) /**< (CAN_IE) Rx FIFO 0 Full Interrupt Enable Mask */ +#define CAN_IE_RF0FE(value) (CAN_IE_RF0FE_Msk & ((value) << CAN_IE_RF0FE_Pos)) +#define CAN_IE_RF0LE_Pos _U_(3) /**< (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF0LE_Msk (_U_(0x1) << CAN_IE_RF0LE_Pos) /**< (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF0LE(value) (CAN_IE_RF0LE_Msk & ((value) << CAN_IE_RF0LE_Pos)) +#define CAN_IE_RF1NE_Pos _U_(4) /**< (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Position */ +#define CAN_IE_RF1NE_Msk (_U_(0x1) << CAN_IE_RF1NE_Pos) /**< (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Mask */ +#define CAN_IE_RF1NE(value) (CAN_IE_RF1NE_Msk & ((value) << CAN_IE_RF1NE_Pos)) +#define CAN_IE_RF1WE_Pos _U_(5) /**< (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF1WE_Msk (_U_(0x1) << CAN_IE_RF1WE_Pos) /**< (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF1WE(value) (CAN_IE_RF1WE_Msk & ((value) << CAN_IE_RF1WE_Pos)) +#define CAN_IE_RF1FE_Pos _U_(6) /**< (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Position */ +#define CAN_IE_RF1FE_Msk (_U_(0x1) << CAN_IE_RF1FE_Pos) /**< (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Mask */ +#define CAN_IE_RF1FE(value) (CAN_IE_RF1FE_Msk & ((value) << CAN_IE_RF1FE_Pos)) +#define CAN_IE_RF1LE_Pos _U_(7) /**< (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF1LE_Msk (_U_(0x1) << CAN_IE_RF1LE_Pos) /**< (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF1LE(value) (CAN_IE_RF1LE_Msk & ((value) << CAN_IE_RF1LE_Pos)) +#define CAN_IE_HPME_Pos _U_(8) /**< (CAN_IE) High Priority Message Interrupt Enable Position */ +#define CAN_IE_HPME_Msk (_U_(0x1) << CAN_IE_HPME_Pos) /**< (CAN_IE) High Priority Message Interrupt Enable Mask */ +#define CAN_IE_HPME(value) (CAN_IE_HPME_Msk & ((value) << CAN_IE_HPME_Pos)) +#define CAN_IE_TCE_Pos _U_(9) /**< (CAN_IE) Timestamp Completed Interrupt Enable Position */ +#define CAN_IE_TCE_Msk (_U_(0x1) << CAN_IE_TCE_Pos) /**< (CAN_IE) Timestamp Completed Interrupt Enable Mask */ +#define CAN_IE_TCE(value) (CAN_IE_TCE_Msk & ((value) << CAN_IE_TCE_Pos)) +#define CAN_IE_TCFE_Pos _U_(10) /**< (CAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ +#define CAN_IE_TCFE_Msk (_U_(0x1) << CAN_IE_TCFE_Pos) /**< (CAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ +#define CAN_IE_TCFE(value) (CAN_IE_TCFE_Msk & ((value) << CAN_IE_TCFE_Pos)) +#define CAN_IE_TFEE_Pos _U_(11) /**< (CAN_IE) Tx FIFO Empty Interrupt Enable Position */ +#define CAN_IE_TFEE_Msk (_U_(0x1) << CAN_IE_TFEE_Pos) /**< (CAN_IE) Tx FIFO Empty Interrupt Enable Mask */ +#define CAN_IE_TFEE(value) (CAN_IE_TFEE_Msk & ((value) << CAN_IE_TFEE_Pos)) +#define CAN_IE_TEFNE_Pos _U_(12) /**< (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ +#define CAN_IE_TEFNE_Msk (_U_(0x1) << CAN_IE_TEFNE_Pos) /**< (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ +#define CAN_IE_TEFNE(value) (CAN_IE_TEFNE_Msk & ((value) << CAN_IE_TEFNE_Pos)) +#define CAN_IE_TEFWE_Pos _U_(13) /**< (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ +#define CAN_IE_TEFWE_Msk (_U_(0x1) << CAN_IE_TEFWE_Pos) /**< (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_TEFWE(value) (CAN_IE_TEFWE_Msk & ((value) << CAN_IE_TEFWE_Pos)) +#define CAN_IE_TEFFE_Pos _U_(14) /**< (CAN_IE) Tx Event FIFO Full Interrupt Enable Position */ +#define CAN_IE_TEFFE_Msk (_U_(0x1) << CAN_IE_TEFFE_Pos) /**< (CAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ +#define CAN_IE_TEFFE(value) (CAN_IE_TEFFE_Msk & ((value) << CAN_IE_TEFFE_Pos)) +#define CAN_IE_TEFLE_Pos _U_(15) /**< (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Position */ +#define CAN_IE_TEFLE_Msk (_U_(0x1) << CAN_IE_TEFLE_Pos) /**< (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Mask */ +#define CAN_IE_TEFLE(value) (CAN_IE_TEFLE_Msk & ((value) << CAN_IE_TEFLE_Pos)) +#define CAN_IE_TSWE_Pos _U_(16) /**< (CAN_IE) Timestamp Wraparound Interrupt Enable Position */ +#define CAN_IE_TSWE_Msk (_U_(0x1) << CAN_IE_TSWE_Pos) /**< (CAN_IE) Timestamp Wraparound Interrupt Enable Mask */ +#define CAN_IE_TSWE(value) (CAN_IE_TSWE_Msk & ((value) << CAN_IE_TSWE_Pos)) +#define CAN_IE_MRAFE_Pos _U_(17) /**< (CAN_IE) Message RAM Access Failure Interrupt Enable Position */ +#define CAN_IE_MRAFE_Msk (_U_(0x1) << CAN_IE_MRAFE_Pos) /**< (CAN_IE) Message RAM Access Failure Interrupt Enable Mask */ +#define CAN_IE_MRAFE(value) (CAN_IE_MRAFE_Msk & ((value) << CAN_IE_MRAFE_Pos)) +#define CAN_IE_TOOE_Pos _U_(18) /**< (CAN_IE) Timeout Occurred Interrupt Enable Position */ +#define CAN_IE_TOOE_Msk (_U_(0x1) << CAN_IE_TOOE_Pos) /**< (CAN_IE) Timeout Occurred Interrupt Enable Mask */ +#define CAN_IE_TOOE(value) (CAN_IE_TOOE_Msk & ((value) << CAN_IE_TOOE_Pos)) +#define CAN_IE_DRXE_Pos _U_(19) /**< (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Position */ +#define CAN_IE_DRXE_Msk (_U_(0x1) << CAN_IE_DRXE_Pos) /**< (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Mask */ +#define CAN_IE_DRXE(value) (CAN_IE_DRXE_Msk & ((value) << CAN_IE_DRXE_Pos)) +#define CAN_IE_BECE_Pos _U_(20) /**< (CAN_IE) Bit Error Corrected Interrupt Enable Position */ +#define CAN_IE_BECE_Msk (_U_(0x1) << CAN_IE_BECE_Pos) /**< (CAN_IE) Bit Error Corrected Interrupt Enable Mask */ +#define CAN_IE_BECE(value) (CAN_IE_BECE_Msk & ((value) << CAN_IE_BECE_Pos)) +#define CAN_IE_BEUE_Pos _U_(21) /**< (CAN_IE) Bit Error Uncorrected Interrupt Enable Position */ +#define CAN_IE_BEUE_Msk (_U_(0x1) << CAN_IE_BEUE_Pos) /**< (CAN_IE) Bit Error Uncorrected Interrupt Enable Mask */ +#define CAN_IE_BEUE(value) (CAN_IE_BEUE_Msk & ((value) << CAN_IE_BEUE_Pos)) +#define CAN_IE_ELOE_Pos _U_(22) /**< (CAN_IE) Error Logging Overflow Interrupt Enable Position */ +#define CAN_IE_ELOE_Msk (_U_(0x1) << CAN_IE_ELOE_Pos) /**< (CAN_IE) Error Logging Overflow Interrupt Enable Mask */ +#define CAN_IE_ELOE(value) (CAN_IE_ELOE_Msk & ((value) << CAN_IE_ELOE_Pos)) +#define CAN_IE_EPE_Pos _U_(23) /**< (CAN_IE) Error Passive Interrupt Enable Position */ +#define CAN_IE_EPE_Msk (_U_(0x1) << CAN_IE_EPE_Pos) /**< (CAN_IE) Error Passive Interrupt Enable Mask */ +#define CAN_IE_EPE(value) (CAN_IE_EPE_Msk & ((value) << CAN_IE_EPE_Pos)) +#define CAN_IE_EWE_Pos _U_(24) /**< (CAN_IE) Warning Status Interrupt Enable Position */ +#define CAN_IE_EWE_Msk (_U_(0x1) << CAN_IE_EWE_Pos) /**< (CAN_IE) Warning Status Interrupt Enable Mask */ +#define CAN_IE_EWE(value) (CAN_IE_EWE_Msk & ((value) << CAN_IE_EWE_Pos)) +#define CAN_IE_BOE_Pos _U_(25) /**< (CAN_IE) Bus_Off Status Interrupt Enable Position */ +#define CAN_IE_BOE_Msk (_U_(0x1) << CAN_IE_BOE_Pos) /**< (CAN_IE) Bus_Off Status Interrupt Enable Mask */ +#define CAN_IE_BOE(value) (CAN_IE_BOE_Msk & ((value) << CAN_IE_BOE_Pos)) +#define CAN_IE_WDIE_Pos _U_(26) /**< (CAN_IE) Watchdog Interrupt Interrupt Enable Position */ +#define CAN_IE_WDIE_Msk (_U_(0x1) << CAN_IE_WDIE_Pos) /**< (CAN_IE) Watchdog Interrupt Interrupt Enable Mask */ +#define CAN_IE_WDIE(value) (CAN_IE_WDIE_Msk & ((value) << CAN_IE_WDIE_Pos)) +#define CAN_IE_PEAE_Pos _U_(27) /**< (CAN_IE) Protocol Error in Arbitration Phase Enable Position */ +#define CAN_IE_PEAE_Msk (_U_(0x1) << CAN_IE_PEAE_Pos) /**< (CAN_IE) Protocol Error in Arbitration Phase Enable Mask */ +#define CAN_IE_PEAE(value) (CAN_IE_PEAE_Msk & ((value) << CAN_IE_PEAE_Pos)) +#define CAN_IE_PEDE_Pos _U_(28) /**< (CAN_IE) Protocol Error in Data Phase Enable Position */ +#define CAN_IE_PEDE_Msk (_U_(0x1) << CAN_IE_PEDE_Pos) /**< (CAN_IE) Protocol Error in Data Phase Enable Mask */ +#define CAN_IE_PEDE(value) (CAN_IE_PEDE_Msk & ((value) << CAN_IE_PEDE_Pos)) +#define CAN_IE_ARAE_Pos _U_(29) /**< (CAN_IE) Access to Reserved Address Enable Position */ +#define CAN_IE_ARAE_Msk (_U_(0x1) << CAN_IE_ARAE_Pos) /**< (CAN_IE) Access to Reserved Address Enable Mask */ +#define CAN_IE_ARAE(value) (CAN_IE_ARAE_Msk & ((value) << CAN_IE_ARAE_Pos)) +#define CAN_IE_Msk _U_(0x3FFFFFFF) /**< (CAN_IE) Register Mask */ + + +/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ +#define CAN_ILS_RESETVALUE _U_(0x00) /**< (CAN_ILS) Interrupt Line Select Reset Value */ + +#define CAN_ILS_RF0NL_Pos _U_(0) /**< (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Position */ +#define CAN_ILS_RF0NL_Msk (_U_(0x1) << CAN_ILS_RF0NL_Pos) /**< (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Mask */ +#define CAN_ILS_RF0NL(value) (CAN_ILS_RF0NL_Msk & ((value) << CAN_ILS_RF0NL_Pos)) +#define CAN_ILS_RF0WL_Pos _U_(1) /**< (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF0WL_Msk (_U_(0x1) << CAN_ILS_RF0WL_Pos) /**< (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF0WL(value) (CAN_ILS_RF0WL_Msk & ((value) << CAN_ILS_RF0WL_Pos)) +#define CAN_ILS_RF0FL_Pos _U_(2) /**< (CAN_ILS) Rx FIFO 0 Full Interrupt Line Position */ +#define CAN_ILS_RF0FL_Msk (_U_(0x1) << CAN_ILS_RF0FL_Pos) /**< (CAN_ILS) Rx FIFO 0 Full Interrupt Line Mask */ +#define CAN_ILS_RF0FL(value) (CAN_ILS_RF0FL_Msk & ((value) << CAN_ILS_RF0FL_Pos)) +#define CAN_ILS_RF0LL_Pos _U_(3) /**< (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF0LL_Msk (_U_(0x1) << CAN_ILS_RF0LL_Pos) /**< (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF0LL(value) (CAN_ILS_RF0LL_Msk & ((value) << CAN_ILS_RF0LL_Pos)) +#define CAN_ILS_RF1NL_Pos _U_(4) /**< (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Position */ +#define CAN_ILS_RF1NL_Msk (_U_(0x1) << CAN_ILS_RF1NL_Pos) /**< (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Mask */ +#define CAN_ILS_RF1NL(value) (CAN_ILS_RF1NL_Msk & ((value) << CAN_ILS_RF1NL_Pos)) +#define CAN_ILS_RF1WL_Pos _U_(5) /**< (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF1WL_Msk (_U_(0x1) << CAN_ILS_RF1WL_Pos) /**< (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF1WL(value) (CAN_ILS_RF1WL_Msk & ((value) << CAN_ILS_RF1WL_Pos)) +#define CAN_ILS_RF1FL_Pos _U_(6) /**< (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Position */ +#define CAN_ILS_RF1FL_Msk (_U_(0x1) << CAN_ILS_RF1FL_Pos) /**< (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Mask */ +#define CAN_ILS_RF1FL(value) (CAN_ILS_RF1FL_Msk & ((value) << CAN_ILS_RF1FL_Pos)) +#define CAN_ILS_RF1LL_Pos _U_(7) /**< (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF1LL_Msk (_U_(0x1) << CAN_ILS_RF1LL_Pos) /**< (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF1LL(value) (CAN_ILS_RF1LL_Msk & ((value) << CAN_ILS_RF1LL_Pos)) +#define CAN_ILS_HPML_Pos _U_(8) /**< (CAN_ILS) High Priority Message Interrupt Line Position */ +#define CAN_ILS_HPML_Msk (_U_(0x1) << CAN_ILS_HPML_Pos) /**< (CAN_ILS) High Priority Message Interrupt Line Mask */ +#define CAN_ILS_HPML(value) (CAN_ILS_HPML_Msk & ((value) << CAN_ILS_HPML_Pos)) +#define CAN_ILS_TCL_Pos _U_(9) /**< (CAN_ILS) Timestamp Completed Interrupt Line Position */ +#define CAN_ILS_TCL_Msk (_U_(0x1) << CAN_ILS_TCL_Pos) /**< (CAN_ILS) Timestamp Completed Interrupt Line Mask */ +#define CAN_ILS_TCL(value) (CAN_ILS_TCL_Msk & ((value) << CAN_ILS_TCL_Pos)) +#define CAN_ILS_TCFL_Pos _U_(10) /**< (CAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ +#define CAN_ILS_TCFL_Msk (_U_(0x1) << CAN_ILS_TCFL_Pos) /**< (CAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ +#define CAN_ILS_TCFL(value) (CAN_ILS_TCFL_Msk & ((value) << CAN_ILS_TCFL_Pos)) +#define CAN_ILS_TFEL_Pos _U_(11) /**< (CAN_ILS) Tx FIFO Empty Interrupt Line Position */ +#define CAN_ILS_TFEL_Msk (_U_(0x1) << CAN_ILS_TFEL_Pos) /**< (CAN_ILS) Tx FIFO Empty Interrupt Line Mask */ +#define CAN_ILS_TFEL(value) (CAN_ILS_TFEL_Msk & ((value) << CAN_ILS_TFEL_Pos)) +#define CAN_ILS_TEFNL_Pos _U_(12) /**< (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ +#define CAN_ILS_TEFNL_Msk (_U_(0x1) << CAN_ILS_TEFNL_Pos) /**< (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ +#define CAN_ILS_TEFNL(value) (CAN_ILS_TEFNL_Msk & ((value) << CAN_ILS_TEFNL_Pos)) +#define CAN_ILS_TEFWL_Pos _U_(13) /**< (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ +#define CAN_ILS_TEFWL_Msk (_U_(0x1) << CAN_ILS_TEFWL_Pos) /**< (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_TEFWL(value) (CAN_ILS_TEFWL_Msk & ((value) << CAN_ILS_TEFWL_Pos)) +#define CAN_ILS_TEFFL_Pos _U_(14) /**< (CAN_ILS) Tx Event FIFO Full Interrupt Line Position */ +#define CAN_ILS_TEFFL_Msk (_U_(0x1) << CAN_ILS_TEFFL_Pos) /**< (CAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ +#define CAN_ILS_TEFFL(value) (CAN_ILS_TEFFL_Msk & ((value) << CAN_ILS_TEFFL_Pos)) +#define CAN_ILS_TEFLL_Pos _U_(15) /**< (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Position */ +#define CAN_ILS_TEFLL_Msk (_U_(0x1) << CAN_ILS_TEFLL_Pos) /**< (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Mask */ +#define CAN_ILS_TEFLL(value) (CAN_ILS_TEFLL_Msk & ((value) << CAN_ILS_TEFLL_Pos)) +#define CAN_ILS_TSWL_Pos _U_(16) /**< (CAN_ILS) Timestamp Wraparound Interrupt Line Position */ +#define CAN_ILS_TSWL_Msk (_U_(0x1) << CAN_ILS_TSWL_Pos) /**< (CAN_ILS) Timestamp Wraparound Interrupt Line Mask */ +#define CAN_ILS_TSWL(value) (CAN_ILS_TSWL_Msk & ((value) << CAN_ILS_TSWL_Pos)) +#define CAN_ILS_MRAFL_Pos _U_(17) /**< (CAN_ILS) Message RAM Access Failure Interrupt Line Position */ +#define CAN_ILS_MRAFL_Msk (_U_(0x1) << CAN_ILS_MRAFL_Pos) /**< (CAN_ILS) Message RAM Access Failure Interrupt Line Mask */ +#define CAN_ILS_MRAFL(value) (CAN_ILS_MRAFL_Msk & ((value) << CAN_ILS_MRAFL_Pos)) +#define CAN_ILS_TOOL_Pos _U_(18) /**< (CAN_ILS) Timeout Occurred Interrupt Line Position */ +#define CAN_ILS_TOOL_Msk (_U_(0x1) << CAN_ILS_TOOL_Pos) /**< (CAN_ILS) Timeout Occurred Interrupt Line Mask */ +#define CAN_ILS_TOOL(value) (CAN_ILS_TOOL_Msk & ((value) << CAN_ILS_TOOL_Pos)) +#define CAN_ILS_DRXL_Pos _U_(19) /**< (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Position */ +#define CAN_ILS_DRXL_Msk (_U_(0x1) << CAN_ILS_DRXL_Pos) /**< (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Mask */ +#define CAN_ILS_DRXL(value) (CAN_ILS_DRXL_Msk & ((value) << CAN_ILS_DRXL_Pos)) +#define CAN_ILS_BECL_Pos _U_(20) /**< (CAN_ILS) Bit Error Corrected Interrupt Line Position */ +#define CAN_ILS_BECL_Msk (_U_(0x1) << CAN_ILS_BECL_Pos) /**< (CAN_ILS) Bit Error Corrected Interrupt Line Mask */ +#define CAN_ILS_BECL(value) (CAN_ILS_BECL_Msk & ((value) << CAN_ILS_BECL_Pos)) +#define CAN_ILS_BEUL_Pos _U_(21) /**< (CAN_ILS) Bit Error Uncorrected Interrupt Line Position */ +#define CAN_ILS_BEUL_Msk (_U_(0x1) << CAN_ILS_BEUL_Pos) /**< (CAN_ILS) Bit Error Uncorrected Interrupt Line Mask */ +#define CAN_ILS_BEUL(value) (CAN_ILS_BEUL_Msk & ((value) << CAN_ILS_BEUL_Pos)) +#define CAN_ILS_ELOL_Pos _U_(22) /**< (CAN_ILS) Error Logging Overflow Interrupt Line Position */ +#define CAN_ILS_ELOL_Msk (_U_(0x1) << CAN_ILS_ELOL_Pos) /**< (CAN_ILS) Error Logging Overflow Interrupt Line Mask */ +#define CAN_ILS_ELOL(value) (CAN_ILS_ELOL_Msk & ((value) << CAN_ILS_ELOL_Pos)) +#define CAN_ILS_EPL_Pos _U_(23) /**< (CAN_ILS) Error Passive Interrupt Line Position */ +#define CAN_ILS_EPL_Msk (_U_(0x1) << CAN_ILS_EPL_Pos) /**< (CAN_ILS) Error Passive Interrupt Line Mask */ +#define CAN_ILS_EPL(value) (CAN_ILS_EPL_Msk & ((value) << CAN_ILS_EPL_Pos)) +#define CAN_ILS_EWL_Pos _U_(24) /**< (CAN_ILS) Warning Status Interrupt Line Position */ +#define CAN_ILS_EWL_Msk (_U_(0x1) << CAN_ILS_EWL_Pos) /**< (CAN_ILS) Warning Status Interrupt Line Mask */ +#define CAN_ILS_EWL(value) (CAN_ILS_EWL_Msk & ((value) << CAN_ILS_EWL_Pos)) +#define CAN_ILS_BOL_Pos _U_(25) /**< (CAN_ILS) Bus_Off Status Interrupt Line Position */ +#define CAN_ILS_BOL_Msk (_U_(0x1) << CAN_ILS_BOL_Pos) /**< (CAN_ILS) Bus_Off Status Interrupt Line Mask */ +#define CAN_ILS_BOL(value) (CAN_ILS_BOL_Msk & ((value) << CAN_ILS_BOL_Pos)) +#define CAN_ILS_WDIL_Pos _U_(26) /**< (CAN_ILS) Watchdog Interrupt Interrupt Line Position */ +#define CAN_ILS_WDIL_Msk (_U_(0x1) << CAN_ILS_WDIL_Pos) /**< (CAN_ILS) Watchdog Interrupt Interrupt Line Mask */ +#define CAN_ILS_WDIL(value) (CAN_ILS_WDIL_Msk & ((value) << CAN_ILS_WDIL_Pos)) +#define CAN_ILS_PEAL_Pos _U_(27) /**< (CAN_ILS) Protocol Error in Arbitration Phase Line Position */ +#define CAN_ILS_PEAL_Msk (_U_(0x1) << CAN_ILS_PEAL_Pos) /**< (CAN_ILS) Protocol Error in Arbitration Phase Line Mask */ +#define CAN_ILS_PEAL(value) (CAN_ILS_PEAL_Msk & ((value) << CAN_ILS_PEAL_Pos)) +#define CAN_ILS_PEDL_Pos _U_(28) /**< (CAN_ILS) Protocol Error in Data Phase Line Position */ +#define CAN_ILS_PEDL_Msk (_U_(0x1) << CAN_ILS_PEDL_Pos) /**< (CAN_ILS) Protocol Error in Data Phase Line Mask */ +#define CAN_ILS_PEDL(value) (CAN_ILS_PEDL_Msk & ((value) << CAN_ILS_PEDL_Pos)) +#define CAN_ILS_ARAL_Pos _U_(29) /**< (CAN_ILS) Access to Reserved Address Line Position */ +#define CAN_ILS_ARAL_Msk (_U_(0x1) << CAN_ILS_ARAL_Pos) /**< (CAN_ILS) Access to Reserved Address Line Mask */ +#define CAN_ILS_ARAL(value) (CAN_ILS_ARAL_Msk & ((value) << CAN_ILS_ARAL_Pos)) +#define CAN_ILS_Msk _U_(0x3FFFFFFF) /**< (CAN_ILS) Register Mask */ + + +/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ +#define CAN_ILE_RESETVALUE _U_(0x00) /**< (CAN_ILE) Interrupt Line Enable Reset Value */ + +#define CAN_ILE_EINT0_Pos _U_(0) /**< (CAN_ILE) Enable Interrupt Line 0 Position */ +#define CAN_ILE_EINT0_Msk (_U_(0x1) << CAN_ILE_EINT0_Pos) /**< (CAN_ILE) Enable Interrupt Line 0 Mask */ +#define CAN_ILE_EINT0(value) (CAN_ILE_EINT0_Msk & ((value) << CAN_ILE_EINT0_Pos)) +#define CAN_ILE_EINT1_Pos _U_(1) /**< (CAN_ILE) Enable Interrupt Line 1 Position */ +#define CAN_ILE_EINT1_Msk (_U_(0x1) << CAN_ILE_EINT1_Pos) /**< (CAN_ILE) Enable Interrupt Line 1 Mask */ +#define CAN_ILE_EINT1(value) (CAN_ILE_EINT1_Msk & ((value) << CAN_ILE_EINT1_Pos)) +#define CAN_ILE_Msk _U_(0x00000003) /**< (CAN_ILE) Register Mask */ + +#define CAN_ILE_EINT_Pos _U_(0) /**< (CAN_ILE Position) Enable Interrupt Line x */ +#define CAN_ILE_EINT_Msk (_U_(0x3) << CAN_ILE_EINT_Pos) /**< (CAN_ILE Mask) EINT */ +#define CAN_ILE_EINT(value) (CAN_ILE_EINT_Msk & ((value) << CAN_ILE_EINT_Pos)) + +/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ +#define CAN_GFC_RESETVALUE _U_(0x00) /**< (CAN_GFC) Global Filter Configuration Reset Value */ + +#define CAN_GFC_RRFE_Pos _U_(0) /**< (CAN_GFC) Reject Remote Frames Extended Position */ +#define CAN_GFC_RRFE_Msk (_U_(0x1) << CAN_GFC_RRFE_Pos) /**< (CAN_GFC) Reject Remote Frames Extended Mask */ +#define CAN_GFC_RRFE(value) (CAN_GFC_RRFE_Msk & ((value) << CAN_GFC_RRFE_Pos)) +#define CAN_GFC_RRFS_Pos _U_(1) /**< (CAN_GFC) Reject Remote Frames Standard Position */ +#define CAN_GFC_RRFS_Msk (_U_(0x1) << CAN_GFC_RRFS_Pos) /**< (CAN_GFC) Reject Remote Frames Standard Mask */ +#define CAN_GFC_RRFS(value) (CAN_GFC_RRFS_Msk & ((value) << CAN_GFC_RRFS_Pos)) +#define CAN_GFC_ANFE_Pos _U_(2) /**< (CAN_GFC) Accept Non-matching Frames Extended Position */ +#define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos) /**< (CAN_GFC) Accept Non-matching Frames Extended Mask */ +#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos)) +#define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< (CAN_GFC) Reject */ +#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) /**< (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) /**< (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) /**< (CAN_GFC) Reject Position */ +#define CAN_GFC_ANFS_Pos _U_(4) /**< (CAN_GFC) Accept Non-matching Frames Standard Position */ +#define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos) /**< (CAN_GFC) Accept Non-matching Frames Standard Mask */ +#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos)) +#define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< (CAN_GFC) Reject */ +#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) /**< (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) /**< (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) /**< (CAN_GFC) Reject Position */ +#define CAN_GFC_Msk _U_(0x0000003F) /**< (CAN_GFC) Register Mask */ + + +/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ +#define CAN_SIDFC_RESETVALUE _U_(0x00) /**< (CAN_SIDFC) Standard ID Filter Configuration Reset Value */ + +#define CAN_SIDFC_FLSSA_Pos _U_(0) /**< (CAN_SIDFC) Filter List Standard Start Address Position */ +#define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) /**< (CAN_SIDFC) Filter List Standard Start Address Mask */ +#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos)) +#define CAN_SIDFC_LSS_Pos _U_(16) /**< (CAN_SIDFC) List Size Standard Position */ +#define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos) /**< (CAN_SIDFC) List Size Standard Mask */ +#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos)) +#define CAN_SIDFC_Msk _U_(0x00FFFFFF) /**< (CAN_SIDFC) Register Mask */ + + +/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_XIDFC_RESETVALUE _U_(0x00) /**< (CAN_XIDFC) Extended ID Filter Configuration Reset Value */ + +#define CAN_XIDFC_FLESA_Pos _U_(0) /**< (CAN_XIDFC) Filter List Extended Start Address Position */ +#define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos) /**< (CAN_XIDFC) Filter List Extended Start Address Mask */ +#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos)) +#define CAN_XIDFC_LSE_Pos _U_(16) /**< (CAN_XIDFC) List Size Extended Position */ +#define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos) /**< (CAN_XIDFC) List Size Extended Mask */ +#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos)) +#define CAN_XIDFC_Msk _U_(0x007FFFFF) /**< (CAN_XIDFC) Register Mask */ + + +/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ +#define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< (CAN_XIDAM) Extended ID AND Mask Reset Value */ + +#define CAN_XIDAM_EIDM_Pos _U_(0) /**< (CAN_XIDAM) Extended ID Mask Position */ +#define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) /**< (CAN_XIDAM) Extended ID Mask Mask */ +#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos)) +#define CAN_XIDAM_Msk _U_(0x1FFFFFFF) /**< (CAN_XIDAM) Register Mask */ + + +/* -------- CAN_HPMS : (CAN Offset: 0x94) ( R/ 32) High Priority Message Status -------- */ +#define CAN_HPMS_RESETVALUE _U_(0x00) /**< (CAN_HPMS) High Priority Message Status Reset Value */ + +#define CAN_HPMS_BIDX_Pos _U_(0) /**< (CAN_HPMS) Buffer Index Position */ +#define CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos) /**< (CAN_HPMS) Buffer Index Mask */ +#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos)) +#define CAN_HPMS_MSI_Pos _U_(6) /**< (CAN_HPMS) Message Storage Indicator Position */ +#define CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos) /**< (CAN_HPMS) Message Storage Indicator Mask */ +#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos)) +#define CAN_HPMS_MSI_NONE_Val _U_(0x0) /**< (CAN_HPMS) No FIFO selected */ +#define CAN_HPMS_MSI_LOST_Val _U_(0x1) /**< (CAN_HPMS) FIFO message lost */ +#define CAN_HPMS_MSI_FIFO0_Val _U_(0x2) /**< (CAN_HPMS) Message stored in FIFO 0 */ +#define CAN_HPMS_MSI_FIFO1_Val _U_(0x3) /**< (CAN_HPMS) Message stored in FIFO 1 */ +#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) /**< (CAN_HPMS) No FIFO selected Position */ +#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) /**< (CAN_HPMS) FIFO message lost Position */ +#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) /**< (CAN_HPMS) Message stored in FIFO 0 Position */ +#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) /**< (CAN_HPMS) Message stored in FIFO 1 Position */ +#define CAN_HPMS_FIDX_Pos _U_(8) /**< (CAN_HPMS) Filter Index Position */ +#define CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos) /**< (CAN_HPMS) Filter Index Mask */ +#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos)) +#define CAN_HPMS_FLST_Pos _U_(15) /**< (CAN_HPMS) Filter List Position */ +#define CAN_HPMS_FLST_Msk (_U_(0x1) << CAN_HPMS_FLST_Pos) /**< (CAN_HPMS) Filter List Mask */ +#define CAN_HPMS_FLST(value) (CAN_HPMS_FLST_Msk & ((value) << CAN_HPMS_FLST_Pos)) +#define CAN_HPMS_Msk _U_(0x0000FFFF) /**< (CAN_HPMS) Register Mask */ + + +/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ +#define CAN_NDAT1_RESETVALUE _U_(0x00) /**< (CAN_NDAT1) New Data 1 Reset Value */ + +#define CAN_NDAT1_ND0_Pos _U_(0) /**< (CAN_NDAT1) New Data 0 Position */ +#define CAN_NDAT1_ND0_Msk (_U_(0x1) << CAN_NDAT1_ND0_Pos) /**< (CAN_NDAT1) New Data 0 Mask */ +#define CAN_NDAT1_ND0(value) (CAN_NDAT1_ND0_Msk & ((value) << CAN_NDAT1_ND0_Pos)) +#define CAN_NDAT1_ND1_Pos _U_(1) /**< (CAN_NDAT1) New Data 1 Position */ +#define CAN_NDAT1_ND1_Msk (_U_(0x1) << CAN_NDAT1_ND1_Pos) /**< (CAN_NDAT1) New Data 1 Mask */ +#define CAN_NDAT1_ND1(value) (CAN_NDAT1_ND1_Msk & ((value) << CAN_NDAT1_ND1_Pos)) +#define CAN_NDAT1_ND2_Pos _U_(2) /**< (CAN_NDAT1) New Data 2 Position */ +#define CAN_NDAT1_ND2_Msk (_U_(0x1) << CAN_NDAT1_ND2_Pos) /**< (CAN_NDAT1) New Data 2 Mask */ +#define CAN_NDAT1_ND2(value) (CAN_NDAT1_ND2_Msk & ((value) << CAN_NDAT1_ND2_Pos)) +#define CAN_NDAT1_ND3_Pos _U_(3) /**< (CAN_NDAT1) New Data 3 Position */ +#define CAN_NDAT1_ND3_Msk (_U_(0x1) << CAN_NDAT1_ND3_Pos) /**< (CAN_NDAT1) New Data 3 Mask */ +#define CAN_NDAT1_ND3(value) (CAN_NDAT1_ND3_Msk & ((value) << CAN_NDAT1_ND3_Pos)) +#define CAN_NDAT1_ND4_Pos _U_(4) /**< (CAN_NDAT1) New Data 4 Position */ +#define CAN_NDAT1_ND4_Msk (_U_(0x1) << CAN_NDAT1_ND4_Pos) /**< (CAN_NDAT1) New Data 4 Mask */ +#define CAN_NDAT1_ND4(value) (CAN_NDAT1_ND4_Msk & ((value) << CAN_NDAT1_ND4_Pos)) +#define CAN_NDAT1_ND5_Pos _U_(5) /**< (CAN_NDAT1) New Data 5 Position */ +#define CAN_NDAT1_ND5_Msk (_U_(0x1) << CAN_NDAT1_ND5_Pos) /**< (CAN_NDAT1) New Data 5 Mask */ +#define CAN_NDAT1_ND5(value) (CAN_NDAT1_ND5_Msk & ((value) << CAN_NDAT1_ND5_Pos)) +#define CAN_NDAT1_ND6_Pos _U_(6) /**< (CAN_NDAT1) New Data 6 Position */ +#define CAN_NDAT1_ND6_Msk (_U_(0x1) << CAN_NDAT1_ND6_Pos) /**< (CAN_NDAT1) New Data 6 Mask */ +#define CAN_NDAT1_ND6(value) (CAN_NDAT1_ND6_Msk & ((value) << CAN_NDAT1_ND6_Pos)) +#define CAN_NDAT1_ND7_Pos _U_(7) /**< (CAN_NDAT1) New Data 7 Position */ +#define CAN_NDAT1_ND7_Msk (_U_(0x1) << CAN_NDAT1_ND7_Pos) /**< (CAN_NDAT1) New Data 7 Mask */ +#define CAN_NDAT1_ND7(value) (CAN_NDAT1_ND7_Msk & ((value) << CAN_NDAT1_ND7_Pos)) +#define CAN_NDAT1_ND8_Pos _U_(8) /**< (CAN_NDAT1) New Data 8 Position */ +#define CAN_NDAT1_ND8_Msk (_U_(0x1) << CAN_NDAT1_ND8_Pos) /**< (CAN_NDAT1) New Data 8 Mask */ +#define CAN_NDAT1_ND8(value) (CAN_NDAT1_ND8_Msk & ((value) << CAN_NDAT1_ND8_Pos)) +#define CAN_NDAT1_ND9_Pos _U_(9) /**< (CAN_NDAT1) New Data 9 Position */ +#define CAN_NDAT1_ND9_Msk (_U_(0x1) << CAN_NDAT1_ND9_Pos) /**< (CAN_NDAT1) New Data 9 Mask */ +#define CAN_NDAT1_ND9(value) (CAN_NDAT1_ND9_Msk & ((value) << CAN_NDAT1_ND9_Pos)) +#define CAN_NDAT1_ND10_Pos _U_(10) /**< (CAN_NDAT1) New Data 10 Position */ +#define CAN_NDAT1_ND10_Msk (_U_(0x1) << CAN_NDAT1_ND10_Pos) /**< (CAN_NDAT1) New Data 10 Mask */ +#define CAN_NDAT1_ND10(value) (CAN_NDAT1_ND10_Msk & ((value) << CAN_NDAT1_ND10_Pos)) +#define CAN_NDAT1_ND11_Pos _U_(11) /**< (CAN_NDAT1) New Data 11 Position */ +#define CAN_NDAT1_ND11_Msk (_U_(0x1) << CAN_NDAT1_ND11_Pos) /**< (CAN_NDAT1) New Data 11 Mask */ +#define CAN_NDAT1_ND11(value) (CAN_NDAT1_ND11_Msk & ((value) << CAN_NDAT1_ND11_Pos)) +#define CAN_NDAT1_ND12_Pos _U_(12) /**< (CAN_NDAT1) New Data 12 Position */ +#define CAN_NDAT1_ND12_Msk (_U_(0x1) << CAN_NDAT1_ND12_Pos) /**< (CAN_NDAT1) New Data 12 Mask */ +#define CAN_NDAT1_ND12(value) (CAN_NDAT1_ND12_Msk & ((value) << CAN_NDAT1_ND12_Pos)) +#define CAN_NDAT1_ND13_Pos _U_(13) /**< (CAN_NDAT1) New Data 13 Position */ +#define CAN_NDAT1_ND13_Msk (_U_(0x1) << CAN_NDAT1_ND13_Pos) /**< (CAN_NDAT1) New Data 13 Mask */ +#define CAN_NDAT1_ND13(value) (CAN_NDAT1_ND13_Msk & ((value) << CAN_NDAT1_ND13_Pos)) +#define CAN_NDAT1_ND14_Pos _U_(14) /**< (CAN_NDAT1) New Data 14 Position */ +#define CAN_NDAT1_ND14_Msk (_U_(0x1) << CAN_NDAT1_ND14_Pos) /**< (CAN_NDAT1) New Data 14 Mask */ +#define CAN_NDAT1_ND14(value) (CAN_NDAT1_ND14_Msk & ((value) << CAN_NDAT1_ND14_Pos)) +#define CAN_NDAT1_ND15_Pos _U_(15) /**< (CAN_NDAT1) New Data 15 Position */ +#define CAN_NDAT1_ND15_Msk (_U_(0x1) << CAN_NDAT1_ND15_Pos) /**< (CAN_NDAT1) New Data 15 Mask */ +#define CAN_NDAT1_ND15(value) (CAN_NDAT1_ND15_Msk & ((value) << CAN_NDAT1_ND15_Pos)) +#define CAN_NDAT1_ND16_Pos _U_(16) /**< (CAN_NDAT1) New Data 16 Position */ +#define CAN_NDAT1_ND16_Msk (_U_(0x1) << CAN_NDAT1_ND16_Pos) /**< (CAN_NDAT1) New Data 16 Mask */ +#define CAN_NDAT1_ND16(value) (CAN_NDAT1_ND16_Msk & ((value) << CAN_NDAT1_ND16_Pos)) +#define CAN_NDAT1_ND17_Pos _U_(17) /**< (CAN_NDAT1) New Data 17 Position */ +#define CAN_NDAT1_ND17_Msk (_U_(0x1) << CAN_NDAT1_ND17_Pos) /**< (CAN_NDAT1) New Data 17 Mask */ +#define CAN_NDAT1_ND17(value) (CAN_NDAT1_ND17_Msk & ((value) << CAN_NDAT1_ND17_Pos)) +#define CAN_NDAT1_ND18_Pos _U_(18) /**< (CAN_NDAT1) New Data 18 Position */ +#define CAN_NDAT1_ND18_Msk (_U_(0x1) << CAN_NDAT1_ND18_Pos) /**< (CAN_NDAT1) New Data 18 Mask */ +#define CAN_NDAT1_ND18(value) (CAN_NDAT1_ND18_Msk & ((value) << CAN_NDAT1_ND18_Pos)) +#define CAN_NDAT1_ND19_Pos _U_(19) /**< (CAN_NDAT1) New Data 19 Position */ +#define CAN_NDAT1_ND19_Msk (_U_(0x1) << CAN_NDAT1_ND19_Pos) /**< (CAN_NDAT1) New Data 19 Mask */ +#define CAN_NDAT1_ND19(value) (CAN_NDAT1_ND19_Msk & ((value) << CAN_NDAT1_ND19_Pos)) +#define CAN_NDAT1_ND20_Pos _U_(20) /**< (CAN_NDAT1) New Data 20 Position */ +#define CAN_NDAT1_ND20_Msk (_U_(0x1) << CAN_NDAT1_ND20_Pos) /**< (CAN_NDAT1) New Data 20 Mask */ +#define CAN_NDAT1_ND20(value) (CAN_NDAT1_ND20_Msk & ((value) << CAN_NDAT1_ND20_Pos)) +#define CAN_NDAT1_ND21_Pos _U_(21) /**< (CAN_NDAT1) New Data 21 Position */ +#define CAN_NDAT1_ND21_Msk (_U_(0x1) << CAN_NDAT1_ND21_Pos) /**< (CAN_NDAT1) New Data 21 Mask */ +#define CAN_NDAT1_ND21(value) (CAN_NDAT1_ND21_Msk & ((value) << CAN_NDAT1_ND21_Pos)) +#define CAN_NDAT1_ND22_Pos _U_(22) /**< (CAN_NDAT1) New Data 22 Position */ +#define CAN_NDAT1_ND22_Msk (_U_(0x1) << CAN_NDAT1_ND22_Pos) /**< (CAN_NDAT1) New Data 22 Mask */ +#define CAN_NDAT1_ND22(value) (CAN_NDAT1_ND22_Msk & ((value) << CAN_NDAT1_ND22_Pos)) +#define CAN_NDAT1_ND23_Pos _U_(23) /**< (CAN_NDAT1) New Data 23 Position */ +#define CAN_NDAT1_ND23_Msk (_U_(0x1) << CAN_NDAT1_ND23_Pos) /**< (CAN_NDAT1) New Data 23 Mask */ +#define CAN_NDAT1_ND23(value) (CAN_NDAT1_ND23_Msk & ((value) << CAN_NDAT1_ND23_Pos)) +#define CAN_NDAT1_ND24_Pos _U_(24) /**< (CAN_NDAT1) New Data 24 Position */ +#define CAN_NDAT1_ND24_Msk (_U_(0x1) << CAN_NDAT1_ND24_Pos) /**< (CAN_NDAT1) New Data 24 Mask */ +#define CAN_NDAT1_ND24(value) (CAN_NDAT1_ND24_Msk & ((value) << CAN_NDAT1_ND24_Pos)) +#define CAN_NDAT1_ND25_Pos _U_(25) /**< (CAN_NDAT1) New Data 25 Position */ +#define CAN_NDAT1_ND25_Msk (_U_(0x1) << CAN_NDAT1_ND25_Pos) /**< (CAN_NDAT1) New Data 25 Mask */ +#define CAN_NDAT1_ND25(value) (CAN_NDAT1_ND25_Msk & ((value) << CAN_NDAT1_ND25_Pos)) +#define CAN_NDAT1_ND26_Pos _U_(26) /**< (CAN_NDAT1) New Data 26 Position */ +#define CAN_NDAT1_ND26_Msk (_U_(0x1) << CAN_NDAT1_ND26_Pos) /**< (CAN_NDAT1) New Data 26 Mask */ +#define CAN_NDAT1_ND26(value) (CAN_NDAT1_ND26_Msk & ((value) << CAN_NDAT1_ND26_Pos)) +#define CAN_NDAT1_ND27_Pos _U_(27) /**< (CAN_NDAT1) New Data 27 Position */ +#define CAN_NDAT1_ND27_Msk (_U_(0x1) << CAN_NDAT1_ND27_Pos) /**< (CAN_NDAT1) New Data 27 Mask */ +#define CAN_NDAT1_ND27(value) (CAN_NDAT1_ND27_Msk & ((value) << CAN_NDAT1_ND27_Pos)) +#define CAN_NDAT1_ND28_Pos _U_(28) /**< (CAN_NDAT1) New Data 28 Position */ +#define CAN_NDAT1_ND28_Msk (_U_(0x1) << CAN_NDAT1_ND28_Pos) /**< (CAN_NDAT1) New Data 28 Mask */ +#define CAN_NDAT1_ND28(value) (CAN_NDAT1_ND28_Msk & ((value) << CAN_NDAT1_ND28_Pos)) +#define CAN_NDAT1_ND29_Pos _U_(29) /**< (CAN_NDAT1) New Data 29 Position */ +#define CAN_NDAT1_ND29_Msk (_U_(0x1) << CAN_NDAT1_ND29_Pos) /**< (CAN_NDAT1) New Data 29 Mask */ +#define CAN_NDAT1_ND29(value) (CAN_NDAT1_ND29_Msk & ((value) << CAN_NDAT1_ND29_Pos)) +#define CAN_NDAT1_ND30_Pos _U_(30) /**< (CAN_NDAT1) New Data 30 Position */ +#define CAN_NDAT1_ND30_Msk (_U_(0x1) << CAN_NDAT1_ND30_Pos) /**< (CAN_NDAT1) New Data 30 Mask */ +#define CAN_NDAT1_ND30(value) (CAN_NDAT1_ND30_Msk & ((value) << CAN_NDAT1_ND30_Pos)) +#define CAN_NDAT1_ND31_Pos _U_(31) /**< (CAN_NDAT1) New Data 31 Position */ +#define CAN_NDAT1_ND31_Msk (_U_(0x1) << CAN_NDAT1_ND31_Pos) /**< (CAN_NDAT1) New Data 31 Mask */ +#define CAN_NDAT1_ND31(value) (CAN_NDAT1_ND31_Msk & ((value) << CAN_NDAT1_ND31_Pos)) +#define CAN_NDAT1_Msk _U_(0xFFFFFFFF) /**< (CAN_NDAT1) Register Mask */ + +#define CAN_NDAT1_ND_Pos _U_(0) /**< (CAN_NDAT1 Position) New Data 3x */ +#define CAN_NDAT1_ND_Msk (_U_(0xFFFFFFFF) << CAN_NDAT1_ND_Pos) /**< (CAN_NDAT1 Mask) ND */ +#define CAN_NDAT1_ND(value) (CAN_NDAT1_ND_Msk & ((value) << CAN_NDAT1_ND_Pos)) + +/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ +#define CAN_NDAT2_RESETVALUE _U_(0x00) /**< (CAN_NDAT2) New Data 2 Reset Value */ + +#define CAN_NDAT2_ND32_Pos _U_(0) /**< (CAN_NDAT2) New Data 32 Position */ +#define CAN_NDAT2_ND32_Msk (_U_(0x1) << CAN_NDAT2_ND32_Pos) /**< (CAN_NDAT2) New Data 32 Mask */ +#define CAN_NDAT2_ND32(value) (CAN_NDAT2_ND32_Msk & ((value) << CAN_NDAT2_ND32_Pos)) +#define CAN_NDAT2_ND33_Pos _U_(1) /**< (CAN_NDAT2) New Data 33 Position */ +#define CAN_NDAT2_ND33_Msk (_U_(0x1) << CAN_NDAT2_ND33_Pos) /**< (CAN_NDAT2) New Data 33 Mask */ +#define CAN_NDAT2_ND33(value) (CAN_NDAT2_ND33_Msk & ((value) << CAN_NDAT2_ND33_Pos)) +#define CAN_NDAT2_ND34_Pos _U_(2) /**< (CAN_NDAT2) New Data 34 Position */ +#define CAN_NDAT2_ND34_Msk (_U_(0x1) << CAN_NDAT2_ND34_Pos) /**< (CAN_NDAT2) New Data 34 Mask */ +#define CAN_NDAT2_ND34(value) (CAN_NDAT2_ND34_Msk & ((value) << CAN_NDAT2_ND34_Pos)) +#define CAN_NDAT2_ND35_Pos _U_(3) /**< (CAN_NDAT2) New Data 35 Position */ +#define CAN_NDAT2_ND35_Msk (_U_(0x1) << CAN_NDAT2_ND35_Pos) /**< (CAN_NDAT2) New Data 35 Mask */ +#define CAN_NDAT2_ND35(value) (CAN_NDAT2_ND35_Msk & ((value) << CAN_NDAT2_ND35_Pos)) +#define CAN_NDAT2_ND36_Pos _U_(4) /**< (CAN_NDAT2) New Data 36 Position */ +#define CAN_NDAT2_ND36_Msk (_U_(0x1) << CAN_NDAT2_ND36_Pos) /**< (CAN_NDAT2) New Data 36 Mask */ +#define CAN_NDAT2_ND36(value) (CAN_NDAT2_ND36_Msk & ((value) << CAN_NDAT2_ND36_Pos)) +#define CAN_NDAT2_ND37_Pos _U_(5) /**< (CAN_NDAT2) New Data 37 Position */ +#define CAN_NDAT2_ND37_Msk (_U_(0x1) << CAN_NDAT2_ND37_Pos) /**< (CAN_NDAT2) New Data 37 Mask */ +#define CAN_NDAT2_ND37(value) (CAN_NDAT2_ND37_Msk & ((value) << CAN_NDAT2_ND37_Pos)) +#define CAN_NDAT2_ND38_Pos _U_(6) /**< (CAN_NDAT2) New Data 38 Position */ +#define CAN_NDAT2_ND38_Msk (_U_(0x1) << CAN_NDAT2_ND38_Pos) /**< (CAN_NDAT2) New Data 38 Mask */ +#define CAN_NDAT2_ND38(value) (CAN_NDAT2_ND38_Msk & ((value) << CAN_NDAT2_ND38_Pos)) +#define CAN_NDAT2_ND39_Pos _U_(7) /**< (CAN_NDAT2) New Data 39 Position */ +#define CAN_NDAT2_ND39_Msk (_U_(0x1) << CAN_NDAT2_ND39_Pos) /**< (CAN_NDAT2) New Data 39 Mask */ +#define CAN_NDAT2_ND39(value) (CAN_NDAT2_ND39_Msk & ((value) << CAN_NDAT2_ND39_Pos)) +#define CAN_NDAT2_ND40_Pos _U_(8) /**< (CAN_NDAT2) New Data 40 Position */ +#define CAN_NDAT2_ND40_Msk (_U_(0x1) << CAN_NDAT2_ND40_Pos) /**< (CAN_NDAT2) New Data 40 Mask */ +#define CAN_NDAT2_ND40(value) (CAN_NDAT2_ND40_Msk & ((value) << CAN_NDAT2_ND40_Pos)) +#define CAN_NDAT2_ND41_Pos _U_(9) /**< (CAN_NDAT2) New Data 41 Position */ +#define CAN_NDAT2_ND41_Msk (_U_(0x1) << CAN_NDAT2_ND41_Pos) /**< (CAN_NDAT2) New Data 41 Mask */ +#define CAN_NDAT2_ND41(value) (CAN_NDAT2_ND41_Msk & ((value) << CAN_NDAT2_ND41_Pos)) +#define CAN_NDAT2_ND42_Pos _U_(10) /**< (CAN_NDAT2) New Data 42 Position */ +#define CAN_NDAT2_ND42_Msk (_U_(0x1) << CAN_NDAT2_ND42_Pos) /**< (CAN_NDAT2) New Data 42 Mask */ +#define CAN_NDAT2_ND42(value) (CAN_NDAT2_ND42_Msk & ((value) << CAN_NDAT2_ND42_Pos)) +#define CAN_NDAT2_ND43_Pos _U_(11) /**< (CAN_NDAT2) New Data 43 Position */ +#define CAN_NDAT2_ND43_Msk (_U_(0x1) << CAN_NDAT2_ND43_Pos) /**< (CAN_NDAT2) New Data 43 Mask */ +#define CAN_NDAT2_ND43(value) (CAN_NDAT2_ND43_Msk & ((value) << CAN_NDAT2_ND43_Pos)) +#define CAN_NDAT2_ND44_Pos _U_(12) /**< (CAN_NDAT2) New Data 44 Position */ +#define CAN_NDAT2_ND44_Msk (_U_(0x1) << CAN_NDAT2_ND44_Pos) /**< (CAN_NDAT2) New Data 44 Mask */ +#define CAN_NDAT2_ND44(value) (CAN_NDAT2_ND44_Msk & ((value) << CAN_NDAT2_ND44_Pos)) +#define CAN_NDAT2_ND45_Pos _U_(13) /**< (CAN_NDAT2) New Data 45 Position */ +#define CAN_NDAT2_ND45_Msk (_U_(0x1) << CAN_NDAT2_ND45_Pos) /**< (CAN_NDAT2) New Data 45 Mask */ +#define CAN_NDAT2_ND45(value) (CAN_NDAT2_ND45_Msk & ((value) << CAN_NDAT2_ND45_Pos)) +#define CAN_NDAT2_ND46_Pos _U_(14) /**< (CAN_NDAT2) New Data 46 Position */ +#define CAN_NDAT2_ND46_Msk (_U_(0x1) << CAN_NDAT2_ND46_Pos) /**< (CAN_NDAT2) New Data 46 Mask */ +#define CAN_NDAT2_ND46(value) (CAN_NDAT2_ND46_Msk & ((value) << CAN_NDAT2_ND46_Pos)) +#define CAN_NDAT2_ND47_Pos _U_(15) /**< (CAN_NDAT2) New Data 47 Position */ +#define CAN_NDAT2_ND47_Msk (_U_(0x1) << CAN_NDAT2_ND47_Pos) /**< (CAN_NDAT2) New Data 47 Mask */ +#define CAN_NDAT2_ND47(value) (CAN_NDAT2_ND47_Msk & ((value) << CAN_NDAT2_ND47_Pos)) +#define CAN_NDAT2_ND48_Pos _U_(16) /**< (CAN_NDAT2) New Data 48 Position */ +#define CAN_NDAT2_ND48_Msk (_U_(0x1) << CAN_NDAT2_ND48_Pos) /**< (CAN_NDAT2) New Data 48 Mask */ +#define CAN_NDAT2_ND48(value) (CAN_NDAT2_ND48_Msk & ((value) << CAN_NDAT2_ND48_Pos)) +#define CAN_NDAT2_ND49_Pos _U_(17) /**< (CAN_NDAT2) New Data 49 Position */ +#define CAN_NDAT2_ND49_Msk (_U_(0x1) << CAN_NDAT2_ND49_Pos) /**< (CAN_NDAT2) New Data 49 Mask */ +#define CAN_NDAT2_ND49(value) (CAN_NDAT2_ND49_Msk & ((value) << CAN_NDAT2_ND49_Pos)) +#define CAN_NDAT2_ND50_Pos _U_(18) /**< (CAN_NDAT2) New Data 50 Position */ +#define CAN_NDAT2_ND50_Msk (_U_(0x1) << CAN_NDAT2_ND50_Pos) /**< (CAN_NDAT2) New Data 50 Mask */ +#define CAN_NDAT2_ND50(value) (CAN_NDAT2_ND50_Msk & ((value) << CAN_NDAT2_ND50_Pos)) +#define CAN_NDAT2_ND51_Pos _U_(19) /**< (CAN_NDAT2) New Data 51 Position */ +#define CAN_NDAT2_ND51_Msk (_U_(0x1) << CAN_NDAT2_ND51_Pos) /**< (CAN_NDAT2) New Data 51 Mask */ +#define CAN_NDAT2_ND51(value) (CAN_NDAT2_ND51_Msk & ((value) << CAN_NDAT2_ND51_Pos)) +#define CAN_NDAT2_ND52_Pos _U_(20) /**< (CAN_NDAT2) New Data 52 Position */ +#define CAN_NDAT2_ND52_Msk (_U_(0x1) << CAN_NDAT2_ND52_Pos) /**< (CAN_NDAT2) New Data 52 Mask */ +#define CAN_NDAT2_ND52(value) (CAN_NDAT2_ND52_Msk & ((value) << CAN_NDAT2_ND52_Pos)) +#define CAN_NDAT2_ND53_Pos _U_(21) /**< (CAN_NDAT2) New Data 53 Position */ +#define CAN_NDAT2_ND53_Msk (_U_(0x1) << CAN_NDAT2_ND53_Pos) /**< (CAN_NDAT2) New Data 53 Mask */ +#define CAN_NDAT2_ND53(value) (CAN_NDAT2_ND53_Msk & ((value) << CAN_NDAT2_ND53_Pos)) +#define CAN_NDAT2_ND54_Pos _U_(22) /**< (CAN_NDAT2) New Data 54 Position */ +#define CAN_NDAT2_ND54_Msk (_U_(0x1) << CAN_NDAT2_ND54_Pos) /**< (CAN_NDAT2) New Data 54 Mask */ +#define CAN_NDAT2_ND54(value) (CAN_NDAT2_ND54_Msk & ((value) << CAN_NDAT2_ND54_Pos)) +#define CAN_NDAT2_ND55_Pos _U_(23) /**< (CAN_NDAT2) New Data 55 Position */ +#define CAN_NDAT2_ND55_Msk (_U_(0x1) << CAN_NDAT2_ND55_Pos) /**< (CAN_NDAT2) New Data 55 Mask */ +#define CAN_NDAT2_ND55(value) (CAN_NDAT2_ND55_Msk & ((value) << CAN_NDAT2_ND55_Pos)) +#define CAN_NDAT2_ND56_Pos _U_(24) /**< (CAN_NDAT2) New Data 56 Position */ +#define CAN_NDAT2_ND56_Msk (_U_(0x1) << CAN_NDAT2_ND56_Pos) /**< (CAN_NDAT2) New Data 56 Mask */ +#define CAN_NDAT2_ND56(value) (CAN_NDAT2_ND56_Msk & ((value) << CAN_NDAT2_ND56_Pos)) +#define CAN_NDAT2_ND57_Pos _U_(25) /**< (CAN_NDAT2) New Data 57 Position */ +#define CAN_NDAT2_ND57_Msk (_U_(0x1) << CAN_NDAT2_ND57_Pos) /**< (CAN_NDAT2) New Data 57 Mask */ +#define CAN_NDAT2_ND57(value) (CAN_NDAT2_ND57_Msk & ((value) << CAN_NDAT2_ND57_Pos)) +#define CAN_NDAT2_ND58_Pos _U_(26) /**< (CAN_NDAT2) New Data 58 Position */ +#define CAN_NDAT2_ND58_Msk (_U_(0x1) << CAN_NDAT2_ND58_Pos) /**< (CAN_NDAT2) New Data 58 Mask */ +#define CAN_NDAT2_ND58(value) (CAN_NDAT2_ND58_Msk & ((value) << CAN_NDAT2_ND58_Pos)) +#define CAN_NDAT2_ND59_Pos _U_(27) /**< (CAN_NDAT2) New Data 59 Position */ +#define CAN_NDAT2_ND59_Msk (_U_(0x1) << CAN_NDAT2_ND59_Pos) /**< (CAN_NDAT2) New Data 59 Mask */ +#define CAN_NDAT2_ND59(value) (CAN_NDAT2_ND59_Msk & ((value) << CAN_NDAT2_ND59_Pos)) +#define CAN_NDAT2_ND60_Pos _U_(28) /**< (CAN_NDAT2) New Data 60 Position */ +#define CAN_NDAT2_ND60_Msk (_U_(0x1) << CAN_NDAT2_ND60_Pos) /**< (CAN_NDAT2) New Data 60 Mask */ +#define CAN_NDAT2_ND60(value) (CAN_NDAT2_ND60_Msk & ((value) << CAN_NDAT2_ND60_Pos)) +#define CAN_NDAT2_ND61_Pos _U_(29) /**< (CAN_NDAT2) New Data 61 Position */ +#define CAN_NDAT2_ND61_Msk (_U_(0x1) << CAN_NDAT2_ND61_Pos) /**< (CAN_NDAT2) New Data 61 Mask */ +#define CAN_NDAT2_ND61(value) (CAN_NDAT2_ND61_Msk & ((value) << CAN_NDAT2_ND61_Pos)) +#define CAN_NDAT2_ND62_Pos _U_(30) /**< (CAN_NDAT2) New Data 62 Position */ +#define CAN_NDAT2_ND62_Msk (_U_(0x1) << CAN_NDAT2_ND62_Pos) /**< (CAN_NDAT2) New Data 62 Mask */ +#define CAN_NDAT2_ND62(value) (CAN_NDAT2_ND62_Msk & ((value) << CAN_NDAT2_ND62_Pos)) +#define CAN_NDAT2_ND63_Pos _U_(31) /**< (CAN_NDAT2) New Data 63 Position */ +#define CAN_NDAT2_ND63_Msk (_U_(0x1) << CAN_NDAT2_ND63_Pos) /**< (CAN_NDAT2) New Data 63 Mask */ +#define CAN_NDAT2_ND63(value) (CAN_NDAT2_ND63_Msk & ((value) << CAN_NDAT2_ND63_Pos)) +#define CAN_NDAT2_Msk _U_(0xFFFFFFFF) /**< (CAN_NDAT2) Register Mask */ + +#define CAN_NDAT2_ND_Pos _U_(0) /**< (CAN_NDAT2 Position) New Data 63 */ +#define CAN_NDAT2_ND_Msk (_U_(0xFFFFFFFF) << CAN_NDAT2_ND_Pos) /**< (CAN_NDAT2 Mask) ND */ +#define CAN_NDAT2_ND(value) (CAN_NDAT2_ND_Msk & ((value) << CAN_NDAT2_ND_Pos)) + +/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ +#define CAN_RXF0C_RESETVALUE _U_(0x00) /**< (CAN_RXF0C) Rx FIFO 0 Configuration Reset Value */ + +#define CAN_RXF0C_F0SA_Pos _U_(0) /**< (CAN_RXF0C) Rx FIFO 0 Start Address Position */ +#define CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos) /**< (CAN_RXF0C) Rx FIFO 0 Start Address Mask */ +#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos)) +#define CAN_RXF0C_F0S_Pos _U_(16) /**< (CAN_RXF0C) Rx FIFO 0 Size Position */ +#define CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos) /**< (CAN_RXF0C) Rx FIFO 0 Size Mask */ +#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos)) +#define CAN_RXF0C_F0WM_Pos _U_(24) /**< (CAN_RXF0C) Rx FIFO 0 Watermark Position */ +#define CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos) /**< (CAN_RXF0C) Rx FIFO 0 Watermark Mask */ +#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos)) +#define CAN_RXF0C_F0OM_Pos _U_(31) /**< (CAN_RXF0C) FIFO 0 Operation Mode Position */ +#define CAN_RXF0C_F0OM_Msk (_U_(0x1) << CAN_RXF0C_F0OM_Pos) /**< (CAN_RXF0C) FIFO 0 Operation Mode Mask */ +#define CAN_RXF0C_F0OM(value) (CAN_RXF0C_F0OM_Msk & ((value) << CAN_RXF0C_F0OM_Pos)) +#define CAN_RXF0C_Msk _U_(0xFF7FFFFF) /**< (CAN_RXF0C) Register Mask */ + + +/* -------- CAN_RXF0S : (CAN Offset: 0xA4) ( R/ 32) Rx FIFO 0 Status -------- */ +#define CAN_RXF0S_RESETVALUE _U_(0x00) /**< (CAN_RXF0S) Rx FIFO 0 Status Reset Value */ + +#define CAN_RXF0S_F0FL_Pos _U_(0) /**< (CAN_RXF0S) Rx FIFO 0 Fill Level Position */ +#define CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos) /**< (CAN_RXF0S) Rx FIFO 0 Fill Level Mask */ +#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos)) +#define CAN_RXF0S_F0GI_Pos _U_(8) /**< (CAN_RXF0S) Rx FIFO 0 Get Index Position */ +#define CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos) /**< (CAN_RXF0S) Rx FIFO 0 Get Index Mask */ +#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos)) +#define CAN_RXF0S_F0PI_Pos _U_(16) /**< (CAN_RXF0S) Rx FIFO 0 Put Index Position */ +#define CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos) /**< (CAN_RXF0S) Rx FIFO 0 Put Index Mask */ +#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos)) +#define CAN_RXF0S_F0F_Pos _U_(24) /**< (CAN_RXF0S) Rx FIFO 0 Full Position */ +#define CAN_RXF0S_F0F_Msk (_U_(0x1) << CAN_RXF0S_F0F_Pos) /**< (CAN_RXF0S) Rx FIFO 0 Full Mask */ +#define CAN_RXF0S_F0F(value) (CAN_RXF0S_F0F_Msk & ((value) << CAN_RXF0S_F0F_Pos)) +#define CAN_RXF0S_RF0L_Pos _U_(25) /**< (CAN_RXF0S) Rx FIFO 0 Message Lost Position */ +#define CAN_RXF0S_RF0L_Msk (_U_(0x1) << CAN_RXF0S_RF0L_Pos) /**< (CAN_RXF0S) Rx FIFO 0 Message Lost Mask */ +#define CAN_RXF0S_RF0L(value) (CAN_RXF0S_RF0L_Msk & ((value) << CAN_RXF0S_RF0L_Pos)) +#define CAN_RXF0S_Msk _U_(0x033F3F7F) /**< (CAN_RXF0S) Register Mask */ + + +/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ +#define CAN_RXF0A_RESETVALUE _U_(0x00) /**< (CAN_RXF0A) Rx FIFO 0 Acknowledge Reset Value */ + +#define CAN_RXF0A_F0AI_Pos _U_(0) /**< (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Position */ +#define CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos) /**< (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Mask */ +#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos)) +#define CAN_RXF0A_Msk _U_(0x0000003F) /**< (CAN_RXF0A) Register Mask */ + + +/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ +#define CAN_RXBC_RESETVALUE _U_(0x00) /**< (CAN_RXBC) Rx Buffer Configuration Reset Value */ + +#define CAN_RXBC_RBSA_Pos _U_(0) /**< (CAN_RXBC) Rx Buffer Start Address Position */ +#define CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos) /**< (CAN_RXBC) Rx Buffer Start Address Mask */ +#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos)) +#define CAN_RXBC_Msk _U_(0x0000FFFF) /**< (CAN_RXBC) Register Mask */ + + +/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ +#define CAN_RXF1C_RESETVALUE _U_(0x00) /**< (CAN_RXF1C) Rx FIFO 1 Configuration Reset Value */ + +#define CAN_RXF1C_F1SA_Pos _U_(0) /**< (CAN_RXF1C) Rx FIFO 1 Start Address Position */ +#define CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos) /**< (CAN_RXF1C) Rx FIFO 1 Start Address Mask */ +#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos)) +#define CAN_RXF1C_F1S_Pos _U_(16) /**< (CAN_RXF1C) Rx FIFO 1 Size Position */ +#define CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos) /**< (CAN_RXF1C) Rx FIFO 1 Size Mask */ +#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos)) +#define CAN_RXF1C_F1WM_Pos _U_(24) /**< (CAN_RXF1C) Rx FIFO 1 Watermark Position */ +#define CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos) /**< (CAN_RXF1C) Rx FIFO 1 Watermark Mask */ +#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos)) +#define CAN_RXF1C_F1OM_Pos _U_(31) /**< (CAN_RXF1C) FIFO 1 Operation Mode Position */ +#define CAN_RXF1C_F1OM_Msk (_U_(0x1) << CAN_RXF1C_F1OM_Pos) /**< (CAN_RXF1C) FIFO 1 Operation Mode Mask */ +#define CAN_RXF1C_F1OM(value) (CAN_RXF1C_F1OM_Msk & ((value) << CAN_RXF1C_F1OM_Pos)) +#define CAN_RXF1C_Msk _U_(0xFF7FFFFF) /**< (CAN_RXF1C) Register Mask */ + + +/* -------- CAN_RXF1S : (CAN Offset: 0xB4) ( R/ 32) Rx FIFO 1 Status -------- */ +#define CAN_RXF1S_RESETVALUE _U_(0x00) /**< (CAN_RXF1S) Rx FIFO 1 Status Reset Value */ + +#define CAN_RXF1S_F1FL_Pos _U_(0) /**< (CAN_RXF1S) Rx FIFO 1 Fill Level Position */ +#define CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos) /**< (CAN_RXF1S) Rx FIFO 1 Fill Level Mask */ +#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos)) +#define CAN_RXF1S_F1GI_Pos _U_(8) /**< (CAN_RXF1S) Rx FIFO 1 Get Index Position */ +#define CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos) /**< (CAN_RXF1S) Rx FIFO 1 Get Index Mask */ +#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos)) +#define CAN_RXF1S_F1PI_Pos _U_(16) /**< (CAN_RXF1S) Rx FIFO 1 Put Index Position */ +#define CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos) /**< (CAN_RXF1S) Rx FIFO 1 Put Index Mask */ +#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos)) +#define CAN_RXF1S_F1F_Pos _U_(24) /**< (CAN_RXF1S) Rx FIFO 1 Full Position */ +#define CAN_RXF1S_F1F_Msk (_U_(0x1) << CAN_RXF1S_F1F_Pos) /**< (CAN_RXF1S) Rx FIFO 1 Full Mask */ +#define CAN_RXF1S_F1F(value) (CAN_RXF1S_F1F_Msk & ((value) << CAN_RXF1S_F1F_Pos)) +#define CAN_RXF1S_RF1L_Pos _U_(25) /**< (CAN_RXF1S) Rx FIFO 1 Message Lost Position */ +#define CAN_RXF1S_RF1L_Msk (_U_(0x1) << CAN_RXF1S_RF1L_Pos) /**< (CAN_RXF1S) Rx FIFO 1 Message Lost Mask */ +#define CAN_RXF1S_RF1L(value) (CAN_RXF1S_RF1L_Msk & ((value) << CAN_RXF1S_RF1L_Pos)) +#define CAN_RXF1S_DMS_Pos _U_(30) /**< (CAN_RXF1S) Debug Message Status Position */ +#define CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos) /**< (CAN_RXF1S) Debug Message Status Mask */ +#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos)) +#define CAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< (CAN_RXF1S) Idle state */ +#define CAN_RXF1S_DMS_DBGA_Val _U_(0x1) /**< (CAN_RXF1S) Debug message A received */ +#define CAN_RXF1S_DMS_DBGB_Val _U_(0x2) /**< (CAN_RXF1S) Debug message A/B received */ +#define CAN_RXF1S_DMS_DBGC_Val _U_(0x3) /**< (CAN_RXF1S) Debug message A/B/C received, DMA request set */ +#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) /**< (CAN_RXF1S) Idle state Position */ +#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) /**< (CAN_RXF1S) Debug message A received Position */ +#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) /**< (CAN_RXF1S) Debug message A/B received Position */ +#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) /**< (CAN_RXF1S) Debug message A/B/C received, DMA request set Position */ +#define CAN_RXF1S_Msk _U_(0xC33F3F7F) /**< (CAN_RXF1S) Register Mask */ + + +/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ +#define CAN_RXF1A_RESETVALUE _U_(0x00) /**< (CAN_RXF1A) Rx FIFO 1 Acknowledge Reset Value */ + +#define CAN_RXF1A_F1AI_Pos _U_(0) /**< (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Position */ +#define CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos) /**< (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Mask */ +#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos)) +#define CAN_RXF1A_Msk _U_(0x0000003F) /**< (CAN_RXF1A) Register Mask */ + + +/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ +#define CAN_RXESC_RESETVALUE _U_(0x00) /**< (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Reset Value */ + +#define CAN_RXESC_F0DS_Pos _U_(0) /**< (CAN_RXESC) Rx FIFO 0 Data Field Size Position */ +#define CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) Rx FIFO 0 Data Field Size Mask */ +#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos)) +#define CAN_RXESC_F0DS_DATA8_Val _U_(0x0) /**< (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F0DS_DATA12_Val _U_(0x1) /**< (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F0DS_DATA16_Val _U_(0x2) /**< (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F0DS_DATA20_Val _U_(0x3) /**< (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F0DS_DATA24_Val _U_(0x4) /**< (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F0DS_DATA32_Val _U_(0x5) /**< (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F0DS_DATA48_Val _U_(0x6) /**< (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F0DS_DATA64_Val _U_(0x7) /**< (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_F1DS_Pos _U_(4) /**< (CAN_RXESC) Rx FIFO 1 Data Field Size Position */ +#define CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) Rx FIFO 1 Data Field Size Mask */ +#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos)) +#define CAN_RXESC_F1DS_DATA8_Val _U_(0x0) /**< (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F1DS_DATA12_Val _U_(0x1) /**< (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F1DS_DATA16_Val _U_(0x2) /**< (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F1DS_DATA20_Val _U_(0x3) /**< (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F1DS_DATA24_Val _U_(0x4) /**< (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F1DS_DATA32_Val _U_(0x5) /**< (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F1DS_DATA48_Val _U_(0x6) /**< (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F1DS_DATA64_Val _U_(0x7) /**< (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_RBDS_Pos _U_(8) /**< (CAN_RXESC) Rx Buffer Data Field Size Position */ +#define CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) Rx Buffer Data Field Size Mask */ +#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos)) +#define CAN_RXESC_RBDS_DATA8_Val _U_(0x0) /**< (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_RBDS_DATA12_Val _U_(0x1) /**< (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_RBDS_DATA16_Val _U_(0x2) /**< (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_RBDS_DATA20_Val _U_(0x3) /**< (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_RBDS_DATA24_Val _U_(0x4) /**< (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_RBDS_DATA32_Val _U_(0x5) /**< (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_RBDS_DATA48_Val _U_(0x6) /**< (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_RBDS_DATA64_Val _U_(0x7) /**< (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_Msk _U_(0x00000777) /**< (CAN_RXESC) Register Mask */ + + +/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ +#define CAN_TXBC_RESETVALUE _U_(0x00) /**< (CAN_TXBC) Tx Buffer Configuration Reset Value */ + +#define CAN_TXBC_TBSA_Pos _U_(0) /**< (CAN_TXBC) Tx Buffers Start Address Position */ +#define CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos) /**< (CAN_TXBC) Tx Buffers Start Address Mask */ +#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos)) +#define CAN_TXBC_NDTB_Pos _U_(16) /**< (CAN_TXBC) Number of Dedicated Transmit Buffers Position */ +#define CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos) /**< (CAN_TXBC) Number of Dedicated Transmit Buffers Mask */ +#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos)) +#define CAN_TXBC_TFQS_Pos _U_(24) /**< (CAN_TXBC) Transmit FIFO/Queue Size Position */ +#define CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos) /**< (CAN_TXBC) Transmit FIFO/Queue Size Mask */ +#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos)) +#define CAN_TXBC_TFQM_Pos _U_(30) /**< (CAN_TXBC) Tx FIFO/Queue Mode Position */ +#define CAN_TXBC_TFQM_Msk (_U_(0x1) << CAN_TXBC_TFQM_Pos) /**< (CAN_TXBC) Tx FIFO/Queue Mode Mask */ +#define CAN_TXBC_TFQM(value) (CAN_TXBC_TFQM_Msk & ((value) << CAN_TXBC_TFQM_Pos)) +#define CAN_TXBC_Msk _U_(0x7F3FFFFF) /**< (CAN_TXBC) Register Mask */ + + +/* -------- CAN_TXFQS : (CAN Offset: 0xC4) ( R/ 32) Tx FIFO / Queue Status -------- */ +#define CAN_TXFQS_RESETVALUE _U_(0x00) /**< (CAN_TXFQS) Tx FIFO / Queue Status Reset Value */ + +#define CAN_TXFQS_TFFL_Pos _U_(0) /**< (CAN_TXFQS) Tx FIFO Free Level Position */ +#define CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos) /**< (CAN_TXFQS) Tx FIFO Free Level Mask */ +#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos)) +#define CAN_TXFQS_TFGI_Pos _U_(8) /**< (CAN_TXFQS) Tx FIFO Get Index Position */ +#define CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos) /**< (CAN_TXFQS) Tx FIFO Get Index Mask */ +#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos)) +#define CAN_TXFQS_TFQPI_Pos _U_(16) /**< (CAN_TXFQS) Tx FIFO/Queue Put Index Position */ +#define CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos) /**< (CAN_TXFQS) Tx FIFO/Queue Put Index Mask */ +#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos)) +#define CAN_TXFQS_TFQF_Pos _U_(21) /**< (CAN_TXFQS) Tx FIFO/Queue Full Position */ +#define CAN_TXFQS_TFQF_Msk (_U_(0x1) << CAN_TXFQS_TFQF_Pos) /**< (CAN_TXFQS) Tx FIFO/Queue Full Mask */ +#define CAN_TXFQS_TFQF(value) (CAN_TXFQS_TFQF_Msk & ((value) << CAN_TXFQS_TFQF_Pos)) +#define CAN_TXFQS_Msk _U_(0x003F1F3F) /**< (CAN_TXFQS) Register Mask */ + + +/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ +#define CAN_TXESC_RESETVALUE _U_(0x00) /**< (CAN_TXESC) Tx Buffer Element Size Configuration Reset Value */ + +#define CAN_TXESC_TBDS_Pos _U_(0) /**< (CAN_TXESC) Tx Buffer Data Field Size Position */ +#define CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) Tx Buffer Data Field Size Mask */ +#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos)) +#define CAN_TXESC_TBDS_DATA8_Val _U_(0x0) /**< (CAN_TXESC) 8 byte data field */ +#define CAN_TXESC_TBDS_DATA12_Val _U_(0x1) /**< (CAN_TXESC) 12 byte data field */ +#define CAN_TXESC_TBDS_DATA16_Val _U_(0x2) /**< (CAN_TXESC) 16 byte data field */ +#define CAN_TXESC_TBDS_DATA20_Val _U_(0x3) /**< (CAN_TXESC) 20 byte data field */ +#define CAN_TXESC_TBDS_DATA24_Val _U_(0x4) /**< (CAN_TXESC) 24 byte data field */ +#define CAN_TXESC_TBDS_DATA32_Val _U_(0x5) /**< (CAN_TXESC) 32 byte data field */ +#define CAN_TXESC_TBDS_DATA48_Val _U_(0x6) /**< (CAN_TXESC) 48 byte data field */ +#define CAN_TXESC_TBDS_DATA64_Val _U_(0x7) /**< (CAN_TXESC) 64 byte data field */ +#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 8 byte data field Position */ +#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 12 byte data field Position */ +#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 16 byte data field Position */ +#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 20 byte data field Position */ +#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 24 byte data field Position */ +#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 32 byte data field Position */ +#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 48 byte data field Position */ +#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 64 byte data field Position */ +#define CAN_TXESC_Msk _U_(0x00000007) /**< (CAN_TXESC) Register Mask */ + + +/* -------- CAN_TXBRP : (CAN Offset: 0xCC) ( R/ 32) Tx Buffer Request Pending -------- */ +#define CAN_TXBRP_RESETVALUE _U_(0x00) /**< (CAN_TXBRP) Tx Buffer Request Pending Reset Value */ + +#define CAN_TXBRP_TRP0_Pos _U_(0) /**< (CAN_TXBRP) Transmission Request Pending 0 Position */ +#define CAN_TXBRP_TRP0_Msk (_U_(0x1) << CAN_TXBRP_TRP0_Pos) /**< (CAN_TXBRP) Transmission Request Pending 0 Mask */ +#define CAN_TXBRP_TRP0(value) (CAN_TXBRP_TRP0_Msk & ((value) << CAN_TXBRP_TRP0_Pos)) +#define CAN_TXBRP_TRP1_Pos _U_(1) /**< (CAN_TXBRP) Transmission Request Pending 1 Position */ +#define CAN_TXBRP_TRP1_Msk (_U_(0x1) << CAN_TXBRP_TRP1_Pos) /**< (CAN_TXBRP) Transmission Request Pending 1 Mask */ +#define CAN_TXBRP_TRP1(value) (CAN_TXBRP_TRP1_Msk & ((value) << CAN_TXBRP_TRP1_Pos)) +#define CAN_TXBRP_TRP2_Pos _U_(2) /**< (CAN_TXBRP) Transmission Request Pending 2 Position */ +#define CAN_TXBRP_TRP2_Msk (_U_(0x1) << CAN_TXBRP_TRP2_Pos) /**< (CAN_TXBRP) Transmission Request Pending 2 Mask */ +#define CAN_TXBRP_TRP2(value) (CAN_TXBRP_TRP2_Msk & ((value) << CAN_TXBRP_TRP2_Pos)) +#define CAN_TXBRP_TRP3_Pos _U_(3) /**< (CAN_TXBRP) Transmission Request Pending 3 Position */ +#define CAN_TXBRP_TRP3_Msk (_U_(0x1) << CAN_TXBRP_TRP3_Pos) /**< (CAN_TXBRP) Transmission Request Pending 3 Mask */ +#define CAN_TXBRP_TRP3(value) (CAN_TXBRP_TRP3_Msk & ((value) << CAN_TXBRP_TRP3_Pos)) +#define CAN_TXBRP_TRP4_Pos _U_(4) /**< (CAN_TXBRP) Transmission Request Pending 4 Position */ +#define CAN_TXBRP_TRP4_Msk (_U_(0x1) << CAN_TXBRP_TRP4_Pos) /**< (CAN_TXBRP) Transmission Request Pending 4 Mask */ +#define CAN_TXBRP_TRP4(value) (CAN_TXBRP_TRP4_Msk & ((value) << CAN_TXBRP_TRP4_Pos)) +#define CAN_TXBRP_TRP5_Pos _U_(5) /**< (CAN_TXBRP) Transmission Request Pending 5 Position */ +#define CAN_TXBRP_TRP5_Msk (_U_(0x1) << CAN_TXBRP_TRP5_Pos) /**< (CAN_TXBRP) Transmission Request Pending 5 Mask */ +#define CAN_TXBRP_TRP5(value) (CAN_TXBRP_TRP5_Msk & ((value) << CAN_TXBRP_TRP5_Pos)) +#define CAN_TXBRP_TRP6_Pos _U_(6) /**< (CAN_TXBRP) Transmission Request Pending 6 Position */ +#define CAN_TXBRP_TRP6_Msk (_U_(0x1) << CAN_TXBRP_TRP6_Pos) /**< (CAN_TXBRP) Transmission Request Pending 6 Mask */ +#define CAN_TXBRP_TRP6(value) (CAN_TXBRP_TRP6_Msk & ((value) << CAN_TXBRP_TRP6_Pos)) +#define CAN_TXBRP_TRP7_Pos _U_(7) /**< (CAN_TXBRP) Transmission Request Pending 7 Position */ +#define CAN_TXBRP_TRP7_Msk (_U_(0x1) << CAN_TXBRP_TRP7_Pos) /**< (CAN_TXBRP) Transmission Request Pending 7 Mask */ +#define CAN_TXBRP_TRP7(value) (CAN_TXBRP_TRP7_Msk & ((value) << CAN_TXBRP_TRP7_Pos)) +#define CAN_TXBRP_TRP8_Pos _U_(8) /**< (CAN_TXBRP) Transmission Request Pending 8 Position */ +#define CAN_TXBRP_TRP8_Msk (_U_(0x1) << CAN_TXBRP_TRP8_Pos) /**< (CAN_TXBRP) Transmission Request Pending 8 Mask */ +#define CAN_TXBRP_TRP8(value) (CAN_TXBRP_TRP8_Msk & ((value) << CAN_TXBRP_TRP8_Pos)) +#define CAN_TXBRP_TRP9_Pos _U_(9) /**< (CAN_TXBRP) Transmission Request Pending 9 Position */ +#define CAN_TXBRP_TRP9_Msk (_U_(0x1) << CAN_TXBRP_TRP9_Pos) /**< (CAN_TXBRP) Transmission Request Pending 9 Mask */ +#define CAN_TXBRP_TRP9(value) (CAN_TXBRP_TRP9_Msk & ((value) << CAN_TXBRP_TRP9_Pos)) +#define CAN_TXBRP_TRP10_Pos _U_(10) /**< (CAN_TXBRP) Transmission Request Pending 10 Position */ +#define CAN_TXBRP_TRP10_Msk (_U_(0x1) << CAN_TXBRP_TRP10_Pos) /**< (CAN_TXBRP) Transmission Request Pending 10 Mask */ +#define CAN_TXBRP_TRP10(value) (CAN_TXBRP_TRP10_Msk & ((value) << CAN_TXBRP_TRP10_Pos)) +#define CAN_TXBRP_TRP11_Pos _U_(11) /**< (CAN_TXBRP) Transmission Request Pending 11 Position */ +#define CAN_TXBRP_TRP11_Msk (_U_(0x1) << CAN_TXBRP_TRP11_Pos) /**< (CAN_TXBRP) Transmission Request Pending 11 Mask */ +#define CAN_TXBRP_TRP11(value) (CAN_TXBRP_TRP11_Msk & ((value) << CAN_TXBRP_TRP11_Pos)) +#define CAN_TXBRP_TRP12_Pos _U_(12) /**< (CAN_TXBRP) Transmission Request Pending 12 Position */ +#define CAN_TXBRP_TRP12_Msk (_U_(0x1) << CAN_TXBRP_TRP12_Pos) /**< (CAN_TXBRP) Transmission Request Pending 12 Mask */ +#define CAN_TXBRP_TRP12(value) (CAN_TXBRP_TRP12_Msk & ((value) << CAN_TXBRP_TRP12_Pos)) +#define CAN_TXBRP_TRP13_Pos _U_(13) /**< (CAN_TXBRP) Transmission Request Pending 13 Position */ +#define CAN_TXBRP_TRP13_Msk (_U_(0x1) << CAN_TXBRP_TRP13_Pos) /**< (CAN_TXBRP) Transmission Request Pending 13 Mask */ +#define CAN_TXBRP_TRP13(value) (CAN_TXBRP_TRP13_Msk & ((value) << CAN_TXBRP_TRP13_Pos)) +#define CAN_TXBRP_TRP14_Pos _U_(14) /**< (CAN_TXBRP) Transmission Request Pending 14 Position */ +#define CAN_TXBRP_TRP14_Msk (_U_(0x1) << CAN_TXBRP_TRP14_Pos) /**< (CAN_TXBRP) Transmission Request Pending 14 Mask */ +#define CAN_TXBRP_TRP14(value) (CAN_TXBRP_TRP14_Msk & ((value) << CAN_TXBRP_TRP14_Pos)) +#define CAN_TXBRP_TRP15_Pos _U_(15) /**< (CAN_TXBRP) Transmission Request Pending 15 Position */ +#define CAN_TXBRP_TRP15_Msk (_U_(0x1) << CAN_TXBRP_TRP15_Pos) /**< (CAN_TXBRP) Transmission Request Pending 15 Mask */ +#define CAN_TXBRP_TRP15(value) (CAN_TXBRP_TRP15_Msk & ((value) << CAN_TXBRP_TRP15_Pos)) +#define CAN_TXBRP_TRP16_Pos _U_(16) /**< (CAN_TXBRP) Transmission Request Pending 16 Position */ +#define CAN_TXBRP_TRP16_Msk (_U_(0x1) << CAN_TXBRP_TRP16_Pos) /**< (CAN_TXBRP) Transmission Request Pending 16 Mask */ +#define CAN_TXBRP_TRP16(value) (CAN_TXBRP_TRP16_Msk & ((value) << CAN_TXBRP_TRP16_Pos)) +#define CAN_TXBRP_TRP17_Pos _U_(17) /**< (CAN_TXBRP) Transmission Request Pending 17 Position */ +#define CAN_TXBRP_TRP17_Msk (_U_(0x1) << CAN_TXBRP_TRP17_Pos) /**< (CAN_TXBRP) Transmission Request Pending 17 Mask */ +#define CAN_TXBRP_TRP17(value) (CAN_TXBRP_TRP17_Msk & ((value) << CAN_TXBRP_TRP17_Pos)) +#define CAN_TXBRP_TRP18_Pos _U_(18) /**< (CAN_TXBRP) Transmission Request Pending 18 Position */ +#define CAN_TXBRP_TRP18_Msk (_U_(0x1) << CAN_TXBRP_TRP18_Pos) /**< (CAN_TXBRP) Transmission Request Pending 18 Mask */ +#define CAN_TXBRP_TRP18(value) (CAN_TXBRP_TRP18_Msk & ((value) << CAN_TXBRP_TRP18_Pos)) +#define CAN_TXBRP_TRP19_Pos _U_(19) /**< (CAN_TXBRP) Transmission Request Pending 19 Position */ +#define CAN_TXBRP_TRP19_Msk (_U_(0x1) << CAN_TXBRP_TRP19_Pos) /**< (CAN_TXBRP) Transmission Request Pending 19 Mask */ +#define CAN_TXBRP_TRP19(value) (CAN_TXBRP_TRP19_Msk & ((value) << CAN_TXBRP_TRP19_Pos)) +#define CAN_TXBRP_TRP20_Pos _U_(20) /**< (CAN_TXBRP) Transmission Request Pending 20 Position */ +#define CAN_TXBRP_TRP20_Msk (_U_(0x1) << CAN_TXBRP_TRP20_Pos) /**< (CAN_TXBRP) Transmission Request Pending 20 Mask */ +#define CAN_TXBRP_TRP20(value) (CAN_TXBRP_TRP20_Msk & ((value) << CAN_TXBRP_TRP20_Pos)) +#define CAN_TXBRP_TRP21_Pos _U_(21) /**< (CAN_TXBRP) Transmission Request Pending 21 Position */ +#define CAN_TXBRP_TRP21_Msk (_U_(0x1) << CAN_TXBRP_TRP21_Pos) /**< (CAN_TXBRP) Transmission Request Pending 21 Mask */ +#define CAN_TXBRP_TRP21(value) (CAN_TXBRP_TRP21_Msk & ((value) << CAN_TXBRP_TRP21_Pos)) +#define CAN_TXBRP_TRP22_Pos _U_(22) /**< (CAN_TXBRP) Transmission Request Pending 22 Position */ +#define CAN_TXBRP_TRP22_Msk (_U_(0x1) << CAN_TXBRP_TRP22_Pos) /**< (CAN_TXBRP) Transmission Request Pending 22 Mask */ +#define CAN_TXBRP_TRP22(value) (CAN_TXBRP_TRP22_Msk & ((value) << CAN_TXBRP_TRP22_Pos)) +#define CAN_TXBRP_TRP23_Pos _U_(23) /**< (CAN_TXBRP) Transmission Request Pending 23 Position */ +#define CAN_TXBRP_TRP23_Msk (_U_(0x1) << CAN_TXBRP_TRP23_Pos) /**< (CAN_TXBRP) Transmission Request Pending 23 Mask */ +#define CAN_TXBRP_TRP23(value) (CAN_TXBRP_TRP23_Msk & ((value) << CAN_TXBRP_TRP23_Pos)) +#define CAN_TXBRP_TRP24_Pos _U_(24) /**< (CAN_TXBRP) Transmission Request Pending 24 Position */ +#define CAN_TXBRP_TRP24_Msk (_U_(0x1) << CAN_TXBRP_TRP24_Pos) /**< (CAN_TXBRP) Transmission Request Pending 24 Mask */ +#define CAN_TXBRP_TRP24(value) (CAN_TXBRP_TRP24_Msk & ((value) << CAN_TXBRP_TRP24_Pos)) +#define CAN_TXBRP_TRP25_Pos _U_(25) /**< (CAN_TXBRP) Transmission Request Pending 25 Position */ +#define CAN_TXBRP_TRP25_Msk (_U_(0x1) << CAN_TXBRP_TRP25_Pos) /**< (CAN_TXBRP) Transmission Request Pending 25 Mask */ +#define CAN_TXBRP_TRP25(value) (CAN_TXBRP_TRP25_Msk & ((value) << CAN_TXBRP_TRP25_Pos)) +#define CAN_TXBRP_TRP26_Pos _U_(26) /**< (CAN_TXBRP) Transmission Request Pending 26 Position */ +#define CAN_TXBRP_TRP26_Msk (_U_(0x1) << CAN_TXBRP_TRP26_Pos) /**< (CAN_TXBRP) Transmission Request Pending 26 Mask */ +#define CAN_TXBRP_TRP26(value) (CAN_TXBRP_TRP26_Msk & ((value) << CAN_TXBRP_TRP26_Pos)) +#define CAN_TXBRP_TRP27_Pos _U_(27) /**< (CAN_TXBRP) Transmission Request Pending 27 Position */ +#define CAN_TXBRP_TRP27_Msk (_U_(0x1) << CAN_TXBRP_TRP27_Pos) /**< (CAN_TXBRP) Transmission Request Pending 27 Mask */ +#define CAN_TXBRP_TRP27(value) (CAN_TXBRP_TRP27_Msk & ((value) << CAN_TXBRP_TRP27_Pos)) +#define CAN_TXBRP_TRP28_Pos _U_(28) /**< (CAN_TXBRP) Transmission Request Pending 28 Position */ +#define CAN_TXBRP_TRP28_Msk (_U_(0x1) << CAN_TXBRP_TRP28_Pos) /**< (CAN_TXBRP) Transmission Request Pending 28 Mask */ +#define CAN_TXBRP_TRP28(value) (CAN_TXBRP_TRP28_Msk & ((value) << CAN_TXBRP_TRP28_Pos)) +#define CAN_TXBRP_TRP29_Pos _U_(29) /**< (CAN_TXBRP) Transmission Request Pending 29 Position */ +#define CAN_TXBRP_TRP29_Msk (_U_(0x1) << CAN_TXBRP_TRP29_Pos) /**< (CAN_TXBRP) Transmission Request Pending 29 Mask */ +#define CAN_TXBRP_TRP29(value) (CAN_TXBRP_TRP29_Msk & ((value) << CAN_TXBRP_TRP29_Pos)) +#define CAN_TXBRP_TRP30_Pos _U_(30) /**< (CAN_TXBRP) Transmission Request Pending 30 Position */ +#define CAN_TXBRP_TRP30_Msk (_U_(0x1) << CAN_TXBRP_TRP30_Pos) /**< (CAN_TXBRP) Transmission Request Pending 30 Mask */ +#define CAN_TXBRP_TRP30(value) (CAN_TXBRP_TRP30_Msk & ((value) << CAN_TXBRP_TRP30_Pos)) +#define CAN_TXBRP_TRP31_Pos _U_(31) /**< (CAN_TXBRP) Transmission Request Pending 31 Position */ +#define CAN_TXBRP_TRP31_Msk (_U_(0x1) << CAN_TXBRP_TRP31_Pos) /**< (CAN_TXBRP) Transmission Request Pending 31 Mask */ +#define CAN_TXBRP_TRP31(value) (CAN_TXBRP_TRP31_Msk & ((value) << CAN_TXBRP_TRP31_Pos)) +#define CAN_TXBRP_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBRP) Register Mask */ + +#define CAN_TXBRP_TRP_Pos _U_(0) /**< (CAN_TXBRP Position) Transmission Request Pending 3x */ +#define CAN_TXBRP_TRP_Msk (_U_(0xFFFFFFFF) << CAN_TXBRP_TRP_Pos) /**< (CAN_TXBRP Mask) TRP */ +#define CAN_TXBRP_TRP(value) (CAN_TXBRP_TRP_Msk & ((value) << CAN_TXBRP_TRP_Pos)) + +/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ +#define CAN_TXBAR_RESETVALUE _U_(0x00) /**< (CAN_TXBAR) Tx Buffer Add Request Reset Value */ + +#define CAN_TXBAR_AR0_Pos _U_(0) /**< (CAN_TXBAR) Add Request 0 Position */ +#define CAN_TXBAR_AR0_Msk (_U_(0x1) << CAN_TXBAR_AR0_Pos) /**< (CAN_TXBAR) Add Request 0 Mask */ +#define CAN_TXBAR_AR0(value) (CAN_TXBAR_AR0_Msk & ((value) << CAN_TXBAR_AR0_Pos)) +#define CAN_TXBAR_AR1_Pos _U_(1) /**< (CAN_TXBAR) Add Request 1 Position */ +#define CAN_TXBAR_AR1_Msk (_U_(0x1) << CAN_TXBAR_AR1_Pos) /**< (CAN_TXBAR) Add Request 1 Mask */ +#define CAN_TXBAR_AR1(value) (CAN_TXBAR_AR1_Msk & ((value) << CAN_TXBAR_AR1_Pos)) +#define CAN_TXBAR_AR2_Pos _U_(2) /**< (CAN_TXBAR) Add Request 2 Position */ +#define CAN_TXBAR_AR2_Msk (_U_(0x1) << CAN_TXBAR_AR2_Pos) /**< (CAN_TXBAR) Add Request 2 Mask */ +#define CAN_TXBAR_AR2(value) (CAN_TXBAR_AR2_Msk & ((value) << CAN_TXBAR_AR2_Pos)) +#define CAN_TXBAR_AR3_Pos _U_(3) /**< (CAN_TXBAR) Add Request 3 Position */ +#define CAN_TXBAR_AR3_Msk (_U_(0x1) << CAN_TXBAR_AR3_Pos) /**< (CAN_TXBAR) Add Request 3 Mask */ +#define CAN_TXBAR_AR3(value) (CAN_TXBAR_AR3_Msk & ((value) << CAN_TXBAR_AR3_Pos)) +#define CAN_TXBAR_AR4_Pos _U_(4) /**< (CAN_TXBAR) Add Request 4 Position */ +#define CAN_TXBAR_AR4_Msk (_U_(0x1) << CAN_TXBAR_AR4_Pos) /**< (CAN_TXBAR) Add Request 4 Mask */ +#define CAN_TXBAR_AR4(value) (CAN_TXBAR_AR4_Msk & ((value) << CAN_TXBAR_AR4_Pos)) +#define CAN_TXBAR_AR5_Pos _U_(5) /**< (CAN_TXBAR) Add Request 5 Position */ +#define CAN_TXBAR_AR5_Msk (_U_(0x1) << CAN_TXBAR_AR5_Pos) /**< (CAN_TXBAR) Add Request 5 Mask */ +#define CAN_TXBAR_AR5(value) (CAN_TXBAR_AR5_Msk & ((value) << CAN_TXBAR_AR5_Pos)) +#define CAN_TXBAR_AR6_Pos _U_(6) /**< (CAN_TXBAR) Add Request 6 Position */ +#define CAN_TXBAR_AR6_Msk (_U_(0x1) << CAN_TXBAR_AR6_Pos) /**< (CAN_TXBAR) Add Request 6 Mask */ +#define CAN_TXBAR_AR6(value) (CAN_TXBAR_AR6_Msk & ((value) << CAN_TXBAR_AR6_Pos)) +#define CAN_TXBAR_AR7_Pos _U_(7) /**< (CAN_TXBAR) Add Request 7 Position */ +#define CAN_TXBAR_AR7_Msk (_U_(0x1) << CAN_TXBAR_AR7_Pos) /**< (CAN_TXBAR) Add Request 7 Mask */ +#define CAN_TXBAR_AR7(value) (CAN_TXBAR_AR7_Msk & ((value) << CAN_TXBAR_AR7_Pos)) +#define CAN_TXBAR_AR8_Pos _U_(8) /**< (CAN_TXBAR) Add Request 8 Position */ +#define CAN_TXBAR_AR8_Msk (_U_(0x1) << CAN_TXBAR_AR8_Pos) /**< (CAN_TXBAR) Add Request 8 Mask */ +#define CAN_TXBAR_AR8(value) (CAN_TXBAR_AR8_Msk & ((value) << CAN_TXBAR_AR8_Pos)) +#define CAN_TXBAR_AR9_Pos _U_(9) /**< (CAN_TXBAR) Add Request 9 Position */ +#define CAN_TXBAR_AR9_Msk (_U_(0x1) << CAN_TXBAR_AR9_Pos) /**< (CAN_TXBAR) Add Request 9 Mask */ +#define CAN_TXBAR_AR9(value) (CAN_TXBAR_AR9_Msk & ((value) << CAN_TXBAR_AR9_Pos)) +#define CAN_TXBAR_AR10_Pos _U_(10) /**< (CAN_TXBAR) Add Request 10 Position */ +#define CAN_TXBAR_AR10_Msk (_U_(0x1) << CAN_TXBAR_AR10_Pos) /**< (CAN_TXBAR) Add Request 10 Mask */ +#define CAN_TXBAR_AR10(value) (CAN_TXBAR_AR10_Msk & ((value) << CAN_TXBAR_AR10_Pos)) +#define CAN_TXBAR_AR11_Pos _U_(11) /**< (CAN_TXBAR) Add Request 11 Position */ +#define CAN_TXBAR_AR11_Msk (_U_(0x1) << CAN_TXBAR_AR11_Pos) /**< (CAN_TXBAR) Add Request 11 Mask */ +#define CAN_TXBAR_AR11(value) (CAN_TXBAR_AR11_Msk & ((value) << CAN_TXBAR_AR11_Pos)) +#define CAN_TXBAR_AR12_Pos _U_(12) /**< (CAN_TXBAR) Add Request 12 Position */ +#define CAN_TXBAR_AR12_Msk (_U_(0x1) << CAN_TXBAR_AR12_Pos) /**< (CAN_TXBAR) Add Request 12 Mask */ +#define CAN_TXBAR_AR12(value) (CAN_TXBAR_AR12_Msk & ((value) << CAN_TXBAR_AR12_Pos)) +#define CAN_TXBAR_AR13_Pos _U_(13) /**< (CAN_TXBAR) Add Request 13 Position */ +#define CAN_TXBAR_AR13_Msk (_U_(0x1) << CAN_TXBAR_AR13_Pos) /**< (CAN_TXBAR) Add Request 13 Mask */ +#define CAN_TXBAR_AR13(value) (CAN_TXBAR_AR13_Msk & ((value) << CAN_TXBAR_AR13_Pos)) +#define CAN_TXBAR_AR14_Pos _U_(14) /**< (CAN_TXBAR) Add Request 14 Position */ +#define CAN_TXBAR_AR14_Msk (_U_(0x1) << CAN_TXBAR_AR14_Pos) /**< (CAN_TXBAR) Add Request 14 Mask */ +#define CAN_TXBAR_AR14(value) (CAN_TXBAR_AR14_Msk & ((value) << CAN_TXBAR_AR14_Pos)) +#define CAN_TXBAR_AR15_Pos _U_(15) /**< (CAN_TXBAR) Add Request 15 Position */ +#define CAN_TXBAR_AR15_Msk (_U_(0x1) << CAN_TXBAR_AR15_Pos) /**< (CAN_TXBAR) Add Request 15 Mask */ +#define CAN_TXBAR_AR15(value) (CAN_TXBAR_AR15_Msk & ((value) << CAN_TXBAR_AR15_Pos)) +#define CAN_TXBAR_AR16_Pos _U_(16) /**< (CAN_TXBAR) Add Request 16 Position */ +#define CAN_TXBAR_AR16_Msk (_U_(0x1) << CAN_TXBAR_AR16_Pos) /**< (CAN_TXBAR) Add Request 16 Mask */ +#define CAN_TXBAR_AR16(value) (CAN_TXBAR_AR16_Msk & ((value) << CAN_TXBAR_AR16_Pos)) +#define CAN_TXBAR_AR17_Pos _U_(17) /**< (CAN_TXBAR) Add Request 17 Position */ +#define CAN_TXBAR_AR17_Msk (_U_(0x1) << CAN_TXBAR_AR17_Pos) /**< (CAN_TXBAR) Add Request 17 Mask */ +#define CAN_TXBAR_AR17(value) (CAN_TXBAR_AR17_Msk & ((value) << CAN_TXBAR_AR17_Pos)) +#define CAN_TXBAR_AR18_Pos _U_(18) /**< (CAN_TXBAR) Add Request 18 Position */ +#define CAN_TXBAR_AR18_Msk (_U_(0x1) << CAN_TXBAR_AR18_Pos) /**< (CAN_TXBAR) Add Request 18 Mask */ +#define CAN_TXBAR_AR18(value) (CAN_TXBAR_AR18_Msk & ((value) << CAN_TXBAR_AR18_Pos)) +#define CAN_TXBAR_AR19_Pos _U_(19) /**< (CAN_TXBAR) Add Request 19 Position */ +#define CAN_TXBAR_AR19_Msk (_U_(0x1) << CAN_TXBAR_AR19_Pos) /**< (CAN_TXBAR) Add Request 19 Mask */ +#define CAN_TXBAR_AR19(value) (CAN_TXBAR_AR19_Msk & ((value) << CAN_TXBAR_AR19_Pos)) +#define CAN_TXBAR_AR20_Pos _U_(20) /**< (CAN_TXBAR) Add Request 20 Position */ +#define CAN_TXBAR_AR20_Msk (_U_(0x1) << CAN_TXBAR_AR20_Pos) /**< (CAN_TXBAR) Add Request 20 Mask */ +#define CAN_TXBAR_AR20(value) (CAN_TXBAR_AR20_Msk & ((value) << CAN_TXBAR_AR20_Pos)) +#define CAN_TXBAR_AR21_Pos _U_(21) /**< (CAN_TXBAR) Add Request 21 Position */ +#define CAN_TXBAR_AR21_Msk (_U_(0x1) << CAN_TXBAR_AR21_Pos) /**< (CAN_TXBAR) Add Request 21 Mask */ +#define CAN_TXBAR_AR21(value) (CAN_TXBAR_AR21_Msk & ((value) << CAN_TXBAR_AR21_Pos)) +#define CAN_TXBAR_AR22_Pos _U_(22) /**< (CAN_TXBAR) Add Request 22 Position */ +#define CAN_TXBAR_AR22_Msk (_U_(0x1) << CAN_TXBAR_AR22_Pos) /**< (CAN_TXBAR) Add Request 22 Mask */ +#define CAN_TXBAR_AR22(value) (CAN_TXBAR_AR22_Msk & ((value) << CAN_TXBAR_AR22_Pos)) +#define CAN_TXBAR_AR23_Pos _U_(23) /**< (CAN_TXBAR) Add Request 23 Position */ +#define CAN_TXBAR_AR23_Msk (_U_(0x1) << CAN_TXBAR_AR23_Pos) /**< (CAN_TXBAR) Add Request 23 Mask */ +#define CAN_TXBAR_AR23(value) (CAN_TXBAR_AR23_Msk & ((value) << CAN_TXBAR_AR23_Pos)) +#define CAN_TXBAR_AR24_Pos _U_(24) /**< (CAN_TXBAR) Add Request 24 Position */ +#define CAN_TXBAR_AR24_Msk (_U_(0x1) << CAN_TXBAR_AR24_Pos) /**< (CAN_TXBAR) Add Request 24 Mask */ +#define CAN_TXBAR_AR24(value) (CAN_TXBAR_AR24_Msk & ((value) << CAN_TXBAR_AR24_Pos)) +#define CAN_TXBAR_AR25_Pos _U_(25) /**< (CAN_TXBAR) Add Request 25 Position */ +#define CAN_TXBAR_AR25_Msk (_U_(0x1) << CAN_TXBAR_AR25_Pos) /**< (CAN_TXBAR) Add Request 25 Mask */ +#define CAN_TXBAR_AR25(value) (CAN_TXBAR_AR25_Msk & ((value) << CAN_TXBAR_AR25_Pos)) +#define CAN_TXBAR_AR26_Pos _U_(26) /**< (CAN_TXBAR) Add Request 26 Position */ +#define CAN_TXBAR_AR26_Msk (_U_(0x1) << CAN_TXBAR_AR26_Pos) /**< (CAN_TXBAR) Add Request 26 Mask */ +#define CAN_TXBAR_AR26(value) (CAN_TXBAR_AR26_Msk & ((value) << CAN_TXBAR_AR26_Pos)) +#define CAN_TXBAR_AR27_Pos _U_(27) /**< (CAN_TXBAR) Add Request 27 Position */ +#define CAN_TXBAR_AR27_Msk (_U_(0x1) << CAN_TXBAR_AR27_Pos) /**< (CAN_TXBAR) Add Request 27 Mask */ +#define CAN_TXBAR_AR27(value) (CAN_TXBAR_AR27_Msk & ((value) << CAN_TXBAR_AR27_Pos)) +#define CAN_TXBAR_AR28_Pos _U_(28) /**< (CAN_TXBAR) Add Request 28 Position */ +#define CAN_TXBAR_AR28_Msk (_U_(0x1) << CAN_TXBAR_AR28_Pos) /**< (CAN_TXBAR) Add Request 28 Mask */ +#define CAN_TXBAR_AR28(value) (CAN_TXBAR_AR28_Msk & ((value) << CAN_TXBAR_AR28_Pos)) +#define CAN_TXBAR_AR29_Pos _U_(29) /**< (CAN_TXBAR) Add Request 29 Position */ +#define CAN_TXBAR_AR29_Msk (_U_(0x1) << CAN_TXBAR_AR29_Pos) /**< (CAN_TXBAR) Add Request 29 Mask */ +#define CAN_TXBAR_AR29(value) (CAN_TXBAR_AR29_Msk & ((value) << CAN_TXBAR_AR29_Pos)) +#define CAN_TXBAR_AR30_Pos _U_(30) /**< (CAN_TXBAR) Add Request 30 Position */ +#define CAN_TXBAR_AR30_Msk (_U_(0x1) << CAN_TXBAR_AR30_Pos) /**< (CAN_TXBAR) Add Request 30 Mask */ +#define CAN_TXBAR_AR30(value) (CAN_TXBAR_AR30_Msk & ((value) << CAN_TXBAR_AR30_Pos)) +#define CAN_TXBAR_AR31_Pos _U_(31) /**< (CAN_TXBAR) Add Request 31 Position */ +#define CAN_TXBAR_AR31_Msk (_U_(0x1) << CAN_TXBAR_AR31_Pos) /**< (CAN_TXBAR) Add Request 31 Mask */ +#define CAN_TXBAR_AR31(value) (CAN_TXBAR_AR31_Msk & ((value) << CAN_TXBAR_AR31_Pos)) +#define CAN_TXBAR_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBAR) Register Mask */ + +#define CAN_TXBAR_AR_Pos _U_(0) /**< (CAN_TXBAR Position) Add Request 3x */ +#define CAN_TXBAR_AR_Msk (_U_(0xFFFFFFFF) << CAN_TXBAR_AR_Pos) /**< (CAN_TXBAR Mask) AR */ +#define CAN_TXBAR_AR(value) (CAN_TXBAR_AR_Msk & ((value) << CAN_TXBAR_AR_Pos)) + +/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ +#define CAN_TXBCR_RESETVALUE _U_(0x00) /**< (CAN_TXBCR) Tx Buffer Cancellation Request Reset Value */ + +#define CAN_TXBCR_CR0_Pos _U_(0) /**< (CAN_TXBCR) Cancellation Request 0 Position */ +#define CAN_TXBCR_CR0_Msk (_U_(0x1) << CAN_TXBCR_CR0_Pos) /**< (CAN_TXBCR) Cancellation Request 0 Mask */ +#define CAN_TXBCR_CR0(value) (CAN_TXBCR_CR0_Msk & ((value) << CAN_TXBCR_CR0_Pos)) +#define CAN_TXBCR_CR1_Pos _U_(1) /**< (CAN_TXBCR) Cancellation Request 1 Position */ +#define CAN_TXBCR_CR1_Msk (_U_(0x1) << CAN_TXBCR_CR1_Pos) /**< (CAN_TXBCR) Cancellation Request 1 Mask */ +#define CAN_TXBCR_CR1(value) (CAN_TXBCR_CR1_Msk & ((value) << CAN_TXBCR_CR1_Pos)) +#define CAN_TXBCR_CR2_Pos _U_(2) /**< (CAN_TXBCR) Cancellation Request 2 Position */ +#define CAN_TXBCR_CR2_Msk (_U_(0x1) << CAN_TXBCR_CR2_Pos) /**< (CAN_TXBCR) Cancellation Request 2 Mask */ +#define CAN_TXBCR_CR2(value) (CAN_TXBCR_CR2_Msk & ((value) << CAN_TXBCR_CR2_Pos)) +#define CAN_TXBCR_CR3_Pos _U_(3) /**< (CAN_TXBCR) Cancellation Request 3 Position */ +#define CAN_TXBCR_CR3_Msk (_U_(0x1) << CAN_TXBCR_CR3_Pos) /**< (CAN_TXBCR) Cancellation Request 3 Mask */ +#define CAN_TXBCR_CR3(value) (CAN_TXBCR_CR3_Msk & ((value) << CAN_TXBCR_CR3_Pos)) +#define CAN_TXBCR_CR4_Pos _U_(4) /**< (CAN_TXBCR) Cancellation Request 4 Position */ +#define CAN_TXBCR_CR4_Msk (_U_(0x1) << CAN_TXBCR_CR4_Pos) /**< (CAN_TXBCR) Cancellation Request 4 Mask */ +#define CAN_TXBCR_CR4(value) (CAN_TXBCR_CR4_Msk & ((value) << CAN_TXBCR_CR4_Pos)) +#define CAN_TXBCR_CR5_Pos _U_(5) /**< (CAN_TXBCR) Cancellation Request 5 Position */ +#define CAN_TXBCR_CR5_Msk (_U_(0x1) << CAN_TXBCR_CR5_Pos) /**< (CAN_TXBCR) Cancellation Request 5 Mask */ +#define CAN_TXBCR_CR5(value) (CAN_TXBCR_CR5_Msk & ((value) << CAN_TXBCR_CR5_Pos)) +#define CAN_TXBCR_CR6_Pos _U_(6) /**< (CAN_TXBCR) Cancellation Request 6 Position */ +#define CAN_TXBCR_CR6_Msk (_U_(0x1) << CAN_TXBCR_CR6_Pos) /**< (CAN_TXBCR) Cancellation Request 6 Mask */ +#define CAN_TXBCR_CR6(value) (CAN_TXBCR_CR6_Msk & ((value) << CAN_TXBCR_CR6_Pos)) +#define CAN_TXBCR_CR7_Pos _U_(7) /**< (CAN_TXBCR) Cancellation Request 7 Position */ +#define CAN_TXBCR_CR7_Msk (_U_(0x1) << CAN_TXBCR_CR7_Pos) /**< (CAN_TXBCR) Cancellation Request 7 Mask */ +#define CAN_TXBCR_CR7(value) (CAN_TXBCR_CR7_Msk & ((value) << CAN_TXBCR_CR7_Pos)) +#define CAN_TXBCR_CR8_Pos _U_(8) /**< (CAN_TXBCR) Cancellation Request 8 Position */ +#define CAN_TXBCR_CR8_Msk (_U_(0x1) << CAN_TXBCR_CR8_Pos) /**< (CAN_TXBCR) Cancellation Request 8 Mask */ +#define CAN_TXBCR_CR8(value) (CAN_TXBCR_CR8_Msk & ((value) << CAN_TXBCR_CR8_Pos)) +#define CAN_TXBCR_CR9_Pos _U_(9) /**< (CAN_TXBCR) Cancellation Request 9 Position */ +#define CAN_TXBCR_CR9_Msk (_U_(0x1) << CAN_TXBCR_CR9_Pos) /**< (CAN_TXBCR) Cancellation Request 9 Mask */ +#define CAN_TXBCR_CR9(value) (CAN_TXBCR_CR9_Msk & ((value) << CAN_TXBCR_CR9_Pos)) +#define CAN_TXBCR_CR10_Pos _U_(10) /**< (CAN_TXBCR) Cancellation Request 10 Position */ +#define CAN_TXBCR_CR10_Msk (_U_(0x1) << CAN_TXBCR_CR10_Pos) /**< (CAN_TXBCR) Cancellation Request 10 Mask */ +#define CAN_TXBCR_CR10(value) (CAN_TXBCR_CR10_Msk & ((value) << CAN_TXBCR_CR10_Pos)) +#define CAN_TXBCR_CR11_Pos _U_(11) /**< (CAN_TXBCR) Cancellation Request 11 Position */ +#define CAN_TXBCR_CR11_Msk (_U_(0x1) << CAN_TXBCR_CR11_Pos) /**< (CAN_TXBCR) Cancellation Request 11 Mask */ +#define CAN_TXBCR_CR11(value) (CAN_TXBCR_CR11_Msk & ((value) << CAN_TXBCR_CR11_Pos)) +#define CAN_TXBCR_CR12_Pos _U_(12) /**< (CAN_TXBCR) Cancellation Request 12 Position */ +#define CAN_TXBCR_CR12_Msk (_U_(0x1) << CAN_TXBCR_CR12_Pos) /**< (CAN_TXBCR) Cancellation Request 12 Mask */ +#define CAN_TXBCR_CR12(value) (CAN_TXBCR_CR12_Msk & ((value) << CAN_TXBCR_CR12_Pos)) +#define CAN_TXBCR_CR13_Pos _U_(13) /**< (CAN_TXBCR) Cancellation Request 13 Position */ +#define CAN_TXBCR_CR13_Msk (_U_(0x1) << CAN_TXBCR_CR13_Pos) /**< (CAN_TXBCR) Cancellation Request 13 Mask */ +#define CAN_TXBCR_CR13(value) (CAN_TXBCR_CR13_Msk & ((value) << CAN_TXBCR_CR13_Pos)) +#define CAN_TXBCR_CR14_Pos _U_(14) /**< (CAN_TXBCR) Cancellation Request 14 Position */ +#define CAN_TXBCR_CR14_Msk (_U_(0x1) << CAN_TXBCR_CR14_Pos) /**< (CAN_TXBCR) Cancellation Request 14 Mask */ +#define CAN_TXBCR_CR14(value) (CAN_TXBCR_CR14_Msk & ((value) << CAN_TXBCR_CR14_Pos)) +#define CAN_TXBCR_CR15_Pos _U_(15) /**< (CAN_TXBCR) Cancellation Request 15 Position */ +#define CAN_TXBCR_CR15_Msk (_U_(0x1) << CAN_TXBCR_CR15_Pos) /**< (CAN_TXBCR) Cancellation Request 15 Mask */ +#define CAN_TXBCR_CR15(value) (CAN_TXBCR_CR15_Msk & ((value) << CAN_TXBCR_CR15_Pos)) +#define CAN_TXBCR_CR16_Pos _U_(16) /**< (CAN_TXBCR) Cancellation Request 16 Position */ +#define CAN_TXBCR_CR16_Msk (_U_(0x1) << CAN_TXBCR_CR16_Pos) /**< (CAN_TXBCR) Cancellation Request 16 Mask */ +#define CAN_TXBCR_CR16(value) (CAN_TXBCR_CR16_Msk & ((value) << CAN_TXBCR_CR16_Pos)) +#define CAN_TXBCR_CR17_Pos _U_(17) /**< (CAN_TXBCR) Cancellation Request 17 Position */ +#define CAN_TXBCR_CR17_Msk (_U_(0x1) << CAN_TXBCR_CR17_Pos) /**< (CAN_TXBCR) Cancellation Request 17 Mask */ +#define CAN_TXBCR_CR17(value) (CAN_TXBCR_CR17_Msk & ((value) << CAN_TXBCR_CR17_Pos)) +#define CAN_TXBCR_CR18_Pos _U_(18) /**< (CAN_TXBCR) Cancellation Request 18 Position */ +#define CAN_TXBCR_CR18_Msk (_U_(0x1) << CAN_TXBCR_CR18_Pos) /**< (CAN_TXBCR) Cancellation Request 18 Mask */ +#define CAN_TXBCR_CR18(value) (CAN_TXBCR_CR18_Msk & ((value) << CAN_TXBCR_CR18_Pos)) +#define CAN_TXBCR_CR19_Pos _U_(19) /**< (CAN_TXBCR) Cancellation Request 19 Position */ +#define CAN_TXBCR_CR19_Msk (_U_(0x1) << CAN_TXBCR_CR19_Pos) /**< (CAN_TXBCR) Cancellation Request 19 Mask */ +#define CAN_TXBCR_CR19(value) (CAN_TXBCR_CR19_Msk & ((value) << CAN_TXBCR_CR19_Pos)) +#define CAN_TXBCR_CR20_Pos _U_(20) /**< (CAN_TXBCR) Cancellation Request 20 Position */ +#define CAN_TXBCR_CR20_Msk (_U_(0x1) << CAN_TXBCR_CR20_Pos) /**< (CAN_TXBCR) Cancellation Request 20 Mask */ +#define CAN_TXBCR_CR20(value) (CAN_TXBCR_CR20_Msk & ((value) << CAN_TXBCR_CR20_Pos)) +#define CAN_TXBCR_CR21_Pos _U_(21) /**< (CAN_TXBCR) Cancellation Request 21 Position */ +#define CAN_TXBCR_CR21_Msk (_U_(0x1) << CAN_TXBCR_CR21_Pos) /**< (CAN_TXBCR) Cancellation Request 21 Mask */ +#define CAN_TXBCR_CR21(value) (CAN_TXBCR_CR21_Msk & ((value) << CAN_TXBCR_CR21_Pos)) +#define CAN_TXBCR_CR22_Pos _U_(22) /**< (CAN_TXBCR) Cancellation Request 22 Position */ +#define CAN_TXBCR_CR22_Msk (_U_(0x1) << CAN_TXBCR_CR22_Pos) /**< (CAN_TXBCR) Cancellation Request 22 Mask */ +#define CAN_TXBCR_CR22(value) (CAN_TXBCR_CR22_Msk & ((value) << CAN_TXBCR_CR22_Pos)) +#define CAN_TXBCR_CR23_Pos _U_(23) /**< (CAN_TXBCR) Cancellation Request 23 Position */ +#define CAN_TXBCR_CR23_Msk (_U_(0x1) << CAN_TXBCR_CR23_Pos) /**< (CAN_TXBCR) Cancellation Request 23 Mask */ +#define CAN_TXBCR_CR23(value) (CAN_TXBCR_CR23_Msk & ((value) << CAN_TXBCR_CR23_Pos)) +#define CAN_TXBCR_CR24_Pos _U_(24) /**< (CAN_TXBCR) Cancellation Request 24 Position */ +#define CAN_TXBCR_CR24_Msk (_U_(0x1) << CAN_TXBCR_CR24_Pos) /**< (CAN_TXBCR) Cancellation Request 24 Mask */ +#define CAN_TXBCR_CR24(value) (CAN_TXBCR_CR24_Msk & ((value) << CAN_TXBCR_CR24_Pos)) +#define CAN_TXBCR_CR25_Pos _U_(25) /**< (CAN_TXBCR) Cancellation Request 25 Position */ +#define CAN_TXBCR_CR25_Msk (_U_(0x1) << CAN_TXBCR_CR25_Pos) /**< (CAN_TXBCR) Cancellation Request 25 Mask */ +#define CAN_TXBCR_CR25(value) (CAN_TXBCR_CR25_Msk & ((value) << CAN_TXBCR_CR25_Pos)) +#define CAN_TXBCR_CR26_Pos _U_(26) /**< (CAN_TXBCR) Cancellation Request 26 Position */ +#define CAN_TXBCR_CR26_Msk (_U_(0x1) << CAN_TXBCR_CR26_Pos) /**< (CAN_TXBCR) Cancellation Request 26 Mask */ +#define CAN_TXBCR_CR26(value) (CAN_TXBCR_CR26_Msk & ((value) << CAN_TXBCR_CR26_Pos)) +#define CAN_TXBCR_CR27_Pos _U_(27) /**< (CAN_TXBCR) Cancellation Request 27 Position */ +#define CAN_TXBCR_CR27_Msk (_U_(0x1) << CAN_TXBCR_CR27_Pos) /**< (CAN_TXBCR) Cancellation Request 27 Mask */ +#define CAN_TXBCR_CR27(value) (CAN_TXBCR_CR27_Msk & ((value) << CAN_TXBCR_CR27_Pos)) +#define CAN_TXBCR_CR28_Pos _U_(28) /**< (CAN_TXBCR) Cancellation Request 28 Position */ +#define CAN_TXBCR_CR28_Msk (_U_(0x1) << CAN_TXBCR_CR28_Pos) /**< (CAN_TXBCR) Cancellation Request 28 Mask */ +#define CAN_TXBCR_CR28(value) (CAN_TXBCR_CR28_Msk & ((value) << CAN_TXBCR_CR28_Pos)) +#define CAN_TXBCR_CR29_Pos _U_(29) /**< (CAN_TXBCR) Cancellation Request 29 Position */ +#define CAN_TXBCR_CR29_Msk (_U_(0x1) << CAN_TXBCR_CR29_Pos) /**< (CAN_TXBCR) Cancellation Request 29 Mask */ +#define CAN_TXBCR_CR29(value) (CAN_TXBCR_CR29_Msk & ((value) << CAN_TXBCR_CR29_Pos)) +#define CAN_TXBCR_CR30_Pos _U_(30) /**< (CAN_TXBCR) Cancellation Request 30 Position */ +#define CAN_TXBCR_CR30_Msk (_U_(0x1) << CAN_TXBCR_CR30_Pos) /**< (CAN_TXBCR) Cancellation Request 30 Mask */ +#define CAN_TXBCR_CR30(value) (CAN_TXBCR_CR30_Msk & ((value) << CAN_TXBCR_CR30_Pos)) +#define CAN_TXBCR_CR31_Pos _U_(31) /**< (CAN_TXBCR) Cancellation Request 31 Position */ +#define CAN_TXBCR_CR31_Msk (_U_(0x1) << CAN_TXBCR_CR31_Pos) /**< (CAN_TXBCR) Cancellation Request 31 Mask */ +#define CAN_TXBCR_CR31(value) (CAN_TXBCR_CR31_Msk & ((value) << CAN_TXBCR_CR31_Pos)) +#define CAN_TXBCR_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBCR) Register Mask */ + +#define CAN_TXBCR_CR_Pos _U_(0) /**< (CAN_TXBCR Position) Cancellation Request 3x */ +#define CAN_TXBCR_CR_Msk (_U_(0xFFFFFFFF) << CAN_TXBCR_CR_Pos) /**< (CAN_TXBCR Mask) CR */ +#define CAN_TXBCR_CR(value) (CAN_TXBCR_CR_Msk & ((value) << CAN_TXBCR_CR_Pos)) + +/* -------- CAN_TXBTO : (CAN Offset: 0xD8) ( R/ 32) Tx Buffer Transmission Occurred -------- */ +#define CAN_TXBTO_RESETVALUE _U_(0x00) /**< (CAN_TXBTO) Tx Buffer Transmission Occurred Reset Value */ + +#define CAN_TXBTO_TO0_Pos _U_(0) /**< (CAN_TXBTO) Transmission Occurred 0 Position */ +#define CAN_TXBTO_TO0_Msk (_U_(0x1) << CAN_TXBTO_TO0_Pos) /**< (CAN_TXBTO) Transmission Occurred 0 Mask */ +#define CAN_TXBTO_TO0(value) (CAN_TXBTO_TO0_Msk & ((value) << CAN_TXBTO_TO0_Pos)) +#define CAN_TXBTO_TO1_Pos _U_(1) /**< (CAN_TXBTO) Transmission Occurred 1 Position */ +#define CAN_TXBTO_TO1_Msk (_U_(0x1) << CAN_TXBTO_TO1_Pos) /**< (CAN_TXBTO) Transmission Occurred 1 Mask */ +#define CAN_TXBTO_TO1(value) (CAN_TXBTO_TO1_Msk & ((value) << CAN_TXBTO_TO1_Pos)) +#define CAN_TXBTO_TO2_Pos _U_(2) /**< (CAN_TXBTO) Transmission Occurred 2 Position */ +#define CAN_TXBTO_TO2_Msk (_U_(0x1) << CAN_TXBTO_TO2_Pos) /**< (CAN_TXBTO) Transmission Occurred 2 Mask */ +#define CAN_TXBTO_TO2(value) (CAN_TXBTO_TO2_Msk & ((value) << CAN_TXBTO_TO2_Pos)) +#define CAN_TXBTO_TO3_Pos _U_(3) /**< (CAN_TXBTO) Transmission Occurred 3 Position */ +#define CAN_TXBTO_TO3_Msk (_U_(0x1) << CAN_TXBTO_TO3_Pos) /**< (CAN_TXBTO) Transmission Occurred 3 Mask */ +#define CAN_TXBTO_TO3(value) (CAN_TXBTO_TO3_Msk & ((value) << CAN_TXBTO_TO3_Pos)) +#define CAN_TXBTO_TO4_Pos _U_(4) /**< (CAN_TXBTO) Transmission Occurred 4 Position */ +#define CAN_TXBTO_TO4_Msk (_U_(0x1) << CAN_TXBTO_TO4_Pos) /**< (CAN_TXBTO) Transmission Occurred 4 Mask */ +#define CAN_TXBTO_TO4(value) (CAN_TXBTO_TO4_Msk & ((value) << CAN_TXBTO_TO4_Pos)) +#define CAN_TXBTO_TO5_Pos _U_(5) /**< (CAN_TXBTO) Transmission Occurred 5 Position */ +#define CAN_TXBTO_TO5_Msk (_U_(0x1) << CAN_TXBTO_TO5_Pos) /**< (CAN_TXBTO) Transmission Occurred 5 Mask */ +#define CAN_TXBTO_TO5(value) (CAN_TXBTO_TO5_Msk & ((value) << CAN_TXBTO_TO5_Pos)) +#define CAN_TXBTO_TO6_Pos _U_(6) /**< (CAN_TXBTO) Transmission Occurred 6 Position */ +#define CAN_TXBTO_TO6_Msk (_U_(0x1) << CAN_TXBTO_TO6_Pos) /**< (CAN_TXBTO) Transmission Occurred 6 Mask */ +#define CAN_TXBTO_TO6(value) (CAN_TXBTO_TO6_Msk & ((value) << CAN_TXBTO_TO6_Pos)) +#define CAN_TXBTO_TO7_Pos _U_(7) /**< (CAN_TXBTO) Transmission Occurred 7 Position */ +#define CAN_TXBTO_TO7_Msk (_U_(0x1) << CAN_TXBTO_TO7_Pos) /**< (CAN_TXBTO) Transmission Occurred 7 Mask */ +#define CAN_TXBTO_TO7(value) (CAN_TXBTO_TO7_Msk & ((value) << CAN_TXBTO_TO7_Pos)) +#define CAN_TXBTO_TO8_Pos _U_(8) /**< (CAN_TXBTO) Transmission Occurred 8 Position */ +#define CAN_TXBTO_TO8_Msk (_U_(0x1) << CAN_TXBTO_TO8_Pos) /**< (CAN_TXBTO) Transmission Occurred 8 Mask */ +#define CAN_TXBTO_TO8(value) (CAN_TXBTO_TO8_Msk & ((value) << CAN_TXBTO_TO8_Pos)) +#define CAN_TXBTO_TO9_Pos _U_(9) /**< (CAN_TXBTO) Transmission Occurred 9 Position */ +#define CAN_TXBTO_TO9_Msk (_U_(0x1) << CAN_TXBTO_TO9_Pos) /**< (CAN_TXBTO) Transmission Occurred 9 Mask */ +#define CAN_TXBTO_TO9(value) (CAN_TXBTO_TO9_Msk & ((value) << CAN_TXBTO_TO9_Pos)) +#define CAN_TXBTO_TO10_Pos _U_(10) /**< (CAN_TXBTO) Transmission Occurred 10 Position */ +#define CAN_TXBTO_TO10_Msk (_U_(0x1) << CAN_TXBTO_TO10_Pos) /**< (CAN_TXBTO) Transmission Occurred 10 Mask */ +#define CAN_TXBTO_TO10(value) (CAN_TXBTO_TO10_Msk & ((value) << CAN_TXBTO_TO10_Pos)) +#define CAN_TXBTO_TO11_Pos _U_(11) /**< (CAN_TXBTO) Transmission Occurred 11 Position */ +#define CAN_TXBTO_TO11_Msk (_U_(0x1) << CAN_TXBTO_TO11_Pos) /**< (CAN_TXBTO) Transmission Occurred 11 Mask */ +#define CAN_TXBTO_TO11(value) (CAN_TXBTO_TO11_Msk & ((value) << CAN_TXBTO_TO11_Pos)) +#define CAN_TXBTO_TO12_Pos _U_(12) /**< (CAN_TXBTO) Transmission Occurred 12 Position */ +#define CAN_TXBTO_TO12_Msk (_U_(0x1) << CAN_TXBTO_TO12_Pos) /**< (CAN_TXBTO) Transmission Occurred 12 Mask */ +#define CAN_TXBTO_TO12(value) (CAN_TXBTO_TO12_Msk & ((value) << CAN_TXBTO_TO12_Pos)) +#define CAN_TXBTO_TO13_Pos _U_(13) /**< (CAN_TXBTO) Transmission Occurred 13 Position */ +#define CAN_TXBTO_TO13_Msk (_U_(0x1) << CAN_TXBTO_TO13_Pos) /**< (CAN_TXBTO) Transmission Occurred 13 Mask */ +#define CAN_TXBTO_TO13(value) (CAN_TXBTO_TO13_Msk & ((value) << CAN_TXBTO_TO13_Pos)) +#define CAN_TXBTO_TO14_Pos _U_(14) /**< (CAN_TXBTO) Transmission Occurred 14 Position */ +#define CAN_TXBTO_TO14_Msk (_U_(0x1) << CAN_TXBTO_TO14_Pos) /**< (CAN_TXBTO) Transmission Occurred 14 Mask */ +#define CAN_TXBTO_TO14(value) (CAN_TXBTO_TO14_Msk & ((value) << CAN_TXBTO_TO14_Pos)) +#define CAN_TXBTO_TO15_Pos _U_(15) /**< (CAN_TXBTO) Transmission Occurred 15 Position */ +#define CAN_TXBTO_TO15_Msk (_U_(0x1) << CAN_TXBTO_TO15_Pos) /**< (CAN_TXBTO) Transmission Occurred 15 Mask */ +#define CAN_TXBTO_TO15(value) (CAN_TXBTO_TO15_Msk & ((value) << CAN_TXBTO_TO15_Pos)) +#define CAN_TXBTO_TO16_Pos _U_(16) /**< (CAN_TXBTO) Transmission Occurred 16 Position */ +#define CAN_TXBTO_TO16_Msk (_U_(0x1) << CAN_TXBTO_TO16_Pos) /**< (CAN_TXBTO) Transmission Occurred 16 Mask */ +#define CAN_TXBTO_TO16(value) (CAN_TXBTO_TO16_Msk & ((value) << CAN_TXBTO_TO16_Pos)) +#define CAN_TXBTO_TO17_Pos _U_(17) /**< (CAN_TXBTO) Transmission Occurred 17 Position */ +#define CAN_TXBTO_TO17_Msk (_U_(0x1) << CAN_TXBTO_TO17_Pos) /**< (CAN_TXBTO) Transmission Occurred 17 Mask */ +#define CAN_TXBTO_TO17(value) (CAN_TXBTO_TO17_Msk & ((value) << CAN_TXBTO_TO17_Pos)) +#define CAN_TXBTO_TO18_Pos _U_(18) /**< (CAN_TXBTO) Transmission Occurred 18 Position */ +#define CAN_TXBTO_TO18_Msk (_U_(0x1) << CAN_TXBTO_TO18_Pos) /**< (CAN_TXBTO) Transmission Occurred 18 Mask */ +#define CAN_TXBTO_TO18(value) (CAN_TXBTO_TO18_Msk & ((value) << CAN_TXBTO_TO18_Pos)) +#define CAN_TXBTO_TO19_Pos _U_(19) /**< (CAN_TXBTO) Transmission Occurred 19 Position */ +#define CAN_TXBTO_TO19_Msk (_U_(0x1) << CAN_TXBTO_TO19_Pos) /**< (CAN_TXBTO) Transmission Occurred 19 Mask */ +#define CAN_TXBTO_TO19(value) (CAN_TXBTO_TO19_Msk & ((value) << CAN_TXBTO_TO19_Pos)) +#define CAN_TXBTO_TO20_Pos _U_(20) /**< (CAN_TXBTO) Transmission Occurred 20 Position */ +#define CAN_TXBTO_TO20_Msk (_U_(0x1) << CAN_TXBTO_TO20_Pos) /**< (CAN_TXBTO) Transmission Occurred 20 Mask */ +#define CAN_TXBTO_TO20(value) (CAN_TXBTO_TO20_Msk & ((value) << CAN_TXBTO_TO20_Pos)) +#define CAN_TXBTO_TO21_Pos _U_(21) /**< (CAN_TXBTO) Transmission Occurred 21 Position */ +#define CAN_TXBTO_TO21_Msk (_U_(0x1) << CAN_TXBTO_TO21_Pos) /**< (CAN_TXBTO) Transmission Occurred 21 Mask */ +#define CAN_TXBTO_TO21(value) (CAN_TXBTO_TO21_Msk & ((value) << CAN_TXBTO_TO21_Pos)) +#define CAN_TXBTO_TO22_Pos _U_(22) /**< (CAN_TXBTO) Transmission Occurred 22 Position */ +#define CAN_TXBTO_TO22_Msk (_U_(0x1) << CAN_TXBTO_TO22_Pos) /**< (CAN_TXBTO) Transmission Occurred 22 Mask */ +#define CAN_TXBTO_TO22(value) (CAN_TXBTO_TO22_Msk & ((value) << CAN_TXBTO_TO22_Pos)) +#define CAN_TXBTO_TO23_Pos _U_(23) /**< (CAN_TXBTO) Transmission Occurred 23 Position */ +#define CAN_TXBTO_TO23_Msk (_U_(0x1) << CAN_TXBTO_TO23_Pos) /**< (CAN_TXBTO) Transmission Occurred 23 Mask */ +#define CAN_TXBTO_TO23(value) (CAN_TXBTO_TO23_Msk & ((value) << CAN_TXBTO_TO23_Pos)) +#define CAN_TXBTO_TO24_Pos _U_(24) /**< (CAN_TXBTO) Transmission Occurred 24 Position */ +#define CAN_TXBTO_TO24_Msk (_U_(0x1) << CAN_TXBTO_TO24_Pos) /**< (CAN_TXBTO) Transmission Occurred 24 Mask */ +#define CAN_TXBTO_TO24(value) (CAN_TXBTO_TO24_Msk & ((value) << CAN_TXBTO_TO24_Pos)) +#define CAN_TXBTO_TO25_Pos _U_(25) /**< (CAN_TXBTO) Transmission Occurred 25 Position */ +#define CAN_TXBTO_TO25_Msk (_U_(0x1) << CAN_TXBTO_TO25_Pos) /**< (CAN_TXBTO) Transmission Occurred 25 Mask */ +#define CAN_TXBTO_TO25(value) (CAN_TXBTO_TO25_Msk & ((value) << CAN_TXBTO_TO25_Pos)) +#define CAN_TXBTO_TO26_Pos _U_(26) /**< (CAN_TXBTO) Transmission Occurred 26 Position */ +#define CAN_TXBTO_TO26_Msk (_U_(0x1) << CAN_TXBTO_TO26_Pos) /**< (CAN_TXBTO) Transmission Occurred 26 Mask */ +#define CAN_TXBTO_TO26(value) (CAN_TXBTO_TO26_Msk & ((value) << CAN_TXBTO_TO26_Pos)) +#define CAN_TXBTO_TO27_Pos _U_(27) /**< (CAN_TXBTO) Transmission Occurred 27 Position */ +#define CAN_TXBTO_TO27_Msk (_U_(0x1) << CAN_TXBTO_TO27_Pos) /**< (CAN_TXBTO) Transmission Occurred 27 Mask */ +#define CAN_TXBTO_TO27(value) (CAN_TXBTO_TO27_Msk & ((value) << CAN_TXBTO_TO27_Pos)) +#define CAN_TXBTO_TO28_Pos _U_(28) /**< (CAN_TXBTO) Transmission Occurred 28 Position */ +#define CAN_TXBTO_TO28_Msk (_U_(0x1) << CAN_TXBTO_TO28_Pos) /**< (CAN_TXBTO) Transmission Occurred 28 Mask */ +#define CAN_TXBTO_TO28(value) (CAN_TXBTO_TO28_Msk & ((value) << CAN_TXBTO_TO28_Pos)) +#define CAN_TXBTO_TO29_Pos _U_(29) /**< (CAN_TXBTO) Transmission Occurred 29 Position */ +#define CAN_TXBTO_TO29_Msk (_U_(0x1) << CAN_TXBTO_TO29_Pos) /**< (CAN_TXBTO) Transmission Occurred 29 Mask */ +#define CAN_TXBTO_TO29(value) (CAN_TXBTO_TO29_Msk & ((value) << CAN_TXBTO_TO29_Pos)) +#define CAN_TXBTO_TO30_Pos _U_(30) /**< (CAN_TXBTO) Transmission Occurred 30 Position */ +#define CAN_TXBTO_TO30_Msk (_U_(0x1) << CAN_TXBTO_TO30_Pos) /**< (CAN_TXBTO) Transmission Occurred 30 Mask */ +#define CAN_TXBTO_TO30(value) (CAN_TXBTO_TO30_Msk & ((value) << CAN_TXBTO_TO30_Pos)) +#define CAN_TXBTO_TO31_Pos _U_(31) /**< (CAN_TXBTO) Transmission Occurred 31 Position */ +#define CAN_TXBTO_TO31_Msk (_U_(0x1) << CAN_TXBTO_TO31_Pos) /**< (CAN_TXBTO) Transmission Occurred 31 Mask */ +#define CAN_TXBTO_TO31(value) (CAN_TXBTO_TO31_Msk & ((value) << CAN_TXBTO_TO31_Pos)) +#define CAN_TXBTO_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBTO) Register Mask */ + +#define CAN_TXBTO_TO_Pos _U_(0) /**< (CAN_TXBTO Position) Transmission Occurred 3x */ +#define CAN_TXBTO_TO_Msk (_U_(0xFFFFFFFF) << CAN_TXBTO_TO_Pos) /**< (CAN_TXBTO Mask) TO */ +#define CAN_TXBTO_TO(value) (CAN_TXBTO_TO_Msk & ((value) << CAN_TXBTO_TO_Pos)) + +/* -------- CAN_TXBCF : (CAN Offset: 0xDC) ( R/ 32) Tx Buffer Cancellation Finished -------- */ +#define CAN_TXBCF_RESETVALUE _U_(0x00) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished Reset Value */ + +#define CAN_TXBCF_CF0_Pos _U_(0) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Position */ +#define CAN_TXBCF_CF0_Msk (_U_(0x1) << CAN_TXBCF_CF0_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Mask */ +#define CAN_TXBCF_CF0(value) (CAN_TXBCF_CF0_Msk & ((value) << CAN_TXBCF_CF0_Pos)) +#define CAN_TXBCF_CF1_Pos _U_(1) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Position */ +#define CAN_TXBCF_CF1_Msk (_U_(0x1) << CAN_TXBCF_CF1_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Mask */ +#define CAN_TXBCF_CF1(value) (CAN_TXBCF_CF1_Msk & ((value) << CAN_TXBCF_CF1_Pos)) +#define CAN_TXBCF_CF2_Pos _U_(2) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Position */ +#define CAN_TXBCF_CF2_Msk (_U_(0x1) << CAN_TXBCF_CF2_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Mask */ +#define CAN_TXBCF_CF2(value) (CAN_TXBCF_CF2_Msk & ((value) << CAN_TXBCF_CF2_Pos)) +#define CAN_TXBCF_CF3_Pos _U_(3) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Position */ +#define CAN_TXBCF_CF3_Msk (_U_(0x1) << CAN_TXBCF_CF3_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Mask */ +#define CAN_TXBCF_CF3(value) (CAN_TXBCF_CF3_Msk & ((value) << CAN_TXBCF_CF3_Pos)) +#define CAN_TXBCF_CF4_Pos _U_(4) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Position */ +#define CAN_TXBCF_CF4_Msk (_U_(0x1) << CAN_TXBCF_CF4_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Mask */ +#define CAN_TXBCF_CF4(value) (CAN_TXBCF_CF4_Msk & ((value) << CAN_TXBCF_CF4_Pos)) +#define CAN_TXBCF_CF5_Pos _U_(5) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Position */ +#define CAN_TXBCF_CF5_Msk (_U_(0x1) << CAN_TXBCF_CF5_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Mask */ +#define CAN_TXBCF_CF5(value) (CAN_TXBCF_CF5_Msk & ((value) << CAN_TXBCF_CF5_Pos)) +#define CAN_TXBCF_CF6_Pos _U_(6) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Position */ +#define CAN_TXBCF_CF6_Msk (_U_(0x1) << CAN_TXBCF_CF6_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Mask */ +#define CAN_TXBCF_CF6(value) (CAN_TXBCF_CF6_Msk & ((value) << CAN_TXBCF_CF6_Pos)) +#define CAN_TXBCF_CF7_Pos _U_(7) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Position */ +#define CAN_TXBCF_CF7_Msk (_U_(0x1) << CAN_TXBCF_CF7_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Mask */ +#define CAN_TXBCF_CF7(value) (CAN_TXBCF_CF7_Msk & ((value) << CAN_TXBCF_CF7_Pos)) +#define CAN_TXBCF_CF8_Pos _U_(8) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Position */ +#define CAN_TXBCF_CF8_Msk (_U_(0x1) << CAN_TXBCF_CF8_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Mask */ +#define CAN_TXBCF_CF8(value) (CAN_TXBCF_CF8_Msk & ((value) << CAN_TXBCF_CF8_Pos)) +#define CAN_TXBCF_CF9_Pos _U_(9) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Position */ +#define CAN_TXBCF_CF9_Msk (_U_(0x1) << CAN_TXBCF_CF9_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Mask */ +#define CAN_TXBCF_CF9(value) (CAN_TXBCF_CF9_Msk & ((value) << CAN_TXBCF_CF9_Pos)) +#define CAN_TXBCF_CF10_Pos _U_(10) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Position */ +#define CAN_TXBCF_CF10_Msk (_U_(0x1) << CAN_TXBCF_CF10_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Mask */ +#define CAN_TXBCF_CF10(value) (CAN_TXBCF_CF10_Msk & ((value) << CAN_TXBCF_CF10_Pos)) +#define CAN_TXBCF_CF11_Pos _U_(11) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Position */ +#define CAN_TXBCF_CF11_Msk (_U_(0x1) << CAN_TXBCF_CF11_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Mask */ +#define CAN_TXBCF_CF11(value) (CAN_TXBCF_CF11_Msk & ((value) << CAN_TXBCF_CF11_Pos)) +#define CAN_TXBCF_CF12_Pos _U_(12) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Position */ +#define CAN_TXBCF_CF12_Msk (_U_(0x1) << CAN_TXBCF_CF12_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Mask */ +#define CAN_TXBCF_CF12(value) (CAN_TXBCF_CF12_Msk & ((value) << CAN_TXBCF_CF12_Pos)) +#define CAN_TXBCF_CF13_Pos _U_(13) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Position */ +#define CAN_TXBCF_CF13_Msk (_U_(0x1) << CAN_TXBCF_CF13_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Mask */ +#define CAN_TXBCF_CF13(value) (CAN_TXBCF_CF13_Msk & ((value) << CAN_TXBCF_CF13_Pos)) +#define CAN_TXBCF_CF14_Pos _U_(14) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Position */ +#define CAN_TXBCF_CF14_Msk (_U_(0x1) << CAN_TXBCF_CF14_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Mask */ +#define CAN_TXBCF_CF14(value) (CAN_TXBCF_CF14_Msk & ((value) << CAN_TXBCF_CF14_Pos)) +#define CAN_TXBCF_CF15_Pos _U_(15) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Position */ +#define CAN_TXBCF_CF15_Msk (_U_(0x1) << CAN_TXBCF_CF15_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Mask */ +#define CAN_TXBCF_CF15(value) (CAN_TXBCF_CF15_Msk & ((value) << CAN_TXBCF_CF15_Pos)) +#define CAN_TXBCF_CF16_Pos _U_(16) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Position */ +#define CAN_TXBCF_CF16_Msk (_U_(0x1) << CAN_TXBCF_CF16_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Mask */ +#define CAN_TXBCF_CF16(value) (CAN_TXBCF_CF16_Msk & ((value) << CAN_TXBCF_CF16_Pos)) +#define CAN_TXBCF_CF17_Pos _U_(17) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Position */ +#define CAN_TXBCF_CF17_Msk (_U_(0x1) << CAN_TXBCF_CF17_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Mask */ +#define CAN_TXBCF_CF17(value) (CAN_TXBCF_CF17_Msk & ((value) << CAN_TXBCF_CF17_Pos)) +#define CAN_TXBCF_CF18_Pos _U_(18) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Position */ +#define CAN_TXBCF_CF18_Msk (_U_(0x1) << CAN_TXBCF_CF18_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Mask */ +#define CAN_TXBCF_CF18(value) (CAN_TXBCF_CF18_Msk & ((value) << CAN_TXBCF_CF18_Pos)) +#define CAN_TXBCF_CF19_Pos _U_(19) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Position */ +#define CAN_TXBCF_CF19_Msk (_U_(0x1) << CAN_TXBCF_CF19_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Mask */ +#define CAN_TXBCF_CF19(value) (CAN_TXBCF_CF19_Msk & ((value) << CAN_TXBCF_CF19_Pos)) +#define CAN_TXBCF_CF20_Pos _U_(20) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Position */ +#define CAN_TXBCF_CF20_Msk (_U_(0x1) << CAN_TXBCF_CF20_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Mask */ +#define CAN_TXBCF_CF20(value) (CAN_TXBCF_CF20_Msk & ((value) << CAN_TXBCF_CF20_Pos)) +#define CAN_TXBCF_CF21_Pos _U_(21) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Position */ +#define CAN_TXBCF_CF21_Msk (_U_(0x1) << CAN_TXBCF_CF21_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Mask */ +#define CAN_TXBCF_CF21(value) (CAN_TXBCF_CF21_Msk & ((value) << CAN_TXBCF_CF21_Pos)) +#define CAN_TXBCF_CF22_Pos _U_(22) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Position */ +#define CAN_TXBCF_CF22_Msk (_U_(0x1) << CAN_TXBCF_CF22_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Mask */ +#define CAN_TXBCF_CF22(value) (CAN_TXBCF_CF22_Msk & ((value) << CAN_TXBCF_CF22_Pos)) +#define CAN_TXBCF_CF23_Pos _U_(23) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Position */ +#define CAN_TXBCF_CF23_Msk (_U_(0x1) << CAN_TXBCF_CF23_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Mask */ +#define CAN_TXBCF_CF23(value) (CAN_TXBCF_CF23_Msk & ((value) << CAN_TXBCF_CF23_Pos)) +#define CAN_TXBCF_CF24_Pos _U_(24) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Position */ +#define CAN_TXBCF_CF24_Msk (_U_(0x1) << CAN_TXBCF_CF24_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Mask */ +#define CAN_TXBCF_CF24(value) (CAN_TXBCF_CF24_Msk & ((value) << CAN_TXBCF_CF24_Pos)) +#define CAN_TXBCF_CF25_Pos _U_(25) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Position */ +#define CAN_TXBCF_CF25_Msk (_U_(0x1) << CAN_TXBCF_CF25_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Mask */ +#define CAN_TXBCF_CF25(value) (CAN_TXBCF_CF25_Msk & ((value) << CAN_TXBCF_CF25_Pos)) +#define CAN_TXBCF_CF26_Pos _U_(26) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Position */ +#define CAN_TXBCF_CF26_Msk (_U_(0x1) << CAN_TXBCF_CF26_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Mask */ +#define CAN_TXBCF_CF26(value) (CAN_TXBCF_CF26_Msk & ((value) << CAN_TXBCF_CF26_Pos)) +#define CAN_TXBCF_CF27_Pos _U_(27) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Position */ +#define CAN_TXBCF_CF27_Msk (_U_(0x1) << CAN_TXBCF_CF27_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Mask */ +#define CAN_TXBCF_CF27(value) (CAN_TXBCF_CF27_Msk & ((value) << CAN_TXBCF_CF27_Pos)) +#define CAN_TXBCF_CF28_Pos _U_(28) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Position */ +#define CAN_TXBCF_CF28_Msk (_U_(0x1) << CAN_TXBCF_CF28_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Mask */ +#define CAN_TXBCF_CF28(value) (CAN_TXBCF_CF28_Msk & ((value) << CAN_TXBCF_CF28_Pos)) +#define CAN_TXBCF_CF29_Pos _U_(29) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Position */ +#define CAN_TXBCF_CF29_Msk (_U_(0x1) << CAN_TXBCF_CF29_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Mask */ +#define CAN_TXBCF_CF29(value) (CAN_TXBCF_CF29_Msk & ((value) << CAN_TXBCF_CF29_Pos)) +#define CAN_TXBCF_CF30_Pos _U_(30) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Position */ +#define CAN_TXBCF_CF30_Msk (_U_(0x1) << CAN_TXBCF_CF30_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Mask */ +#define CAN_TXBCF_CF30(value) (CAN_TXBCF_CF30_Msk & ((value) << CAN_TXBCF_CF30_Pos)) +#define CAN_TXBCF_CF31_Pos _U_(31) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Position */ +#define CAN_TXBCF_CF31_Msk (_U_(0x1) << CAN_TXBCF_CF31_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Mask */ +#define CAN_TXBCF_CF31(value) (CAN_TXBCF_CF31_Msk & ((value) << CAN_TXBCF_CF31_Pos)) +#define CAN_TXBCF_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBCF) Register Mask */ + +#define CAN_TXBCF_CF_Pos _U_(0) /**< (CAN_TXBCF Position) Tx Buffer Cancellation Finished 3x */ +#define CAN_TXBCF_CF_Msk (_U_(0xFFFFFFFF) << CAN_TXBCF_CF_Pos) /**< (CAN_TXBCF Mask) CF */ +#define CAN_TXBCF_CF(value) (CAN_TXBCF_CF_Msk & ((value) << CAN_TXBCF_CF_Pos)) + +/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ +#define CAN_TXBTIE_RESETVALUE _U_(0x00) /**< (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Reset Value */ + +#define CAN_TXBTIE_TIE0_Pos _U_(0) /**< (CAN_TXBTIE) Transmission Interrupt Enable 0 Position */ +#define CAN_TXBTIE_TIE0_Msk (_U_(0x1) << CAN_TXBTIE_TIE0_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 0 Mask */ +#define CAN_TXBTIE_TIE0(value) (CAN_TXBTIE_TIE0_Msk & ((value) << CAN_TXBTIE_TIE0_Pos)) +#define CAN_TXBTIE_TIE1_Pos _U_(1) /**< (CAN_TXBTIE) Transmission Interrupt Enable 1 Position */ +#define CAN_TXBTIE_TIE1_Msk (_U_(0x1) << CAN_TXBTIE_TIE1_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 1 Mask */ +#define CAN_TXBTIE_TIE1(value) (CAN_TXBTIE_TIE1_Msk & ((value) << CAN_TXBTIE_TIE1_Pos)) +#define CAN_TXBTIE_TIE2_Pos _U_(2) /**< (CAN_TXBTIE) Transmission Interrupt Enable 2 Position */ +#define CAN_TXBTIE_TIE2_Msk (_U_(0x1) << CAN_TXBTIE_TIE2_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 2 Mask */ +#define CAN_TXBTIE_TIE2(value) (CAN_TXBTIE_TIE2_Msk & ((value) << CAN_TXBTIE_TIE2_Pos)) +#define CAN_TXBTIE_TIE3_Pos _U_(3) /**< (CAN_TXBTIE) Transmission Interrupt Enable 3 Position */ +#define CAN_TXBTIE_TIE3_Msk (_U_(0x1) << CAN_TXBTIE_TIE3_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 3 Mask */ +#define CAN_TXBTIE_TIE3(value) (CAN_TXBTIE_TIE3_Msk & ((value) << CAN_TXBTIE_TIE3_Pos)) +#define CAN_TXBTIE_TIE4_Pos _U_(4) /**< (CAN_TXBTIE) Transmission Interrupt Enable 4 Position */ +#define CAN_TXBTIE_TIE4_Msk (_U_(0x1) << CAN_TXBTIE_TIE4_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 4 Mask */ +#define CAN_TXBTIE_TIE4(value) (CAN_TXBTIE_TIE4_Msk & ((value) << CAN_TXBTIE_TIE4_Pos)) +#define CAN_TXBTIE_TIE5_Pos _U_(5) /**< (CAN_TXBTIE) Transmission Interrupt Enable 5 Position */ +#define CAN_TXBTIE_TIE5_Msk (_U_(0x1) << CAN_TXBTIE_TIE5_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 5 Mask */ +#define CAN_TXBTIE_TIE5(value) (CAN_TXBTIE_TIE5_Msk & ((value) << CAN_TXBTIE_TIE5_Pos)) +#define CAN_TXBTIE_TIE6_Pos _U_(6) /**< (CAN_TXBTIE) Transmission Interrupt Enable 6 Position */ +#define CAN_TXBTIE_TIE6_Msk (_U_(0x1) << CAN_TXBTIE_TIE6_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 6 Mask */ +#define CAN_TXBTIE_TIE6(value) (CAN_TXBTIE_TIE6_Msk & ((value) << CAN_TXBTIE_TIE6_Pos)) +#define CAN_TXBTIE_TIE7_Pos _U_(7) /**< (CAN_TXBTIE) Transmission Interrupt Enable 7 Position */ +#define CAN_TXBTIE_TIE7_Msk (_U_(0x1) << CAN_TXBTIE_TIE7_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 7 Mask */ +#define CAN_TXBTIE_TIE7(value) (CAN_TXBTIE_TIE7_Msk & ((value) << CAN_TXBTIE_TIE7_Pos)) +#define CAN_TXBTIE_TIE8_Pos _U_(8) /**< (CAN_TXBTIE) Transmission Interrupt Enable 8 Position */ +#define CAN_TXBTIE_TIE8_Msk (_U_(0x1) << CAN_TXBTIE_TIE8_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 8 Mask */ +#define CAN_TXBTIE_TIE8(value) (CAN_TXBTIE_TIE8_Msk & ((value) << CAN_TXBTIE_TIE8_Pos)) +#define CAN_TXBTIE_TIE9_Pos _U_(9) /**< (CAN_TXBTIE) Transmission Interrupt Enable 9 Position */ +#define CAN_TXBTIE_TIE9_Msk (_U_(0x1) << CAN_TXBTIE_TIE9_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 9 Mask */ +#define CAN_TXBTIE_TIE9(value) (CAN_TXBTIE_TIE9_Msk & ((value) << CAN_TXBTIE_TIE9_Pos)) +#define CAN_TXBTIE_TIE10_Pos _U_(10) /**< (CAN_TXBTIE) Transmission Interrupt Enable 10 Position */ +#define CAN_TXBTIE_TIE10_Msk (_U_(0x1) << CAN_TXBTIE_TIE10_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 10 Mask */ +#define CAN_TXBTIE_TIE10(value) (CAN_TXBTIE_TIE10_Msk & ((value) << CAN_TXBTIE_TIE10_Pos)) +#define CAN_TXBTIE_TIE11_Pos _U_(11) /**< (CAN_TXBTIE) Transmission Interrupt Enable 11 Position */ +#define CAN_TXBTIE_TIE11_Msk (_U_(0x1) << CAN_TXBTIE_TIE11_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 11 Mask */ +#define CAN_TXBTIE_TIE11(value) (CAN_TXBTIE_TIE11_Msk & ((value) << CAN_TXBTIE_TIE11_Pos)) +#define CAN_TXBTIE_TIE12_Pos _U_(12) /**< (CAN_TXBTIE) Transmission Interrupt Enable 12 Position */ +#define CAN_TXBTIE_TIE12_Msk (_U_(0x1) << CAN_TXBTIE_TIE12_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 12 Mask */ +#define CAN_TXBTIE_TIE12(value) (CAN_TXBTIE_TIE12_Msk & ((value) << CAN_TXBTIE_TIE12_Pos)) +#define CAN_TXBTIE_TIE13_Pos _U_(13) /**< (CAN_TXBTIE) Transmission Interrupt Enable 13 Position */ +#define CAN_TXBTIE_TIE13_Msk (_U_(0x1) << CAN_TXBTIE_TIE13_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 13 Mask */ +#define CAN_TXBTIE_TIE13(value) (CAN_TXBTIE_TIE13_Msk & ((value) << CAN_TXBTIE_TIE13_Pos)) +#define CAN_TXBTIE_TIE14_Pos _U_(14) /**< (CAN_TXBTIE) Transmission Interrupt Enable 14 Position */ +#define CAN_TXBTIE_TIE14_Msk (_U_(0x1) << CAN_TXBTIE_TIE14_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 14 Mask */ +#define CAN_TXBTIE_TIE14(value) (CAN_TXBTIE_TIE14_Msk & ((value) << CAN_TXBTIE_TIE14_Pos)) +#define CAN_TXBTIE_TIE15_Pos _U_(15) /**< (CAN_TXBTIE) Transmission Interrupt Enable 15 Position */ +#define CAN_TXBTIE_TIE15_Msk (_U_(0x1) << CAN_TXBTIE_TIE15_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 15 Mask */ +#define CAN_TXBTIE_TIE15(value) (CAN_TXBTIE_TIE15_Msk & ((value) << CAN_TXBTIE_TIE15_Pos)) +#define CAN_TXBTIE_TIE16_Pos _U_(16) /**< (CAN_TXBTIE) Transmission Interrupt Enable 16 Position */ +#define CAN_TXBTIE_TIE16_Msk (_U_(0x1) << CAN_TXBTIE_TIE16_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 16 Mask */ +#define CAN_TXBTIE_TIE16(value) (CAN_TXBTIE_TIE16_Msk & ((value) << CAN_TXBTIE_TIE16_Pos)) +#define CAN_TXBTIE_TIE17_Pos _U_(17) /**< (CAN_TXBTIE) Transmission Interrupt Enable 17 Position */ +#define CAN_TXBTIE_TIE17_Msk (_U_(0x1) << CAN_TXBTIE_TIE17_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 17 Mask */ +#define CAN_TXBTIE_TIE17(value) (CAN_TXBTIE_TIE17_Msk & ((value) << CAN_TXBTIE_TIE17_Pos)) +#define CAN_TXBTIE_TIE18_Pos _U_(18) /**< (CAN_TXBTIE) Transmission Interrupt Enable 18 Position */ +#define CAN_TXBTIE_TIE18_Msk (_U_(0x1) << CAN_TXBTIE_TIE18_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 18 Mask */ +#define CAN_TXBTIE_TIE18(value) (CAN_TXBTIE_TIE18_Msk & ((value) << CAN_TXBTIE_TIE18_Pos)) +#define CAN_TXBTIE_TIE19_Pos _U_(19) /**< (CAN_TXBTIE) Transmission Interrupt Enable 19 Position */ +#define CAN_TXBTIE_TIE19_Msk (_U_(0x1) << CAN_TXBTIE_TIE19_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 19 Mask */ +#define CAN_TXBTIE_TIE19(value) (CAN_TXBTIE_TIE19_Msk & ((value) << CAN_TXBTIE_TIE19_Pos)) +#define CAN_TXBTIE_TIE20_Pos _U_(20) /**< (CAN_TXBTIE) Transmission Interrupt Enable 20 Position */ +#define CAN_TXBTIE_TIE20_Msk (_U_(0x1) << CAN_TXBTIE_TIE20_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 20 Mask */ +#define CAN_TXBTIE_TIE20(value) (CAN_TXBTIE_TIE20_Msk & ((value) << CAN_TXBTIE_TIE20_Pos)) +#define CAN_TXBTIE_TIE21_Pos _U_(21) /**< (CAN_TXBTIE) Transmission Interrupt Enable 21 Position */ +#define CAN_TXBTIE_TIE21_Msk (_U_(0x1) << CAN_TXBTIE_TIE21_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 21 Mask */ +#define CAN_TXBTIE_TIE21(value) (CAN_TXBTIE_TIE21_Msk & ((value) << CAN_TXBTIE_TIE21_Pos)) +#define CAN_TXBTIE_TIE22_Pos _U_(22) /**< (CAN_TXBTIE) Transmission Interrupt Enable 22 Position */ +#define CAN_TXBTIE_TIE22_Msk (_U_(0x1) << CAN_TXBTIE_TIE22_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 22 Mask */ +#define CAN_TXBTIE_TIE22(value) (CAN_TXBTIE_TIE22_Msk & ((value) << CAN_TXBTIE_TIE22_Pos)) +#define CAN_TXBTIE_TIE23_Pos _U_(23) /**< (CAN_TXBTIE) Transmission Interrupt Enable 23 Position */ +#define CAN_TXBTIE_TIE23_Msk (_U_(0x1) << CAN_TXBTIE_TIE23_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 23 Mask */ +#define CAN_TXBTIE_TIE23(value) (CAN_TXBTIE_TIE23_Msk & ((value) << CAN_TXBTIE_TIE23_Pos)) +#define CAN_TXBTIE_TIE24_Pos _U_(24) /**< (CAN_TXBTIE) Transmission Interrupt Enable 24 Position */ +#define CAN_TXBTIE_TIE24_Msk (_U_(0x1) << CAN_TXBTIE_TIE24_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 24 Mask */ +#define CAN_TXBTIE_TIE24(value) (CAN_TXBTIE_TIE24_Msk & ((value) << CAN_TXBTIE_TIE24_Pos)) +#define CAN_TXBTIE_TIE25_Pos _U_(25) /**< (CAN_TXBTIE) Transmission Interrupt Enable 25 Position */ +#define CAN_TXBTIE_TIE25_Msk (_U_(0x1) << CAN_TXBTIE_TIE25_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 25 Mask */ +#define CAN_TXBTIE_TIE25(value) (CAN_TXBTIE_TIE25_Msk & ((value) << CAN_TXBTIE_TIE25_Pos)) +#define CAN_TXBTIE_TIE26_Pos _U_(26) /**< (CAN_TXBTIE) Transmission Interrupt Enable 26 Position */ +#define CAN_TXBTIE_TIE26_Msk (_U_(0x1) << CAN_TXBTIE_TIE26_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 26 Mask */ +#define CAN_TXBTIE_TIE26(value) (CAN_TXBTIE_TIE26_Msk & ((value) << CAN_TXBTIE_TIE26_Pos)) +#define CAN_TXBTIE_TIE27_Pos _U_(27) /**< (CAN_TXBTIE) Transmission Interrupt Enable 27 Position */ +#define CAN_TXBTIE_TIE27_Msk (_U_(0x1) << CAN_TXBTIE_TIE27_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 27 Mask */ +#define CAN_TXBTIE_TIE27(value) (CAN_TXBTIE_TIE27_Msk & ((value) << CAN_TXBTIE_TIE27_Pos)) +#define CAN_TXBTIE_TIE28_Pos _U_(28) /**< (CAN_TXBTIE) Transmission Interrupt Enable 28 Position */ +#define CAN_TXBTIE_TIE28_Msk (_U_(0x1) << CAN_TXBTIE_TIE28_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 28 Mask */ +#define CAN_TXBTIE_TIE28(value) (CAN_TXBTIE_TIE28_Msk & ((value) << CAN_TXBTIE_TIE28_Pos)) +#define CAN_TXBTIE_TIE29_Pos _U_(29) /**< (CAN_TXBTIE) Transmission Interrupt Enable 29 Position */ +#define CAN_TXBTIE_TIE29_Msk (_U_(0x1) << CAN_TXBTIE_TIE29_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 29 Mask */ +#define CAN_TXBTIE_TIE29(value) (CAN_TXBTIE_TIE29_Msk & ((value) << CAN_TXBTIE_TIE29_Pos)) +#define CAN_TXBTIE_TIE30_Pos _U_(30) /**< (CAN_TXBTIE) Transmission Interrupt Enable 30 Position */ +#define CAN_TXBTIE_TIE30_Msk (_U_(0x1) << CAN_TXBTIE_TIE30_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 30 Mask */ +#define CAN_TXBTIE_TIE30(value) (CAN_TXBTIE_TIE30_Msk & ((value) << CAN_TXBTIE_TIE30_Pos)) +#define CAN_TXBTIE_TIE31_Pos _U_(31) /**< (CAN_TXBTIE) Transmission Interrupt Enable 31 Position */ +#define CAN_TXBTIE_TIE31_Msk (_U_(0x1) << CAN_TXBTIE_TIE31_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 31 Mask */ +#define CAN_TXBTIE_TIE31(value) (CAN_TXBTIE_TIE31_Msk & ((value) << CAN_TXBTIE_TIE31_Pos)) +#define CAN_TXBTIE_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBTIE) Register Mask */ + +#define CAN_TXBTIE_TIE_Pos _U_(0) /**< (CAN_TXBTIE Position) Transmission Interrupt Enable 3x */ +#define CAN_TXBTIE_TIE_Msk (_U_(0xFFFFFFFF) << CAN_TXBTIE_TIE_Pos) /**< (CAN_TXBTIE Mask) TIE */ +#define CAN_TXBTIE_TIE(value) (CAN_TXBTIE_TIE_Msk & ((value) << CAN_TXBTIE_TIE_Pos)) + +/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ +#define CAN_TXBCIE_RESETVALUE _U_(0x00) /**< (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Reset Value */ + +#define CAN_TXBCIE_CFIE0_Pos _U_(0) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Position */ +#define CAN_TXBCIE_CFIE0_Msk (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Mask */ +#define CAN_TXBCIE_CFIE0(value) (CAN_TXBCIE_CFIE0_Msk & ((value) << CAN_TXBCIE_CFIE0_Pos)) +#define CAN_TXBCIE_CFIE1_Pos _U_(1) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Position */ +#define CAN_TXBCIE_CFIE1_Msk (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Mask */ +#define CAN_TXBCIE_CFIE1(value) (CAN_TXBCIE_CFIE1_Msk & ((value) << CAN_TXBCIE_CFIE1_Pos)) +#define CAN_TXBCIE_CFIE2_Pos _U_(2) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Position */ +#define CAN_TXBCIE_CFIE2_Msk (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Mask */ +#define CAN_TXBCIE_CFIE2(value) (CAN_TXBCIE_CFIE2_Msk & ((value) << CAN_TXBCIE_CFIE2_Pos)) +#define CAN_TXBCIE_CFIE3_Pos _U_(3) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Position */ +#define CAN_TXBCIE_CFIE3_Msk (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Mask */ +#define CAN_TXBCIE_CFIE3(value) (CAN_TXBCIE_CFIE3_Msk & ((value) << CAN_TXBCIE_CFIE3_Pos)) +#define CAN_TXBCIE_CFIE4_Pos _U_(4) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Position */ +#define CAN_TXBCIE_CFIE4_Msk (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Mask */ +#define CAN_TXBCIE_CFIE4(value) (CAN_TXBCIE_CFIE4_Msk & ((value) << CAN_TXBCIE_CFIE4_Pos)) +#define CAN_TXBCIE_CFIE5_Pos _U_(5) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Position */ +#define CAN_TXBCIE_CFIE5_Msk (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Mask */ +#define CAN_TXBCIE_CFIE5(value) (CAN_TXBCIE_CFIE5_Msk & ((value) << CAN_TXBCIE_CFIE5_Pos)) +#define CAN_TXBCIE_CFIE6_Pos _U_(6) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Position */ +#define CAN_TXBCIE_CFIE6_Msk (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Mask */ +#define CAN_TXBCIE_CFIE6(value) (CAN_TXBCIE_CFIE6_Msk & ((value) << CAN_TXBCIE_CFIE6_Pos)) +#define CAN_TXBCIE_CFIE7_Pos _U_(7) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Position */ +#define CAN_TXBCIE_CFIE7_Msk (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Mask */ +#define CAN_TXBCIE_CFIE7(value) (CAN_TXBCIE_CFIE7_Msk & ((value) << CAN_TXBCIE_CFIE7_Pos)) +#define CAN_TXBCIE_CFIE8_Pos _U_(8) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Position */ +#define CAN_TXBCIE_CFIE8_Msk (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Mask */ +#define CAN_TXBCIE_CFIE8(value) (CAN_TXBCIE_CFIE8_Msk & ((value) << CAN_TXBCIE_CFIE8_Pos)) +#define CAN_TXBCIE_CFIE9_Pos _U_(9) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Position */ +#define CAN_TXBCIE_CFIE9_Msk (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Mask */ +#define CAN_TXBCIE_CFIE9(value) (CAN_TXBCIE_CFIE9_Msk & ((value) << CAN_TXBCIE_CFIE9_Pos)) +#define CAN_TXBCIE_CFIE10_Pos _U_(10) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Position */ +#define CAN_TXBCIE_CFIE10_Msk (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Mask */ +#define CAN_TXBCIE_CFIE10(value) (CAN_TXBCIE_CFIE10_Msk & ((value) << CAN_TXBCIE_CFIE10_Pos)) +#define CAN_TXBCIE_CFIE11_Pos _U_(11) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Position */ +#define CAN_TXBCIE_CFIE11_Msk (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Mask */ +#define CAN_TXBCIE_CFIE11(value) (CAN_TXBCIE_CFIE11_Msk & ((value) << CAN_TXBCIE_CFIE11_Pos)) +#define CAN_TXBCIE_CFIE12_Pos _U_(12) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Position */ +#define CAN_TXBCIE_CFIE12_Msk (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Mask */ +#define CAN_TXBCIE_CFIE12(value) (CAN_TXBCIE_CFIE12_Msk & ((value) << CAN_TXBCIE_CFIE12_Pos)) +#define CAN_TXBCIE_CFIE13_Pos _U_(13) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Position */ +#define CAN_TXBCIE_CFIE13_Msk (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Mask */ +#define CAN_TXBCIE_CFIE13(value) (CAN_TXBCIE_CFIE13_Msk & ((value) << CAN_TXBCIE_CFIE13_Pos)) +#define CAN_TXBCIE_CFIE14_Pos _U_(14) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Position */ +#define CAN_TXBCIE_CFIE14_Msk (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Mask */ +#define CAN_TXBCIE_CFIE14(value) (CAN_TXBCIE_CFIE14_Msk & ((value) << CAN_TXBCIE_CFIE14_Pos)) +#define CAN_TXBCIE_CFIE15_Pos _U_(15) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Position */ +#define CAN_TXBCIE_CFIE15_Msk (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Mask */ +#define CAN_TXBCIE_CFIE15(value) (CAN_TXBCIE_CFIE15_Msk & ((value) << CAN_TXBCIE_CFIE15_Pos)) +#define CAN_TXBCIE_CFIE16_Pos _U_(16) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Position */ +#define CAN_TXBCIE_CFIE16_Msk (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Mask */ +#define CAN_TXBCIE_CFIE16(value) (CAN_TXBCIE_CFIE16_Msk & ((value) << CAN_TXBCIE_CFIE16_Pos)) +#define CAN_TXBCIE_CFIE17_Pos _U_(17) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Position */ +#define CAN_TXBCIE_CFIE17_Msk (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Mask */ +#define CAN_TXBCIE_CFIE17(value) (CAN_TXBCIE_CFIE17_Msk & ((value) << CAN_TXBCIE_CFIE17_Pos)) +#define CAN_TXBCIE_CFIE18_Pos _U_(18) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Position */ +#define CAN_TXBCIE_CFIE18_Msk (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Mask */ +#define CAN_TXBCIE_CFIE18(value) (CAN_TXBCIE_CFIE18_Msk & ((value) << CAN_TXBCIE_CFIE18_Pos)) +#define CAN_TXBCIE_CFIE19_Pos _U_(19) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Position */ +#define CAN_TXBCIE_CFIE19_Msk (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Mask */ +#define CAN_TXBCIE_CFIE19(value) (CAN_TXBCIE_CFIE19_Msk & ((value) << CAN_TXBCIE_CFIE19_Pos)) +#define CAN_TXBCIE_CFIE20_Pos _U_(20) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Position */ +#define CAN_TXBCIE_CFIE20_Msk (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Mask */ +#define CAN_TXBCIE_CFIE20(value) (CAN_TXBCIE_CFIE20_Msk & ((value) << CAN_TXBCIE_CFIE20_Pos)) +#define CAN_TXBCIE_CFIE21_Pos _U_(21) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Position */ +#define CAN_TXBCIE_CFIE21_Msk (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Mask */ +#define CAN_TXBCIE_CFIE21(value) (CAN_TXBCIE_CFIE21_Msk & ((value) << CAN_TXBCIE_CFIE21_Pos)) +#define CAN_TXBCIE_CFIE22_Pos _U_(22) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Position */ +#define CAN_TXBCIE_CFIE22_Msk (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Mask */ +#define CAN_TXBCIE_CFIE22(value) (CAN_TXBCIE_CFIE22_Msk & ((value) << CAN_TXBCIE_CFIE22_Pos)) +#define CAN_TXBCIE_CFIE23_Pos _U_(23) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Position */ +#define CAN_TXBCIE_CFIE23_Msk (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Mask */ +#define CAN_TXBCIE_CFIE23(value) (CAN_TXBCIE_CFIE23_Msk & ((value) << CAN_TXBCIE_CFIE23_Pos)) +#define CAN_TXBCIE_CFIE24_Pos _U_(24) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Position */ +#define CAN_TXBCIE_CFIE24_Msk (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Mask */ +#define CAN_TXBCIE_CFIE24(value) (CAN_TXBCIE_CFIE24_Msk & ((value) << CAN_TXBCIE_CFIE24_Pos)) +#define CAN_TXBCIE_CFIE25_Pos _U_(25) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Position */ +#define CAN_TXBCIE_CFIE25_Msk (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Mask */ +#define CAN_TXBCIE_CFIE25(value) (CAN_TXBCIE_CFIE25_Msk & ((value) << CAN_TXBCIE_CFIE25_Pos)) +#define CAN_TXBCIE_CFIE26_Pos _U_(26) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Position */ +#define CAN_TXBCIE_CFIE26_Msk (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Mask */ +#define CAN_TXBCIE_CFIE26(value) (CAN_TXBCIE_CFIE26_Msk & ((value) << CAN_TXBCIE_CFIE26_Pos)) +#define CAN_TXBCIE_CFIE27_Pos _U_(27) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Position */ +#define CAN_TXBCIE_CFIE27_Msk (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Mask */ +#define CAN_TXBCIE_CFIE27(value) (CAN_TXBCIE_CFIE27_Msk & ((value) << CAN_TXBCIE_CFIE27_Pos)) +#define CAN_TXBCIE_CFIE28_Pos _U_(28) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Position */ +#define CAN_TXBCIE_CFIE28_Msk (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Mask */ +#define CAN_TXBCIE_CFIE28(value) (CAN_TXBCIE_CFIE28_Msk & ((value) << CAN_TXBCIE_CFIE28_Pos)) +#define CAN_TXBCIE_CFIE29_Pos _U_(29) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Position */ +#define CAN_TXBCIE_CFIE29_Msk (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Mask */ +#define CAN_TXBCIE_CFIE29(value) (CAN_TXBCIE_CFIE29_Msk & ((value) << CAN_TXBCIE_CFIE29_Pos)) +#define CAN_TXBCIE_CFIE30_Pos _U_(30) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Position */ +#define CAN_TXBCIE_CFIE30_Msk (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Mask */ +#define CAN_TXBCIE_CFIE30(value) (CAN_TXBCIE_CFIE30_Msk & ((value) << CAN_TXBCIE_CFIE30_Pos)) +#define CAN_TXBCIE_CFIE31_Pos _U_(31) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Position */ +#define CAN_TXBCIE_CFIE31_Msk (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Mask */ +#define CAN_TXBCIE_CFIE31(value) (CAN_TXBCIE_CFIE31_Msk & ((value) << CAN_TXBCIE_CFIE31_Pos)) +#define CAN_TXBCIE_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBCIE) Register Mask */ + +#define CAN_TXBCIE_CFIE_Pos _U_(0) /**< (CAN_TXBCIE Position) Cancellation Finished Interrupt Enable 3x */ +#define CAN_TXBCIE_CFIE_Msk (_U_(0xFFFFFFFF) << CAN_TXBCIE_CFIE_Pos) /**< (CAN_TXBCIE Mask) CFIE */ +#define CAN_TXBCIE_CFIE(value) (CAN_TXBCIE_CFIE_Msk & ((value) << CAN_TXBCIE_CFIE_Pos)) + +/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ +#define CAN_TXEFC_RESETVALUE _U_(0x00) /**< (CAN_TXEFC) Tx Event FIFO Configuration Reset Value */ + +#define CAN_TXEFC_EFSA_Pos _U_(0) /**< (CAN_TXEFC) Event FIFO Start Address Position */ +#define CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos) /**< (CAN_TXEFC) Event FIFO Start Address Mask */ +#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos)) +#define CAN_TXEFC_EFS_Pos _U_(16) /**< (CAN_TXEFC) Event FIFO Size Position */ +#define CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos) /**< (CAN_TXEFC) Event FIFO Size Mask */ +#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos)) +#define CAN_TXEFC_EFWM_Pos _U_(24) /**< (CAN_TXEFC) Event FIFO Watermark Position */ +#define CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos) /**< (CAN_TXEFC) Event FIFO Watermark Mask */ +#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos)) +#define CAN_TXEFC_Msk _U_(0x3F3FFFFF) /**< (CAN_TXEFC) Register Mask */ + + +/* -------- CAN_TXEFS : (CAN Offset: 0xF4) ( R/ 32) Tx Event FIFO Status -------- */ +#define CAN_TXEFS_RESETVALUE _U_(0x00) /**< (CAN_TXEFS) Tx Event FIFO Status Reset Value */ + +#define CAN_TXEFS_EFFL_Pos _U_(0) /**< (CAN_TXEFS) Event FIFO Fill Level Position */ +#define CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos) /**< (CAN_TXEFS) Event FIFO Fill Level Mask */ +#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos)) +#define CAN_TXEFS_EFGI_Pos _U_(8) /**< (CAN_TXEFS) Event FIFO Get Index Position */ +#define CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos) /**< (CAN_TXEFS) Event FIFO Get Index Mask */ +#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos)) +#define CAN_TXEFS_EFPI_Pos _U_(16) /**< (CAN_TXEFS) Event FIFO Put Index Position */ +#define CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos) /**< (CAN_TXEFS) Event FIFO Put Index Mask */ +#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos)) +#define CAN_TXEFS_EFF_Pos _U_(24) /**< (CAN_TXEFS) Event FIFO Full Position */ +#define CAN_TXEFS_EFF_Msk (_U_(0x1) << CAN_TXEFS_EFF_Pos) /**< (CAN_TXEFS) Event FIFO Full Mask */ +#define CAN_TXEFS_EFF(value) (CAN_TXEFS_EFF_Msk & ((value) << CAN_TXEFS_EFF_Pos)) +#define CAN_TXEFS_TEFL_Pos _U_(25) /**< (CAN_TXEFS) Tx Event FIFO Element Lost Position */ +#define CAN_TXEFS_TEFL_Msk (_U_(0x1) << CAN_TXEFS_TEFL_Pos) /**< (CAN_TXEFS) Tx Event FIFO Element Lost Mask */ +#define CAN_TXEFS_TEFL(value) (CAN_TXEFS_TEFL_Msk & ((value) << CAN_TXEFS_TEFL_Pos)) +#define CAN_TXEFS_Msk _U_(0x031F1F3F) /**< (CAN_TXEFS) Register Mask */ + + +/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ +#define CAN_TXEFA_RESETVALUE _U_(0x00) /**< (CAN_TXEFA) Tx Event FIFO Acknowledge Reset Value */ + +#define CAN_TXEFA_EFAI_Pos _U_(0) /**< (CAN_TXEFA) Event FIFO Acknowledge Index Position */ +#define CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos) /**< (CAN_TXEFA) Event FIFO Acknowledge Index Mask */ +#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos)) +#define CAN_TXEFA_Msk _U_(0x0000001F) /**< (CAN_TXEFA) Register Mask */ + + +/** \brief CAN register offsets definitions */ +#define CAN_RXBE_0_REG_OFST (0x00) /**< (CAN_RXBE_0) Rx Buffer Element 0 Offset */ +#define CAN_RXBE_1_REG_OFST (0x04) /**< (CAN_RXBE_1) Rx Buffer Element 1 Offset */ +#define CAN_RXBE_DATA_REG_OFST (0x08) /**< (CAN_RXBE_DATA) Rx Buffer Element Data Offset */ +#define CAN_RXF0E_0_REG_OFST (0x00) /**< (CAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ +#define CAN_RXF0E_1_REG_OFST (0x04) /**< (CAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ +#define CAN_RXF0E_DATA_REG_OFST (0x08) /**< (CAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ +#define CAN_RXF1E_0_REG_OFST (0x00) /**< (CAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ +#define CAN_RXF1E_1_REG_OFST (0x04) /**< (CAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ +#define CAN_RXF1E_DATA_REG_OFST (0x08) /**< (CAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ +#define CAN_TXBE_0_REG_OFST (0x00) /**< (CAN_TXBE_0) Tx Buffer Element 0 Offset */ +#define CAN_TXBE_1_REG_OFST (0x04) /**< (CAN_TXBE_1) Tx Buffer Element 1 Offset */ +#define CAN_TXBE_DATA_REG_OFST (0x08) /**< (CAN_TXBE_DATA) Tx Buffer Element Data Offset */ +#define CAN_TXEFE_0_REG_OFST (0x00) /**< (CAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ +#define CAN_TXEFE_1_REG_OFST (0x04) /**< (CAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ +#define CAN_SIDFE_0_REG_OFST (0x00) /**< (CAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_0_REG_OFST (0x00) /**< (CAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_1_REG_OFST (0x04) /**< (CAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ +#define CAN_CREL_REG_OFST (0x00) /**< (CAN_CREL) Core Release Offset */ +#define CAN_ENDN_REG_OFST (0x04) /**< (CAN_ENDN) Endian Offset */ +#define CAN_MRCFG_REG_OFST (0x08) /**< (CAN_MRCFG) Message RAM Configuration Offset */ +#define CAN_DBTP_REG_OFST (0x0C) /**< (CAN_DBTP) Fast Bit Timing and Prescaler Offset */ +#define CAN_TEST_REG_OFST (0x10) /**< (CAN_TEST) Test Offset */ +#define CAN_RWD_REG_OFST (0x14) /**< (CAN_RWD) RAM Watchdog Offset */ +#define CAN_CCCR_REG_OFST (0x18) /**< (CAN_CCCR) CC Control Offset */ +#define CAN_NBTP_REG_OFST (0x1C) /**< (CAN_NBTP) Nominal Bit Timing and Prescaler Offset */ +#define CAN_TSCC_REG_OFST (0x20) /**< (CAN_TSCC) Timestamp Counter Configuration Offset */ +#define CAN_TSCV_REG_OFST (0x24) /**< (CAN_TSCV) Timestamp Counter Value Offset */ +#define CAN_TOCC_REG_OFST (0x28) /**< (CAN_TOCC) Timeout Counter Configuration Offset */ +#define CAN_TOCV_REG_OFST (0x2C) /**< (CAN_TOCV) Timeout Counter Value Offset */ +#define CAN_ECR_REG_OFST (0x40) /**< (CAN_ECR) Error Counter Offset */ +#define CAN_PSR_REG_OFST (0x44) /**< (CAN_PSR) Protocol Status Offset */ +#define CAN_TDCR_REG_OFST (0x48) /**< (CAN_TDCR) Extended ID Filter Configuration Offset */ +#define CAN_IR_REG_OFST (0x50) /**< (CAN_IR) Interrupt Offset */ +#define CAN_IE_REG_OFST (0x54) /**< (CAN_IE) Interrupt Enable Offset */ +#define CAN_ILS_REG_OFST (0x58) /**< (CAN_ILS) Interrupt Line Select Offset */ +#define CAN_ILE_REG_OFST (0x5C) /**< (CAN_ILE) Interrupt Line Enable Offset */ +#define CAN_GFC_REG_OFST (0x80) /**< (CAN_GFC) Global Filter Configuration Offset */ +#define CAN_SIDFC_REG_OFST (0x84) /**< (CAN_SIDFC) Standard ID Filter Configuration Offset */ +#define CAN_XIDFC_REG_OFST (0x88) /**< (CAN_XIDFC) Extended ID Filter Configuration Offset */ +#define CAN_XIDAM_REG_OFST (0x90) /**< (CAN_XIDAM) Extended ID AND Mask Offset */ +#define CAN_HPMS_REG_OFST (0x94) /**< (CAN_HPMS) High Priority Message Status Offset */ +#define CAN_NDAT1_REG_OFST (0x98) /**< (CAN_NDAT1) New Data 1 Offset */ +#define CAN_NDAT2_REG_OFST (0x9C) /**< (CAN_NDAT2) New Data 2 Offset */ +#define CAN_RXF0C_REG_OFST (0xA0) /**< (CAN_RXF0C) Rx FIFO 0 Configuration Offset */ +#define CAN_RXF0S_REG_OFST (0xA4) /**< (CAN_RXF0S) Rx FIFO 0 Status Offset */ +#define CAN_RXF0A_REG_OFST (0xA8) /**< (CAN_RXF0A) Rx FIFO 0 Acknowledge Offset */ +#define CAN_RXBC_REG_OFST (0xAC) /**< (CAN_RXBC) Rx Buffer Configuration Offset */ +#define CAN_RXF1C_REG_OFST (0xB0) /**< (CAN_RXF1C) Rx FIFO 1 Configuration Offset */ +#define CAN_RXF1S_REG_OFST (0xB4) /**< (CAN_RXF1S) Rx FIFO 1 Status Offset */ +#define CAN_RXF1A_REG_OFST (0xB8) /**< (CAN_RXF1A) Rx FIFO 1 Acknowledge Offset */ +#define CAN_RXESC_REG_OFST (0xBC) /**< (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Offset */ +#define CAN_TXBC_REG_OFST (0xC0) /**< (CAN_TXBC) Tx Buffer Configuration Offset */ +#define CAN_TXFQS_REG_OFST (0xC4) /**< (CAN_TXFQS) Tx FIFO / Queue Status Offset */ +#define CAN_TXESC_REG_OFST (0xC8) /**< (CAN_TXESC) Tx Buffer Element Size Configuration Offset */ +#define CAN_TXBRP_REG_OFST (0xCC) /**< (CAN_TXBRP) Tx Buffer Request Pending Offset */ +#define CAN_TXBAR_REG_OFST (0xD0) /**< (CAN_TXBAR) Tx Buffer Add Request Offset */ +#define CAN_TXBCR_REG_OFST (0xD4) /**< (CAN_TXBCR) Tx Buffer Cancellation Request Offset */ +#define CAN_TXBTO_REG_OFST (0xD8) /**< (CAN_TXBTO) Tx Buffer Transmission Occurred Offset */ +#define CAN_TXBCF_REG_OFST (0xDC) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished Offset */ +#define CAN_TXBTIE_REG_OFST (0xE0) /**< (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Offset */ +#define CAN_TXBCIE_REG_OFST (0xE4) /**< (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Offset */ +#define CAN_TXEFC_REG_OFST (0xF0) /**< (CAN_TXEFC) Tx Event FIFO Configuration Offset */ +#define CAN_TXEFS_REG_OFST (0xF4) /**< (CAN_TXEFS) Tx Event FIFO Status Offset */ +#define CAN_TXEFA_REG_OFST (0xF8) /**< (CAN_TXEFA) Tx Event FIFO Acknowledge Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CAN_RXBE register API structure */ +typedef struct +{ /* Rx Buffer Element */ + __IO uint32_t CAN_RXBE_0; /**< Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO uint32_t CAN_RXBE_1; /**< Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO uint32_t CAN_RXBE_DATA; /**< Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} can_rxbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_RXF0E register API structure */ +typedef struct +{ /* Rx FIFO 0 Element */ + __IO uint32_t CAN_RXF0E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO uint32_t CAN_RXF0E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO uint32_t CAN_RXF0E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} can_rxf0e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_RXF1E register API structure */ +typedef struct +{ /* Rx FIFO 1 Element */ + __IO uint32_t CAN_RXF1E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO uint32_t CAN_RXF1E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO uint32_t CAN_RXF1E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} can_rxf1e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_TXBE register API structure */ +typedef struct +{ /* Tx Buffer Element */ + __IO uint32_t CAN_TXBE_0; /**< Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO uint32_t CAN_TXBE_1; /**< Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO uint32_t CAN_TXBE_DATA; /**< Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} can_txbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_TXEFE register API structure */ +typedef struct +{ /* Tx Event FIFO Element */ + __IO uint32_t CAN_TXEFE_0; /**< Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO uint32_t CAN_TXEFE_1; /**< Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} can_txefe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_SIDFE register API structure */ +typedef struct +{ /* Standard Message ID Filter Element */ + __IO uint32_t CAN_SIDFE_0; /**< Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ +} can_sidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_XIDFE register API structure */ +typedef struct +{ /* Extended Message ID Filter Element */ + __IO uint32_t CAN_XIDFE_0; /**< Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO uint32_t CAN_XIDFE_1; /**< Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} can_xidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN register API structure */ +typedef struct +{ /* Control Area Network */ + __I uint32_t CAN_CREL; /**< Offset: 0x00 (R/ 32) Core Release */ + __I uint32_t CAN_ENDN; /**< Offset: 0x04 (R/ 32) Endian */ + __IO uint32_t CAN_MRCFG; /**< Offset: 0x08 (R/W 32) Message RAM Configuration */ + __IO uint32_t CAN_DBTP; /**< Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ + __IO uint32_t CAN_TEST; /**< Offset: 0x10 (R/W 32) Test */ + __IO uint32_t CAN_RWD; /**< Offset: 0x14 (R/W 32) RAM Watchdog */ + __IO uint32_t CAN_CCCR; /**< Offset: 0x18 (R/W 32) CC Control */ + __IO uint32_t CAN_NBTP; /**< Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ + __IO uint32_t CAN_TSCC; /**< Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ + __I uint32_t CAN_TSCV; /**< Offset: 0x24 (R/ 32) Timestamp Counter Value */ + __IO uint32_t CAN_TOCC; /**< Offset: 0x28 (R/W 32) Timeout Counter Configuration */ + __IO uint32_t CAN_TOCV; /**< Offset: 0x2C (R/W 32) Timeout Counter Value */ + __I uint8_t Reserved1[0x10]; + __I uint32_t CAN_ECR; /**< Offset: 0x40 (R/ 32) Error Counter */ + __I uint32_t CAN_PSR; /**< Offset: 0x44 (R/ 32) Protocol Status */ + __IO uint32_t CAN_TDCR; /**< Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t CAN_IR; /**< Offset: 0x50 (R/W 32) Interrupt */ + __IO uint32_t CAN_IE; /**< Offset: 0x54 (R/W 32) Interrupt Enable */ + __IO uint32_t CAN_ILS; /**< Offset: 0x58 (R/W 32) Interrupt Line Select */ + __IO uint32_t CAN_ILE; /**< Offset: 0x5C (R/W 32) Interrupt Line Enable */ + __I uint8_t Reserved3[0x20]; + __IO uint32_t CAN_GFC; /**< Offset: 0x80 (R/W 32) Global Filter Configuration */ + __IO uint32_t CAN_SIDFC; /**< Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ + __IO uint32_t CAN_XIDFC; /**< Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t CAN_XIDAM; /**< Offset: 0x90 (R/W 32) Extended ID AND Mask */ + __I uint32_t CAN_HPMS; /**< Offset: 0x94 (R/ 32) High Priority Message Status */ + __IO uint32_t CAN_NDAT1; /**< Offset: 0x98 (R/W 32) New Data 1 */ + __IO uint32_t CAN_NDAT2; /**< Offset: 0x9C (R/W 32) New Data 2 */ + __IO uint32_t CAN_RXF0C; /**< Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ + __I uint32_t CAN_RXF0S; /**< Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ + __IO uint32_t CAN_RXF0A; /**< Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ + __IO uint32_t CAN_RXBC; /**< Offset: 0xAC (R/W 32) Rx Buffer Configuration */ + __IO uint32_t CAN_RXF1C; /**< Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ + __I uint32_t CAN_RXF1S; /**< Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ + __IO uint32_t CAN_RXF1A; /**< Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ + __IO uint32_t CAN_RXESC; /**< Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ + __IO uint32_t CAN_TXBC; /**< Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ + __I uint32_t CAN_TXFQS; /**< Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ + __IO uint32_t CAN_TXESC; /**< Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ + __I uint32_t CAN_TXBRP; /**< Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ + __IO uint32_t CAN_TXBAR; /**< Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ + __IO uint32_t CAN_TXBCR; /**< Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ + __I uint32_t CAN_TXBTO; /**< Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ + __I uint32_t CAN_TXBCF; /**< Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ + __IO uint32_t CAN_TXBTIE; /**< Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ + __IO uint32_t CAN_TXBCIE; /**< Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ + __I uint8_t Reserved5[0x08]; + __IO uint32_t CAN_TXEFC; /**< Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ + __I uint32_t CAN_TXEFS; /**< Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ + __IO uint32_t CAN_TXEFA; /**< Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ +} can_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_CAN_COMPONENT_H_ */ diff --git a/arch/arm/SAME54/mcu/inc/component/ccl.h b/arch/arm/SAME54/mcu/inc/component/ccl.h new file mode 100644 index 00000000..5175d3a5 --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/component/ccl.h @@ -0,0 +1,217 @@ +/** + * \brief Component description for CCL + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-12T17:27:04Z */ +#ifndef _SAME54_CCL_COMPONENT_H_ +#define _SAME54_CCL_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CCL */ +/* ************************************************************************** */ + +/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */ +#define CCL_CTRL_RESETVALUE _U_(0x00) /**< (CCL_CTRL) Control Reset Value */ + +#define CCL_CTRL_SWRST_Pos _U_(0) /**< (CCL_CTRL) Software Reset Position */ +#define CCL_CTRL_SWRST_Msk (_U_(0x1) << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) Software Reset Mask */ +#define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & ((value) << CCL_CTRL_SWRST_Pos)) +#define CCL_CTRL_SWRST_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) The peripheral is not reset */ +#define CCL_CTRL_SWRST_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) The peripheral is reset */ +#define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) The peripheral is not reset Position */ +#define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) The peripheral is reset Position */ +#define CCL_CTRL_ENABLE_Pos _U_(1) /**< (CCL_CTRL) Enable Position */ +#define CCL_CTRL_ENABLE_Msk (_U_(0x1) << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) Enable Mask */ +#define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & ((value) << CCL_CTRL_ENABLE_Pos)) +#define CCL_CTRL_ENABLE_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) The peripheral is disabled */ +#define CCL_CTRL_ENABLE_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) The peripheral is enabled */ +#define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) The peripheral is disabled Position */ +#define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) The peripheral is enabled Position */ +#define CCL_CTRL_RUNSTDBY_Pos _U_(6) /**< (CCL_CTRL) Run in Standby Position */ +#define CCL_CTRL_RUNSTDBY_Msk (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Run in Standby Mask */ +#define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & ((value) << CCL_CTRL_RUNSTDBY_Pos)) +#define CCL_CTRL_RUNSTDBY_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) Generic clock is not required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) Generic clock is required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Generic clock is not required in standby sleep mode Position */ +#define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Generic clock is required in standby sleep mode Position */ +#define CCL_CTRL_Msk _U_(0x43) /**< (CCL_CTRL) Register Mask */ + + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */ +#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< (CCL_SEQCTRL) SEQ Control x Reset Value */ + +#define CCL_SEQCTRL_SEQSEL_Pos _U_(0) /**< (CCL_SEQCTRL) Sequential Selection Position */ +#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) Sequential Selection Mask */ +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) Sequential logic is disabled Position */ +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) D flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) JK flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) D latch Position */ +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) RS latch Position */ +#define CCL_SEQCTRL_Msk _U_(0x0F) /**< (CCL_SEQCTRL) Register Mask */ + + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */ +#define CCL_LUTCTRL_RESETVALUE _U_(0x00) /**< (CCL_LUTCTRL) LUT Control x Reset Value */ + +#define CCL_LUTCTRL_ENABLE_Pos _U_(1) /**< (CCL_LUTCTRL) LUT Enable Position */ +#define CCL_LUTCTRL_ENABLE_Msk (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT Enable Mask */ +#define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & ((value) << CCL_LUTCTRL_ENABLE_Pos)) +#define CCL_LUTCTRL_ENABLE_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT block is disabled */ +#define CCL_LUTCTRL_ENABLE_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT block is enabled */ +#define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT block is disabled Position */ +#define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT block is enabled Position */ +#define CCL_LUTCTRL_FILTSEL_Pos _U_(4) /**< (CCL_LUTCTRL) Filter Selection Position */ +#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter Selection Mask */ +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter disabled Position */ +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Synchronizer enabled Position */ +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter enabled Position */ +#define CCL_LUTCTRL_EDGESEL_Pos _U_(7) /**< (CCL_LUTCTRL) Edge Selection Position */ +#define CCL_LUTCTRL_EDGESEL_Msk (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge Selection Mask */ +#define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & ((value) << CCL_LUTCTRL_EDGESEL_Pos)) +#define CCL_LUTCTRL_EDGESEL_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Edge detector is disabled */ +#define CCL_LUTCTRL_EDGESEL_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) Edge detector is enabled */ +#define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge detector is disabled Position */ +#define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge detector is enabled Position */ +#define CCL_LUTCTRL_INSEL0_Pos _U_(8) /**< (CCL_LUTCTRL) Input Selection 0 Position */ +#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Input Selection 0 Mask */ +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL1_Pos _U_(12) /**< (CCL_LUTCTRL) Input Selection 1 Position */ +#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Input Selection 1 Mask */ +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL2_Pos _U_(16) /**< (CCL_LUTCTRL) Input Selection 2 Position */ +#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Input Selection 2 Mask */ +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INVEI_Pos _U_(20) /**< (CCL_LUTCTRL) Inverted Event Input Enable Position */ +#define CCL_LUTCTRL_INVEI_Msk (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Inverted Event Input Enable Mask */ +#define CCL_LUTCTRL_INVEI(value) (CCL_LUTCTRL_INVEI_Msk & ((value) << CCL_LUTCTRL_INVEI_Pos)) +#define CCL_LUTCTRL_INVEI_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Incoming event is not inverted */ +#define CCL_LUTCTRL_INVEI_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) Incoming event is inverted */ +#define CCL_LUTCTRL_INVEI_DISABLE (CCL_LUTCTRL_INVEI_DISABLE_Val << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Incoming event is not inverted Position */ +#define CCL_LUTCTRL_INVEI_ENABLE (CCL_LUTCTRL_INVEI_ENABLE_Val << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Incoming event is inverted Position */ +#define CCL_LUTCTRL_LUTEI_Pos _U_(21) /**< (CCL_LUTCTRL) LUT Event Input Enable Position */ +#define CCL_LUTCTRL_LUTEI_Msk (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT Event Input Enable Mask */ +#define CCL_LUTCTRL_LUTEI(value) (CCL_LUTCTRL_LUTEI_Msk & ((value) << CCL_LUTCTRL_LUTEI_Pos)) +#define CCL_LUTCTRL_LUTEI_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT incoming event is disabled */ +#define CCL_LUTCTRL_LUTEI_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT incoming event is enabled */ +#define CCL_LUTCTRL_LUTEI_DISABLE (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT incoming event is disabled Position */ +#define CCL_LUTCTRL_LUTEI_ENABLE (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT incoming event is enabled Position */ +#define CCL_LUTCTRL_LUTEO_Pos _U_(22) /**< (CCL_LUTCTRL) LUT Event Output Enable Position */ +#define CCL_LUTCTRL_LUTEO_Msk (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT Event Output Enable Mask */ +#define CCL_LUTCTRL_LUTEO(value) (CCL_LUTCTRL_LUTEO_Msk & ((value) << CCL_LUTCTRL_LUTEO_Pos)) +#define CCL_LUTCTRL_LUTEO_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT event output is disabled */ +#define CCL_LUTCTRL_LUTEO_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT event output is enabled */ +#define CCL_LUTCTRL_LUTEO_DISABLE (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT event output is disabled Position */ +#define CCL_LUTCTRL_LUTEO_ENABLE (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT event output is enabled Position */ +#define CCL_LUTCTRL_TRUTH_Pos _U_(24) /**< (CCL_LUTCTRL) Truth Value Position */ +#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) /**< (CCL_LUTCTRL) Truth Value Mask */ +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_Msk _U_(0xFF7FFFB2) /**< (CCL_LUTCTRL) Register Mask */ + + +/** \brief CCL register offsets definitions */ +#define CCL_CTRL_REG_OFST (0x00) /**< (CCL_CTRL) Control Offset */ +#define CCL_SEQCTRL_REG_OFST (0x04) /**< (CCL_SEQCTRL) SEQ Control x Offset */ +#define CCL_LUTCTRL_REG_OFST (0x08) /**< (CCL_LUTCTRL) LUT Control x Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CCL register API structure */ +typedef struct +{ /* Configurable Custom Logic */ + __IO uint8_t CCL_CTRL; /**< Offset: 0x00 (R/W 8) Control */ + __I uint8_t Reserved1[0x03]; + __IO uint8_t CCL_SEQCTRL[2]; /**< Offset: 0x04 (R/W 8) SEQ Control x */ + __I uint8_t Reserved2[0x02]; + __IO uint32_t CCL_LUTCTRL[4]; /**< Offset: 0x08 (R/W 32) LUT Control x */ +} ccl_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_CCL_COMPONENT_H_ */ diff --git a/arch/arm/SAME54/mcu/inc/component/cmcc.h b/arch/arm/SAME54/mcu/inc/component/cmcc.h new file mode 100644 index 00000000..73f1952a --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/component/cmcc.h @@ -0,0 +1,247 @@ +/** + * \brief Component description for CMCC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-12T17:27:04Z */ +#ifndef _SAME54_CMCC_COMPONENT_H_ +#define _SAME54_CMCC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CMCC */ +/* ************************************************************************** */ + +/* -------- CMCC_TYPE : (CMCC Offset: 0x00) ( R/ 32) Cache Type Register -------- */ +#define CMCC_TYPE_RESETVALUE _U_(0x12D2) /**< (CMCC_TYPE) Cache Type Register Reset Value */ + +#define CMCC_TYPE_GCLK_Pos _U_(1) /**< (CMCC_TYPE) dynamic Clock Gating supported Position */ +#define CMCC_TYPE_GCLK_Msk (_U_(0x1) << CMCC_TYPE_GCLK_Pos) /**< (CMCC_TYPE) dynamic Clock Gating supported Mask */ +#define CMCC_TYPE_GCLK(value) (CMCC_TYPE_GCLK_Msk & ((value) << CMCC_TYPE_GCLK_Pos)) +#define CMCC_TYPE_RRP_Pos _U_(4) /**< (CMCC_TYPE) Round Robin Policy supported Position */ +#define CMCC_TYPE_RRP_Msk (_U_(0x1) << CMCC_TYPE_RRP_Pos) /**< (CMCC_TYPE) Round Robin Policy supported Mask */ +#define CMCC_TYPE_RRP(value) (CMCC_TYPE_RRP_Msk & ((value) << CMCC_TYPE_RRP_Pos)) +#define CMCC_TYPE_WAYNUM_Pos _U_(5) /**< (CMCC_TYPE) Number of Way Position */ +#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) Number of Way Mask */ +#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) +#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< (CMCC_TYPE) Direct Mapped Cache */ +#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< (CMCC_TYPE) 2-WAY set associative */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< (CMCC_TYPE) 4-WAY set associative */ +#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) Direct Mapped Cache Position */ +#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) 2-WAY set associative Position */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) 4-WAY set associative Position */ +#define CMCC_TYPE_LCKDOWN_Pos _U_(7) /**< (CMCC_TYPE) Lock Down supported Position */ +#define CMCC_TYPE_LCKDOWN_Msk (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) /**< (CMCC_TYPE) Lock Down supported Mask */ +#define CMCC_TYPE_LCKDOWN(value) (CMCC_TYPE_LCKDOWN_Msk & ((value) << CMCC_TYPE_LCKDOWN_Pos)) +#define CMCC_TYPE_CSIZE_Pos _U_(8) /**< (CMCC_TYPE) Cache Size Position */ +#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size Mask */ +#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) +#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< (CMCC_TYPE) Cache Size is 1 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< (CMCC_TYPE) Cache Size is 2 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< (CMCC_TYPE) Cache Size is 4 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< (CMCC_TYPE) Cache Size is 8 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< (CMCC_TYPE) Cache Size is 16 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< (CMCC_TYPE) Cache Size is 32 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< (CMCC_TYPE) Cache Size is 64 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 1 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 2 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 4 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 8 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 16 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 32 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 64 KB Position */ +#define CMCC_TYPE_CLSIZE_Pos _U_(11) /**< (CMCC_TYPE) Cache Line Size Position */ +#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size Mask */ +#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) +#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< (CMCC_TYPE) Cache Line Size is 4 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< (CMCC_TYPE) Cache Line Size is 8 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< (CMCC_TYPE) Cache Line Size is 16 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< (CMCC_TYPE) Cache Line Size is 32 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< (CMCC_TYPE) Cache Line Size is 64 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< (CMCC_TYPE) Cache Line Size is 128 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 4 bytes Position */ +#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 8 bytes Position */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 16 bytes Position */ +#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 32 bytes Position */ +#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 64 bytes Position */ +#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 128 bytes Position */ +#define CMCC_TYPE_Msk _U_(0x00003FF2) /**< (CMCC_TYPE) Register Mask */ + + +/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ +#define CMCC_CFG_RESETVALUE _U_(0x20) /**< (CMCC_CFG) Cache Configuration Register Reset Value */ + +#define CMCC_CFG_ICDIS_Pos _U_(1) /**< (CMCC_CFG) Instruction Cache Disable Position */ +#define CMCC_CFG_ICDIS_Msk (_U_(0x1) << CMCC_CFG_ICDIS_Pos) /**< (CMCC_CFG) Instruction Cache Disable Mask */ +#define CMCC_CFG_ICDIS(value) (CMCC_CFG_ICDIS_Msk & ((value) << CMCC_CFG_ICDIS_Pos)) +#define CMCC_CFG_DCDIS_Pos _U_(2) /**< (CMCC_CFG) Data Cache Disable Position */ +#define CMCC_CFG_DCDIS_Msk (_U_(0x1) << CMCC_CFG_DCDIS_Pos) /**< (CMCC_CFG) Data Cache Disable Mask */ +#define CMCC_CFG_DCDIS(value) (CMCC_CFG_DCDIS_Msk & ((value) << CMCC_CFG_DCDIS_Pos)) +#define CMCC_CFG_CSIZESW_Pos _U_(4) /**< (CMCC_CFG) Cache size configured by software Position */ +#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) Cache size configured by software Mask */ +#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< (CMCC_CFG) The Cache Size is configured to 1KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< (CMCC_CFG) The Cache Size is configured to 2KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< (CMCC_CFG) The Cache Size is configured to 4KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< (CMCC_CFG) The Cache Size is configured to 8KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< (CMCC_CFG) The Cache Size is configured to 16KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< (CMCC_CFG) The Cache Size is configured to 32KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< (CMCC_CFG) The Cache Size is configured to 64KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 1KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 2KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 4KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 8KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 16KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 32KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 64KB Position */ +#define CMCC_CFG_Msk _U_(0x00000076) /**< (CMCC_CFG) Register Mask */ + + +/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ +#define CMCC_CTRL_RESETVALUE _U_(0x00) /**< (CMCC_CTRL) Cache Control Register Reset Value */ + +#define CMCC_CTRL_CEN_Pos _U_(0) /**< (CMCC_CTRL) Cache Controller Enable Position */ +#define CMCC_CTRL_CEN_Msk (_U_(0x1) << CMCC_CTRL_CEN_Pos) /**< (CMCC_CTRL) Cache Controller Enable Mask */ +#define CMCC_CTRL_CEN(value) (CMCC_CTRL_CEN_Msk & ((value) << CMCC_CTRL_CEN_Pos)) +#define CMCC_CTRL_Msk _U_(0x00000001) /**< (CMCC_CTRL) Register Mask */ + + +/* -------- CMCC_SR : (CMCC Offset: 0x0C) ( R/ 32) Cache Status Register -------- */ +#define CMCC_SR_RESETVALUE _U_(0x00) /**< (CMCC_SR) Cache Status Register Reset Value */ + +#define CMCC_SR_CSTS_Pos _U_(0) /**< (CMCC_SR) Cache Controller Status Position */ +#define CMCC_SR_CSTS_Msk (_U_(0x1) << CMCC_SR_CSTS_Pos) /**< (CMCC_SR) Cache Controller Status Mask */ +#define CMCC_SR_CSTS(value) (CMCC_SR_CSTS_Msk & ((value) << CMCC_SR_CSTS_Pos)) +#define CMCC_SR_Msk _U_(0x00000001) /**< (CMCC_SR) Register Mask */ + + +/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ +#define CMCC_LCKWAY_RESETVALUE _U_(0x00) /**< (CMCC_LCKWAY) Cache Lock per Way Register Reset Value */ + +#define CMCC_LCKWAY_LCKWAY_Pos _U_(0) /**< (CMCC_LCKWAY) Lockdown way Register Position */ +#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) /**< (CMCC_LCKWAY) Lockdown way Register Mask */ +#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) +#define CMCC_LCKWAY_Msk _U_(0x0000000F) /**< (CMCC_LCKWAY) Register Mask */ + + +/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ +#define CMCC_MAINT0_RESETVALUE _U_(0x00) /**< (CMCC_MAINT0) Cache Maintenance Register 0 Reset Value */ + +#define CMCC_MAINT0_INVALL_Pos _U_(0) /**< (CMCC_MAINT0) Cache Controller invalidate All Position */ +#define CMCC_MAINT0_INVALL_Msk (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) /**< (CMCC_MAINT0) Cache Controller invalidate All Mask */ +#define CMCC_MAINT0_INVALL(value) (CMCC_MAINT0_INVALL_Msk & ((value) << CMCC_MAINT0_INVALL_Pos)) +#define CMCC_MAINT0_Msk _U_(0x00000001) /**< (CMCC_MAINT0) Register Mask */ + + +/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ +#define CMCC_MAINT1_RESETVALUE _U_(0x00) /**< (CMCC_MAINT1) Cache Maintenance Register 1 Reset Value */ + +#define CMCC_MAINT1_INDEX_Pos _U_(4) /**< (CMCC_MAINT1) Invalidate Index Position */ +#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) /**< (CMCC_MAINT1) Invalidate Index Mask */ +#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) +#define CMCC_MAINT1_WAY_Pos _U_(28) /**< (CMCC_MAINT1) Invalidate Way Position */ +#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Invalidate Way Mask */ +#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) +#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< (CMCC_MAINT1) Way 0 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< (CMCC_MAINT1) Way 1 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< (CMCC_MAINT1) Way 2 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< (CMCC_MAINT1) Way 3 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 0 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 1 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 2 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 3 is selection for index invalidation Position */ +#define CMCC_MAINT1_Msk _U_(0xF0000FF0) /**< (CMCC_MAINT1) Register Mask */ + + +/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ +#define CMCC_MCFG_RESETVALUE _U_(0x00) /**< (CMCC_MCFG) Cache Monitor Configuration Register Reset Value */ + +#define CMCC_MCFG_MODE_Pos _U_(0) /**< (CMCC_MCFG) Cache Controller Monitor Counter Mode Position */ +#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Cache Controller Monitor Counter Mode Mask */ +#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) +#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< (CMCC_MCFG) Cycle counter */ +#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< (CMCC_MCFG) Instruction hit counter */ +#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< (CMCC_MCFG) Data hit counter */ +#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Cycle counter Position */ +#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Instruction hit counter Position */ +#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Data hit counter Position */ +#define CMCC_MCFG_Msk _U_(0x00000003) /**< (CMCC_MCFG) Register Mask */ + + +/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ +#define CMCC_MEN_RESETVALUE _U_(0x00) /**< (CMCC_MEN) Cache Monitor Enable Register Reset Value */ + +#define CMCC_MEN_MENABLE_Pos _U_(0) /**< (CMCC_MEN) Cache Controller Monitor Enable Position */ +#define CMCC_MEN_MENABLE_Msk (_U_(0x1) << CMCC_MEN_MENABLE_Pos) /**< (CMCC_MEN) Cache Controller Monitor Enable Mask */ +#define CMCC_MEN_MENABLE(value) (CMCC_MEN_MENABLE_Msk & ((value) << CMCC_MEN_MENABLE_Pos)) +#define CMCC_MEN_Msk _U_(0x00000001) /**< (CMCC_MEN) Register Mask */ + + +/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ +#define CMCC_MCTRL_RESETVALUE _U_(0x00) /**< (CMCC_MCTRL) Cache Monitor Control Register Reset Value */ + +#define CMCC_MCTRL_SWRST_Pos _U_(0) /**< (CMCC_MCTRL) Cache Controller Software Reset Position */ +#define CMCC_MCTRL_SWRST_Msk (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) /**< (CMCC_MCTRL) Cache Controller Software Reset Mask */ +#define CMCC_MCTRL_SWRST(value) (CMCC_MCTRL_SWRST_Msk & ((value) << CMCC_MCTRL_SWRST_Pos)) +#define CMCC_MCTRL_Msk _U_(0x00000001) /**< (CMCC_MCTRL) Register Mask */ + + +/* -------- CMCC_MSR : (CMCC Offset: 0x34) ( R/ 32) Cache Monitor Status Register -------- */ +#define CMCC_MSR_RESETVALUE _U_(0x00) /**< (CMCC_MSR) Cache Monitor Status Register Reset Value */ + +#define CMCC_MSR_EVENT_CNT_Pos _U_(0) /**< (CMCC_MSR) Monitor Event Counter Position */ +#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) /**< (CMCC_MSR) Monitor Event Counter Mask */ +#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) +#define CMCC_MSR_Msk _U_(0xFFFFFFFF) /**< (CMCC_MSR) Register Mask */ + + +/** \brief CMCC register offsets definitions */ +#define CMCC_TYPE_REG_OFST (0x00) /**< (CMCC_TYPE) Cache Type Register Offset */ +#define CMCC_CFG_REG_OFST (0x04) /**< (CMCC_CFG) Cache Configuration Register Offset */ +#define CMCC_CTRL_REG_OFST (0x08) /**< (CMCC_CTRL) Cache Control Register Offset */ +#define CMCC_SR_REG_OFST (0x0C) /**< (CMCC_SR) Cache Status Register Offset */ +#define CMCC_LCKWAY_REG_OFST (0x10) /**< (CMCC_LCKWAY) Cache Lock per Way Register Offset */ +#define CMCC_MAINT0_REG_OFST (0x20) /**< (CMCC_MAINT0) Cache Maintenance Register 0 Offset */ +#define CMCC_MAINT1_REG_OFST (0x24) /**< (CMCC_MAINT1) Cache Maintenance Register 1 Offset */ +#define CMCC_MCFG_REG_OFST (0x28) /**< (CMCC_MCFG) Cache Monitor Configuration Register Offset */ +#define CMCC_MEN_REG_OFST (0x2C) /**< (CMCC_MEN) Cache Monitor Enable Register Offset */ +#define CMCC_MCTRL_REG_OFST (0x30) /**< (CMCC_MCTRL) Cache Monitor Control Register Offset */ +#define CMCC_MSR_REG_OFST (0x34) /**< (CMCC_MSR) Cache Monitor Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CMCC register API structure */ +typedef struct +{ /* Cortex M Cache Controller */ + __I uint32_t CMCC_TYPE; /**< Offset: 0x00 (R/ 32) Cache Type Register */ + __IO uint32_t CMCC_CFG; /**< Offset: 0x04 (R/W 32) Cache Configuration Register */ + __O uint32_t CMCC_CTRL; /**< Offset: 0x08 ( /W 32) Cache Control Register */ + __I uint32_t CMCC_SR; /**< Offset: 0x0C (R/ 32) Cache Status Register */ + __IO uint32_t CMCC_LCKWAY; /**< Offset: 0x10 (R/W 32) Cache Lock per Way Register */ + __I uint8_t Reserved1[0x0C]; + __O uint32_t CMCC_MAINT0; /**< Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ + __O uint32_t CMCC_MAINT1; /**< Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ + __IO uint32_t CMCC_MCFG; /**< Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ + __IO uint32_t CMCC_MEN; /**< Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ + __O uint32_t CMCC_MCTRL; /**< Offset: 0x30 ( /W 32) Cache Monitor Control Register */ + __I uint32_t CMCC_MSR; /**< Offset: 0x34 (R/ 32) Cache Monitor Status Register */ +} cmcc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_CMCC_COMPONENT_H_ */ diff --git a/arch/arm/SAME54/mcu/inc/component/dac.h b/arch/arm/SAME54/mcu/inc/component/dac.h new file mode 100644 index 00000000..3582ef5e --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/component/dac.h @@ -0,0 +1,439 @@ +/** + * \brief Component description for DAC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-12T17:27:04Z */ +#ifndef _SAME54_DAC_COMPONENT_H_ +#define _SAME54_DAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DAC */ +/* ************************************************************************** */ + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< (DAC_CTRLA) Control A Reset Value */ + +#define DAC_CTRLA_SWRST_Pos _U_(0) /**< (DAC_CTRLA) Software Reset Position */ +#define DAC_CTRLA_SWRST_Msk (_U_(0x1) << DAC_CTRLA_SWRST_Pos) /**< (DAC_CTRLA) Software Reset Mask */ +#define DAC_CTRLA_SWRST(value) (DAC_CTRLA_SWRST_Msk & ((value) << DAC_CTRLA_SWRST_Pos)) +#define DAC_CTRLA_ENABLE_Pos _U_(1) /**< (DAC_CTRLA) Enable DAC Controller Position */ +#define DAC_CTRLA_ENABLE_Msk (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) /**< (DAC_CTRLA) Enable DAC Controller Mask */ +#define DAC_CTRLA_ENABLE(value) (DAC_CTRLA_ENABLE_Msk & ((value) << DAC_CTRLA_ENABLE_Pos)) +#define DAC_CTRLA_Msk _U_(0x03) /**< (DAC_CTRLA) Register Mask */ + + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< (DAC_CTRLB) Control B Reset Value */ + +#define DAC_CTRLB_DIFF_Pos _U_(0) /**< (DAC_CTRLB) Differential mode enable Position */ +#define DAC_CTRLB_DIFF_Msk (_U_(0x1) << DAC_CTRLB_DIFF_Pos) /**< (DAC_CTRLB) Differential mode enable Mask */ +#define DAC_CTRLB_DIFF(value) (DAC_CTRLB_DIFF_Msk & ((value) << DAC_CTRLB_DIFF_Pos)) +#define DAC_CTRLB_REFSEL_Pos _U_(1) /**< (DAC_CTRLB) Reference Selection for DAC0/1 Position */ +#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Reference Selection for DAC0/1 Mask */ +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< (DAC_CTRLB) External reference unbuffered */ +#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< (DAC_CTRLB) Analog supply */ +#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< (DAC_CTRLB) External reference buffered */ +#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< (DAC_CTRLB) Internal bandgap reference */ +#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) External reference unbuffered Position */ +#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Analog supply Position */ +#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) External reference buffered Position */ +#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Internal bandgap reference Position */ +#define DAC_CTRLB_Msk _U_(0x07) /**< (DAC_CTRLB) Register Mask */ + + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< (DAC_EVCTRL) Event Control Reset Value */ + +#define DAC_EVCTRL_STARTEI0_Pos _U_(0) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 0 Position */ +#define DAC_EVCTRL_STARTEI0_Msk (_U_(0x1) << DAC_EVCTRL_STARTEI0_Pos) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 0 Mask */ +#define DAC_EVCTRL_STARTEI0(value) (DAC_EVCTRL_STARTEI0_Msk & ((value) << DAC_EVCTRL_STARTEI0_Pos)) +#define DAC_EVCTRL_STARTEI1_Pos _U_(1) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 1 Position */ +#define DAC_EVCTRL_STARTEI1_Msk (_U_(0x1) << DAC_EVCTRL_STARTEI1_Pos) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 1 Mask */ +#define DAC_EVCTRL_STARTEI1(value) (DAC_EVCTRL_STARTEI1_Msk & ((value) << DAC_EVCTRL_STARTEI1_Pos)) +#define DAC_EVCTRL_EMPTYEO0_Pos _U_(2) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Position */ +#define DAC_EVCTRL_EMPTYEO0_Msk (_U_(0x1) << DAC_EVCTRL_EMPTYEO0_Pos) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Mask */ +#define DAC_EVCTRL_EMPTYEO0(value) (DAC_EVCTRL_EMPTYEO0_Msk & ((value) << DAC_EVCTRL_EMPTYEO0_Pos)) +#define DAC_EVCTRL_EMPTYEO1_Pos _U_(3) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Position */ +#define DAC_EVCTRL_EMPTYEO1_Msk (_U_(0x1) << DAC_EVCTRL_EMPTYEO1_Pos) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Mask */ +#define DAC_EVCTRL_EMPTYEO1(value) (DAC_EVCTRL_EMPTYEO1_Msk & ((value) << DAC_EVCTRL_EMPTYEO1_Pos)) +#define DAC_EVCTRL_INVEI0_Pos _U_(4) /**< (DAC_EVCTRL) Enable Invertion of DAC 0 input event Position */ +#define DAC_EVCTRL_INVEI0_Msk (_U_(0x1) << DAC_EVCTRL_INVEI0_Pos) /**< (DAC_EVCTRL) Enable Invertion of DAC 0 input event Mask */ +#define DAC_EVCTRL_INVEI0(value) (DAC_EVCTRL_INVEI0_Msk & ((value) << DAC_EVCTRL_INVEI0_Pos)) +#define DAC_EVCTRL_INVEI1_Pos _U_(5) /**< (DAC_EVCTRL) Enable Invertion of DAC 1 input event Position */ +#define DAC_EVCTRL_INVEI1_Msk (_U_(0x1) << DAC_EVCTRL_INVEI1_Pos) /**< (DAC_EVCTRL) Enable Invertion of DAC 1 input event Mask */ +#define DAC_EVCTRL_INVEI1(value) (DAC_EVCTRL_INVEI1_Msk & ((value) << DAC_EVCTRL_INVEI1_Pos)) +#define DAC_EVCTRL_RESRDYEO0_Pos _U_(6) /**< (DAC_EVCTRL) Result Ready Event Output 0 Position */ +#define DAC_EVCTRL_RESRDYEO0_Msk (_U_(0x1) << DAC_EVCTRL_RESRDYEO0_Pos) /**< (DAC_EVCTRL) Result Ready Event Output 0 Mask */ +#define DAC_EVCTRL_RESRDYEO0(value) (DAC_EVCTRL_RESRDYEO0_Msk & ((value) << DAC_EVCTRL_RESRDYEO0_Pos)) +#define DAC_EVCTRL_RESRDYEO1_Pos _U_(7) /**< (DAC_EVCTRL) Result Ready Event Output 1 Position */ +#define DAC_EVCTRL_RESRDYEO1_Msk (_U_(0x1) << DAC_EVCTRL_RESRDYEO1_Pos) /**< (DAC_EVCTRL) Result Ready Event Output 1 Mask */ +#define DAC_EVCTRL_RESRDYEO1(value) (DAC_EVCTRL_RESRDYEO1_Msk & ((value) << DAC_EVCTRL_RESRDYEO1_Pos)) +#define DAC_EVCTRL_Msk _U_(0xFF) /**< (DAC_EVCTRL) Register Mask */ + +#define DAC_EVCTRL_STARTEI_Pos _U_(0) /**< (DAC_EVCTRL Position) Start Conversion Event Input DAC x */ +#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) /**< (DAC_EVCTRL Mask) STARTEI */ +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) +#define DAC_EVCTRL_EMPTYEO_Pos _U_(2) /**< (DAC_EVCTRL Position) Data Buffer Empty Event Output DAC x */ +#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) /**< (DAC_EVCTRL Mask) EMPTYEO */ +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) +#define DAC_EVCTRL_INVEI_Pos _U_(4) /**< (DAC_EVCTRL Position) Enable Invertion of DAC x input event */ +#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) /**< (DAC_EVCTRL Mask) INVEI */ +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) +#define DAC_EVCTRL_RESRDYEO_Pos _U_(6) /**< (DAC_EVCTRL Position) Result Ready Event Output x */ +#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) /**< (DAC_EVCTRL Mask) RESRDYEO */ +#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< (DAC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define DAC_INTENCLR_UNDERRUN0_Pos _U_(0) /**< (DAC_INTENCLR) Underrun 0 Interrupt Enable Position */ +#define DAC_INTENCLR_UNDERRUN0_Msk (_U_(0x1) << DAC_INTENCLR_UNDERRUN0_Pos) /**< (DAC_INTENCLR) Underrun 0 Interrupt Enable Mask */ +#define DAC_INTENCLR_UNDERRUN0(value) (DAC_INTENCLR_UNDERRUN0_Msk & ((value) << DAC_INTENCLR_UNDERRUN0_Pos)) +#define DAC_INTENCLR_UNDERRUN1_Pos _U_(1) /**< (DAC_INTENCLR) Underrun 1 Interrupt Enable Position */ +#define DAC_INTENCLR_UNDERRUN1_Msk (_U_(0x1) << DAC_INTENCLR_UNDERRUN1_Pos) /**< (DAC_INTENCLR) Underrun 1 Interrupt Enable Mask */ +#define DAC_INTENCLR_UNDERRUN1(value) (DAC_INTENCLR_UNDERRUN1_Msk & ((value) << DAC_INTENCLR_UNDERRUN1_Pos)) +#define DAC_INTENCLR_EMPTY0_Pos _U_(2) /**< (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Position */ +#define DAC_INTENCLR_EMPTY0_Msk (_U_(0x1) << DAC_INTENCLR_EMPTY0_Pos) /**< (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Mask */ +#define DAC_INTENCLR_EMPTY0(value) (DAC_INTENCLR_EMPTY0_Msk & ((value) << DAC_INTENCLR_EMPTY0_Pos)) +#define DAC_INTENCLR_EMPTY1_Pos _U_(3) /**< (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Position */ +#define DAC_INTENCLR_EMPTY1_Msk (_U_(0x1) << DAC_INTENCLR_EMPTY1_Pos) /**< (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Mask */ +#define DAC_INTENCLR_EMPTY1(value) (DAC_INTENCLR_EMPTY1_Msk & ((value) << DAC_INTENCLR_EMPTY1_Pos)) +#define DAC_INTENCLR_RESRDY0_Pos _U_(4) /**< (DAC_INTENCLR) Result 0 Ready Interrupt Enable Position */ +#define DAC_INTENCLR_RESRDY0_Msk (_U_(0x1) << DAC_INTENCLR_RESRDY0_Pos) /**< (DAC_INTENCLR) Result 0 Ready Interrupt Enable Mask */ +#define DAC_INTENCLR_RESRDY0(value) (DAC_INTENCLR_RESRDY0_Msk & ((value) << DAC_INTENCLR_RESRDY0_Pos)) +#define DAC_INTENCLR_RESRDY1_Pos _U_(5) /**< (DAC_INTENCLR) Result 1 Ready Interrupt Enable Position */ +#define DAC_INTENCLR_RESRDY1_Msk (_U_(0x1) << DAC_INTENCLR_RESRDY1_Pos) /**< (DAC_INTENCLR) Result 1 Ready Interrupt Enable Mask */ +#define DAC_INTENCLR_RESRDY1(value) (DAC_INTENCLR_RESRDY1_Msk & ((value) << DAC_INTENCLR_RESRDY1_Pos)) +#define DAC_INTENCLR_OVERRUN0_Pos _U_(6) /**< (DAC_INTENCLR) Overrun 0 Interrupt Enable Position */ +#define DAC_INTENCLR_OVERRUN0_Msk (_U_(0x1) << DAC_INTENCLR_OVERRUN0_Pos) /**< (DAC_INTENCLR) Overrun 0 Interrupt Enable Mask */ +#define DAC_INTENCLR_OVERRUN0(value) (DAC_INTENCLR_OVERRUN0_Msk & ((value) << DAC_INTENCLR_OVERRUN0_Pos)) +#define DAC_INTENCLR_OVERRUN1_Pos _U_(7) /**< (DAC_INTENCLR) Overrun 1 Interrupt Enable Position */ +#define DAC_INTENCLR_OVERRUN1_Msk (_U_(0x1) << DAC_INTENCLR_OVERRUN1_Pos) /**< (DAC_INTENCLR) Overrun 1 Interrupt Enable Mask */ +#define DAC_INTENCLR_OVERRUN1(value) (DAC_INTENCLR_OVERRUN1_Msk & ((value) << DAC_INTENCLR_OVERRUN1_Pos)) +#define DAC_INTENCLR_Msk _U_(0xFF) /**< (DAC_INTENCLR) Register Mask */ + +#define DAC_INTENCLR_UNDERRUN_Pos _U_(0) /**< (DAC_INTENCLR Position) Underrun x Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) /**< (DAC_INTENCLR Mask) UNDERRUN */ +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) +#define DAC_INTENCLR_EMPTY_Pos _U_(2) /**< (DAC_INTENCLR Position) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) /**< (DAC_INTENCLR Mask) EMPTY */ +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) +#define DAC_INTENCLR_RESRDY_Pos _U_(4) /**< (DAC_INTENCLR Position) Result x Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) /**< (DAC_INTENCLR Mask) RESRDY */ +#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) +#define DAC_INTENCLR_OVERRUN_Pos _U_(6) /**< (DAC_INTENCLR Position) Overrun x Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) /**< (DAC_INTENCLR Mask) OVERRUN */ +#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< (DAC_INTENSET) Interrupt Enable Set Reset Value */ + +#define DAC_INTENSET_UNDERRUN0_Pos _U_(0) /**< (DAC_INTENSET) Underrun 0 Interrupt Enable Position */ +#define DAC_INTENSET_UNDERRUN0_Msk (_U_(0x1) << DAC_INTENSET_UNDERRUN0_Pos) /**< (DAC_INTENSET) Underrun 0 Interrupt Enable Mask */ +#define DAC_INTENSET_UNDERRUN0(value) (DAC_INTENSET_UNDERRUN0_Msk & ((value) << DAC_INTENSET_UNDERRUN0_Pos)) +#define DAC_INTENSET_UNDERRUN1_Pos _U_(1) /**< (DAC_INTENSET) Underrun 1 Interrupt Enable Position */ +#define DAC_INTENSET_UNDERRUN1_Msk (_U_(0x1) << DAC_INTENSET_UNDERRUN1_Pos) /**< (DAC_INTENSET) Underrun 1 Interrupt Enable Mask */ +#define DAC_INTENSET_UNDERRUN1(value) (DAC_INTENSET_UNDERRUN1_Msk & ((value) << DAC_INTENSET_UNDERRUN1_Pos)) +#define DAC_INTENSET_EMPTY0_Pos _U_(2) /**< (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Position */ +#define DAC_INTENSET_EMPTY0_Msk (_U_(0x1) << DAC_INTENSET_EMPTY0_Pos) /**< (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Mask */ +#define DAC_INTENSET_EMPTY0(value) (DAC_INTENSET_EMPTY0_Msk & ((value) << DAC_INTENSET_EMPTY0_Pos)) +#define DAC_INTENSET_EMPTY1_Pos _U_(3) /**< (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Position */ +#define DAC_INTENSET_EMPTY1_Msk (_U_(0x1) << DAC_INTENSET_EMPTY1_Pos) /**< (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Mask */ +#define DAC_INTENSET_EMPTY1(value) (DAC_INTENSET_EMPTY1_Msk & ((value) << DAC_INTENSET_EMPTY1_Pos)) +#define DAC_INTENSET_RESRDY0_Pos _U_(4) /**< (DAC_INTENSET) Result 0 Ready Interrupt Enable Position */ +#define DAC_INTENSET_RESRDY0_Msk (_U_(0x1) << DAC_INTENSET_RESRDY0_Pos) /**< (DAC_INTENSET) Result 0 Ready Interrupt Enable Mask */ +#define DAC_INTENSET_RESRDY0(value) (DAC_INTENSET_RESRDY0_Msk & ((value) << DAC_INTENSET_RESRDY0_Pos)) +#define DAC_INTENSET_RESRDY1_Pos _U_(5) /**< (DAC_INTENSET) Result 1 Ready Interrupt Enable Position */ +#define DAC_INTENSET_RESRDY1_Msk (_U_(0x1) << DAC_INTENSET_RESRDY1_Pos) /**< (DAC_INTENSET) Result 1 Ready Interrupt Enable Mask */ +#define DAC_INTENSET_RESRDY1(value) (DAC_INTENSET_RESRDY1_Msk & ((value) << DAC_INTENSET_RESRDY1_Pos)) +#define DAC_INTENSET_OVERRUN0_Pos _U_(6) /**< (DAC_INTENSET) Overrun 0 Interrupt Enable Position */ +#define DAC_INTENSET_OVERRUN0_Msk (_U_(0x1) << DAC_INTENSET_OVERRUN0_Pos) /**< (DAC_INTENSET) Overrun 0 Interrupt Enable Mask */ +#define DAC_INTENSET_OVERRUN0(value) (DAC_INTENSET_OVERRUN0_Msk & ((value) << DAC_INTENSET_OVERRUN0_Pos)) +#define DAC_INTENSET_OVERRUN1_Pos _U_(7) /**< (DAC_INTENSET) Overrun 1 Interrupt Enable Position */ +#define DAC_INTENSET_OVERRUN1_Msk (_U_(0x1) << DAC_INTENSET_OVERRUN1_Pos) /**< (DAC_INTENSET) Overrun 1 Interrupt Enable Mask */ +#define DAC_INTENSET_OVERRUN1(value) (DAC_INTENSET_OVERRUN1_Msk & ((value) << DAC_INTENSET_OVERRUN1_Pos)) +#define DAC_INTENSET_Msk _U_(0xFF) /**< (DAC_INTENSET) Register Mask */ + +#define DAC_INTENSET_UNDERRUN_Pos _U_(0) /**< (DAC_INTENSET Position) Underrun x Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) /**< (DAC_INTENSET Mask) UNDERRUN */ +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) +#define DAC_INTENSET_EMPTY_Pos _U_(2) /**< (DAC_INTENSET Position) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) /**< (DAC_INTENSET Mask) EMPTY */ +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) +#define DAC_INTENSET_RESRDY_Pos _U_(4) /**< (DAC_INTENSET Position) Result x Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) /**< (DAC_INTENSET Mask) RESRDY */ +#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) +#define DAC_INTENSET_OVERRUN_Pos _U_(6) /**< (DAC_INTENSET Position) Overrun x Interrupt Enable */ +#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) /**< (DAC_INTENSET Mask) OVERRUN */ +#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< (DAC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define DAC_INTFLAG_UNDERRUN0_Pos _U_(0) /**< (DAC_INTFLAG) Result 0 Underrun Position */ +#define DAC_INTFLAG_UNDERRUN0_Msk (_U_(0x1) << DAC_INTFLAG_UNDERRUN0_Pos) /**< (DAC_INTFLAG) Result 0 Underrun Mask */ +#define DAC_INTFLAG_UNDERRUN0(value) (DAC_INTFLAG_UNDERRUN0_Msk & ((value) << DAC_INTFLAG_UNDERRUN0_Pos)) +#define DAC_INTFLAG_UNDERRUN1_Pos _U_(1) /**< (DAC_INTFLAG) Result 1 Underrun Position */ +#define DAC_INTFLAG_UNDERRUN1_Msk (_U_(0x1) << DAC_INTFLAG_UNDERRUN1_Pos) /**< (DAC_INTFLAG) Result 1 Underrun Mask */ +#define DAC_INTFLAG_UNDERRUN1(value) (DAC_INTFLAG_UNDERRUN1_Msk & ((value) << DAC_INTFLAG_UNDERRUN1_Pos)) +#define DAC_INTFLAG_EMPTY0_Pos _U_(2) /**< (DAC_INTFLAG) Data Buffer 0 Empty Position */ +#define DAC_INTFLAG_EMPTY0_Msk (_U_(0x1) << DAC_INTFLAG_EMPTY0_Pos) /**< (DAC_INTFLAG) Data Buffer 0 Empty Mask */ +#define DAC_INTFLAG_EMPTY0(value) (DAC_INTFLAG_EMPTY0_Msk & ((value) << DAC_INTFLAG_EMPTY0_Pos)) +#define DAC_INTFLAG_EMPTY1_Pos _U_(3) /**< (DAC_INTFLAG) Data Buffer 1 Empty Position */ +#define DAC_INTFLAG_EMPTY1_Msk (_U_(0x1) << DAC_INTFLAG_EMPTY1_Pos) /**< (DAC_INTFLAG) Data Buffer 1 Empty Mask */ +#define DAC_INTFLAG_EMPTY1(value) (DAC_INTFLAG_EMPTY1_Msk & ((value) << DAC_INTFLAG_EMPTY1_Pos)) +#define DAC_INTFLAG_RESRDY0_Pos _U_(4) /**< (DAC_INTFLAG) Result 0 Ready Position */ +#define DAC_INTFLAG_RESRDY0_Msk (_U_(0x1) << DAC_INTFLAG_RESRDY0_Pos) /**< (DAC_INTFLAG) Result 0 Ready Mask */ +#define DAC_INTFLAG_RESRDY0(value) (DAC_INTFLAG_RESRDY0_Msk & ((value) << DAC_INTFLAG_RESRDY0_Pos)) +#define DAC_INTFLAG_RESRDY1_Pos _U_(5) /**< (DAC_INTFLAG) Result 1 Ready Position */ +#define DAC_INTFLAG_RESRDY1_Msk (_U_(0x1) << DAC_INTFLAG_RESRDY1_Pos) /**< (DAC_INTFLAG) Result 1 Ready Mask */ +#define DAC_INTFLAG_RESRDY1(value) (DAC_INTFLAG_RESRDY1_Msk & ((value) << DAC_INTFLAG_RESRDY1_Pos)) +#define DAC_INTFLAG_OVERRUN0_Pos _U_(6) /**< (DAC_INTFLAG) Result 0 Overrun Position */ +#define DAC_INTFLAG_OVERRUN0_Msk (_U_(0x1) << DAC_INTFLAG_OVERRUN0_Pos) /**< (DAC_INTFLAG) Result 0 Overrun Mask */ +#define DAC_INTFLAG_OVERRUN0(value) (DAC_INTFLAG_OVERRUN0_Msk & ((value) << DAC_INTFLAG_OVERRUN0_Pos)) +#define DAC_INTFLAG_OVERRUN1_Pos _U_(7) /**< (DAC_INTFLAG) Result 1 Overrun Position */ +#define DAC_INTFLAG_OVERRUN1_Msk (_U_(0x1) << DAC_INTFLAG_OVERRUN1_Pos) /**< (DAC_INTFLAG) Result 1 Overrun Mask */ +#define DAC_INTFLAG_OVERRUN1(value) (DAC_INTFLAG_OVERRUN1_Msk & ((value) << DAC_INTFLAG_OVERRUN1_Pos)) +#define DAC_INTFLAG_Msk _U_(0xFF) /**< (DAC_INTFLAG) Register Mask */ + +#define DAC_INTFLAG_UNDERRUN_Pos _U_(0) /**< (DAC_INTFLAG Position) Result x Underrun */ +#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) /**< (DAC_INTFLAG Mask) UNDERRUN */ +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) +#define DAC_INTFLAG_EMPTY_Pos _U_(2) /**< (DAC_INTFLAG Position) Data Buffer x Empty */ +#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) /**< (DAC_INTFLAG Mask) EMPTY */ +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) +#define DAC_INTFLAG_RESRDY_Pos _U_(4) /**< (DAC_INTFLAG Position) Result x Ready */ +#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) /**< (DAC_INTFLAG Mask) RESRDY */ +#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) +#define DAC_INTFLAG_OVERRUN_Pos _U_(6) /**< (DAC_INTFLAG Position) Result x Overrun */ +#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) /**< (DAC_INTFLAG Mask) OVERRUN */ +#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) + +/* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */ +#define DAC_STATUS_RESETVALUE _U_(0x00) /**< (DAC_STATUS) Status Reset Value */ + +#define DAC_STATUS_READY0_Pos _U_(0) /**< (DAC_STATUS) DAC 0 Startup Ready Position */ +#define DAC_STATUS_READY0_Msk (_U_(0x1) << DAC_STATUS_READY0_Pos) /**< (DAC_STATUS) DAC 0 Startup Ready Mask */ +#define DAC_STATUS_READY0(value) (DAC_STATUS_READY0_Msk & ((value) << DAC_STATUS_READY0_Pos)) +#define DAC_STATUS_READY1_Pos _U_(1) /**< (DAC_STATUS) DAC 1 Startup Ready Position */ +#define DAC_STATUS_READY1_Msk (_U_(0x1) << DAC_STATUS_READY1_Pos) /**< (DAC_STATUS) DAC 1 Startup Ready Mask */ +#define DAC_STATUS_READY1(value) (DAC_STATUS_READY1_Msk & ((value) << DAC_STATUS_READY1_Pos)) +#define DAC_STATUS_EOC0_Pos _U_(2) /**< (DAC_STATUS) DAC 0 End of Conversion Position */ +#define DAC_STATUS_EOC0_Msk (_U_(0x1) << DAC_STATUS_EOC0_Pos) /**< (DAC_STATUS) DAC 0 End of Conversion Mask */ +#define DAC_STATUS_EOC0(value) (DAC_STATUS_EOC0_Msk & ((value) << DAC_STATUS_EOC0_Pos)) +#define DAC_STATUS_EOC1_Pos _U_(3) /**< (DAC_STATUS) DAC 1 End of Conversion Position */ +#define DAC_STATUS_EOC1_Msk (_U_(0x1) << DAC_STATUS_EOC1_Pos) /**< (DAC_STATUS) DAC 1 End of Conversion Mask */ +#define DAC_STATUS_EOC1(value) (DAC_STATUS_EOC1_Msk & ((value) << DAC_STATUS_EOC1_Pos)) +#define DAC_STATUS_Msk _U_(0x0F) /**< (DAC_STATUS) Register Mask */ + +#define DAC_STATUS_READY_Pos _U_(0) /**< (DAC_STATUS Position) DAC x Startup Ready */ +#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) /**< (DAC_STATUS Mask) READY */ +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) +#define DAC_STATUS_EOC_Pos _U_(2) /**< (DAC_STATUS Position) DAC x End of Conversion */ +#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) /**< (DAC_STATUS Mask) EOC */ +#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) ( R/ 32) Synchronization Busy -------- */ +#define DAC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (DAC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define DAC_SYNCBUSY_SWRST_Pos _U_(0) /**< (DAC_SYNCBUSY) Software Reset Position */ +#define DAC_SYNCBUSY_SWRST_Msk (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) /**< (DAC_SYNCBUSY) Software Reset Mask */ +#define DAC_SYNCBUSY_SWRST(value) (DAC_SYNCBUSY_SWRST_Msk & ((value) << DAC_SYNCBUSY_SWRST_Pos)) +#define DAC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (DAC_SYNCBUSY) DAC Enable Status Position */ +#define DAC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) /**< (DAC_SYNCBUSY) DAC Enable Status Mask */ +#define DAC_SYNCBUSY_ENABLE(value) (DAC_SYNCBUSY_ENABLE_Msk & ((value) << DAC_SYNCBUSY_ENABLE_Pos)) +#define DAC_SYNCBUSY_DATA0_Pos _U_(2) /**< (DAC_SYNCBUSY) Data DAC 0 Position */ +#define DAC_SYNCBUSY_DATA0_Msk (_U_(0x1) << DAC_SYNCBUSY_DATA0_Pos) /**< (DAC_SYNCBUSY) Data DAC 0 Mask */ +#define DAC_SYNCBUSY_DATA0(value) (DAC_SYNCBUSY_DATA0_Msk & ((value) << DAC_SYNCBUSY_DATA0_Pos)) +#define DAC_SYNCBUSY_DATA1_Pos _U_(3) /**< (DAC_SYNCBUSY) Data DAC 1 Position */ +#define DAC_SYNCBUSY_DATA1_Msk (_U_(0x1) << DAC_SYNCBUSY_DATA1_Pos) /**< (DAC_SYNCBUSY) Data DAC 1 Mask */ +#define DAC_SYNCBUSY_DATA1(value) (DAC_SYNCBUSY_DATA1_Msk & ((value) << DAC_SYNCBUSY_DATA1_Pos)) +#define DAC_SYNCBUSY_DATABUF0_Pos _U_(4) /**< (DAC_SYNCBUSY) Data Buffer DAC 0 Position */ +#define DAC_SYNCBUSY_DATABUF0_Msk (_U_(0x1) << DAC_SYNCBUSY_DATABUF0_Pos) /**< (DAC_SYNCBUSY) Data Buffer DAC 0 Mask */ +#define DAC_SYNCBUSY_DATABUF0(value) (DAC_SYNCBUSY_DATABUF0_Msk & ((value) << DAC_SYNCBUSY_DATABUF0_Pos)) +#define DAC_SYNCBUSY_DATABUF1_Pos _U_(5) /**< (DAC_SYNCBUSY) Data Buffer DAC 1 Position */ +#define DAC_SYNCBUSY_DATABUF1_Msk (_U_(0x1) << DAC_SYNCBUSY_DATABUF1_Pos) /**< (DAC_SYNCBUSY) Data Buffer DAC 1 Mask */ +#define DAC_SYNCBUSY_DATABUF1(value) (DAC_SYNCBUSY_DATABUF1_Msk & ((value) << DAC_SYNCBUSY_DATABUF1_Pos)) +#define DAC_SYNCBUSY_Msk _U_(0x0000003F) /**< (DAC_SYNCBUSY) Register Mask */ + +#define DAC_SYNCBUSY_DATA_Pos _U_(2) /**< (DAC_SYNCBUSY Position) Data DAC x */ +#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) /**< (DAC_SYNCBUSY Mask) DATA */ +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) +#define DAC_SYNCBUSY_DATABUF_Pos _U_(4) /**< (DAC_SYNCBUSY Position) Data Buffer DAC x */ +#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) /**< (DAC_SYNCBUSY Mask) DATABUF */ +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) + +/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ +#define DAC_DACCTRL_RESETVALUE _U_(0x00) /**< (DAC_DACCTRL) DAC n Control Reset Value */ + +#define DAC_DACCTRL_LEFTADJ_Pos _U_(0) /**< (DAC_DACCTRL) Left Adjusted Data Position */ +#define DAC_DACCTRL_LEFTADJ_Msk (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) /**< (DAC_DACCTRL) Left Adjusted Data Mask */ +#define DAC_DACCTRL_LEFTADJ(value) (DAC_DACCTRL_LEFTADJ_Msk & ((value) << DAC_DACCTRL_LEFTADJ_Pos)) +#define DAC_DACCTRL_ENABLE_Pos _U_(1) /**< (DAC_DACCTRL) Enable DAC0 Position */ +#define DAC_DACCTRL_ENABLE_Msk (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) /**< (DAC_DACCTRL) Enable DAC0 Mask */ +#define DAC_DACCTRL_ENABLE(value) (DAC_DACCTRL_ENABLE_Msk & ((value) << DAC_DACCTRL_ENABLE_Pos)) +#define DAC_DACCTRL_CCTRL_Pos _U_(2) /**< (DAC_DACCTRL) Current Control Position */ +#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) Current Control Mask */ +#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) +#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< (DAC_DACCTRL) 100kSPS */ +#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< (DAC_DACCTRL) 500kSPS */ +#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< (DAC_DACCTRL) 1MSPS */ +#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 100kSPS Position */ +#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 500kSPS Position */ +#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 1MSPS Position */ +#define DAC_DACCTRL_FEXT_Pos _U_(5) /**< (DAC_DACCTRL) Standalone Filter Position */ +#define DAC_DACCTRL_FEXT_Msk (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) /**< (DAC_DACCTRL) Standalone Filter Mask */ +#define DAC_DACCTRL_FEXT(value) (DAC_DACCTRL_FEXT_Msk & ((value) << DAC_DACCTRL_FEXT_Pos)) +#define DAC_DACCTRL_RUNSTDBY_Pos _U_(6) /**< (DAC_DACCTRL) Run in Standby Position */ +#define DAC_DACCTRL_RUNSTDBY_Msk (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) /**< (DAC_DACCTRL) Run in Standby Mask */ +#define DAC_DACCTRL_RUNSTDBY(value) (DAC_DACCTRL_RUNSTDBY_Msk & ((value) << DAC_DACCTRL_RUNSTDBY_Pos)) +#define DAC_DACCTRL_DITHER_Pos _U_(7) /**< (DAC_DACCTRL) Dithering Mode Position */ +#define DAC_DACCTRL_DITHER_Msk (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) /**< (DAC_DACCTRL) Dithering Mode Mask */ +#define DAC_DACCTRL_DITHER(value) (DAC_DACCTRL_DITHER_Msk & ((value) << DAC_DACCTRL_DITHER_Pos)) +#define DAC_DACCTRL_REFRESH_Pos _U_(8) /**< (DAC_DACCTRL) Refresh period Position */ +#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh period Mask */ +#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) +#define DAC_DACCTRL_REFRESH_REFRESH_0_Val _U_(0x0) /**< (DAC_DACCTRL) Do not Refresh */ +#define DAC_DACCTRL_REFRESH_REFRESH_1_Val _U_(0x1) /**< (DAC_DACCTRL) Refresh every 30 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_2_Val _U_(0x2) /**< (DAC_DACCTRL) Refresh every 60 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_3_Val _U_(0x3) /**< (DAC_DACCTRL) Refresh every 90 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_4_Val _U_(0x4) /**< (DAC_DACCTRL) Refresh every 120 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_5_Val _U_(0x5) /**< (DAC_DACCTRL) Refresh every 150 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_6_Val _U_(0x6) /**< (DAC_DACCTRL) Refresh every 180 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_7_Val _U_(0x7) /**< (DAC_DACCTRL) Refresh every 210 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_8_Val _U_(0x8) /**< (DAC_DACCTRL) Refresh every 240 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_9_Val _U_(0x9) /**< (DAC_DACCTRL) Refresh every 270 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_10_Val _U_(0xA) /**< (DAC_DACCTRL) Refresh every 300 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_11_Val _U_(0xB) /**< (DAC_DACCTRL) Refresh every 330 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_12_Val _U_(0xC) /**< (DAC_DACCTRL) Refresh every 360 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_13_Val _U_(0xD) /**< (DAC_DACCTRL) Refresh every 390 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_14_Val _U_(0xE) /**< (DAC_DACCTRL) Refresh every 420 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_15_Val _U_(0xF) /**< (DAC_DACCTRL) Refresh every 450 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_0 (DAC_DACCTRL_REFRESH_REFRESH_0_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Do not Refresh Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_1 (DAC_DACCTRL_REFRESH_REFRESH_1_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 30 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_2 (DAC_DACCTRL_REFRESH_REFRESH_2_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 60 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_3 (DAC_DACCTRL_REFRESH_REFRESH_3_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 90 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_4 (DAC_DACCTRL_REFRESH_REFRESH_4_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 120 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_5 (DAC_DACCTRL_REFRESH_REFRESH_5_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 150 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_6 (DAC_DACCTRL_REFRESH_REFRESH_6_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 180 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_7 (DAC_DACCTRL_REFRESH_REFRESH_7_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 210 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_8 (DAC_DACCTRL_REFRESH_REFRESH_8_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 240 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_9 (DAC_DACCTRL_REFRESH_REFRESH_9_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 270 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_10 (DAC_DACCTRL_REFRESH_REFRESH_10_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 300 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_11 (DAC_DACCTRL_REFRESH_REFRESH_11_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 330 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_12 (DAC_DACCTRL_REFRESH_REFRESH_12_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 360 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_13 (DAC_DACCTRL_REFRESH_REFRESH_13_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 390 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_14 (DAC_DACCTRL_REFRESH_REFRESH_14_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 420 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_15 (DAC_DACCTRL_REFRESH_REFRESH_15_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 450 us Position */ +#define DAC_DACCTRL_OSR_Pos _U_(13) /**< (DAC_DACCTRL) Sampling Rate Position */ +#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) Sampling Rate Mask */ +#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) +#define DAC_DACCTRL_OSR_OSR_1_Val _U_(0x0) /**< (DAC_DACCTRL) No Over Sampling */ +#define DAC_DACCTRL_OSR_OSR_2_Val _U_(0x1) /**< (DAC_DACCTRL) 2x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_4_Val _U_(0x2) /**< (DAC_DACCTRL) 4x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_8_Val _U_(0x3) /**< (DAC_DACCTRL) 8x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_16_Val _U_(0x4) /**< (DAC_DACCTRL) 16x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_32_Val _U_(0x5) /**< (DAC_DACCTRL) 32x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_1 (DAC_DACCTRL_OSR_OSR_1_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) No Over Sampling Position */ +#define DAC_DACCTRL_OSR_OSR_2 (DAC_DACCTRL_OSR_OSR_2_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 2x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_4 (DAC_DACCTRL_OSR_OSR_4_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 4x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_8 (DAC_DACCTRL_OSR_OSR_8_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 8x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_16 (DAC_DACCTRL_OSR_OSR_16_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 16x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_32 (DAC_DACCTRL_OSR_OSR_32_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 32x Over Sampling Ratio Position */ +#define DAC_DACCTRL_Msk _U_(0xEFEF) /**< (DAC_DACCTRL) Register Mask */ + + +/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ +#define DAC_DATA_RESETVALUE _U_(0x00) /**< (DAC_DATA) DAC n Data Reset Value */ + +#define DAC_DATA_DATA_Pos _U_(0) /**< (DAC_DATA) DAC0 Data Position */ +#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) /**< (DAC_DATA) DAC0 Data Mask */ +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_Msk _U_(0xFFFF) /**< (DAC_DATA) Register Mask */ + + +/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ +#define DAC_DATABUF_RESETVALUE _U_(0x00) /**< (DAC_DATABUF) DAC n Data Buffer Reset Value */ + +#define DAC_DATABUF_DATABUF_Pos _U_(0) /**< (DAC_DATABUF) DAC0 Data Buffer Position */ +#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) /**< (DAC_DATABUF) DAC0 Data Buffer Mask */ +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_Msk _U_(0xFFFF) /**< (DAC_DATABUF) Register Mask */ + + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ +#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< (DAC_DBGCTRL) Debug Control Reset Value */ + +#define DAC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (DAC_DBGCTRL) Debug Run Position */ +#define DAC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) /**< (DAC_DBGCTRL) Debug Run Mask */ +#define DAC_DBGCTRL_DBGRUN(value) (DAC_DBGCTRL_DBGRUN_Msk & ((value) << DAC_DBGCTRL_DBGRUN_Pos)) +#define DAC_DBGCTRL_Msk _U_(0x01) /**< (DAC_DBGCTRL) Register Mask */ + + +/* -------- DAC_RESULT : (DAC Offset: 0x1C) ( R/ 16) Filter Result -------- */ +#define DAC_RESULT_RESETVALUE _U_(0x00) /**< (DAC_RESULT) Filter Result Reset Value */ + +#define DAC_RESULT_RESULT_Pos _U_(0) /**< (DAC_RESULT) Filter Result Position */ +#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) /**< (DAC_RESULT) Filter Result Mask */ +#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) +#define DAC_RESULT_Msk _U_(0xFFFF) /**< (DAC_RESULT) Register Mask */ + + +/** \brief DAC register offsets definitions */ +#define DAC_CTRLA_REG_OFST (0x00) /**< (DAC_CTRLA) Control A Offset */ +#define DAC_CTRLB_REG_OFST (0x01) /**< (DAC_CTRLB) Control B Offset */ +#define DAC_EVCTRL_REG_OFST (0x02) /**< (DAC_EVCTRL) Event Control Offset */ +#define DAC_INTENCLR_REG_OFST (0x04) /**< (DAC_INTENCLR) Interrupt Enable Clear Offset */ +#define DAC_INTENSET_REG_OFST (0x05) /**< (DAC_INTENSET) Interrupt Enable Set Offset */ +#define DAC_INTFLAG_REG_OFST (0x06) /**< (DAC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define DAC_STATUS_REG_OFST (0x07) /**< (DAC_STATUS) Status Offset */ +#define DAC_SYNCBUSY_REG_OFST (0x08) /**< (DAC_SYNCBUSY) Synchronization Busy Offset */ +#define DAC_DACCTRL_REG_OFST (0x0C) /**< (DAC_DACCTRL) DAC n Control Offset */ +#define DAC_DATA_REG_OFST (0x10) /**< (DAC_DATA) DAC n Data Offset */ +#define DAC_DATABUF_REG_OFST (0x14) /**< (DAC_DATABUF) DAC n Data Buffer Offset */ +#define DAC_DBGCTRL_REG_OFST (0x18) /**< (DAC_DBGCTRL) Debug Control Offset */ +#define DAC_RESULT_REG_OFST (0x1C) /**< (DAC_RESULT) Filter Result Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DAC register API structure */ +typedef struct +{ /* Digital-to-Analog Converter */ + __IO uint8_t DAC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __IO uint8_t DAC_CTRLB; /**< Offset: 0x01 (R/W 8) Control B */ + __IO uint8_t DAC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t DAC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t DAC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t DAC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t DAC_STATUS; /**< Offset: 0x07 (R/ 8) Status */ + __I uint32_t DAC_SYNCBUSY; /**< Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO uint16_t DAC_DACCTRL[2]; /**< Offset: 0x0C (R/W 16) DAC n Control */ + __O uint16_t DAC_DATA[2]; /**< Offset: 0x10 ( /W 16) DAC n Data */ + __O uint16_t DAC_DATABUF[2]; /**< Offset: 0x14 ( /W 16) DAC n Data Buffer */ + __IO uint8_t DAC_DBGCTRL; /**< Offset: 0x18 (R/W 8) Debug Control */ + __I uint8_t Reserved2[0x03]; + __I uint16_t DAC_RESULT[2]; /**< Offset: 0x1C (R/ 16) Filter Result */ +} dac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_DAC_COMPONENT_H_ */ diff --git a/arch/arm/SAME54/mcu/inc/component/dmac.h b/arch/arm/SAME54/mcu/inc/component/dmac.h new file mode 100644 index 00000000..e4486c99 --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/component/dmac.h @@ -0,0 +1,1125 @@ +/** + * \brief Component description for DMAC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-12T17:27:04Z */ +#ifndef _SAME54_DMAC_COMPONENT_H_ +#define _SAME54_DMAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DMAC */ +/* ************************************************************************** */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#define DMAC_BTCTRL_RESETVALUE _U_(0x00) /**< (DMAC_BTCTRL) Block Transfer Control Reset Value */ + +#define DMAC_BTCTRL_VALID_Pos _U_(0) /**< (DMAC_BTCTRL) Descriptor Valid Position */ +#define DMAC_BTCTRL_VALID_Msk (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) /**< (DMAC_BTCTRL) Descriptor Valid Mask */ +#define DMAC_BTCTRL_VALID(value) (DMAC_BTCTRL_VALID_Msk & ((value) << DMAC_BTCTRL_VALID_Pos)) +#define DMAC_BTCTRL_EVOSEL_Pos _U_(1) /**< (DMAC_BTCTRL) Block Event Output Selection Position */ +#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Block Event Output Selection Mask */ +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< (DMAC_BTCTRL) Block event strobe */ +#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< (DMAC_BTCTRL) Burst event strobe */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Event generation disabled Position */ +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Block event strobe Position */ +#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Burst event strobe Position */ +#define DMAC_BTCTRL_BLOCKACT_Pos _U_(3) /**< (DMAC_BTCTRL) Block Action Position */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Block Action Mask */ +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction Position */ +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt Position */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Channel suspend operation is completed Position */ +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Both channel suspend operation and block interrupt Position */ +#define DMAC_BTCTRL_BEATSIZE_Pos _U_(8) /**< (DMAC_BTCTRL) Beat Size Position */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) Beat Size Mask */ +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 8-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 16-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 32-bit bus transfer Position */ +#define DMAC_BTCTRL_SRCINC_Pos _U_(10) /**< (DMAC_BTCTRL) Source Address Increment Enable Position */ +#define DMAC_BTCTRL_SRCINC_Msk (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) /**< (DMAC_BTCTRL) Source Address Increment Enable Mask */ +#define DMAC_BTCTRL_SRCINC(value) (DMAC_BTCTRL_SRCINC_Msk & ((value) << DMAC_BTCTRL_SRCINC_Pos)) +#define DMAC_BTCTRL_DSTINC_Pos _U_(11) /**< (DMAC_BTCTRL) Destination Address Increment Enable Position */ +#define DMAC_BTCTRL_DSTINC_Msk (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) /**< (DMAC_BTCTRL) Destination Address Increment Enable Mask */ +#define DMAC_BTCTRL_DSTINC(value) (DMAC_BTCTRL_DSTINC_Msk & ((value) << DMAC_BTCTRL_DSTINC_Pos)) +#define DMAC_BTCTRL_STEPSEL_Pos _U_(12) /**< (DMAC_BTCTRL) Step Selection Position */ +#define DMAC_BTCTRL_STEPSEL_Msk (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step Selection Mask */ +#define DMAC_BTCTRL_STEPSEL(value) (DMAC_BTCTRL_STEPSEL_Msk & ((value) << DMAC_BTCTRL_STEPSEL_Pos)) +#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step size settings apply to the destination address Position */ +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step size settings apply to the source address Position */ +#define DMAC_BTCTRL_STEPSIZE_Pos _U_(13) /**< (DMAC_BTCTRL) Address Increment Step Size Position */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Address Increment Step Size Mask */ +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) +#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< (DMAC_BTCTRL) Next ADDR = ADDR + (1< +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME54N19A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ + CAN0_IRQn = 78, /**< 78 Control Area Network (CAN0) */ + CAN1_IRQn = 79, /**< 79 Control Area Network (CAN1) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + GMAC_IRQn = 84, /**< 84 Ethernet MAC (GMAC) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ + void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF*/ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility*/ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility*/ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility*/ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility*/ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* + * \brief Configuration of the CORTEX-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_same54.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME54N19A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N19A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME54N19A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_CAN0 ( 64) /**< \brief Control Area Network (CAN0) */ +#define ID_CAN1 ( 65) /**< \brief Control Area Network (CAN1) */ +#define ID_GMAC ( 66) /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ +#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ +#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ +#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ +#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ +#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ +#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME54N19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42000000) /**< \brief CAN0 Registers Address */ +#define CAN1_REGS ((can_registers_t*)0x42000400) /**< \brief CAN1 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x42000800) /**< \brief GMAC Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME54N19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CAN0_BASE_ADDRESS _UL_(0x42000000) /**< \brief CAN0 Base Address */ +#define CAN1_BASE_ADDRESS _UL_(0x42000400) /**< \brief CAN1 Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x42000800) /**< \brief GMAC Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ +#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ +#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ +#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME54N19A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#include "pio/same54n19a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 1024) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00030000) /* 192kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME54N19A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X61840303) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAME54N19A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /**< ID for GMAC event generator TSU_CMP */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAME54N19A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME54N19A definitions */ + + +#endif /* _SAME54N19A_H_ */ + diff --git a/arch/arm/SAME54/mcu/inc/same54n20a.h b/arch/arm/SAME54/mcu/inc/same54n20a.h new file mode 100644 index 00000000..2842aba2 --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/same54n20a.h @@ -0,0 +1,1113 @@ +/** + * \brief Header file for ATSAME54N20A + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-12T17:26:59Z */ +#ifndef _SAME54N20A_H_ +#define _SAME54N20A_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME54N20A_definitions SAME54N20A definitions + This file defines all structures and symbols for SAME54N20A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME54N20A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ + CAN0_IRQn = 78, /**< 78 Control Area Network (CAN0) */ + CAN1_IRQn = 79, /**< 79 Control Area Network (CAN1) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + GMAC_IRQn = 84, /**< 84 Ethernet MAC (GMAC) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ + void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF*/ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility*/ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility*/ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility*/ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility*/ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* + * \brief Configuration of the CORTEX-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_same54.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME54N20A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N20A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME54N20A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_CAN0 ( 64) /**< \brief Control Area Network (CAN0) */ +#define ID_CAN1 ( 65) /**< \brief Control Area Network (CAN1) */ +#define ID_GMAC ( 66) /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ +#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ +#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ +#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ +#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ +#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ +#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME54N20A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42000000) /**< \brief CAN0 Registers Address */ +#define CAN1_REGS ((can_registers_t*)0x42000400) /**< \brief CAN1 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x42000800) /**< \brief GMAC Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME54N20A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CAN0_BASE_ADDRESS _UL_(0x42000000) /**< \brief CAN0 Base Address */ +#define CAN1_BASE_ADDRESS _UL_(0x42000400) /**< \brief CAN1 Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x42000800) /**< \brief GMAC Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ +#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ +#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ +#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME54N20A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#include "pio/same54n20a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 2048) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME54N20A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X61840302) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAME54N20A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /**< ID for GMAC event generator TSU_CMP */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAME54N20A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME54N20A definitions */ + + +#endif /* _SAME54N20A_H_ */ + diff --git a/arch/arm/SAME54/mcu/inc/same54p19a.h b/arch/arm/SAME54/mcu/inc/same54p19a.h new file mode 100644 index 00000000..fab2edc9 --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/same54p19a.h @@ -0,0 +1,1113 @@ +/** + * \brief Header file for ATSAME54P19A + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-12T17:27:01Z */ +#ifndef _SAME54P19A_H_ +#define _SAME54P19A_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME54P19A_definitions SAME54P19A definitions + This file defines all structures and symbols for SAME54P19A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME54P19A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ + CAN0_IRQn = 78, /**< 78 Control Area Network (CAN0) */ + CAN1_IRQn = 79, /**< 79 Control Area Network (CAN1) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + GMAC_IRQn = 84, /**< 84 Ethernet MAC (GMAC) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ + void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF*/ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility*/ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility*/ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility*/ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility*/ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* + * \brief Configuration of the CORTEX-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_same54.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME54P19A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P19A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME54P19A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_CAN0 ( 64) /**< \brief Control Area Network (CAN0) */ +#define ID_CAN1 ( 65) /**< \brief Control Area Network (CAN1) */ +#define ID_GMAC ( 66) /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ +#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ +#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ +#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ +#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ +#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ +#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME54P19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42000000) /**< \brief CAN0 Registers Address */ +#define CAN1_REGS ((can_registers_t*)0x42000400) /**< \brief CAN1 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x42000800) /**< \brief GMAC Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME54P19A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CAN0_BASE_ADDRESS _UL_(0x42000000) /**< \brief CAN0 Base Address */ +#define CAN1_BASE_ADDRESS _UL_(0x42000400) /**< \brief CAN1 Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x42000800) /**< \brief GMAC Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ +#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ +#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ +#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME54P19A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#include "pio/same54p19a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 1024) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00030000) /* 192kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME54P19A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X61840301) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAME54P19A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /**< ID for GMAC event generator TSU_CMP */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAME54P19A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME54P19A definitions */ + + +#endif /* _SAME54P19A_H_ */ + diff --git a/arch/arm/SAME54/mcu/inc/same54p20a.h b/arch/arm/SAME54/mcu/inc/same54p20a.h new file mode 100644 index 00000000..ce9e2e93 --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/same54p20a.h @@ -0,0 +1,1113 @@ +/** + * \brief Header file for ATSAME54P20A + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-12T17:27:04Z */ +#ifndef _SAME54P20A_H_ +#define _SAME54P20A_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME54P20A_definitions SAME54P20A definitions + This file defines all structures and symbols for SAME54P20A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME54P20A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /**< 0 Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ + CAN0_IRQn = 78, /**< 78 Control Area Network (CAN0) */ + CAN1_IRQn = 79, /**< 79 Control Area Network (CAN1) */ + USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ + GMAC_IRQn = 84, /**< 84 Ethernet MAC (GMAC) */ + TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ + void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF*/ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF*/ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility*/ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility*/ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility*/ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility*/ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* + * \brief Configuration of the CORTEX-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /**< Debug Level */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /**< Trace Level */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_same54.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME54P20A_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P20A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME54P20A_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /**< \brief Power Manager (PM) */ +#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ +#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ +#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ +#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ +#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ +#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ +#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ +#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ +#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ +#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ +#define ID_CAN0 ( 64) /**< \brief Control Area Network (CAN0) */ +#define ID_CAN1 ( 65) /**< \brief Control Area Network (CAN1) */ +#define ID_GMAC ( 66) /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ +#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ +#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ +#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ +#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ +#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ +#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ +#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ +#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ +#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ +#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ +#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ +#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ +#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ +#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ +#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ + +#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME54P20A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42000000) /**< \brief CAN0 Registers Address */ +#define CAN1_REGS ((can_registers_t*)0x42000400) /**< \brief CAN1 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x42000800) /**< \brief GMAC Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME54P20A_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ +#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ +#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ +#define CAN0_BASE_ADDRESS _UL_(0x42000000) /**< \brief CAN0 Base Address */ +#define CAN1_BASE_ADDRESS _UL_(0x42000400) /**< \brief CAN1 Base Address */ +#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ +#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ +#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ +#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ +#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ +#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x42000800) /**< \brief GMAC Base Address */ +#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ +#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ +#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ +#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ +#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ +#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ +#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ +#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ +#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ +#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ +#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ +#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ +#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME54P20A_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#include "pio/same54p20a.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UL_( 512) +#define FLASH_NB_OF_PAGES _UL_( 2048) + +#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UL_( 512) +#define TEMP_LOG_NB_OF_PAGES _UL_( 1) + +#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UL_( 512) +#define USER_PAGE_NB_OF_PAGES _UL_( 1) + +#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ +#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ +#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME54P20A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UL_(0X61840300) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/** Event Generator IDs for SAME54P20A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /**< ID for GMAC event generator TSU_CMP */ +#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/** Event User IDs for SAME54P20A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME54P20A definitions */ + + +#endif /* _SAME54P20A_H_ */ + diff --git a/arch/arm/SAME54/mcu/inc/system_same54.h b/arch/arm/SAME54/mcu/inc/system_same54.h new file mode 100644 index 00000000..91261ab3 --- /dev/null +++ b/arch/arm/SAME54/mcu/inc/system_same54.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon device startup + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SYSTEM_SAME54_H_INCLUDED_ +#define _SYSTEM_SAME54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_SAME54_H_INCLUDED */ diff --git a/arch/arm/SAME54/mcu/src/startup_same54n19a.c b/arch/arm/SAME54/mcu/src/startup_same54n19a.c new file mode 100644 index 00000000..47c8f48a --- /dev/null +++ b/arch/arm/SAME54/mcu/src/startup_same54n19a.c @@ -0,0 +1,409 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME54N19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same54n19a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ + .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ + .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ + .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ + .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ + .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ + .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ + .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ + .pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network */ + .pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ + .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ + .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ + .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ + .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ + .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ + .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME54/mcu/src/startup_same54n20a.c b/arch/arm/SAME54/mcu/src/startup_same54n20a.c new file mode 100644 index 00000000..b9cd7a90 --- /dev/null +++ b/arch/arm/SAME54/mcu/src/startup_same54n20a.c @@ -0,0 +1,409 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME54N20A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same54n20a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ + .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ + .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ + .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ + .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ + .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ + .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ + .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ + .pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network */ + .pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ + .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ + .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ + .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ + .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ + .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ + .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME54/mcu/src/startup_same54p19a.c b/arch/arm/SAME54/mcu/src/startup_same54p19a.c new file mode 100644 index 00000000..544ebb82 --- /dev/null +++ b/arch/arm/SAME54/mcu/src/startup_same54p19a.c @@ -0,0 +1,409 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME54P19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same54p19a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ + .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ + .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ + .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ + .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ + .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ + .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ + .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ + .pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network */ + .pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ + .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ + .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ + .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ + .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ + .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ + .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME54/mcu/src/startup_same54p20a.c b/arch/arm/SAME54/mcu/src/startup_same54p20a.c new file mode 100644 index 00000000..9f29857e --- /dev/null +++ b/arch/arm/SAME54/mcu/src/startup_same54p20a.c @@ -0,0 +1,409 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME54P20A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same54p20a.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ + .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ + .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ + .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ + .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ + .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ + .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ + .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ + .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ + .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ + .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ + .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ + .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ + .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ + .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ + .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ + .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ + .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ + .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ + .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ + .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ + .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ + .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ + .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ + .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ + .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ + .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ + .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ + .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ + .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ + .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ + .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ + .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ + .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ + .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ + .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ + .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ + .pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network */ + .pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network */ + .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ + .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ + .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ + .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */ + .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ + .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ + .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ + .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ + .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ + .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ + .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ + .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ + .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ + .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ + .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ + .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ + .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ + .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ + .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ + .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ + .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ + .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ + .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ + .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ + .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ + .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ + .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ + .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ + .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ + .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ + .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ + .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ + .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ + .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ + .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ + .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ + .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME54/mcu/src/system_same54n19a.c b/arch/arm/SAME54/mcu/src/system_same54n19a.c new file mode 100644 index 00000000..8c074ccb --- /dev/null +++ b/arch/arm/SAME54/mcu/src/system_same54n19a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME54N19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same54n19a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME54/mcu/src/system_same54n20a.c b/arch/arm/SAME54/mcu/src/system_same54n20a.c new file mode 100644 index 00000000..77ddcacd --- /dev/null +++ b/arch/arm/SAME54/mcu/src/system_same54n20a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME54N20A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same54n20a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME54/mcu/src/system_same54p19a.c b/arch/arm/SAME54/mcu/src/system_same54p19a.c new file mode 100644 index 00000000..74babf14 --- /dev/null +++ b/arch/arm/SAME54/mcu/src/system_same54p19a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME54P19A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same54p19a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME54/mcu/src/system_same54p20a.c b/arch/arm/SAME54/mcu/src/system_same54p20a.c new file mode 100644 index 00000000..d9161030 --- /dev/null +++ b/arch/arm/SAME54/mcu/src/system_same54p20a.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME54P20A + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same54p20a.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/helper-manifest.toml b/arch/make-manifest.toml similarity index 100% rename from arch/helper-manifest.toml rename to arch/make-manifest.toml diff --git a/arch/mcu-lookup.toml b/arch/mcu-lookup.toml new file mode 100644 index 00000000..0e3f2712 --- /dev/null +++ b/arch/mcu-lookup.toml @@ -0,0 +1,15 @@ +[mcu] +samd21e15a = "arch.arm.samd21a.samd21e15a" +samd21e16a = "arch.arm.samd21a.samd21e16a" +samd21e17a = "arch.arm.samd21a.samd21e17a" +samd21e18a = "arch.arm.samd21a.samd21e18a" +samd21g15a = "arch.arm.samd21a.samd21g15a" +samd21g16a = "arch.arm.samd21a.samd21g16a" +samd21g17a = "arch.arm.samd21a.samd21g17a" +samd21g17au = "arch.arm.samd2a1.samd21g17au" +samd21g18a = "arch.arm.samd21a.samd21g18a" +samd21g18au = "arch.arm.samd21a.samd21g18au" +samd21j15a = "arch.arm.samd21a.samd21j15a" +samd21j16a = "arch.arm.samd21a.samd21j16a" +samd21j17a = "arch.arm.samd21a.samd21j17a" +samd21j18a = "arch.arm.samd21a.samd21j18a" \ No newline at end of file diff --git a/arch/toml_learning/.gdb_history b/arch/toml_learning/.gdb_history new file mode 100644 index 00000000..51cd79d1 --- /dev/null +++ b/arch/toml_learning/.gdb_history @@ -0,0 +1,38 @@ +break main +r +n +n +n +s +s +s +s +s +n +n +n +n +n +n +n +n +n +n +n +n +n +n +n +n +n +s +s +s +s +s +s +n +n +n +n +q diff --git a/arch/toml_learning/Cargo.lock b/arch/toml_learning/Cargo.lock index 5849de4f..7fca1783 100644 --- a/arch/toml_learning/Cargo.lock +++ b/arch/toml_learning/Cargo.lock @@ -39,7 +39,7 @@ version = "0.10.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "19b076e143e1d9538dde65da30f8481c2a6c44040edb8e02b9bf1351edb92ce3" dependencies = [ - "lazy_static", + "lazy_static 1.4.0", "nom", "rust-ini", "serde 1.0.117", @@ -49,24 +49,122 @@ dependencies = [ "yaml-rust", ] +[[package]] +name = "filetime" +version = "0.2.12" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3ed85775dcc68644b5c950ac06a2b23768d3bc9390464151aaf27136998dcf9e" +dependencies = [ + "cfg-if", + "libc", + "redox_syscall", + "winapi 0.3.9", +] + +[[package]] +name = "fsevent" +version = "0.4.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5ab7d1bd1bd33cc98b0889831b72da23c0aa4df9cec7e0702f46ecea04b35db6" +dependencies = [ + "bitflags", + "fsevent-sys", +] + +[[package]] +name = "fsevent-sys" +version = "2.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f41b048a94555da0f42f1d632e2e19510084fb8e303b0daa2816e733fb3644a0" +dependencies = [ + "libc", +] + +[[package]] +name = "fuchsia-zircon" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2e9763c69ebaae630ba35f74888db465e49e259ba1bc0eda7d06f4a067615d82" +dependencies = [ + "bitflags", + "fuchsia-zircon-sys", +] + +[[package]] +name = "fuchsia-zircon-sys" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3dcaa9ae7725d12cdb85b3ad99a434db70b468c09ded17e012d86b5c1010f7a7" + [[package]] name = "glob" version = "0.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "9b919933a397b79c37e33b77bb2aa3dc8eb6e165ad809e58ff75bc7db2e34574" +[[package]] +name = "inotify" +version = "0.7.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4816c66d2c8ae673df83366c18341538f234a26d65a9ecea5c348b453ac1d02f" +dependencies = [ + "bitflags", + "inotify-sys", + "libc", +] + +[[package]] +name = "inotify-sys" +version = "0.1.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e74a1aa87c59aeff6ef2cc2fa62d41bc43f54952f55652656b18a02fd5e356c0" +dependencies = [ + "libc", +] + +[[package]] +name = "iovec" +version = "0.1.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b2b3ea6ff95e175473f8ffe6a7eb7c00d054240321b84c57051175fe3c1e075e" +dependencies = [ + "libc", +] + [[package]] name = "itoa" version = "0.4.6" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "dc6f3ad7b9d11a0c00842ff8de1b60ee58661048eb8049ed33c73594f359d7e6" +[[package]] +name = "kernel32-sys" +version = "0.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7507624b29483431c0ba2d82aece8ca6cdba9382bff4ddd0f7490560c056098d" +dependencies = [ + "winapi 0.2.8", + "winapi-build", +] + +[[package]] +name = "lazy_static" +version = "0.2.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "76f033c7ad61445c5b347c7382dd1237847eb1bce590fe50365dcb33d546be73" + [[package]] name = "lazy_static" version = "1.4.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "e2abad23fbc42b3700f2f279844dc832adb2b2eb069b2df918f455c4e18cc646" +[[package]] +name = "lazycell" +version = "1.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "830d08ce1d1d941e6b30645f1a0eb5643013d835ce3779a5fc208261dbe10f55" + [[package]] name = "lexical-core" version = "0.7.4" @@ -80,6 +178,12 @@ dependencies = [ "static_assertions", ] +[[package]] +name = "libc" +version = "0.2.79" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2448f6066e80e3bfc792e9c98bf705b4b0fc6e8ef5b43e5889aff0eaa9c58743" + [[package]] name = "linked-hash-map" version = "0.3.0" @@ -96,12 +200,75 @@ version = "0.5.3" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "8dd5a6d5999d9907cda8ed67bbd137d3af8085216c2ac62de5be860bd41f304a" +[[package]] +name = "log" +version = "0.4.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4fabed175da42fed1fa0746b0ea71f412aa9d35e76e95e59b192c64b9dc2bf8b" +dependencies = [ + "cfg-if", +] + [[package]] name = "memchr" version = "2.3.3" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "3728d817d99e5ac407411fa471ff9800a778d88a24685968b36824eaf4bee400" +[[package]] +name = "mio" +version = "0.6.22" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "fce347092656428bc8eaf6201042cb551b8d67855af7374542a92a0fbfcac430" +dependencies = [ + "cfg-if", + "fuchsia-zircon", + "fuchsia-zircon-sys", + "iovec", + "kernel32-sys", + "libc", + "log", + "miow", + "net2", + "slab", + "winapi 0.2.8", +] + +[[package]] +name = "mio-extras" +version = "2.0.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "52403fe290012ce777c4626790c8951324a2b9e3316b3143779c72b029742f19" +dependencies = [ + "lazycell", + "log", + "mio", + "slab", +] + +[[package]] +name = "miow" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8c1f2f3b1cf331de6896aabf6e9d55dca90356cc9960cca7eaaf408a355ae919" +dependencies = [ + "kernel32-sys", + "net2", + "winapi 0.2.8", + "ws2_32-sys", +] + +[[package]] +name = "net2" +version = "0.2.35" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3ebc3ec692ed7c9a255596c67808dee269f64655d8baf7b4f0638e51ba1d6853" +dependencies = [ + "cfg-if", + "libc", + "winapi 0.3.9", +] + [[package]] name = "nom" version = "5.1.2" @@ -113,6 +280,24 @@ dependencies = [ "version_check", ] +[[package]] +name = "notify" +version = "4.0.15" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "80ae4a7688d1fab81c5bf19c64fc8db920be8d519ce6336ed4e7efe024724dbd" +dependencies = [ + "bitflags", + "filetime", + "fsevent", + "fsevent-sys", + "inotify", + "libc", + "mio", + "mio-extras", + "walkdir", + "winapi 0.3.9", +] + [[package]] name = "num-traits" version = "0.1.43" @@ -131,6 +316,12 @@ dependencies = [ "autocfg", ] +[[package]] +name = "redox_syscall" +version = "0.1.57" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "41cc0f7e4d5d4544e8861606a285bb08d3e70712ccc7d2b84d7c0ccfaf4b05ce" + [[package]] name = "regex" version = "1.4.1" @@ -161,6 +352,15 @@ version = "1.0.5" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "71d301d4193d031abdd79ff7e3dd721168a9572ef3fe51a1517aba235bd8f86e" +[[package]] +name = "same-file" +version = "1.0.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "93fc1dc3aaa9bfed95e02e6eadabb4baf7e3078b0bd1b4d7b6b0b68378900502" +dependencies = [ + "winapi-util", +] + [[package]] name = "serde" version = "0.8.23" @@ -179,7 +379,7 @@ version = "0.9.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "6a3a4e0ea8a88553209f6cc6cfe8724ecad22e1acf372793c27d995290fe74f8" dependencies = [ - "lazy_static", + "lazy_static 1.4.0", "linked-hash-map 0.3.0", "num-traits 0.1.43", "regex", @@ -206,6 +406,12 @@ dependencies = [ "serde 0.8.23", ] +[[package]] +name = "slab" +version = "0.4.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c111b5bd5695e56cffe5129854aa230b39c93a305372fdbb2668ca2394eea9f8" + [[package]] name = "static_assertions" version = "1.1.0" @@ -218,7 +424,7 @@ version = "1.0.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "d40c6d1b69745a6ec6fb1ca717914848da4b44ae29d9b3080cbee91d72a69b14" dependencies = [ - "lazy_static", + "lazy_static 1.4.0", ] [[package]] @@ -236,6 +442,10 @@ version = "0.1.0" dependencies = [ "config", "glob", + "lazy_static 0.2.11", + "notify", + "serde 1.0.117", + "toml", ] [[package]] @@ -244,6 +454,70 @@ version = "0.9.2" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "b5a972e5669d67ba988ce3dc826706fb0a8b01471c088cb0b6110b805cc36aed" +[[package]] +name = "walkdir" +version = "2.3.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "777182bc735b6424e1a57516d35ed72cb8019d85c8c9bf536dccb3445c1a2f7d" +dependencies = [ + "same-file", + "winapi 0.3.9", + "winapi-util", +] + +[[package]] +name = "winapi" +version = "0.2.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "167dc9d6949a9b857f3451275e911c3f44255842c1f7a76f33c55103a909087a" + +[[package]] +name = "winapi" +version = "0.3.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5c839a674fcd7a98952e593242ea400abe93992746761e38641405d28b00f419" +dependencies = [ + "winapi-i686-pc-windows-gnu", + "winapi-x86_64-pc-windows-gnu", +] + +[[package]] +name = "winapi-build" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2d315eee3b34aca4797b2da6b13ed88266e6d612562a0c46390af8299fc699bc" + +[[package]] +name = "winapi-i686-pc-windows-gnu" +version = "0.4.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ac3b87c63620426dd9b991e5ce0329eff545bccbbb34f3be09ff6fb6ab51b7b6" + +[[package]] +name = "winapi-util" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "70ec6ce85bb158151cae5e5c87f95a8e97d2c0c4b001223f33a334e3ce5de178" +dependencies = [ + "winapi 0.3.9", +] + +[[package]] +name = "winapi-x86_64-pc-windows-gnu" +version = "0.4.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f" + +[[package]] +name = "ws2_32-sys" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d59cefebd0c892fa2dd6de581e937301d8552cb44489cdff035c6187cb63fa5e" +dependencies = [ + "winapi 0.2.8", + "winapi-build", +] + [[package]] name = "yaml-rust" version = "0.4.4" diff --git a/arch/toml_learning/Cargo.toml b/arch/toml_learning/Cargo.toml index 7c54ca65..80e4bff4 100644 --- a/arch/toml_learning/Cargo.toml +++ b/arch/toml_learning/Cargo.toml @@ -8,4 +8,8 @@ edition = "2018" [dependencies] config = "0.10" -glob = "0.3.0" \ No newline at end of file +glob = "0.3.0" +toml = "0.5" +serde = "1.0" +lazy_static = "^0.2.8" +notify = "^4.0.0" \ No newline at end of file diff --git a/arch/toml_learning/src/main.rs b/arch/toml_learning/src/main.rs index 22a0bb76..6c9cc2b2 100644 --- a/arch/toml_learning/src/main.rs +++ b/arch/toml_learning/src/main.rs @@ -1,14 +1,59 @@ -extern crate glob; -extern crate config; - -use std::path::Path; +use config::{Config, File, Environment, Value}; use std::collections::HashMap; -use config::*; -use glob::glob; fn main() { - let mut settings = Config::default(); - settings.merge(File::with_name("/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/helper-manifest.toml")).unwrap(); - println!("\n{:?} \n\n------------", settings); + let mut mcu_lookup_table = Config::new(); + let mut make_manifest: Config = Config::new(); + mcu_lookup_table.merge(File::with_name("\ + /storage/Shared/Documents/Projects/ePenguin/\ + ePenguin-Software-Framework/arch/mcu-lookup.toml")).unwrap(); + make_manifest.merge(File::with_name("\ + /storage/Shared/Documents/Projects/ePenguin/\ + ePenguin-Software-Framework/arch/make-manifest.toml")).unwrap(); + let mut _table_name = mcu_lookup_table.get_str("mcu.samd21j18a").unwrap(); + let mut table_head = &_table_name[0.._table_name.len()]; + let mut makefile: HashMap = HashMap::new(); + let mut b_quit: bool = false; + loop + { + let mut _active_table = make_manifest.get_table(&table_head).unwrap(); + for (name, val) in _active_table + { + match val.clone().into_table() + { + Err(_e) => + { + if !makefile.contains_key(&name) + { + makefile.insert(name, val); + } + else + { + let mut new_arr = makefile.get_key_value(&name).unwrap().1.clone().into_array().unwrap(); + new_arr.push(val); + makefile.insert(name, config::Value::from(new_arr)); + } + } + Ok(_v) => + { + + } + } + } + match table_head.rfind('.') + { + None => b_quit = true, + Some(v) => table_head = &table_head[0..v], + } + if b_quit + { + + break; + } + } + for (key_id, val) in &makefile + { + println!("\n{}: {:?}", key_id, val); + } } diff --git a/arch/manifest.toml b/arch/toml_learning/target/debug/.fingerprint/filetime-727651744b3a6fd0/dep-lib-filetime similarity index 100% rename from arch/manifest.toml rename to arch/toml_learning/target/debug/.fingerprint/filetime-727651744b3a6fd0/dep-lib-filetime diff --git a/arch/toml_learning/target/debug/.fingerprint/filetime-727651744b3a6fd0/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/filetime-727651744b3a6fd0/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/filetime-727651744b3a6fd0/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/filetime-727651744b3a6fd0/lib-filetime b/arch/toml_learning/target/debug/.fingerprint/filetime-727651744b3a6fd0/lib-filetime new file mode 100644 index 00000000..b9fe822e --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/filetime-727651744b3a6fd0/lib-filetime @@ -0,0 +1 @@ +4ac14be7862db014 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/filetime-727651744b3a6fd0/lib-filetime.json b/arch/toml_learning/target/debug/.fingerprint/filetime-727651744b3a6fd0/lib-filetime.json new file mode 100644 index 00000000..cb028aeb --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/filetime-727651744b3a6fd0/lib-filetime.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":3194576745162206706,"profile":11677938664258541388,"path":8506414418509802360,"deps":[[9354177244160890506,"libc",false,1769811338463775193],[13837234849270857574,"cfg_if",false,14270946183722601413]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/filetime-727651744b3a6fd0/dep-lib-filetime"}}],"rustflags":[],"metadata":6142837673842625563} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/inotify-227c9a24fd07857b/dep-lib-inotify b/arch/toml_learning/target/debug/.fingerprint/inotify-227c9a24fd07857b/dep-lib-inotify new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/inotify-227c9a24fd07857b/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/inotify-227c9a24fd07857b/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/inotify-227c9a24fd07857b/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/inotify-227c9a24fd07857b/lib-inotify b/arch/toml_learning/target/debug/.fingerprint/inotify-227c9a24fd07857b/lib-inotify new file mode 100644 index 00000000..be27acba --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/inotify-227c9a24fd07857b/lib-inotify @@ -0,0 +1 @@ +15e3c766dc726b2c \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/inotify-227c9a24fd07857b/lib-inotify.json b/arch/toml_learning/target/debug/.fingerprint/inotify-227c9a24fd07857b/lib-inotify.json new file mode 100644 index 00000000..fc6f443e --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/inotify-227c9a24fd07857b/lib-inotify.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":10106793199706288507,"profile":11677938664258541388,"path":8373113282109897073,"deps":[[1535610106599956303,"inotify_sys",false,11452371603355365170],[4117749705314174326,"bitflags",false,1973756016592835707],[9354177244160890506,"libc",false,1769811338463775193]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/inotify-227c9a24fd07857b/dep-lib-inotify"}}],"rustflags":[],"metadata":17270876855136421480} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/dep-lib-inotify-sys b/arch/toml_learning/target/debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/dep-lib-inotify-sys new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/lib-inotify-sys b/arch/toml_learning/target/debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/lib-inotify-sys new file mode 100644 index 00000000..56a693d0 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/lib-inotify-sys @@ -0,0 +1 @@ +326fc4c54bffee9e \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/lib-inotify-sys.json b/arch/toml_learning/target/debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/lib-inotify-sys.json new file mode 100644 index 00000000..df4efdbe --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/lib-inotify-sys.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":1114463511556614207,"profile":11677938664258541388,"path":3195450586770819546,"deps":[[9354177244160890506,"libc",false,1769811338463775193]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/inotify-sys-e7b33fbf21e4ccdd/dep-lib-inotify-sys"}}],"rustflags":[],"metadata":7193815289792856449} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/iovec-6d60102019e1348b/dep-lib-iovec b/arch/toml_learning/target/debug/.fingerprint/iovec-6d60102019e1348b/dep-lib-iovec new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/iovec-6d60102019e1348b/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/iovec-6d60102019e1348b/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/iovec-6d60102019e1348b/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/iovec-6d60102019e1348b/lib-iovec b/arch/toml_learning/target/debug/.fingerprint/iovec-6d60102019e1348b/lib-iovec new file mode 100644 index 00000000..c21ddbe8 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/iovec-6d60102019e1348b/lib-iovec @@ -0,0 +1 @@ +071cc209dff45edd \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/iovec-6d60102019e1348b/lib-iovec.json b/arch/toml_learning/target/debug/.fingerprint/iovec-6d60102019e1348b/lib-iovec.json new file mode 100644 index 00000000..2ca31e39 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/iovec-6d60102019e1348b/lib-iovec.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":9964660163749110840,"profile":11677938664258541388,"path":12880867705819710931,"deps":[[9354177244160890506,"libc",false,1769811338463775193]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/iovec-6d60102019e1348b/dep-lib-iovec"}}],"rustflags":[],"metadata":13381672237506315297} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/lazy_static-c93b4732a572fb60/dep-lib-lazy_static b/arch/toml_learning/target/debug/.fingerprint/lazy_static-c93b4732a572fb60/dep-lib-lazy_static new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/lazy_static-c93b4732a572fb60/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/lazy_static-c93b4732a572fb60/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/lazy_static-c93b4732a572fb60/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/lazy_static-c93b4732a572fb60/lib-lazy_static b/arch/toml_learning/target/debug/.fingerprint/lazy_static-c93b4732a572fb60/lib-lazy_static new file mode 100644 index 00000000..f1c06384 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/lazy_static-c93b4732a572fb60/lib-lazy_static @@ -0,0 +1 @@ +124f84b807449ec9 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/lazy_static-c93b4732a572fb60/lib-lazy_static.json b/arch/toml_learning/target/debug/.fingerprint/lazy_static-c93b4732a572fb60/lib-lazy_static.json new file mode 100644 index 00000000..04f30afe --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/lazy_static-c93b4732a572fb60/lib-lazy_static.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":3310758268438181623,"profile":11677938664258541388,"path":16319952949464954345,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/lazy_static-c93b4732a572fb60/dep-lib-lazy_static"}}],"rustflags":[],"metadata":111743654650316589} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/lazycell-5309ca3a766221bf/dep-lib-lazycell b/arch/toml_learning/target/debug/.fingerprint/lazycell-5309ca3a766221bf/dep-lib-lazycell new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/lazycell-5309ca3a766221bf/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/lazycell-5309ca3a766221bf/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/lazycell-5309ca3a766221bf/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/lazycell-5309ca3a766221bf/lib-lazycell b/arch/toml_learning/target/debug/.fingerprint/lazycell-5309ca3a766221bf/lib-lazycell new file mode 100644 index 00000000..49d7db09 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/lazycell-5309ca3a766221bf/lib-lazycell @@ -0,0 +1 @@ +30b1de58b8518c87 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/lazycell-5309ca3a766221bf/lib-lazycell.json b/arch/toml_learning/target/debug/.fingerprint/lazycell-5309ca3a766221bf/lib-lazycell.json new file mode 100644 index 00000000..ca00705e --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/lazycell-5309ca3a766221bf/lib-lazycell.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":9076603029916651789,"profile":11677938664258541388,"path":8604029688242996357,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/lazycell-5309ca3a766221bf/dep-lib-lazycell"}}],"rustflags":[],"metadata":9081195101616900511} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/libc-0ac771bf9f21d7c8/run-build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/libc-0ac771bf9f21d7c8/run-build-script-build-script-build new file mode 100644 index 00000000..cfc9b4da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/libc-0ac771bf9f21d7c8/run-build-script-build-script-build @@ -0,0 +1 @@ +c6fd9d49b758d2db \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/libc-0ac771bf9f21d7c8/run-build-script-build-script-build.json b/arch/toml_learning/target/debug/.fingerprint/libc-0ac771bf9f21d7c8/run-build-script-build-script-build.json new file mode 100644 index 00000000..2dabbb9a --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/libc-0ac771bf9f21d7c8/run-build-script-build-script-build.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"","target":0,"profile":0,"path":0,"deps":[[9354177244160890506,"build_script_build",false,17442491153488153041]],"local":[{"Precalculated":"0.2.79"}],"rustflags":[],"metadata":0} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/libc-7623b6e835e99b3f/build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/libc-7623b6e835e99b3f/build-script-build-script-build new file mode 100644 index 00000000..c8457afd --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/libc-7623b6e835e99b3f/build-script-build-script-build @@ -0,0 +1 @@ +d1098e314a2d10f2 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/libc-7623b6e835e99b3f/build-script-build-script-build.json b/arch/toml_learning/target/debug/.fingerprint/libc-7623b6e835e99b3f/build-script-build-script-build.json new file mode 100644 index 00000000..063de1b7 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/libc-7623b6e835e99b3f/build-script-build-script-build.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"default\", \"std\"]","target":10088282520713642473,"profile":11677938664258541388,"path":4862230917885271189,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/libc-7623b6e835e99b3f/dep-build-script-build-script-build"}}],"rustflags":[],"metadata":14998826085014762512} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/libc-7623b6e835e99b3f/dep-build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/libc-7623b6e835e99b3f/dep-build-script-build-script-build new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/libc-7623b6e835e99b3f/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/libc-7623b6e835e99b3f/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/libc-7623b6e835e99b3f/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/libc-f957e64c74520dcc/dep-lib-libc b/arch/toml_learning/target/debug/.fingerprint/libc-f957e64c74520dcc/dep-lib-libc new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/libc-f957e64c74520dcc/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/libc-f957e64c74520dcc/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/libc-f957e64c74520dcc/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/libc-f957e64c74520dcc/lib-libc b/arch/toml_learning/target/debug/.fingerprint/libc-f957e64c74520dcc/lib-libc new file mode 100644 index 00000000..a0500709 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/libc-f957e64c74520dcc/lib-libc @@ -0,0 +1 @@ +d989971409a28f18 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/libc-f957e64c74520dcc/lib-libc.json b/arch/toml_learning/target/debug/.fingerprint/libc-f957e64c74520dcc/lib-libc.json new file mode 100644 index 00000000..8370e330 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/libc-f957e64c74520dcc/lib-libc.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"default\", \"std\"]","target":1047533068072243941,"profile":11677938664258541388,"path":11060151438798720977,"deps":[[9354177244160890506,"build_script_build",false,15839820383652806086]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/libc-f957e64c74520dcc/dep-lib-libc"}}],"rustflags":[],"metadata":14998826085014762512} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/log-86f8d34791d1ea32/dep-lib-log b/arch/toml_learning/target/debug/.fingerprint/log-86f8d34791d1ea32/dep-lib-log new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/log-86f8d34791d1ea32/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/log-86f8d34791d1ea32/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/log-86f8d34791d1ea32/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/log-86f8d34791d1ea32/lib-log b/arch/toml_learning/target/debug/.fingerprint/log-86f8d34791d1ea32/lib-log new file mode 100644 index 00000000..69a927f0 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/log-86f8d34791d1ea32/lib-log @@ -0,0 +1 @@ +e8bb8a392599594e \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/log-86f8d34791d1ea32/lib-log.json b/arch/toml_learning/target/debug/.fingerprint/log-86f8d34791d1ea32/lib-log.json new file mode 100644 index 00000000..a42a692d --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/log-86f8d34791d1ea32/lib-log.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":2735847673528249900,"profile":11677938664258541388,"path":224509318319670974,"deps":[[5027596198908666028,"build_script_build",false,12235367662317524943],[13837234849270857574,"cfg_if",false,14270946183722601413]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/log-86f8d34791d1ea32/dep-lib-log"}}],"rustflags":[],"metadata":179143468214550567} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/log-98622275a955444b/run-build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/log-98622275a955444b/run-build-script-build-script-build new file mode 100644 index 00000000..015db6f2 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/log-98622275a955444b/run-build-script-build-script-build @@ -0,0 +1 @@ +cfd7bc2810c2cca9 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/log-98622275a955444b/run-build-script-build-script-build.json b/arch/toml_learning/target/debug/.fingerprint/log-98622275a955444b/run-build-script-build-script-build.json new file mode 100644 index 00000000..7d5e7ae3 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/log-98622275a955444b/run-build-script-build-script-build.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"","target":0,"profile":0,"path":0,"deps":[[5027596198908666028,"build_script_build",false,2562574399181898527]],"local":[{"RerunIfChanged":{"output":"debug/build/log-98622275a955444b/output","paths":["build.rs"]}}],"rustflags":[],"metadata":0} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/log-b21fc8c2d7201e78/build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/log-b21fc8c2d7201e78/build-script-build-script-build new file mode 100644 index 00000000..184827fd --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/log-b21fc8c2d7201e78/build-script-build-script-build @@ -0,0 +1 @@ +1f43bfc5d6179023 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/log-b21fc8c2d7201e78/build-script-build-script-build.json b/arch/toml_learning/target/debug/.fingerprint/log-b21fc8c2d7201e78/build-script-build-script-build.json new file mode 100644 index 00000000..b3d524ed --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/log-b21fc8c2d7201e78/build-script-build-script-build.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":10088282520713642473,"profile":11677938664258541388,"path":12789986868091722243,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/log-b21fc8c2d7201e78/dep-build-script-build-script-build"}}],"rustflags":[],"metadata":179143468214550567} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/log-b21fc8c2d7201e78/dep-build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/log-b21fc8c2d7201e78/dep-build-script-build-script-build new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/log-b21fc8c2d7201e78/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/log-b21fc8c2d7201e78/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/log-b21fc8c2d7201e78/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/mio-40897f326420dab3/dep-lib-mio b/arch/toml_learning/target/debug/.fingerprint/mio-40897f326420dab3/dep-lib-mio new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/mio-40897f326420dab3/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/mio-40897f326420dab3/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/mio-40897f326420dab3/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/mio-40897f326420dab3/lib-mio b/arch/toml_learning/target/debug/.fingerprint/mio-40897f326420dab3/lib-mio new file mode 100644 index 00000000..c08c23ee --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/mio-40897f326420dab3/lib-mio @@ -0,0 +1 @@ +f6a34200c66cf25c \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/mio-40897f326420dab3/lib-mio.json b/arch/toml_learning/target/debug/.fingerprint/mio-40897f326420dab3/lib-mio.json new file mode 100644 index 00000000..8de8d6b8 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/mio-40897f326420dab3/lib-mio.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"default\", \"with-deprecated\"]","target":2539711157639226077,"profile":11677938664258541388,"path":17122102584350561460,"deps":[[4014851421258823018,"net2",false,13146031200177133997],[5027596198908666028,"log",false,5645711993043860456],[6754996699345501776,"slab",false,14303761386035796081],[9354177244160890506,"libc",false,1769811338463775193],[12956776279495519648,"iovec",false,15951456168971475975],[13837234849270857574,"cfg_if",false,14270946183722601413]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/mio-40897f326420dab3/dep-lib-mio"}}],"rustflags":[],"metadata":13401525147478723630} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/mio-extras-aecc5d72143b7262/dep-lib-mio-extras b/arch/toml_learning/target/debug/.fingerprint/mio-extras-aecc5d72143b7262/dep-lib-mio-extras new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/mio-extras-aecc5d72143b7262/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/mio-extras-aecc5d72143b7262/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/mio-extras-aecc5d72143b7262/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/mio-extras-aecc5d72143b7262/lib-mio-extras b/arch/toml_learning/target/debug/.fingerprint/mio-extras-aecc5d72143b7262/lib-mio-extras new file mode 100644 index 00000000..9f20928b --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/mio-extras-aecc5d72143b7262/lib-mio-extras @@ -0,0 +1 @@ +efd93b48b6c38d8d \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/mio-extras-aecc5d72143b7262/lib-mio-extras.json b/arch/toml_learning/target/debug/.fingerprint/mio-extras-aecc5d72143b7262/lib-mio-extras.json new file mode 100644 index 00000000..5d377986 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/mio-extras-aecc5d72143b7262/lib-mio-extras.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":3704945143473564050,"profile":11677938664258541388,"path":18318530757946065140,"deps":[[3580225804074155036,"mio",false,6697535193517040630],[5027596198908666028,"log",false,5645711993043860456],[6754996699345501776,"slab",false,14303761386035796081],[15078758276232438380,"lazycell",false,9767271544066584880]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/mio-extras-aecc5d72143b7262/dep-lib-mio-extras"}}],"rustflags":[],"metadata":3300289108706468134} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/net2-47f78eb9630d276c/dep-lib-net2 b/arch/toml_learning/target/debug/.fingerprint/net2-47f78eb9630d276c/dep-lib-net2 new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/net2-47f78eb9630d276c/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/net2-47f78eb9630d276c/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/net2-47f78eb9630d276c/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/net2-47f78eb9630d276c/lib-net2 b/arch/toml_learning/target/debug/.fingerprint/net2-47f78eb9630d276c/lib-net2 new file mode 100644 index 00000000..6e06e6d2 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/net2-47f78eb9630d276c/lib-net2 @@ -0,0 +1 @@ +ad99c2d4b91570b6 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/net2-47f78eb9630d276c/lib-net2.json b/arch/toml_learning/target/debug/.fingerprint/net2-47f78eb9630d276c/lib-net2.json new file mode 100644 index 00000000..4c729db4 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/net2-47f78eb9630d276c/lib-net2.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"default\", \"duration\"]","target":1347876483790261947,"profile":11677938664258541388,"path":8862565380267738064,"deps":[[9354177244160890506,"libc",false,1769811338463775193],[13837234849270857574,"cfg_if",false,14270946183722601413]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/net2-47f78eb9630d276c/dep-lib-net2"}}],"rustflags":[],"metadata":8156400345628516919} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/notify-460f5b0501989ba5/dep-lib-notify b/arch/toml_learning/target/debug/.fingerprint/notify-460f5b0501989ba5/dep-lib-notify new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/notify-460f5b0501989ba5/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/notify-460f5b0501989ba5/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/notify-460f5b0501989ba5/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/notify-460f5b0501989ba5/lib-notify b/arch/toml_learning/target/debug/.fingerprint/notify-460f5b0501989ba5/lib-notify new file mode 100644 index 00000000..7f6c3945 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/notify-460f5b0501989ba5/lib-notify @@ -0,0 +1 @@ +d6df7828a9877c09 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/notify-460f5b0501989ba5/lib-notify.json b/arch/toml_learning/target/debug/.fingerprint/notify-460f5b0501989ba5/lib-notify.json new file mode 100644 index 00000000..fa4aeb29 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/notify-460f5b0501989ba5/lib-notify.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":9568175691343950667,"profile":11677938664258541388,"path":12146718503361309104,"deps":[[3175233130860357906,"inotify",false,3200778251119616789],[3580225804074155036,"mio",false,6697535193517040630],[4117749705314174326,"bitflags",false,1973756016592835707],[6083436579325553451,"walkdir",false,7983456755630336155],[9354177244160890506,"libc",false,1769811338463775193],[9387478816472089132,"filetime",false,1490741534089003338],[12899235606239544079,"mio_extras",false,10200023918727387631]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/notify-460f5b0501989ba5/dep-lib-notify"}}],"rustflags":[],"metadata":808560472100773384} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/proc-macro2-10ba1809e1dbc902/dep-lib-proc-macro2 b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-10ba1809e1dbc902/dep-lib-proc-macro2 new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/proc-macro2-10ba1809e1dbc902/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-10ba1809e1dbc902/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-10ba1809e1dbc902/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/proc-macro2-10ba1809e1dbc902/lib-proc-macro2 b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-10ba1809e1dbc902/lib-proc-macro2 new file mode 100644 index 00000000..13db3df9 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-10ba1809e1dbc902/lib-proc-macro2 @@ -0,0 +1 @@ +d07dd3dbe0b197ca \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/proc-macro2-10ba1809e1dbc902/lib-proc-macro2.json b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-10ba1809e1dbc902/lib-proc-macro2.json new file mode 100644 index 00000000..1275fb04 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-10ba1809e1dbc902/lib-proc-macro2.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"default\", \"proc-macro\"]","target":2048968770155376255,"profile":11677938664258541388,"path":18307547115188568097,"deps":[[7525965102115876890,"unicode_xid",false,9971239689925264399],[16745173101903655211,"build_script_build",false,2623699874861502791]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/proc-macro2-10ba1809e1dbc902/dep-lib-proc-macro2"}}],"rustflags":[],"metadata":14399165043509735265} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/proc-macro2-18e23bd5f760ab2a/run-build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-18e23bd5f760ab2a/run-build-script-build-script-build new file mode 100644 index 00000000..d8283996 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-18e23bd5f760ab2a/run-build-script-build-script-build @@ -0,0 +1 @@ +47515b9e22416924 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/proc-macro2-18e23bd5f760ab2a/run-build-script-build-script-build.json b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-18e23bd5f760ab2a/run-build-script-build-script-build.json new file mode 100644 index 00000000..06de54f5 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-18e23bd5f760ab2a/run-build-script-build-script-build.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"","target":0,"profile":0,"path":0,"deps":[[16745173101903655211,"build_script_build",false,15070456360261919588]],"local":[{"RerunIfChanged":{"output":"debug/build/proc-macro2-18e23bd5f760ab2a/output","paths":["build.rs"]}}],"rustflags":[],"metadata":0} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/build-script-build-script-build new file mode 100644 index 00000000..71292ba4 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/build-script-build-script-build @@ -0,0 +1 @@ +64237084360425d1 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/build-script-build-script-build.json b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/build-script-build-script-build.json new file mode 100644 index 00000000..bee7e041 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/build-script-build-script-build.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"default\", \"proc-macro\"]","target":10429514197457385088,"profile":11677938664258541388,"path":5711236808831911872,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/dep-build-script-build-script-build"}}],"rustflags":[],"metadata":14399165043509735265} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/dep-build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/dep-build-script-build-script-build new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/proc-macro2-bc60f0d61e99c4b5/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/quote-af750ed0964881fc/dep-lib-quote b/arch/toml_learning/target/debug/.fingerprint/quote-af750ed0964881fc/dep-lib-quote new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/quote-af750ed0964881fc/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/quote-af750ed0964881fc/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/quote-af750ed0964881fc/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/quote-af750ed0964881fc/lib-quote b/arch/toml_learning/target/debug/.fingerprint/quote-af750ed0964881fc/lib-quote new file mode 100644 index 00000000..33bd72d8 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/quote-af750ed0964881fc/lib-quote @@ -0,0 +1 @@ +7127fcd7e187ffcd \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/quote-af750ed0964881fc/lib-quote.json b/arch/toml_learning/target/debug/.fingerprint/quote-af750ed0964881fc/lib-quote.json new file mode 100644 index 00000000..ad647578 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/quote-af750ed0964881fc/lib-quote.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"default\", \"proc-macro\"]","target":5822405929374872038,"profile":11677938664258541388,"path":17556376264291188435,"deps":[[16745173101903655211,"proc_macro2",false,14598332296463613392]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/quote-af750ed0964881fc/dep-lib-quote"}}],"rustflags":[],"metadata":2717943770976187624} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/same-file-d6c46a96b8ab29ad/dep-lib-same-file b/arch/toml_learning/target/debug/.fingerprint/same-file-d6c46a96b8ab29ad/dep-lib-same-file new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/same-file-d6c46a96b8ab29ad/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/same-file-d6c46a96b8ab29ad/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/same-file-d6c46a96b8ab29ad/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/same-file-d6c46a96b8ab29ad/lib-same-file b/arch/toml_learning/target/debug/.fingerprint/same-file-d6c46a96b8ab29ad/lib-same-file new file mode 100644 index 00000000..462fcf75 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/same-file-d6c46a96b8ab29ad/lib-same-file @@ -0,0 +1 @@ +3929d35ad3d0847d \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/same-file-d6c46a96b8ab29ad/lib-same-file.json b/arch/toml_learning/target/debug/.fingerprint/same-file-d6c46a96b8ab29ad/lib-same-file.json new file mode 100644 index 00000000..5cfd982f --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/same-file-d6c46a96b8ab29ad/lib-same-file.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":4323499674810460189,"profile":11677938664258541388,"path":8157399539588464464,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/same-file-d6c46a96b8ab29ad/dep-lib-same-file"}}],"rustflags":[],"metadata":11023981866482830203} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/serde_derive-4a4dbbd361dc80da/dep-lib-serde_derive b/arch/toml_learning/target/debug/.fingerprint/serde_derive-4a4dbbd361dc80da/dep-lib-serde_derive new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/serde_derive-4a4dbbd361dc80da/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/serde_derive-4a4dbbd361dc80da/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/serde_derive-4a4dbbd361dc80da/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/serde_derive-4a4dbbd361dc80da/lib-serde_derive b/arch/toml_learning/target/debug/.fingerprint/serde_derive-4a4dbbd361dc80da/lib-serde_derive new file mode 100644 index 00000000..f86550b1 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/serde_derive-4a4dbbd361dc80da/lib-serde_derive @@ -0,0 +1 @@ +d4dec8f2c32b3932 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/serde_derive-4a4dbbd361dc80da/lib-serde_derive.json b/arch/toml_learning/target/debug/.fingerprint/serde_derive-4a4dbbd361dc80da/lib-serde_derive.json new file mode 100644 index 00000000..4a712e7d --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/serde_derive-4a4dbbd361dc80da/lib-serde_derive.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"default\"]","target":14939371488459447851,"profile":11677938664258541388,"path":682727825342084438,"deps":[[6555828555352911943,"quote",false,14843732300897462129],[6773936731788865364,"build_script_build",false,6944853471635922555],[12763460456890314314,"syn",false,1957769660918271117],[16745173101903655211,"proc_macro2",false,14598332296463613392]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/serde_derive-4a4dbbd361dc80da/dep-lib-serde_derive"}}],"rustflags":[],"metadata":14452199383429553764} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/serde_derive-7005aabd08e2511f/run-build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/serde_derive-7005aabd08e2511f/run-build-script-build-script-build new file mode 100644 index 00000000..20758c02 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/serde_derive-7005aabd08e2511f/run-build-script-build-script-build @@ -0,0 +1 @@ +7b5effe16f136160 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/serde_derive-7005aabd08e2511f/run-build-script-build-script-build.json b/arch/toml_learning/target/debug/.fingerprint/serde_derive-7005aabd08e2511f/run-build-script-build-script-build.json new file mode 100644 index 00000000..2b3b7f02 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/serde_derive-7005aabd08e2511f/run-build-script-build-script-build.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"","target":0,"profile":0,"path":0,"deps":[[6773936731788865364,"build_script_build",false,3344328180241154323]],"local":[{"Precalculated":"1.0.117"}],"rustflags":[],"metadata":0} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/build-script-build-script-build new file mode 100644 index 00000000..88f7ff05 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/build-script-build-script-build @@ -0,0 +1 @@ +13419acbc270692e \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/build-script-build-script-build.json b/arch/toml_learning/target/debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/build-script-build-script-build.json new file mode 100644 index 00000000..3a12d2ac --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/build-script-build-script-build.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"default\"]","target":10088282520713642473,"profile":11677938664258541388,"path":8556688144242608373,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/dep-build-script-build-script-build"}}],"rustflags":[],"metadata":14452199383429553764} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/dep-build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/dep-build-script-build-script-build new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/serde_derive-fda8cd5f1bf4f7be/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/slab-f4af9e03a066116e/dep-lib-slab b/arch/toml_learning/target/debug/.fingerprint/slab-f4af9e03a066116e/dep-lib-slab new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/slab-f4af9e03a066116e/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/slab-f4af9e03a066116e/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/slab-f4af9e03a066116e/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/slab-f4af9e03a066116e/lib-slab b/arch/toml_learning/target/debug/.fingerprint/slab-f4af9e03a066116e/lib-slab new file mode 100644 index 00000000..0e2e6980 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/slab-f4af9e03a066116e/lib-slab @@ -0,0 +1 @@ +71d89c2e322b81c6 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/slab-f4af9e03a066116e/lib-slab.json b/arch/toml_learning/target/debug/.fingerprint/slab-f4af9e03a066116e/lib-slab.json new file mode 100644 index 00000000..98840a47 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/slab-f4af9e03a066116e/lib-slab.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":3755413576892652283,"profile":11677938664258541388,"path":17218070861130977558,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/slab-f4af9e03a066116e/dep-lib-slab"}}],"rustflags":[],"metadata":15209347383686928192} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/syn-590ded94d59e41a3/dep-lib-syn b/arch/toml_learning/target/debug/.fingerprint/syn-590ded94d59e41a3/dep-lib-syn new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/syn-590ded94d59e41a3/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/syn-590ded94d59e41a3/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/syn-590ded94d59e41a3/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/syn-590ded94d59e41a3/lib-syn b/arch/toml_learning/target/debug/.fingerprint/syn-590ded94d59e41a3/lib-syn new file mode 100644 index 00000000..a7e033c5 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/syn-590ded94d59e41a3/lib-syn @@ -0,0 +1 @@ +8d0c124722652b1b \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/syn-590ded94d59e41a3/lib-syn.json b/arch/toml_learning/target/debug/.fingerprint/syn-590ded94d59e41a3/lib-syn.json new file mode 100644 index 00000000..65d5f5ca --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/syn-590ded94d59e41a3/lib-syn.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"clone-impls\", \"default\", \"derive\", \"parsing\", \"printing\", \"proc-macro\", \"quote\", \"visit\"]","target":18164850629821630209,"profile":11677938664258541388,"path":7704210380264754514,"deps":[[6555828555352911943,"quote",false,14843732300897462129],[7525965102115876890,"unicode_xid",false,9971239689925264399],[12763460456890314314,"build_script_build",false,3180503829662352994],[16745173101903655211,"proc_macro2",false,14598332296463613392]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/syn-590ded94d59e41a3/dep-lib-syn"}}],"rustflags":[],"metadata":6886477143387768027} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/syn-beb75ac107fbd1be/build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/syn-beb75ac107fbd1be/build-script-build-script-build new file mode 100644 index 00000000..307896ac --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/syn-beb75ac107fbd1be/build-script-build-script-build @@ -0,0 +1 @@ +e3f475b51d6a2b16 \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/syn-beb75ac107fbd1be/build-script-build-script-build.json b/arch/toml_learning/target/debug/.fingerprint/syn-beb75ac107fbd1be/build-script-build-script-build.json new file mode 100644 index 00000000..109b69d6 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/syn-beb75ac107fbd1be/build-script-build-script-build.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"clone-impls\", \"default\", \"derive\", \"parsing\", \"printing\", \"proc-macro\", \"quote\", \"visit\"]","target":10429514197457385088,"profile":11677938664258541388,"path":6953822267141954629,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/syn-beb75ac107fbd1be/dep-build-script-build-script-build"}}],"rustflags":[],"metadata":6886477143387768027} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/syn-beb75ac107fbd1be/dep-build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/syn-beb75ac107fbd1be/dep-build-script-build-script-build new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/syn-beb75ac107fbd1be/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/syn-beb75ac107fbd1be/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/syn-beb75ac107fbd1be/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/syn-ca295c6494f2b39c/run-build-script-build-script-build b/arch/toml_learning/target/debug/.fingerprint/syn-ca295c6494f2b39c/run-build-script-build-script-build new file mode 100644 index 00000000..d06bd7e6 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/syn-ca295c6494f2b39c/run-build-script-build-script-build @@ -0,0 +1 @@ +6246cbcd616b232c \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/syn-ca295c6494f2b39c/run-build-script-build-script-build.json b/arch/toml_learning/target/debug/.fingerprint/syn-ca295c6494f2b39c/run-build-script-build-script-build.json new file mode 100644 index 00000000..8377eb4d --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/syn-ca295c6494f2b39c/run-build-script-build-script-build.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"","target":0,"profile":0,"path":0,"deps":[[12763460456890314314,"build_script_build",false,1597487168663975139]],"local":[{"Precalculated":"1.0.45"}],"rustflags":[],"metadata":0} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-208d529ca3eead4d/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/toml_learning-208d529ca3eead4d/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-208d529ca3eead4d/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-208d529ca3eead4d/output-test-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-208d529ca3eead4d/output-test-bin-toml_learning new file mode 100644 index 00000000..df454366 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-208d529ca3eead4d/output-test-bin-toml_learning @@ -0,0 +1,6 @@ +{"message":"unused import: `std::path::Path`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":45,"byte_end":60,"line_start":4,"line_end":4,"column_start":5,"column_end":20,"is_primary":true,"text":[{"text":"use std::path::Path;","highlight_start":5,"highlight_end":20}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"`#[warn(unused_imports)]` on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":41,"byte_end":61,"line_start":4,"line_end":4,"column_start":1,"column_end":21,"is_primary":true,"text":[{"text":"use std::path::Path;","highlight_start":1,"highlight_end":21}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `std::path::Path`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:4:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m4\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse std::path::Path;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^^^^^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: `#[warn(unused_imports)]` on by default\u001b[0m\n\n"} +{"message":"unused import: `std::collections::HashMap`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":66,"byte_end":91,"line_start":5,"line_end":5,"column_start":5,"column_end":30,"is_primary":true,"text":[{"text":"use std::collections::HashMap;","highlight_start":5,"highlight_end":30}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":62,"byte_end":92,"line_start":5,"line_end":5,"column_start":1,"column_end":31,"is_primary":true,"text":[{"text":"use std::collections::HashMap;","highlight_start":1,"highlight_end":31}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `std::collections::HashMap`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:5:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m5\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse std::collections::HashMap;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^^^^^^^^^^^^^^^\u001b[0m\n\n"} +{"message":"unused import: `glob::glob`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":112,"byte_end":122,"line_start":7,"line_end":7,"column_start":5,"column_end":15,"is_primary":true,"text":[{"text":"use glob::glob;","highlight_start":5,"highlight_end":15}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":108,"byte_end":123,"line_start":7,"line_end":7,"column_start":1,"column_end":16,"is_primary":true,"text":[{"text":"use glob::glob;","highlight_start":1,"highlight_end":16}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `glob::glob`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:7:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m7\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse glob::glob;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^\u001b[0m\n\n"} +{"message":"mismatched types","code":{"code":"E0308","explanation":"Expected type did not match the received type.\n\nErroneous code example:\n\n```compile_fail,E0308\nlet x: i32 = \"I am not a number!\";\n// ~~~ ~~~~~~~~~~~~~~~~~~~~\n// | |\n// | initializing expression;\n// | compiler infers type `&str`\n// |\n// type `i32` assigned to variable `x`\n```\n\nThis error occurs when the compiler is unable to infer the concrete type of a\nvariable. It can occur in several cases, the most common being a mismatch\nbetween two types: the type the author explicitly assigned, and the type the\ncompiler inferred.\n"},"level":"error","spans":[{"file_name":"src/main.rs","byte_start":370,"byte_end":378,"line_start":15,"line_end":15,"column_start":2,"column_end":10,"is_primary":true,"text":[{"text":"\tsettings","highlight_start":2,"highlight_end":10}],"label":"expected `()`, found struct `config::Config`","suggested_replacement":null,"suggestion_applicability":null,"expansion":null},{"file_name":"src/main.rs","byte_start":136,"byte_end":136,"line_start":11,"line_end":11,"column_start":1,"column_end":1,"is_primary":false,"text":[{"text":"{","highlight_start":1,"highlight_end":1}],"label":"expected `()` because of default return type","suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror[E0308]\u001b[0m\u001b[0m\u001b[1m: mismatched types\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:15:2\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m11\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m{\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m-\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12mexpected `()` because of default return type\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m...\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m15\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m settings\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^^^^^^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9mexpected `()`, found struct `config::Config`\u001b[0m\n\n"} +{"message":"aborting due to previous error; 3 warnings emitted","code":null,"level":"error","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror\u001b[0m\u001b[0m\u001b[1m: aborting due to previous error; 3 warnings emitted\u001b[0m\n\n"} +{"message":"For more information about this error, try `rustc --explain E0308`.","code":null,"level":"failure-note","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1mFor more information about this error, try `rustc --explain E0308`.\u001b[0m\n"} diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-33399023b514f49c/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/toml_learning-33399023b514f49c/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-33399023b514f49c/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-33399023b514f49c/output-test-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-33399023b514f49c/output-test-bin-toml_learning new file mode 100644 index 00000000..194efed2 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-33399023b514f49c/output-test-bin-toml_learning @@ -0,0 +1,3 @@ +{"message":"can't find crate for `lazy_static`","code":{"code":"E0463","explanation":"A plugin/crate was declared but cannot be found.\n\nErroneous code example:\n\n```compile_fail,E0463\n#![feature(plugin)]\n#![plugin(cookie_monster)] // error: can't find crate for `cookie_monster`\nextern crate cake_is_a_lie; // error: can't find crate for `cake_is_a_lie`\n```\n\nYou need to link your code to the relevant crate in order to be able to use it\n(through Cargo or the `-L` option of rustc example). Plugins are crates as\nwell, and you link to them the same way.\n"},"level":"error","spans":[{"file_name":"src/main.rs","byte_start":53,"byte_end":78,"line_start":4,"line_end":4,"column_start":1,"column_end":26,"is_primary":true,"text":[{"text":"extern crate lazy_static;","highlight_start":1,"highlight_end":26}],"label":"can't find crate","suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror[E0463]\u001b[0m\u001b[0m\u001b[1m: can't find crate for `lazy_static`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:4:1\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m4\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0mextern crate lazy_static;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^^^^^^^^^^^^^^^^^^^^^^^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9mcan't find crate\u001b[0m\n\n"} +{"message":"aborting due to previous error","code":null,"level":"error","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror\u001b[0m\u001b[0m\u001b[1m: aborting due to previous error\u001b[0m\n\n"} +{"message":"For more information about this error, try `rustc --explain E0463`.","code":null,"level":"failure-note","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1mFor more information about this error, try `rustc --explain E0463`.\u001b[0m\n"} diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/dep-test-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/dep-test-bin-toml_learning new file mode 100644 index 00000000..cdefce33 Binary files /dev/null and b/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/dep-test-bin-toml_learning differ diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/output-test-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/output-test-bin-toml_learning new file mode 100644 index 00000000..361ecd7b --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/output-test-bin-toml_learning @@ -0,0 +1,2 @@ +{"message":"unused imports: `Environment`, `Value`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":27,"byte_end":38,"line_start":1,"line_end":1,"column_start":28,"column_end":39,"is_primary":true,"text":[{"text":"use config::{Config, File, Environment, Value};","highlight_start":28,"highlight_end":39}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null},{"file_name":"src/main.rs","byte_start":40,"byte_end":45,"line_start":1,"line_end":1,"column_start":41,"column_end":46,"is_primary":true,"text":[{"text":"use config::{Config, File, Environment, Value};","highlight_start":41,"highlight_end":46}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"`#[warn(unused_imports)]` on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"remove the unused imports","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":25,"byte_end":45,"line_start":1,"line_end":1,"column_start":26,"column_end":46,"is_primary":true,"text":[{"text":"use config::{Config, File, Environment, Value};","highlight_start":26,"highlight_end":46}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused imports: `Environment`, `Value`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:1:28\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m1\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse config::{Config, File, Environment, Value};\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: `#[warn(unused_imports)]` on by default\u001b[0m\n\n"} +{"message":"1 warning emitted","code":null,"level":"warning","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: 1 warning emitted\u001b[0m\n\n"} diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/test-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/test-bin-toml_learning new file mode 100644 index 00000000..1d3f20f7 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/test-bin-toml_learning @@ -0,0 +1 @@ +f83a362512c21d8f \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/test-bin-toml_learning.json b/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/test-bin-toml_learning.json new file mode 100644 index 00000000..ab3c4525 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-3466204c4e7cc508/test-bin-toml_learning.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":5276335068378583393,"profile":936164052202214828,"path":1036222786711178230,"deps":[[1122423871155493656,"config",false,12076975891298977181],[2428412896888309155,"notify",false,683570404051705814],[7231915146259649043,"toml",false,12188567688172400698],[9391121987967877039,"serde",false,13841648393061603091],[11936193490253047359,"glob",false,10717629618522360262],[13968346382989319657,"lazy_static",false,14528124247894937362]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/toml_learning-3466204c4e7cc508/dep-test-bin-toml_learning"}}],"rustflags":[],"metadata":3437543006848290768} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/bin-toml_learning new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/bin-toml_learning.json b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/bin-toml_learning.json new file mode 100644 index 00000000..517b4e0d --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/bin-toml_learning.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":5276335068378583393,"profile":14762027784537775720,"path":1036222786711178230,"deps":[[1122423871155493656,"config",false,12076975891298977181],[2428412896888309155,"notify",false,683570404051705814],[6773936731788865364,"serde_derive",false,3618971896160771796],[7231915146259649043,"toml",false,12188567688172400698],[9391121987967877039,"serde",false,13841648393061603091],[11936193490253047359,"glob",false,10717629618522360262],[13968346382989319657,"lazy_static",false,14528124247894937362]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/toml_learning-6271efe665464c9f/dep-bin-toml_learning"}}],"rustflags":[],"metadata":3437543006848290768} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/dep-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/dep-bin-toml_learning new file mode 100644 index 00000000..cdefce33 Binary files /dev/null and b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/dep-bin-toml_learning differ diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/output-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/output-bin-toml_learning new file mode 100644 index 00000000..4f86c822 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6271efe665464c9f/output-bin-toml_learning @@ -0,0 +1,9 @@ +{"message":"comparison operators cannot be chained","code":null,"level":"error","spans":[{"file_name":"src/main.rs","byte_start":462,"byte_end":463,"line_start":16,"line_end":16,"column_start":34,"column_end":35,"is_primary":true,"text":[{"text":"\t\tif toml::value::Value::try_from(val)","highlight_start":34,"highlight_end":35}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null},{"file_name":"src/main.rs","byte_start":484,"byte_end":485,"line_start":16,"line_end":16,"column_start":56,"column_end":57,"is_primary":true,"text":[{"text":"\t\tif toml::value::Value::try_from(val)","highlight_start":56,"highlight_end":57}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"use `::<...>` instead of `<...>` to specify type arguments","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":462,"byte_end":462,"line_start":16,"line_end":16,"column_start":34,"column_end":34,"is_primary":true,"text":[{"text":"\t\tif toml::value::Value::try_from(val)","highlight_start":34,"highlight_end":34}],"label":null,"suggested_replacement":"::","suggestion_applicability":"MaybeIncorrect","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror\u001b[0m\u001b[0m\u001b[1m: comparison operators cannot be chained\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:16:34\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m16\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m if toml::value::Value::try_from(val)\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;14mhelp\u001b[0m\u001b[0m: use `::<...>` instead of `<...>` to specify type arguments\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m16\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m if toml::value::Value::try_from::(val)\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;14m^^\u001b[0m\n\n"} +{"message":"expected `{`, found `.`","code":null,"level":"error","spans":[{"file_name":"src/main.rs","byte_start":494,"byte_end":495,"line_start":17,"line_end":17,"column_start":4,"column_end":5,"is_primary":true,"text":[{"text":"\t\t\t.unwrap()","highlight_start":4,"highlight_end":5}],"label":"expected `{`","suggested_replacement":null,"suggestion_applicability":null,"expansion":null},{"file_name":"src/main.rs","byte_start":431,"byte_end":433,"line_start":16,"line_end":16,"column_start":3,"column_end":5,"is_primary":false,"text":[{"text":"\t\tif toml::value::Value::try_from(val)","highlight_start":3,"highlight_end":5}],"label":"this `if` expression has a condition, but no block","suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror\u001b[0m\u001b[0m\u001b[1m: expected `{`, found `.`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:17:4\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m16\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m if toml::value::Value::try_from(val)\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12mthis `if` expression has a condition, but no block\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m17\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m .unwrap()\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9mexpected `{`\u001b[0m\n\n"} +{"message":"unused import: `std::env`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":4,"byte_end":12,"line_start":1,"line_end":1,"column_start":5,"column_end":13,"is_primary":true,"text":[{"text":"use std::env;","highlight_start":5,"highlight_end":13}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"`#[warn(unused_imports)]` on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":0,"byte_end":13,"line_start":1,"line_end":1,"column_start":1,"column_end":14,"is_primary":true,"text":[{"text":"use std::env;","highlight_start":1,"highlight_end":14}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `std::env`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:1:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m1\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse std::env;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: `#[warn(unused_imports)]` on by default\u001b[0m\n\n"} +{"message":"unused import: `Environment`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":41,"byte_end":52,"line_start":2,"line_end":2,"column_start":28,"column_end":39,"is_primary":true,"text":[{"text":"use config::{Config, File, Environment};","highlight_start":28,"highlight_end":39}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the unused import","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":39,"byte_end":52,"line_start":2,"line_end":2,"column_start":26,"column_end":39,"is_primary":true,"text":[{"text":"use config::{Config, File, Environment};","highlight_start":26,"highlight_end":39}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `Environment`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:2:28\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m2\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse config::{Config, File, Environment};\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^\u001b[0m\n\n"} +{"message":"unused import: `std::path::PathBuf`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":59,"byte_end":77,"line_start":3,"line_end":3,"column_start":5,"column_end":23,"is_primary":true,"text":[{"text":"use std::path::PathBuf;","highlight_start":5,"highlight_end":23}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":55,"byte_end":78,"line_start":3,"line_end":3,"column_start":1,"column_end":24,"is_primary":true,"text":[{"text":"use std::path::PathBuf;","highlight_start":1,"highlight_end":24}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `std::path::PathBuf`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:3:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m3\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse std::path::PathBuf;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^^^^^^^^\u001b[0m\n\n"} +{"message":"unused import: `serde::de::Deserializer`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":94,"byte_end":117,"line_start":5,"line_end":5,"column_start":5,"column_end":28,"is_primary":true,"text":[{"text":"use serde::de::Deserializer;","highlight_start":5,"highlight_end":28}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":90,"byte_end":118,"line_start":5,"line_end":5,"column_start":1,"column_end":29,"is_primary":true,"text":[{"text":"use serde::de::Deserializer;","highlight_start":1,"highlight_end":29}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `serde::de::Deserializer`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:5:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m5\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse serde::de::Deserializer;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^^^^^^^^^^^^^\u001b[0m\n\n"} +{"message":"unused import: `serde::Deserialize`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":123,"byte_end":141,"line_start":6,"line_end":6,"column_start":5,"column_end":23,"is_primary":true,"text":[{"text":"use serde::Deserialize;","highlight_start":5,"highlight_end":23}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":119,"byte_end":142,"line_start":6,"line_end":6,"column_start":1,"column_end":24,"is_primary":true,"text":[{"text":"use serde::Deserialize;","highlight_start":1,"highlight_end":24}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `serde::Deserialize`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:6:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m6\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse serde::Deserialize;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^^^^^^^^\u001b[0m\n\n"} +{"message":"unused import: `toml::*`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":147,"byte_end":154,"line_start":7,"line_end":7,"column_start":5,"column_end":12,"is_primary":true,"text":[{"text":"use toml::*;","highlight_start":5,"highlight_end":12}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":143,"byte_end":155,"line_start":7,"line_end":7,"column_start":1,"column_end":13,"is_primary":true,"text":[{"text":"use toml::*;","highlight_start":1,"highlight_end":13}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `toml::*`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:7:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m7\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse toml::*;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^\u001b[0m\n\n"} +{"message":"aborting due to 2 previous errors; 6 warnings emitted","code":null,"level":"error","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror\u001b[0m\u001b[0m\u001b[1m: aborting due to 2 previous errors; 6 warnings emitted\u001b[0m\n\n"} diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-6419956b58e4a978/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6419956b58e4a978/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6419956b58e4a978/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-6419956b58e4a978/output-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6419956b58e4a978/output-bin-toml_learning new file mode 100644 index 00000000..e7f7d0c3 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-6419956b58e4a978/output-bin-toml_learning @@ -0,0 +1,9 @@ +{"message":"failed to resolve: use of undeclared type or module `RwLock`","code":{"code":"E0433","explanation":"An undeclared type or module was used.\n\nErroneous code example:\n\n```compile_fail,E0433\nlet map = HashMap::new();\n// error: failed to resolve: use of undeclared type or module `HashMap`\n```\n\nPlease verify you didn't misspell the type/module's name or that you didn't\nforget to import it:\n\n\n```\nuse std::collections::HashMap; // HashMap has been imported.\nlet map: HashMap = HashMap::new(); // So it can be used!\n```\n"},"level":"error","spans":[{"file_name":"src/main.rs","byte_start":220,"byte_end":226,"line_start":11,"line_end":11,"column_start":43,"column_end":49,"is_primary":true,"text":[{"text":" static ref SETTINGS: RwLock = RwLock::new({","highlight_start":43,"highlight_end":49}],"label":"use of undeclared type or module `RwLock`","suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror[E0433]\u001b[0m\u001b[0m\u001b[1m: failed to resolve: use of undeclared type or module `RwLock`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:11:43\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m11\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m static ref SETTINGS: RwLock = RwLock::new({\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^^^^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9muse of undeclared type or module `RwLock`\u001b[0m\n\n"} +{"message":"cannot find type `RwLock` in this scope","code":{"code":"E0412","explanation":"A used type name is not in scope.\n\nErroneous code examples:\n\n```compile_fail,E0412\nimpl Something {} // error: type name `Something` is not in scope\n\n// or:\n\ntrait Foo {\n fn bar(N); // error: type name `N` is not in scope\n}\n\n// or:\n\nfn foo(x: T) {} // type name `T` is not in scope\n```\n\nTo fix this error, please verify you didn't misspell the type name, you did\ndeclare it or imported it into the scope. Examples:\n\n```\nstruct Something;\n\nimpl Something {} // ok!\n\n// or:\n\ntrait Foo {\n type N;\n\n fn bar(_: Self::N); // ok!\n}\n\n// or:\n\nfn foo(x: T) {} // ok!\n```\n\nAnother case that causes this error is when a type is imported into a parent\nmodule. To fix this, you can follow the suggestion and use File directly or\n`use super::File;` which will import the types from the parent namespace. An\nexample that causes this error is below:\n\n```compile_fail,E0412\nuse std::fs::File;\n\nmod foo {\n fn some_function(f: File) {}\n}\n```\n\n```\nuse std::fs::File;\n\nmod foo {\n // either\n use super::File;\n // or\n // use std::fs::File;\n fn foo(f: File) {}\n}\n# fn main() {} // don't insert it for us; that'll break imports\n```\n"},"level":"error","spans":[{"file_name":"src/main.rs","byte_start":203,"byte_end":209,"line_start":11,"line_end":11,"column_start":26,"column_end":32,"is_primary":true,"text":[{"text":" static ref SETTINGS: RwLock = RwLock::new({","highlight_start":26,"highlight_end":32}],"label":"not found in this scope","suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"consider importing this struct","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":79,"byte_end":79,"line_start":5,"line_end":5,"column_start":1,"column_end":1,"is_primary":true,"text":[{"text":"use std::path::Path;","highlight_start":1,"highlight_end":1}],"label":null,"suggested_replacement":"use std::sync::RwLock;\n","suggestion_applicability":"Unspecified","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror[E0412]\u001b[0m\u001b[0m\u001b[1m: cannot find type `RwLock` in this scope\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:11:26\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m11\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m static ref SETTINGS: RwLock = RwLock::new({\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^^^^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9mnot found in this scope\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;14mhelp\u001b[0m\u001b[0m: consider importing this struct\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m5\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse std::sync::RwLock;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\n"} +{"message":"unused import: `std::path::Path`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":83,"byte_end":98,"line_start":5,"line_end":5,"column_start":5,"column_end":20,"is_primary":true,"text":[{"text":"use std::path::Path;","highlight_start":5,"highlight_end":20}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"`#[warn(unused_imports)]` on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":79,"byte_end":99,"line_start":5,"line_end":5,"column_start":1,"column_end":21,"is_primary":true,"text":[{"text":"use std::path::Path;","highlight_start":1,"highlight_end":21}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `std::path::Path`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:5:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m5\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse std::path::Path;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^^^^^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: `#[warn(unused_imports)]` on by default\u001b[0m\n\n"} +{"message":"unused import: `glob::glob`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":150,"byte_end":160,"line_start":8,"line_end":8,"column_start":5,"column_end":15,"is_primary":true,"text":[{"text":"use glob::glob;","highlight_start":5,"highlight_end":15}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":146,"byte_end":161,"line_start":8,"line_end":8,"column_start":1,"column_end":16,"is_primary":true,"text":[{"text":"use glob::glob;","highlight_start":1,"highlight_end":16}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `glob::glob`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:8:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m8\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse glob::glob;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^\u001b[0m\n\n"} +{"message":"use of deprecated item 'std::sync::ONCE_INIT': the `new` function is now preferred","code":{"code":"deprecated","explanation":null},"level":"warning","spans":[{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lazy.rs","byte_start":1041,"byte_end":1064,"line_start":37,"line_end":37,"column_start":87,"column_end":110,"is_primary":true,"text":[{"text":" static mut $NAME: $crate::lazy::Lazy<$T> = $crate::lazy::Lazy(0 as *const $T, $crate::lazy::ONCE_INIT);","highlight_start":87,"highlight_end":110}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":{"span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":4136,"byte_end":4168,"line_start":137,"line_end":137,"column_start":25,"column_end":57,"is_primary":false,"text":[{"text":" __lazy_static_create!(LAZY, $T);","highlight_start":25,"highlight_end":57}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":{"span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":3620,"byte_end":3665,"line_start":123,"line_end":123,"column_start":9,"column_end":54,"is_primary":false,"text":[{"text":" __lazy_static_internal!(@TAIL, $N : $T = $e);","highlight_start":9,"highlight_end":54}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":{"span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":5092,"byte_end":5165,"line_start":167,"line_end":167,"column_start":9,"column_end":82,"is_primary":false,"text":[{"text":" __lazy_static_internal!($(#[$attr])* () static ref $N : $T = $e; $($t)*);","highlight_start":9,"highlight_end":82}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":{"span":{"file_name":"src/main.rs","byte_start":163,"byte_end":458,"line_start":10,"line_end":17,"column_start":1,"column_end":2,"is_primary":false,"text":[{"text":"lazy_static! {","highlight_start":1,"highlight_end":15},{"text":" static ref SETTINGS: RwLock = RwLock::new({","highlight_start":1,"highlight_end":56},{"text":" let mut settings = Config::default();","highlight_start":1,"highlight_end":46},{"text":" settings.merge(File::with_name(\"/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/helper-manifest.toml\")).unwrap();","highlight_start":1,"highlight_end":151},{"text":"","highlight_start":1,"highlight_end":1},{"text":" settings","highlight_start":1,"highlight_end":17},{"text":" });","highlight_start":1,"highlight_end":8},{"text":"}","highlight_start":1,"highlight_end":2}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null},"macro_decl_name":"lazy_static!","def_site_span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":4901,"byte_end":5560,"line_start":164,"line_end":176,"column_start":1,"column_end":2,"is_primary":false,"text":[{"text":"macro_rules! lazy_static {","highlight_start":1,"highlight_end":1},{"text":" ($(#[$attr:meta])* static ref $N:ident : $T:ty = $e:expr; $($t:tt)*) => {","highlight_start":1,"highlight_end":1},{"text":" // use `()` to explicitly forward the information about private items","highlight_start":1,"highlight_end":1},{"text":" __lazy_static_internal!($(#[$attr])* () static ref $N : $T = $e; $($t)*);","highlight_start":1,"highlight_end":1},{"text":" };","highlight_start":1,"highlight_end":1},{"text":" ($(#[$attr:meta])* pub static ref $N:ident : $T:ty = $e:expr; $($t:tt)*) => {","highlight_start":1,"highlight_end":1},{"text":" __lazy_static_internal!($(#[$attr])* (pub) static ref $N : $T = $e; $($t)*);","highlight_start":1,"highlight_end":1},{"text":" };","highlight_start":1,"highlight_end":1},{"text":" ($(#[$attr:meta])* pub ($($vis:tt)+) static ref $N:ident : $T:ty = $e:expr; $($t:tt)*) => {","highlight_start":1,"highlight_end":1},{"text":" __lazy_static_internal!($(#[$attr])* (pub ($($vis)+)) static ref $N : $T = $e; $($t)*);","highlight_start":1,"highlight_end":1},{"text":" };","highlight_start":1,"highlight_end":1},{"text":" () => ()","highlight_start":1,"highlight_end":1},{"text":"}","highlight_start":1,"highlight_end":2}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}}},"macro_decl_name":"__lazy_static_internal!","def_site_span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":3259,"byte_end":4883,"line_start":118,"line_end":161,"column_start":1,"column_end":2,"is_primary":false,"text":[{"text":"macro_rules! __lazy_static_internal {","highlight_start":1,"highlight_end":38},{"text":" // optional visibility restrictions are wrapped in `()` to allow for","highlight_start":1,"highlight_end":73},{"text":" // explicitly passing otherwise implicit information about private items","highlight_start":1,"highlight_end":77},{"text":" ($(#[$attr:meta])* ($($vis:tt)*) static ref $N:ident : $T:ty = $e:expr; $($t:tt)*) => {","highlight_start":1,"highlight_end":92},{"text":" __lazy_static_internal!(@MAKE TY, $(#[$attr])*, ($($vis)*), $N);","highlight_start":1,"highlight_end":73},{"text":" __lazy_static_internal!(@TAIL, $N : $T = $e);","highlight_start":1,"highlight_end":54},{"text":" lazy_static!($($t)*);","highlight_start":1,"highlight_end":30},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" (@TAIL, $N:ident : $T:ty = $e:expr) => {","highlight_start":1,"highlight_end":45},{"text":" impl $crate::__Deref for $N {","highlight_start":1,"highlight_end":38},{"text":" type Target = $T;","highlight_start":1,"highlight_end":30},{"text":" #[allow(unsafe_code)]","highlight_start":1,"highlight_end":34},{"text":" fn deref(&self) -> &$T {","highlight_start":1,"highlight_end":37},{"text":" unsafe {","highlight_start":1,"highlight_end":25},{"text":" #[inline(always)]","highlight_start":1,"highlight_end":38},{"text":" fn __static_ref_initialize() -> $T { $e }","highlight_start":1,"highlight_end":62},{"text":"","highlight_start":1,"highlight_end":1},{"text":" #[inline(always)]","highlight_start":1,"highlight_end":38},{"text":" unsafe fn __stability() -> &'static $T {","highlight_start":1,"highlight_end":61},{"text":" __lazy_static_create!(LAZY, $T);","highlight_start":1,"highlight_end":57},{"text":" LAZY.get(__static_ref_initialize)","highlight_start":1,"highlight_end":58},{"text":" }","highlight_start":1,"highlight_end":22},{"text":" __stability()","highlight_start":1,"highlight_end":34},{"text":" }","highlight_start":1,"highlight_end":18},{"text":" }","highlight_start":1,"highlight_end":14},{"text":" }","highlight_start":1,"highlight_end":10},{"text":" impl $crate::LazyStatic for $N {","highlight_start":1,"highlight_end":41},{"text":" fn initialize(lazy: &Self) {","highlight_start":1,"highlight_end":41},{"text":" let _ = &**lazy;","highlight_start":1,"highlight_end":33},{"text":" }","highlight_start":1,"highlight_end":14},{"text":" }","highlight_start":1,"highlight_end":10},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" // `vis` is wrapped in `()` to prevent parsing ambiguity","highlight_start":1,"highlight_end":61},{"text":" (@MAKE TY, $(#[$attr:meta])*, ($($vis:tt)*), $N:ident) => {","highlight_start":1,"highlight_end":64},{"text":" #[allow(missing_copy_implementations)]","highlight_start":1,"highlight_end":47},{"text":" #[allow(non_camel_case_types)]","highlight_start":1,"highlight_end":39},{"text":" #[allow(dead_code)]","highlight_start":1,"highlight_end":28},{"text":" $(#[$attr])*","highlight_start":1,"highlight_end":21},{"text":" $($vis)* struct $N {__private_field: ()}","highlight_start":1,"highlight_end":49},{"text":" #[doc(hidden)]","highlight_start":1,"highlight_end":23},{"text":" $($vis)* static $N: $N = $N {__private_field: ()};","highlight_start":1,"highlight_end":59},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" () => ()","highlight_start":1,"highlight_end":13},{"text":"}","highlight_start":1,"highlight_end":2}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}}},"macro_decl_name":"__lazy_static_internal!","def_site_span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":3259,"byte_end":4883,"line_start":118,"line_end":161,"column_start":1,"column_end":2,"is_primary":false,"text":[{"text":"macro_rules! __lazy_static_internal {","highlight_start":1,"highlight_end":38},{"text":" // optional visibility restrictions are wrapped in `()` to allow for","highlight_start":1,"highlight_end":73},{"text":" // explicitly passing otherwise implicit information about private items","highlight_start":1,"highlight_end":77},{"text":" ($(#[$attr:meta])* ($($vis:tt)*) static ref $N:ident : $T:ty = $e:expr; $($t:tt)*) => {","highlight_start":1,"highlight_end":92},{"text":" __lazy_static_internal!(@MAKE TY, $(#[$attr])*, ($($vis)*), $N);","highlight_start":1,"highlight_end":73},{"text":" __lazy_static_internal!(@TAIL, $N : $T = $e);","highlight_start":1,"highlight_end":54},{"text":" lazy_static!($($t)*);","highlight_start":1,"highlight_end":30},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" (@TAIL, $N:ident : $T:ty = $e:expr) => {","highlight_start":1,"highlight_end":45},{"text":" impl $crate::__Deref for $N {","highlight_start":1,"highlight_end":38},{"text":" type Target = $T;","highlight_start":1,"highlight_end":30},{"text":" #[allow(unsafe_code)]","highlight_start":1,"highlight_end":34},{"text":" fn deref(&self) -> &$T {","highlight_start":1,"highlight_end":37},{"text":" unsafe {","highlight_start":1,"highlight_end":25},{"text":" #[inline(always)]","highlight_start":1,"highlight_end":38},{"text":" fn __static_ref_initialize() -> $T { $e }","highlight_start":1,"highlight_end":62},{"text":"","highlight_start":1,"highlight_end":1},{"text":" #[inline(always)]","highlight_start":1,"highlight_end":38},{"text":" unsafe fn __stability() -> &'static $T {","highlight_start":1,"highlight_end":61},{"text":" __lazy_static_create!(LAZY, $T);","highlight_start":1,"highlight_end":57},{"text":" LAZY.get(__static_ref_initialize)","highlight_start":1,"highlight_end":58},{"text":" }","highlight_start":1,"highlight_end":22},{"text":" __stability()","highlight_start":1,"highlight_end":34},{"text":" }","highlight_start":1,"highlight_end":18},{"text":" }","highlight_start":1,"highlight_end":14},{"text":" }","highlight_start":1,"highlight_end":10},{"text":" impl $crate::LazyStatic for $N {","highlight_start":1,"highlight_end":41},{"text":" fn initialize(lazy: &Self) {","highlight_start":1,"highlight_end":41},{"text":" let _ = &**lazy;","highlight_start":1,"highlight_end":33},{"text":" }","highlight_start":1,"highlight_end":14},{"text":" }","highlight_start":1,"highlight_end":10},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" // `vis` is wrapped in `()` to prevent parsing ambiguity","highlight_start":1,"highlight_end":61},{"text":" (@MAKE TY, $(#[$attr:meta])*, ($($vis:tt)*), $N:ident) => {","highlight_start":1,"highlight_end":64},{"text":" #[allow(missing_copy_implementations)]","highlight_start":1,"highlight_end":47},{"text":" #[allow(non_camel_case_types)]","highlight_start":1,"highlight_end":39},{"text":" #[allow(dead_code)]","highlight_start":1,"highlight_end":28},{"text":" $(#[$attr])*","highlight_start":1,"highlight_end":21},{"text":" $($vis)* struct $N {__private_field: ()}","highlight_start":1,"highlight_end":49},{"text":" #[doc(hidden)]","highlight_start":1,"highlight_end":23},{"text":" $($vis)* static $N: $N = $N {__private_field: ()};","highlight_start":1,"highlight_end":59},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" () => ()","highlight_start":1,"highlight_end":13},{"text":"}","highlight_start":1,"highlight_end":2}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}}},"macro_decl_name":"__lazy_static_create!","def_site_span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lazy.rs","byte_start":889,"byte_end":1074,"line_start":35,"line_end":39,"column_start":1,"column_end":2,"is_primary":false,"text":[{"text":"macro_rules! __lazy_static_create {","highlight_start":1,"highlight_end":1},{"text":" ($NAME:ident, $T:ty) => {","highlight_start":1,"highlight_end":1},{"text":" static mut $NAME: $crate::lazy::Lazy<$T> = $crate::lazy::Lazy(0 as *const $T, $crate::lazy::ONCE_INIT);","highlight_start":1,"highlight_end":1},{"text":" }","highlight_start":1,"highlight_end":1},{"text":"}","highlight_start":1,"highlight_end":2}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}}}],"children":[{"message":"`#[warn(deprecated)]` on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: use of deprecated item 'std::sync::ONCE_INIT': the `new` function is now preferred\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:10:1\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m10\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[33m/\u001b[0m\u001b[0m \u001b[0m\u001b[0mlazy_static! {\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m11\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[33m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m static ref SETTINGS: RwLock = RwLock::new({\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m12\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[33m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m let mut settings = Config::default();\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m13\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[33m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m settings.merge(File::with_name(\"/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/helper-manifest.toml\")).unwrap();\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m...\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m16\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[33m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m });\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m17\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[33m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m}\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[33m|_^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: `#[warn(deprecated)]` on by default\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: this warning originates in a macro (in Nightly builds, run with -Z macro-backtrace for more info)\u001b[0m\n\n"} +{"message":"no method named `read` found for struct `SETTINGS` in the current scope","code":{"code":"E0599","explanation":"This error occurs when a method is used on a type which doesn't implement it:\n\nErroneous code example:\n\n```compile_fail,E0599\nstruct Mouth;\n\nlet x = Mouth;\nx.chocolate(); // error: no method named `chocolate` found for type `Mouth`\n // in the current scope\n```\n\nIn this case, you need to implement the `chocolate` method to fix the error:\n\n```\nstruct Mouth;\n\nimpl Mouth {\n fn chocolate(&self) { // We implement the `chocolate` method here.\n println!(\"Hmmm! I love chocolate!\");\n }\n}\n\nlet x = Mouth;\nx.chocolate(); // ok!\n```\n"},"level":"error","spans":[{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":4748,"byte_end":4757,"line_start":156,"line_end":156,"column_start":18,"column_end":27,"is_primary":false,"text":[{"text":" $($vis)* struct $N {__private_field: ()}","highlight_start":18,"highlight_end":27}],"label":"method `read` not found for this","suggested_replacement":null,"suggestion_applicability":null,"expansion":{"span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":3547,"byte_end":3611,"line_start":122,"line_end":122,"column_start":9,"column_end":73,"is_primary":false,"text":[{"text":" __lazy_static_internal!(@MAKE TY, $(#[$attr])*, ($($vis)*), $N);","highlight_start":9,"highlight_end":73}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":{"span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":5092,"byte_end":5165,"line_start":167,"line_end":167,"column_start":9,"column_end":82,"is_primary":false,"text":[{"text":" __lazy_static_internal!($(#[$attr])* () static ref $N : $T = $e; $($t)*);","highlight_start":9,"highlight_end":82}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":{"span":{"file_name":"src/main.rs","byte_start":163,"byte_end":458,"line_start":10,"line_end":17,"column_start":1,"column_end":2,"is_primary":false,"text":[{"text":"lazy_static! {","highlight_start":1,"highlight_end":15},{"text":" static ref SETTINGS: RwLock = RwLock::new({","highlight_start":1,"highlight_end":56},{"text":" let mut settings = Config::default();","highlight_start":1,"highlight_end":46},{"text":" settings.merge(File::with_name(\"/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/helper-manifest.toml\")).unwrap();","highlight_start":1,"highlight_end":151},{"text":"","highlight_start":1,"highlight_end":1},{"text":" settings","highlight_start":1,"highlight_end":17},{"text":" });","highlight_start":1,"highlight_end":8},{"text":"}","highlight_start":1,"highlight_end":2}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null},"macro_decl_name":"lazy_static!","def_site_span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":4901,"byte_end":5560,"line_start":164,"line_end":176,"column_start":1,"column_end":2,"is_primary":false,"text":[{"text":"macro_rules! lazy_static {","highlight_start":1,"highlight_end":27},{"text":" ($(#[$attr:meta])* static ref $N:ident : $T:ty = $e:expr; $($t:tt)*) => {","highlight_start":1,"highlight_end":78},{"text":" // use `()` to explicitly forward the information about private items","highlight_start":1,"highlight_end":78},{"text":" __lazy_static_internal!($(#[$attr])* () static ref $N : $T = $e; $($t)*);","highlight_start":1,"highlight_end":82},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" ($(#[$attr:meta])* pub static ref $N:ident : $T:ty = $e:expr; $($t:tt)*) => {","highlight_start":1,"highlight_end":82},{"text":" __lazy_static_internal!($(#[$attr])* (pub) static ref $N : $T = $e; $($t)*);","highlight_start":1,"highlight_end":85},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" ($(#[$attr:meta])* pub ($($vis:tt)+) static ref $N:ident : $T:ty = $e:expr; $($t:tt)*) => {","highlight_start":1,"highlight_end":96},{"text":" __lazy_static_internal!($(#[$attr])* (pub ($($vis)+)) static ref $N : $T = $e; $($t)*);","highlight_start":1,"highlight_end":96},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" () => ()","highlight_start":1,"highlight_end":13},{"text":"}","highlight_start":1,"highlight_end":2}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}}},"macro_decl_name":"__lazy_static_internal!","def_site_span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":3259,"byte_end":4883,"line_start":118,"line_end":161,"column_start":1,"column_end":2,"is_primary":false,"text":[{"text":"macro_rules! __lazy_static_internal {","highlight_start":1,"highlight_end":38},{"text":" // optional visibility restrictions are wrapped in `()` to allow for","highlight_start":1,"highlight_end":73},{"text":" // explicitly passing otherwise implicit information about private items","highlight_start":1,"highlight_end":77},{"text":" ($(#[$attr:meta])* ($($vis:tt)*) static ref $N:ident : $T:ty = $e:expr; $($t:tt)*) => {","highlight_start":1,"highlight_end":92},{"text":" __lazy_static_internal!(@MAKE TY, $(#[$attr])*, ($($vis)*), $N);","highlight_start":1,"highlight_end":73},{"text":" __lazy_static_internal!(@TAIL, $N : $T = $e);","highlight_start":1,"highlight_end":54},{"text":" lazy_static!($($t)*);","highlight_start":1,"highlight_end":30},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" (@TAIL, $N:ident : $T:ty = $e:expr) => {","highlight_start":1,"highlight_end":45},{"text":" impl $crate::__Deref for $N {","highlight_start":1,"highlight_end":38},{"text":" type Target = $T;","highlight_start":1,"highlight_end":30},{"text":" #[allow(unsafe_code)]","highlight_start":1,"highlight_end":34},{"text":" fn deref(&self) -> &$T {","highlight_start":1,"highlight_end":37},{"text":" unsafe {","highlight_start":1,"highlight_end":25},{"text":" #[inline(always)]","highlight_start":1,"highlight_end":38},{"text":" fn __static_ref_initialize() -> $T { $e }","highlight_start":1,"highlight_end":62},{"text":"","highlight_start":1,"highlight_end":1},{"text":" #[inline(always)]","highlight_start":1,"highlight_end":38},{"text":" unsafe fn __stability() -> &'static $T {","highlight_start":1,"highlight_end":61},{"text":" __lazy_static_create!(LAZY, $T);","highlight_start":1,"highlight_end":57},{"text":" LAZY.get(__static_ref_initialize)","highlight_start":1,"highlight_end":58},{"text":" }","highlight_start":1,"highlight_end":22},{"text":" __stability()","highlight_start":1,"highlight_end":34},{"text":" }","highlight_start":1,"highlight_end":18},{"text":" }","highlight_start":1,"highlight_end":14},{"text":" }","highlight_start":1,"highlight_end":10},{"text":" impl $crate::LazyStatic for $N {","highlight_start":1,"highlight_end":41},{"text":" fn initialize(lazy: &Self) {","highlight_start":1,"highlight_end":41},{"text":" let _ = &**lazy;","highlight_start":1,"highlight_end":33},{"text":" }","highlight_start":1,"highlight_end":14},{"text":" }","highlight_start":1,"highlight_end":10},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" // `vis` is wrapped in `()` to prevent parsing ambiguity","highlight_start":1,"highlight_end":61},{"text":" (@MAKE TY, $(#[$attr:meta])*, ($($vis:tt)*), $N:ident) => {","highlight_start":1,"highlight_end":64},{"text":" #[allow(missing_copy_implementations)]","highlight_start":1,"highlight_end":47},{"text":" #[allow(non_camel_case_types)]","highlight_start":1,"highlight_end":39},{"text":" #[allow(dead_code)]","highlight_start":1,"highlight_end":28},{"text":" $(#[$attr])*","highlight_start":1,"highlight_end":21},{"text":" $($vis)* struct $N {__private_field: ()}","highlight_start":1,"highlight_end":49},{"text":" #[doc(hidden)]","highlight_start":1,"highlight_end":23},{"text":" $($vis)* static $N: $N = $N {__private_field: ()};","highlight_start":1,"highlight_end":59},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" () => ()","highlight_start":1,"highlight_end":13},{"text":"}","highlight_start":1,"highlight_end":2}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}}},"macro_decl_name":"__lazy_static_internal!","def_site_span":{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs","byte_start":3259,"byte_end":4883,"line_start":118,"line_end":161,"column_start":1,"column_end":2,"is_primary":false,"text":[{"text":"macro_rules! __lazy_static_internal {","highlight_start":1,"highlight_end":38},{"text":" // optional visibility restrictions are wrapped in `()` to allow for","highlight_start":1,"highlight_end":73},{"text":" // explicitly passing otherwise implicit information about private items","highlight_start":1,"highlight_end":77},{"text":" ($(#[$attr:meta])* ($($vis:tt)*) static ref $N:ident : $T:ty = $e:expr; $($t:tt)*) => {","highlight_start":1,"highlight_end":92},{"text":" __lazy_static_internal!(@MAKE TY, $(#[$attr])*, ($($vis)*), $N);","highlight_start":1,"highlight_end":73},{"text":" __lazy_static_internal!(@TAIL, $N : $T = $e);","highlight_start":1,"highlight_end":54},{"text":" lazy_static!($($t)*);","highlight_start":1,"highlight_end":30},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" (@TAIL, $N:ident : $T:ty = $e:expr) => {","highlight_start":1,"highlight_end":45},{"text":" impl $crate::__Deref for $N {","highlight_start":1,"highlight_end":38},{"text":" type Target = $T;","highlight_start":1,"highlight_end":30},{"text":" #[allow(unsafe_code)]","highlight_start":1,"highlight_end":34},{"text":" fn deref(&self) -> &$T {","highlight_start":1,"highlight_end":37},{"text":" unsafe {","highlight_start":1,"highlight_end":25},{"text":" #[inline(always)]","highlight_start":1,"highlight_end":38},{"text":" fn __static_ref_initialize() -> $T { $e }","highlight_start":1,"highlight_end":62},{"text":"","highlight_start":1,"highlight_end":1},{"text":" #[inline(always)]","highlight_start":1,"highlight_end":38},{"text":" unsafe fn __stability() -> &'static $T {","highlight_start":1,"highlight_end":61},{"text":" __lazy_static_create!(LAZY, $T);","highlight_start":1,"highlight_end":57},{"text":" LAZY.get(__static_ref_initialize)","highlight_start":1,"highlight_end":58},{"text":" }","highlight_start":1,"highlight_end":22},{"text":" __stability()","highlight_start":1,"highlight_end":34},{"text":" }","highlight_start":1,"highlight_end":18},{"text":" }","highlight_start":1,"highlight_end":14},{"text":" }","highlight_start":1,"highlight_end":10},{"text":" impl $crate::LazyStatic for $N {","highlight_start":1,"highlight_end":41},{"text":" fn initialize(lazy: &Self) {","highlight_start":1,"highlight_end":41},{"text":" let _ = &**lazy;","highlight_start":1,"highlight_end":33},{"text":" }","highlight_start":1,"highlight_end":14},{"text":" }","highlight_start":1,"highlight_end":10},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" // `vis` is wrapped in `()` to prevent parsing ambiguity","highlight_start":1,"highlight_end":61},{"text":" (@MAKE TY, $(#[$attr:meta])*, ($($vis:tt)*), $N:ident) => {","highlight_start":1,"highlight_end":64},{"text":" #[allow(missing_copy_implementations)]","highlight_start":1,"highlight_end":47},{"text":" #[allow(non_camel_case_types)]","highlight_start":1,"highlight_end":39},{"text":" #[allow(dead_code)]","highlight_start":1,"highlight_end":28},{"text":" $(#[$attr])*","highlight_start":1,"highlight_end":21},{"text":" $($vis)* struct $N {__private_field: ()}","highlight_start":1,"highlight_end":49},{"text":" #[doc(hidden)]","highlight_start":1,"highlight_end":23},{"text":" $($vis)* static $N: $N = $N {__private_field: ()};","highlight_start":1,"highlight_end":59},{"text":" };","highlight_start":1,"highlight_end":7},{"text":" () => ()","highlight_start":1,"highlight_end":13},{"text":"}","highlight_start":1,"highlight_end":2}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}}},{"file_name":"src/main.rs","byte_start":583,"byte_end":587,"line_start":25,"line_end":25,"column_start":15,"column_end":19,"is_primary":true,"text":[{"text":" .read()","highlight_start":15,"highlight_end":19}],"label":"method not found in `SETTINGS`","suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"items from traits can only be used if the trait is implemented and in scope","code":null,"level":"help","spans":[],"children":[],"rendered":null},{"message":"the following trait defines an item `read`, perhaps you need to implement it:\ncandidate #1: `std::io::Read`","code":null,"level":"note","spans":[],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror[E0599]\u001b[0m\u001b[0m\u001b[1m: no method named `read` found for struct `SETTINGS` in the current scope\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:25:15\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m10\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m/\u001b[0m\u001b[0m \u001b[0m\u001b[0mlazy_static! {\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m11\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m static ref SETTINGS: RwLock = RwLock::new({\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m12\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m let mut settings = Config::default();\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m13\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m settings.merge(File::with_name(\"/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/helper-manifest.toml\")).unwrap();\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m...\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m16\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m });\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m17\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m}\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|_-\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12mmethod `read` not found for this\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m...\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m25\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m .read()\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9mmethod not found in `SETTINGS`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mhelp\u001b[0m\u001b[0m: items from traits can only be used if the trait is implemented and in scope\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: the following trait defines an item `read`, perhaps you need to implement it:\u001b[0m\n\u001b[0m candidate #1: `std::io::Read`\u001b[0m\n\n"} +{"message":"aborting due to 3 previous errors; 3 warnings emitted","code":null,"level":"error","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror\u001b[0m\u001b[0m\u001b[1m: aborting due to 3 previous errors; 3 warnings emitted\u001b[0m\n\n"} +{"message":"Some errors have detailed explanations: E0412, E0433, E0599.","code":null,"level":"failure-note","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1mSome errors have detailed explanations: E0412, E0433, E0599.\u001b[0m\n"} +{"message":"For more information about an error, try `rustc --explain E0412`.","code":null,"level":"failure-note","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1mFor more information about an error, try `rustc --explain E0412`.\u001b[0m\n"} diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/dep-test-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/dep-test-bin-toml_learning new file mode 100644 index 00000000..cdefce33 Binary files /dev/null and b/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/dep-test-bin-toml_learning differ diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/output-test-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/output-test-bin-toml_learning new file mode 100644 index 00000000..fdab6b04 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/output-test-bin-toml_learning @@ -0,0 +1,10 @@ +{"message":"unused import: `std::env`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":4,"byte_end":12,"line_start":1,"line_end":1,"column_start":5,"column_end":13,"is_primary":true,"text":[{"text":"use std::env;","highlight_start":5,"highlight_end":13}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"`#[warn(unused_imports)]` on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":0,"byte_end":13,"line_start":1,"line_end":1,"column_start":1,"column_end":14,"is_primary":true,"text":[{"text":"use std::env;","highlight_start":1,"highlight_end":14}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `std::env`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:1:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m1\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse std::env;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: `#[warn(unused_imports)]` on by default\u001b[0m\n\n"} +{"message":"unused import: `Environment`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":41,"byte_end":52,"line_start":2,"line_end":2,"column_start":28,"column_end":39,"is_primary":true,"text":[{"text":"use config::{Config, File, Environment};","highlight_start":28,"highlight_end":39}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the unused import","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":39,"byte_end":52,"line_start":2,"line_end":2,"column_start":26,"column_end":39,"is_primary":true,"text":[{"text":"use config::{Config, File, Environment};","highlight_start":26,"highlight_end":39}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `Environment`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:2:28\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m2\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse config::{Config, File, Environment};\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^\u001b[0m\n\n"} +{"message":"unused import: `std::path::PathBuf`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":59,"byte_end":77,"line_start":3,"line_end":3,"column_start":5,"column_end":23,"is_primary":true,"text":[{"text":"use std::path::PathBuf;","highlight_start":5,"highlight_end":23}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":55,"byte_end":78,"line_start":3,"line_end":3,"column_start":1,"column_end":24,"is_primary":true,"text":[{"text":"use std::path::PathBuf;","highlight_start":1,"highlight_end":24}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `std::path::PathBuf`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:3:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m3\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse std::path::PathBuf;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^^^^^^^^\u001b[0m\n\n"} +{"message":"unused import: `serde::de::Deserializer`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":94,"byte_end":117,"line_start":5,"line_end":5,"column_start":5,"column_end":28,"is_primary":true,"text":[{"text":"use serde::de::Deserializer;","highlight_start":5,"highlight_end":28}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":90,"byte_end":118,"line_start":5,"line_end":5,"column_start":1,"column_end":29,"is_primary":true,"text":[{"text":"use serde::de::Deserializer;","highlight_start":1,"highlight_end":29}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `serde::de::Deserializer`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:5:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m5\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse serde::de::Deserializer;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^^^^^^^^^^^^^\u001b[0m\n\n"} +{"message":"unused import: `toml::*`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":123,"byte_end":130,"line_start":6,"line_end":6,"column_start":5,"column_end":12,"is_primary":true,"text":[{"text":"use toml::*;","highlight_start":5,"highlight_end":12}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":119,"byte_end":131,"line_start":6,"line_end":6,"column_start":1,"column_end":13,"is_primary":true,"text":[{"text":"use toml::*;","highlight_start":1,"highlight_end":13}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `toml::*`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:6:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m6\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse toml::*;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^\u001b[0m\n\n"} +{"message":"mismatched types","code":{"code":"E0308","explanation":"Expected type did not match the received type.\n\nErroneous code example:\n\n```compile_fail,E0308\nlet x: i32 = \"I am not a number!\";\n// ~~~ ~~~~~~~~~~~~~~~~~~~~\n// | |\n// | initializing expression;\n// | compiler infers type `&str`\n// |\n// type `i32` assigned to variable `x`\n```\n\nThis error occurs when the compiler is unable to infer the concrete type of a\nvariable. It can occur in several cases, the most common being a mismatch\nbetween two types: the type the author explicitly assigned, and the type the\ncompiler inferred.\n"},"level":"error","spans":[{"file_name":"src/main.rs","byte_start":456,"byte_end":459,"line_start":15,"line_end":15,"column_start":52,"column_end":55,"is_primary":true,"text":[{"text":"\t\tif toml::value::Value::try_from::(val)","highlight_start":52,"highlight_end":55}],"label":"expected struct `config::value::Value`, found `&config::value::Value`","suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror[E0308]\u001b[0m\u001b[0m\u001b[1m: mismatched types\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:15:52\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m15\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m if toml::value::Value::try_from::(val)\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9mexpected struct `config::value::Value`, found `&config::value::Value`\u001b[0m\n\n"} +{"message":"the trait bound `config::value::Value: serde::ser::Serialize` is not satisfied","code":{"code":"E0277","explanation":"You tried to use a type which doesn't implement some trait in a place which\nexpected that trait.\n\nErroneous code example:\n\n```compile_fail,E0277\n// here we declare the Foo trait with a bar method\ntrait Foo {\n fn bar(&self);\n}\n\n// we now declare a function which takes an object implementing the Foo trait\nfn some_func(foo: T) {\n foo.bar();\n}\n\nfn main() {\n // we now call the method with the i32 type, which doesn't implement\n // the Foo trait\n some_func(5i32); // error: the trait bound `i32 : Foo` is not satisfied\n}\n```\n\nIn order to fix this error, verify that the type you're using does implement\nthe trait. Example:\n\n```\ntrait Foo {\n fn bar(&self);\n}\n\nfn some_func(foo: T) {\n foo.bar(); // we can now use this method since i32 implements the\n // Foo trait\n}\n\n// we implement the trait on the i32 type\nimpl Foo for i32 {\n fn bar(&self) {}\n}\n\nfn main() {\n some_func(5i32); // ok!\n}\n```\n\nOr in a generic context, an erroneous code example would look like:\n\n```compile_fail,E0277\nfn some_func(foo: T) {\n println!(\"{:?}\", foo); // error: the trait `core::fmt::Debug` is not\n // implemented for the type `T`\n}\n\nfn main() {\n // We now call the method with the i32 type,\n // which *does* implement the Debug trait.\n some_func(5i32);\n}\n```\n\nNote that the error here is in the definition of the generic function: Although\nwe only call it with a parameter that does implement `Debug`, the compiler\nstill rejects the function: It must work with all possible input types. In\norder to make this example compile, we need to restrict the generic type we're\naccepting:\n\n```\nuse std::fmt;\n\n// Restrict the input type to types that implement Debug.\nfn some_func(foo: T) {\n println!(\"{:?}\", foo);\n}\n\nfn main() {\n // Calling the method is still fine, as i32 implements Debug.\n some_func(5i32);\n\n // This would fail to compile now:\n // struct WithoutDebug;\n // some_func(WithoutDebug);\n}\n```\n\nRust only looks at the signature of the called function, as such it must\nalready specify all requirements that will be used for every type parameter.\n"},"level":"error","spans":[{"file_name":"src/main.rs","byte_start":456,"byte_end":459,"line_start":15,"line_end":15,"column_start":52,"column_end":55,"is_primary":true,"text":[{"text":"\t\tif toml::value::Value::try_from::(val)","highlight_start":52,"highlight_end":55}],"label":"the trait `serde::ser::Serialize` is not implemented for `config::value::Value`","suggested_replacement":null,"suggestion_applicability":null,"expansion":null},{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/toml-0.5.7/src/value.rs","byte_start":1555,"byte_end":1569,"line_start":56,"line_end":56,"column_start":12,"column_end":26,"is_primary":false,"text":[{"text":" T: ser::Serialize,","highlight_start":12,"highlight_end":26}],"label":"required by this bound in `toml::value::Value::try_from`","suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"trait impl with same name found","code":null,"level":"help","spans":[{"file_name":"/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde-0.8.23/src/ser/impls.rs","byte_start":13439,"byte_end":13670,"line_start":558,"line_end":565,"column_start":1,"column_end":2,"is_primary":true,"text":[{"text":"impl<'a, T: ?Sized> Serialize for &'a mut T where T: Serialize {","highlight_start":1,"highlight_end":65},{"text":" #[inline]","highlight_start":1,"highlight_end":14},{"text":" fn serialize(&self, serializer: &mut S) -> Result<(), S::Error>","highlight_start":1,"highlight_end":71},{"text":" where S: Serializer,","highlight_start":1,"highlight_end":29},{"text":" {","highlight_start":1,"highlight_end":6},{"text":" (**self).serialize(serializer)","highlight_start":1,"highlight_end":39},{"text":" }","highlight_start":1,"highlight_end":6},{"text":"}","highlight_start":1,"highlight_end":2}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[],"rendered":null},{"message":"perhaps two different versions of crate `serde` are being used?","code":null,"level":"note","spans":[],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror[E0277]\u001b[0m\u001b[0m\u001b[1m: the trait bound `config::value::Value: serde::ser::Serialize` is not satisfied\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:15:52\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m15\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m if toml::value::Value::try_from::(val)\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9mthe trait `serde::ser::Serialize` is not implemented for `config::value::Value`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m::: \u001b[0m\u001b[0m/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/toml-0.5.7/src/value.rs:56:12\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m56\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m T: ser::Serialize,\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--------------\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12mrequired by this bound in `toml::value::Value::try_from`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;14mhelp\u001b[0m\u001b[0m: trait impl with same name found\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0m/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde-0.8.23/src/ser/impls.rs:558:1\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m558\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;14m/\u001b[0m\u001b[0m \u001b[0m\u001b[0mimpl<'a, T: ?Sized> Serialize for &'a mut T where T: Serialize {\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m559\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;14m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m #[inline]\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m560\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;14m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m fn serialize(&self, serializer: &mut S) -> Result<(), S::Error>\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m561\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;14m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m where S: Serializer,\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m...\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;14m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m564\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;14m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m }\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m565\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;14m|\u001b[0m\u001b[0m \u001b[0m\u001b[0m}\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;14m|_^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: perhaps two different versions of crate `serde` are being used?\u001b[0m\n\n"} +{"message":"aborting due to 2 previous errors; 5 warnings emitted","code":null,"level":"error","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror\u001b[0m\u001b[0m\u001b[1m: aborting due to 2 previous errors; 5 warnings emitted\u001b[0m\n\n"} +{"message":"Some errors have detailed explanations: E0277, E0308.","code":null,"level":"failure-note","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1mSome errors have detailed explanations: E0277, E0308.\u001b[0m\n"} +{"message":"For more information about an error, try `rustc --explain E0277`.","code":null,"level":"failure-note","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1mFor more information about an error, try `rustc --explain E0277`.\u001b[0m\n"} diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/test-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/test-bin-toml_learning new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/test-bin-toml_learning.json b/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/test-bin-toml_learning.json new file mode 100644 index 00000000..5d85f904 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-65bd0e9c59799ac6/test-bin-toml_learning.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":5276335068378583393,"profile":936164052202214828,"path":1036222786711178230,"deps":[[1122423871155493656,"config",false,12076975891298977181],[2428412896888309155,"notify",false,683570404051705814],[6773936731788865364,"serde_derive",false,3618971896160771796],[7231915146259649043,"toml",false,12188567688172400698],[9391121987967877039,"serde",false,13841648393061603091],[11936193490253047359,"glob",false,10717629618522360262],[13968346382989319657,"lazy_static",false,14528124247894937362]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/toml_learning-65bd0e9c59799ac6/dep-test-bin-toml_learning"}}],"rustflags":[],"metadata":3437543006848290768} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/bin-toml_learning new file mode 100644 index 00000000..2b59624c --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/bin-toml_learning @@ -0,0 +1 @@ +8b70cf824186ecfc \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/bin-toml_learning.json b/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/bin-toml_learning.json new file mode 100644 index 00000000..7df5ffbf --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/bin-toml_learning.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":5276335068378583393,"profile":14762027784537775720,"path":1036222786711178230,"deps":[[1122423871155493656,"config",false,12076975891298977181],[2428412896888309155,"notify",false,683570404051705814],[7231915146259649043,"toml",false,12188567688172400698],[9391121987967877039,"serde",false,13841648393061603091],[11936193490253047359,"glob",false,10717629618522360262],[13968346382989319657,"lazy_static",false,14528124247894937362]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/toml_learning-925af306dd53129b/dep-bin-toml_learning"}}],"rustflags":[],"metadata":3437543006848290768} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/dep-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/dep-bin-toml_learning new file mode 100644 index 00000000..cdefce33 Binary files /dev/null and b/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/dep-bin-toml_learning differ diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/output-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/output-bin-toml_learning new file mode 100644 index 00000000..d458587a --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-925af306dd53129b/output-bin-toml_learning @@ -0,0 +1,13 @@ +{"message":"unused import: `std::env`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":4,"byte_end":12,"line_start":1,"line_end":1,"column_start":5,"column_end":13,"is_primary":true,"text":[{"text":"use std::env;","highlight_start":5,"highlight_end":13}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"`#[warn(unused_imports)]` on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":0,"byte_end":13,"line_start":1,"line_end":1,"column_start":1,"column_end":14,"is_primary":true,"text":[{"text":"use std::env;","highlight_start":1,"highlight_end":14}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `std::env`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:1:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m1\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse std::env;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: `#[warn(unused_imports)]` on by default\u001b[0m\n\n"} +{"message":"unused imports: `Environment`, `Value`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":41,"byte_end":52,"line_start":2,"line_end":2,"column_start":28,"column_end":39,"is_primary":true,"text":[{"text":"use config::{Config, File, Environment, Value};","highlight_start":28,"highlight_end":39}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null},{"file_name":"src/main.rs","byte_start":54,"byte_end":59,"line_start":2,"line_end":2,"column_start":41,"column_end":46,"is_primary":true,"text":[{"text":"use config::{Config, File, Environment, Value};","highlight_start":41,"highlight_end":46}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the unused imports","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":39,"byte_end":59,"line_start":2,"line_end":2,"column_start":26,"column_end":46,"is_primary":true,"text":[{"text":"use config::{Config, File, Environment, Value};","highlight_start":26,"highlight_end":46}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused imports: `Environment`, `Value`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:2:28\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m2\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse config::{Config, File, Environment, Value};\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^\u001b[0m\n\n"} +{"message":"unused import: `std::path::PathBuf`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":66,"byte_end":84,"line_start":3,"line_end":3,"column_start":5,"column_end":23,"is_primary":true,"text":[{"text":"use std::path::PathBuf;","highlight_start":5,"highlight_end":23}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":62,"byte_end":85,"line_start":3,"line_end":3,"column_start":1,"column_end":24,"is_primary":true,"text":[{"text":"use std::path::PathBuf;","highlight_start":1,"highlight_end":24}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `std::path::PathBuf`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:3:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m3\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse std::path::PathBuf;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^^^^^^^^\u001b[0m\n\n"} +{"message":"unused import: `serde`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":90,"byte_end":95,"line_start":4,"line_end":4,"column_start":5,"column_end":10,"is_primary":true,"text":[{"text":"use serde;","highlight_start":5,"highlight_end":10}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":86,"byte_end":96,"line_start":4,"line_end":4,"column_start":1,"column_end":11,"is_primary":true,"text":[{"text":"use serde;","highlight_start":1,"highlight_end":11}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `serde`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:4:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m4\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse serde;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^\u001b[0m\n\n"} +{"message":"unused import: `toml::*`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":101,"byte_end":108,"line_start":5,"line_end":5,"column_start":5,"column_end":12,"is_primary":true,"text":[{"text":"use toml::*;","highlight_start":5,"highlight_end":12}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":97,"byte_end":109,"line_start":5,"line_end":5,"column_start":1,"column_end":13,"is_primary":true,"text":[{"text":"use toml::*;","highlight_start":1,"highlight_end":13}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `toml::*`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:5:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m5\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse toml::*;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^\u001b[0m\n\n"} +{"message":"unused variable: `tempVec`","code":{"code":"unused_variables","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":758,"byte_end":769,"line_start":20,"line_end":20,"column_start":6,"column_end":17,"is_primary":true,"text":[{"text":"\tlet mut tempVec: std::vec::Vec = std::vec::Vec::new();","highlight_start":6,"highlight_end":17}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"`#[warn(unused_variables)]` on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"if this is intentional, prefix it with an underscore","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":758,"byte_end":769,"line_start":20,"line_end":20,"column_start":6,"column_end":17,"is_primary":true,"text":[{"text":"\tlet mut tempVec: std::vec::Vec = std::vec::Vec::new();","highlight_start":6,"highlight_end":17}],"label":null,"suggested_replacement":"_tempVec","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused variable: `tempVec`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:20:6\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m20\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m let mut tempVec: std::vec::Vec = std::vec::Vec::new();\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33mhelp: if this is intentional, prefix it with an underscore: `_tempVec`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: `#[warn(unused_variables)]` on by default\u001b[0m\n\n"} +{"message":"unused variable: `e`","code":{"code":"unused_variables","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":1021,"byte_end":1022,"line_start":29,"line_end":29,"column_start":9,"column_end":10,"is_primary":true,"text":[{"text":"\t\t\t\tErr(e) =>","highlight_start":9,"highlight_end":10}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"if this is intentional, prefix it with an underscore","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":1021,"byte_end":1022,"line_start":29,"line_end":29,"column_start":9,"column_end":10,"is_primary":true,"text":[{"text":"\t\t\t\tErr(e) =>","highlight_start":9,"highlight_end":10}],"label":null,"suggested_replacement":"_e","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused variable: `e`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:29:9\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m29\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m Err(e) =>\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33mhelp: if this is intentional, prefix it with an underscore: `_e`\u001b[0m\n\n"} +{"message":"unused variable: `v`","code":{"code":"unused_variables","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":1336,"byte_end":1337,"line_start":42,"line_end":42,"column_start":8,"column_end":9,"is_primary":true,"text":[{"text":"\t\t\t\tOk(v) =>","highlight_start":8,"highlight_end":9}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"if this is intentional, prefix it with an underscore","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":1336,"byte_end":1337,"line_start":42,"line_end":42,"column_start":8,"column_end":9,"is_primary":true,"text":[{"text":"\t\t\t\tOk(v) =>","highlight_start":8,"highlight_end":9}],"label":null,"suggested_replacement":"_v","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused variable: `v`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:42:8\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m42\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m Ok(v) =>\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33mhelp: if this is intentional, prefix it with an underscore: `_v`\u001b[0m\n\n"} +{"message":"variable does not need to be mutable","code":{"code":"unused_mut","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":559,"byte_end":573,"line_start":17,"line_end":17,"column_start":6,"column_end":20,"is_primary":true,"text":[{"text":"\tlet mut table_name = mcu_lookup_table.get_str(\"mcu.samd21j18a\").unwrap();","highlight_start":6,"highlight_end":20}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"`#[warn(unused_mut)]` on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"remove this `mut`","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":559,"byte_end":563,"line_start":17,"line_end":17,"column_start":6,"column_end":10,"is_primary":true,"text":[{"text":"\tlet mut table_name = mcu_lookup_table.get_str(\"mcu.samd21j18a\").unwrap();","highlight_start":6,"highlight_end":10}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: variable does not need to be mutable\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:17:6\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m17\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m let mut table_name = mcu_lookup_table.get_str(\"mcu.samd21j18a\").unwrap();\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m----\u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12mhelp: remove this `mut`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: `#[warn(unused_mut)]` on by default\u001b[0m\n\n"} +{"message":"variable does not need to be mutable","code":{"code":"unused_mut","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":758,"byte_end":769,"line_start":20,"line_end":20,"column_start":6,"column_end":17,"is_primary":true,"text":[{"text":"\tlet mut tempVec: std::vec::Vec = std::vec::Vec::new();","highlight_start":6,"highlight_end":17}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove this `mut`","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":758,"byte_end":762,"line_start":20,"line_end":20,"column_start":6,"column_end":10,"is_primary":true,"text":[{"text":"\tlet mut tempVec: std::vec::Vec = std::vec::Vec::new();","highlight_start":6,"highlight_end":10}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: variable does not need to be mutable\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:20:6\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m20\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m let mut tempVec: std::vec::Vec = std::vec::Vec::new();\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m----\u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12mhelp: remove this `mut`\u001b[0m\n\n"} +{"message":"variable does not need to be mutable","code":{"code":"unused_mut","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":870,"byte_end":886,"line_start":24,"line_end":24,"column_start":7,"column_end":23,"is_primary":true,"text":[{"text":"\t\tlet mut active_table = make_manifest.get_table(&table_head).unwrap();","highlight_start":7,"highlight_end":23}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove this `mut`","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":870,"byte_end":874,"line_start":24,"line_end":24,"column_start":7,"column_end":11,"is_primary":true,"text":[{"text":"\t\tlet mut active_table = make_manifest.get_table(&table_head).unwrap();","highlight_start":7,"highlight_end":11}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: variable does not need to be mutable\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:24:7\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m24\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m let mut active_table = make_manifest.get_table(&table_head).unwrap();\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m----\u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12mhelp: remove this `mut`\u001b[0m\n\n"} +{"message":"variable `tempVec` should have a snake case name","code":{"code":"non_snake_case","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":762,"byte_end":769,"line_start":20,"line_end":20,"column_start":10,"column_end":17,"is_primary":true,"text":[{"text":"\tlet mut tempVec: std::vec::Vec = std::vec::Vec::new();","highlight_start":10,"highlight_end":17}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"`#[warn(non_snake_case)]` on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"convert the identifier to snake case","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":762,"byte_end":769,"line_start":20,"line_end":20,"column_start":10,"column_end":17,"is_primary":true,"text":[{"text":"\tlet mut tempVec: std::vec::Vec = std::vec::Vec::new();","highlight_start":10,"highlight_end":17}],"label":null,"suggested_replacement":"temp_vec","suggestion_applicability":"MaybeIncorrect","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: variable `tempVec` should have a snake case name\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:20:10\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m20\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m let mut tempVec: std::vec::Vec = std::vec::Vec::new();\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33mhelp: convert the identifier to snake case: `temp_vec`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: `#[warn(non_snake_case)]` on by default\u001b[0m\n\n"} +{"message":"12 warnings emitted","code":null,"level":"warning","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: 12 warnings emitted\u001b[0m\n\n"} diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-a92aac385bf1f0e2/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/toml_learning-a92aac385bf1f0e2/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-a92aac385bf1f0e2/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-a92aac385bf1f0e2/output-test-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-a92aac385bf1f0e2/output-test-bin-toml_learning new file mode 100644 index 00000000..a35eac79 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-a92aac385bf1f0e2/output-test-bin-toml_learning @@ -0,0 +1,3 @@ +{"message":"can't find crate for `notify`","code":{"code":"E0463","explanation":"A plugin/crate was declared but cannot be found.\n\nErroneous code example:\n\n```compile_fail,E0463\n#![feature(plugin)]\n#![plugin(cookie_monster)] // error: can't find crate for `cookie_monster`\nextern crate cake_is_a_lie; // error: can't find crate for `cake_is_a_lie`\n```\n\nYou need to link your code to the relevant crate in order to be able to use it\n(through Cargo or the `-L` option of rustc example). Plugins are crates as\nwell, and you link to them the same way.\n"},"level":"error","spans":[{"file_name":"src/main.rs","byte_start":21,"byte_end":41,"line_start":2,"line_end":2,"column_start":1,"column_end":21,"is_primary":true,"text":[{"text":"extern crate notify;","highlight_start":1,"highlight_end":21}],"label":"can't find crate","suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror[E0463]\u001b[0m\u001b[0m\u001b[1m: can't find crate for `notify`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:2:1\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m2\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0mextern crate notify;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^^^^^^^^^^^^^^^^^^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9mcan't find crate\u001b[0m\n\n"} +{"message":"aborting due to previous error","code":null,"level":"error","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror\u001b[0m\u001b[0m\u001b[1m: aborting due to previous error\u001b[0m\n\n"} +{"message":"For more information about this error, try `rustc --explain E0463`.","code":null,"level":"failure-note","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1mFor more information about this error, try `rustc --explain E0463`.\u001b[0m\n"} diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-c1fd577076318815/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/toml_learning-c1fd577076318815/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-c1fd577076318815/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/toml_learning-c1fd577076318815/output-bin-toml_learning b/arch/toml_learning/target/debug/.fingerprint/toml_learning-c1fd577076318815/output-bin-toml_learning new file mode 100644 index 00000000..137a3201 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/toml_learning-c1fd577076318815/output-bin-toml_learning @@ -0,0 +1,7 @@ +{"message":"cannot find macro `lazy_static` in this scope","code":null,"level":"error","spans":[{"file_name":"src/main.rs","byte_start":125,"byte_end":136,"line_start":9,"line_end":9,"column_start":1,"column_end":12,"is_primary":true,"text":[{"text":"lazy_static! {","highlight_start":1,"highlight_end":12}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror\u001b[0m\u001b[0m\u001b[1m: cannot find macro `lazy_static` in this scope\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:9:1\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m9\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0mlazy_static! {\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^^^^^^^^^^^\u001b[0m\n\n"} +{"message":"cannot find value `SETTINGS` in this scope","code":{"code":"E0425","explanation":"An unresolved name was used.\n\nErroneous code examples:\n\n```compile_fail,E0425\nsomething_that_doesnt_exist::foo;\n// error: unresolved name `something_that_doesnt_exist::foo`\n\n// or:\n\ntrait Foo {\n fn bar() {\n Self; // error: unresolved name `Self`\n }\n}\n\n// or:\n\nlet x = unknown_variable; // error: unresolved name `unknown_variable`\n```\n\nPlease verify that the name wasn't misspelled and ensure that the\nidentifier being referred to is valid for the given situation. Example:\n\n```\nenum something_that_does_exist {\n Foo,\n}\n```\n\nOr:\n\n```\nmod something_that_does_exist {\n pub static foo : i32 = 0i32;\n}\n\nsomething_that_does_exist::foo; // ok!\n```\n\nOr:\n\n```\nlet unknown_variable = 12u32;\nlet x = unknown_variable; // ok!\n```\n\nIf the item is not defined in the current module, it must be imported using a\n`use` statement, like so:\n\n```\n# mod foo { pub fn bar() {} }\n# fn main() {\nuse foo::bar;\nbar();\n# }\n```\n\nIf the item you are importing is not defined in some super-module of the\ncurrent module, then it must also be declared as public (e.g., `pub fn`).\n"},"level":"error","spans":[{"file_name":"src/main.rs","byte_start":522,"byte_end":530,"line_start":23,"line_end":23,"column_start":14,"column_end":22,"is_primary":true,"text":[{"text":" SETTINGS","highlight_start":14,"highlight_end":22}],"label":"not found in this scope","suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror[E0425]\u001b[0m\u001b[0m\u001b[1m: cannot find value `SETTINGS` in this scope\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:23:14\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m23\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m SETTINGS\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9m^^^^^^^^\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;9mnot found in this scope\u001b[0m\n\n"} +{"message":"unused import: `std::path::Path`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":45,"byte_end":60,"line_start":4,"line_end":4,"column_start":5,"column_end":20,"is_primary":true,"text":[{"text":"use std::path::Path;","highlight_start":5,"highlight_end":20}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"`#[warn(unused_imports)]` on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":41,"byte_end":61,"line_start":4,"line_end":4,"column_start":1,"column_end":21,"is_primary":true,"text":[{"text":"use std::path::Path;","highlight_start":1,"highlight_end":21}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `std::path::Path`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:4:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m4\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse std::path::Path;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^^^^^^\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m= \u001b[0m\u001b[0m\u001b[1mnote\u001b[0m\u001b[0m: `#[warn(unused_imports)]` on by default\u001b[0m\n\n"} +{"message":"unused import: `config::*`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":97,"byte_end":106,"line_start":6,"line_end":6,"column_start":5,"column_end":14,"is_primary":true,"text":[{"text":"use config::*;","highlight_start":5,"highlight_end":14}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":93,"byte_end":107,"line_start":6,"line_end":6,"column_start":1,"column_end":15,"is_primary":true,"text":[{"text":"use config::*;","highlight_start":1,"highlight_end":15}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `config::*`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:6:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m6\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse config::*;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^\u001b[0m\n\n"} +{"message":"unused import: `glob::glob`","code":{"code":"unused_imports","explanation":null},"level":"warning","spans":[{"file_name":"src/main.rs","byte_start":112,"byte_end":122,"line_start":7,"line_end":7,"column_start":5,"column_end":15,"is_primary":true,"text":[{"text":"use glob::glob;","highlight_start":5,"highlight_end":15}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"remove the whole `use` item","code":null,"level":"help","spans":[{"file_name":"src/main.rs","byte_start":108,"byte_end":123,"line_start":7,"line_end":7,"column_start":1,"column_end":16,"is_primary":true,"text":[{"text":"use glob::glob;","highlight_start":1,"highlight_end":16}],"label":null,"suggested_replacement":"","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"\u001b[0m\u001b[1m\u001b[33mwarning\u001b[0m\u001b[0m\u001b[1m: unused import: `glob::glob`\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m--> \u001b[0m\u001b[0msrc/main.rs:7:5\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m|\u001b[0m\n\u001b[0m\u001b[1m\u001b[38;5;12m7\u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0muse glob::glob;\u001b[0m\n\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[38;5;12m| \u001b[0m\u001b[0m \u001b[0m\u001b[0m\u001b[1m\u001b[33m^^^^^^^^^^\u001b[0m\n\n"} +{"message":"aborting due to 2 previous errors; 3 warnings emitted","code":null,"level":"error","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1m\u001b[38;5;9merror\u001b[0m\u001b[0m\u001b[1m: aborting due to 2 previous errors; 3 warnings emitted\u001b[0m\n\n"} +{"message":"For more information about this error, try `rustc --explain E0425`.","code":null,"level":"failure-note","spans":[],"children":[],"rendered":"\u001b[0m\u001b[1mFor more information about this error, try `rustc --explain E0425`.\u001b[0m\n"} diff --git a/arch/toml_learning/target/debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/dep-lib-unicode-xid b/arch/toml_learning/target/debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/dep-lib-unicode-xid new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/lib-unicode-xid b/arch/toml_learning/target/debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/lib-unicode-xid new file mode 100644 index 00000000..6e1105af --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/lib-unicode-xid @@ -0,0 +1 @@ +0f844508abf5608a \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/lib-unicode-xid.json b/arch/toml_learning/target/debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/lib-unicode-xid.json new file mode 100644 index 00000000..1c79174a --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/lib-unicode-xid.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[\"default\"]","target":17781475209714866777,"profile":11677938664258541388,"path":18105095019634073149,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/unicode-xid-1640b40d9f6a97fc/dep-lib-unicode-xid"}}],"rustflags":[],"metadata":8984739024795042354} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/walkdir-85931a15254ccde6/dep-lib-walkdir b/arch/toml_learning/target/debug/.fingerprint/walkdir-85931a15254ccde6/dep-lib-walkdir new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/.fingerprint/walkdir-85931a15254ccde6/invoked.timestamp b/arch/toml_learning/target/debug/.fingerprint/walkdir-85931a15254ccde6/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/walkdir-85931a15254ccde6/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/walkdir-85931a15254ccde6/lib-walkdir b/arch/toml_learning/target/debug/.fingerprint/walkdir-85931a15254ccde6/lib-walkdir new file mode 100644 index 00000000..4f02a1d3 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/walkdir-85931a15254ccde6/lib-walkdir @@ -0,0 +1 @@ +9be809ff9eefca6e \ No newline at end of file diff --git a/arch/toml_learning/target/debug/.fingerprint/walkdir-85931a15254ccde6/lib-walkdir.json b/arch/toml_learning/target/debug/.fingerprint/walkdir-85931a15254ccde6/lib-walkdir.json new file mode 100644 index 00000000..4da509c3 --- /dev/null +++ b/arch/toml_learning/target/debug/.fingerprint/walkdir-85931a15254ccde6/lib-walkdir.json @@ -0,0 +1 @@ +{"rustc":6030236523401801000,"features":"[]","target":12029561625079948131,"profile":11677938664258541388,"path":8320208164068762145,"deps":[[3160971919143743810,"same_file",false,9044583557847263545]],"local":[{"CheckDepInfo":{"dep_info":"debug/.fingerprint/walkdir-85931a15254ccde6/dep-lib-walkdir"}}],"rustflags":[],"metadata":4122289770401600519} \ No newline at end of file diff --git a/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/invoked.timestamp b/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/output b/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/output new file mode 100644 index 00000000..6f1b6a95 --- /dev/null +++ b/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/output @@ -0,0 +1,8 @@ +cargo:rustc-cfg=freebsd11 +cargo:rustc-cfg=libc_priv_mod_use +cargo:rustc-cfg=libc_union +cargo:rustc-cfg=libc_const_size_of +cargo:rustc-cfg=libc_align +cargo:rustc-cfg=libc_core_cvoid +cargo:rustc-cfg=libc_packedN +cargo:rustc-cfg=libc_cfg_target_vendor diff --git a/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/root-output b/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/root-output new file mode 100644 index 00000000..20b85dce --- /dev/null +++ b/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/root-output @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/out \ No newline at end of file diff --git a/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/stderr b/arch/toml_learning/target/debug/build/libc-0ac771bf9f21d7c8/stderr new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/build/libc-7623b6e835e99b3f/build-script-build b/arch/toml_learning/target/debug/build/libc-7623b6e835e99b3f/build-script-build new file mode 100644 index 00000000..8530f20b Binary files /dev/null and b/arch/toml_learning/target/debug/build/libc-7623b6e835e99b3f/build-script-build differ diff --git a/arch/toml_learning/target/debug/build/libc-7623b6e835e99b3f/build_script_build-7623b6e835e99b3f b/arch/toml_learning/target/debug/build/libc-7623b6e835e99b3f/build_script_build-7623b6e835e99b3f new file mode 100644 index 00000000..8530f20b Binary files /dev/null and b/arch/toml_learning/target/debug/build/libc-7623b6e835e99b3f/build_script_build-7623b6e835e99b3f differ diff --git a/arch/toml_learning/target/debug/build/libc-7623b6e835e99b3f/build_script_build-7623b6e835e99b3f.d b/arch/toml_learning/target/debug/build/libc-7623b6e835e99b3f/build_script_build-7623b6e835e99b3f.d new file mode 100644 index 00000000..64248eab --- /dev/null +++ b/arch/toml_learning/target/debug/build/libc-7623b6e835e99b3f/build_script_build-7623b6e835e99b3f.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/libc-7623b6e835e99b3f/build_script_build-7623b6e835e99b3f: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/build.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/libc-7623b6e835e99b3f/build_script_build-7623b6e835e99b3f.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/build.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/build.rs: diff --git a/arch/toml_learning/target/debug/build/log-98622275a955444b/invoked.timestamp b/arch/toml_learning/target/debug/build/log-98622275a955444b/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/build/log-98622275a955444b/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/build/log-98622275a955444b/output b/arch/toml_learning/target/debug/build/log-98622275a955444b/output new file mode 100644 index 00000000..535a1627 --- /dev/null +++ b/arch/toml_learning/target/debug/build/log-98622275a955444b/output @@ -0,0 +1,2 @@ +cargo:rustc-cfg=atomic_cas +cargo:rerun-if-changed=build.rs diff --git a/arch/toml_learning/target/debug/build/log-98622275a955444b/root-output b/arch/toml_learning/target/debug/build/log-98622275a955444b/root-output new file mode 100644 index 00000000..6a9bcc27 --- /dev/null +++ b/arch/toml_learning/target/debug/build/log-98622275a955444b/root-output @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/log-98622275a955444b/out \ No newline at end of file diff --git a/arch/toml_learning/target/debug/build/log-98622275a955444b/stderr b/arch/toml_learning/target/debug/build/log-98622275a955444b/stderr new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/build/log-b21fc8c2d7201e78/build-script-build b/arch/toml_learning/target/debug/build/log-b21fc8c2d7201e78/build-script-build new file mode 100644 index 00000000..15bc6764 Binary files /dev/null and b/arch/toml_learning/target/debug/build/log-b21fc8c2d7201e78/build-script-build differ diff --git a/arch/toml_learning/target/debug/build/log-b21fc8c2d7201e78/build_script_build-b21fc8c2d7201e78 b/arch/toml_learning/target/debug/build/log-b21fc8c2d7201e78/build_script_build-b21fc8c2d7201e78 new file mode 100644 index 00000000..15bc6764 Binary files /dev/null and b/arch/toml_learning/target/debug/build/log-b21fc8c2d7201e78/build_script_build-b21fc8c2d7201e78 differ diff --git a/arch/toml_learning/target/debug/build/log-b21fc8c2d7201e78/build_script_build-b21fc8c2d7201e78.d b/arch/toml_learning/target/debug/build/log-b21fc8c2d7201e78/build_script_build-b21fc8c2d7201e78.d new file mode 100644 index 00000000..6ea8a717 --- /dev/null +++ b/arch/toml_learning/target/debug/build/log-b21fc8c2d7201e78/build_script_build-b21fc8c2d7201e78.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/log-b21fc8c2d7201e78/build_script_build-b21fc8c2d7201e78: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/build.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/log-b21fc8c2d7201e78/build_script_build-b21fc8c2d7201e78.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/build.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/build.rs: diff --git a/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/invoked.timestamp b/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/output b/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/output new file mode 100644 index 00000000..22fb7109 --- /dev/null +++ b/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/output @@ -0,0 +1,5 @@ +cargo:rerun-if-changed=build.rs +cargo:rustc-cfg=lexerror_display +cargo:rustc-cfg=hygiene +cargo:rustc-cfg=use_proc_macro +cargo:rustc-cfg=wrap_proc_macro diff --git a/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/root-output b/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/root-output new file mode 100644 index 00000000..bab5e75e --- /dev/null +++ b/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/root-output @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/out \ No newline at end of file diff --git a/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/stderr b/arch/toml_learning/target/debug/build/proc-macro2-18e23bd5f760ab2a/stderr new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/build/proc-macro2-bc60f0d61e99c4b5/build-script-build b/arch/toml_learning/target/debug/build/proc-macro2-bc60f0d61e99c4b5/build-script-build new file mode 100644 index 00000000..7e83a011 Binary files /dev/null and b/arch/toml_learning/target/debug/build/proc-macro2-bc60f0d61e99c4b5/build-script-build differ diff --git a/arch/toml_learning/target/debug/build/proc-macro2-bc60f0d61e99c4b5/build_script_build-bc60f0d61e99c4b5 b/arch/toml_learning/target/debug/build/proc-macro2-bc60f0d61e99c4b5/build_script_build-bc60f0d61e99c4b5 new file mode 100644 index 00000000..7e83a011 Binary files /dev/null and b/arch/toml_learning/target/debug/build/proc-macro2-bc60f0d61e99c4b5/build_script_build-bc60f0d61e99c4b5 differ diff --git a/arch/toml_learning/target/debug/build/proc-macro2-bc60f0d61e99c4b5/build_script_build-bc60f0d61e99c4b5.d b/arch/toml_learning/target/debug/build/proc-macro2-bc60f0d61e99c4b5/build_script_build-bc60f0d61e99c4b5.d new file mode 100644 index 00000000..b12173dd --- /dev/null +++ b/arch/toml_learning/target/debug/build/proc-macro2-bc60f0d61e99c4b5/build_script_build-bc60f0d61e99c4b5.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/proc-macro2-bc60f0d61e99c4b5/build_script_build-bc60f0d61e99c4b5: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/build.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/proc-macro2-bc60f0d61e99c4b5/build_script_build-bc60f0d61e99c4b5.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/build.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/build.rs: diff --git a/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/invoked.timestamp b/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/output b/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/output new file mode 100644 index 00000000..c73cc706 --- /dev/null +++ b/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/output @@ -0,0 +1 @@ +cargo:rustc-cfg=underscore_consts diff --git a/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/root-output b/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/root-output new file mode 100644 index 00000000..f922ba37 --- /dev/null +++ b/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/root-output @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/out \ No newline at end of file diff --git a/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/stderr b/arch/toml_learning/target/debug/build/serde_derive-7005aabd08e2511f/stderr new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/build/serde_derive-fda8cd5f1bf4f7be/build-script-build b/arch/toml_learning/target/debug/build/serde_derive-fda8cd5f1bf4f7be/build-script-build new file mode 100644 index 00000000..5acd36af Binary files /dev/null and b/arch/toml_learning/target/debug/build/serde_derive-fda8cd5f1bf4f7be/build-script-build differ diff --git a/arch/toml_learning/target/debug/build/serde_derive-fda8cd5f1bf4f7be/build_script_build-fda8cd5f1bf4f7be b/arch/toml_learning/target/debug/build/serde_derive-fda8cd5f1bf4f7be/build_script_build-fda8cd5f1bf4f7be new file mode 100644 index 00000000..5acd36af Binary files /dev/null and b/arch/toml_learning/target/debug/build/serde_derive-fda8cd5f1bf4f7be/build_script_build-fda8cd5f1bf4f7be differ diff --git a/arch/toml_learning/target/debug/build/serde_derive-fda8cd5f1bf4f7be/build_script_build-fda8cd5f1bf4f7be.d b/arch/toml_learning/target/debug/build/serde_derive-fda8cd5f1bf4f7be/build_script_build-fda8cd5f1bf4f7be.d new file mode 100644 index 00000000..a7ca2a9d --- /dev/null +++ b/arch/toml_learning/target/debug/build/serde_derive-fda8cd5f1bf4f7be/build_script_build-fda8cd5f1bf4f7be.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/serde_derive-fda8cd5f1bf4f7be/build_script_build-fda8cd5f1bf4f7be: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/build.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/serde_derive-fda8cd5f1bf4f7be/build_script_build-fda8cd5f1bf4f7be.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/build.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/build.rs: diff --git a/arch/toml_learning/target/debug/build/syn-beb75ac107fbd1be/build-script-build b/arch/toml_learning/target/debug/build/syn-beb75ac107fbd1be/build-script-build new file mode 100644 index 00000000..186b697a Binary files /dev/null and b/arch/toml_learning/target/debug/build/syn-beb75ac107fbd1be/build-script-build differ diff --git a/arch/toml_learning/target/debug/build/syn-beb75ac107fbd1be/build_script_build-beb75ac107fbd1be b/arch/toml_learning/target/debug/build/syn-beb75ac107fbd1be/build_script_build-beb75ac107fbd1be new file mode 100644 index 00000000..186b697a Binary files /dev/null and b/arch/toml_learning/target/debug/build/syn-beb75ac107fbd1be/build_script_build-beb75ac107fbd1be differ diff --git a/arch/toml_learning/target/debug/build/syn-beb75ac107fbd1be/build_script_build-beb75ac107fbd1be.d b/arch/toml_learning/target/debug/build/syn-beb75ac107fbd1be/build_script_build-beb75ac107fbd1be.d new file mode 100644 index 00000000..2280ab0b --- /dev/null +++ b/arch/toml_learning/target/debug/build/syn-beb75ac107fbd1be/build_script_build-beb75ac107fbd1be.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/syn-beb75ac107fbd1be/build_script_build-beb75ac107fbd1be: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/build.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/syn-beb75ac107fbd1be/build_script_build-beb75ac107fbd1be.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/build.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/build.rs: diff --git a/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/invoked.timestamp b/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/invoked.timestamp new file mode 100644 index 00000000..e00328da --- /dev/null +++ b/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/output b/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/output new file mode 100644 index 00000000..614b9485 --- /dev/null +++ b/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/output @@ -0,0 +1 @@ +cargo:rustc-cfg=syn_disable_nightly_tests diff --git a/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/root-output b/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/root-output new file mode 100644 index 00000000..df388482 --- /dev/null +++ b/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/root-output @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/out \ No newline at end of file diff --git a/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/stderr b/arch/toml_learning/target/debug/build/syn-ca295c6494f2b39c/stderr new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/deps/filetime-727651744b3a6fd0.d b/arch/toml_learning/target/debug/deps/filetime-727651744b3a6fd0.d new file mode 100644 index 00000000..33075b6f --- /dev/null +++ b/arch/toml_learning/target/debug/deps/filetime-727651744b3a6fd0.d @@ -0,0 +1,10 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/filetime-727651744b3a6fd0.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/utimes.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/linux.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libfiletime-727651744b3a6fd0.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/utimes.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/linux.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/filetime-727651744b3a6fd0.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/utimes.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/linux.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/utimes.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/filetime-0.2.12/src/unix/linux.rs: diff --git a/arch/toml_learning/target/debug/deps/inotify-227c9a24fd07857b.d b/arch/toml_learning/target/debug/deps/inotify-227c9a24fd07857b.d new file mode 100644 index 00000000..2b8da1e9 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/inotify-227c9a24fd07857b.d @@ -0,0 +1,12 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/inotify-227c9a24fd07857b.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/events.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/fd_guard.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/inotify.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/util.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/watches.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libinotify-227c9a24fd07857b.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/events.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/fd_guard.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/inotify.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/util.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/watches.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/inotify-227c9a24fd07857b.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/events.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/fd_guard.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/inotify.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/util.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/watches.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/events.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/fd_guard.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/inotify.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/util.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-0.7.1/src/watches.rs: diff --git a/arch/toml_learning/target/debug/deps/inotify_sys-e7b33fbf21e4ccdd.d b/arch/toml_learning/target/debug/deps/inotify_sys-e7b33fbf21e4ccdd.d new file mode 100644 index 00000000..8869828c --- /dev/null +++ b/arch/toml_learning/target/debug/deps/inotify_sys-e7b33fbf21e4ccdd.d @@ -0,0 +1,7 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/inotify_sys-e7b33fbf21e4ccdd.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-sys-0.1.3/src/lib.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libinotify_sys-e7b33fbf21e4ccdd.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-sys-0.1.3/src/lib.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/inotify_sys-e7b33fbf21e4ccdd.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-sys-0.1.3/src/lib.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/inotify-sys-0.1.3/src/lib.rs: diff --git a/arch/toml_learning/target/debug/deps/iovec-6d60102019e1348b.d b/arch/toml_learning/target/debug/deps/iovec-6d60102019e1348b.d new file mode 100644 index 00000000..df8a81c9 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/iovec-6d60102019e1348b.d @@ -0,0 +1,10 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/iovec-6d60102019e1348b.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/sys/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/sys/unix.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/unix.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libiovec-6d60102019e1348b.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/sys/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/sys/unix.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/unix.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/iovec-6d60102019e1348b.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/sys/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/sys/unix.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/unix.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/sys/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/sys/unix.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/iovec-0.1.4/src/unix.rs: diff --git a/arch/toml_learning/target/debug/deps/lazy_static-c93b4732a572fb60.d b/arch/toml_learning/target/debug/deps/lazy_static-c93b4732a572fb60.d new file mode 100644 index 00000000..c5ddd12d --- /dev/null +++ b/arch/toml_learning/target/debug/deps/lazy_static-c93b4732a572fb60.d @@ -0,0 +1,8 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/lazy_static-c93b4732a572fb60.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lazy.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/liblazy_static-c93b4732a572fb60.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lazy.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/lazy_static-c93b4732a572fb60.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lazy.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazy_static-0.2.11/src/lazy.rs: diff --git a/arch/toml_learning/target/debug/deps/lazycell-5309ca3a766221bf.d b/arch/toml_learning/target/debug/deps/lazycell-5309ca3a766221bf.d new file mode 100644 index 00000000..82d5968a --- /dev/null +++ b/arch/toml_learning/target/debug/deps/lazycell-5309ca3a766221bf.d @@ -0,0 +1,7 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/lazycell-5309ca3a766221bf.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazycell-1.3.0/src/lib.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/liblazycell-5309ca3a766221bf.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazycell-1.3.0/src/lib.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/lazycell-5309ca3a766221bf.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazycell-1.3.0/src/lib.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/lazycell-1.3.0/src/lib.rs: diff --git a/arch/toml_learning/target/debug/deps/libc-f957e64c74520dcc.d b/arch/toml_learning/target/debug/deps/libc-f957e64c74520dcc.d new file mode 100644 index 00000000..9c5395d8 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/libc-f957e64c74520dcc.d @@ -0,0 +1,20 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libc-f957e64c74520dcc.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/macros.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/fixed_width_ints.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/not_x32.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/align.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/align.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/align.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/align.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/liblibc-f957e64c74520dcc.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/macros.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/fixed_width_ints.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/not_x32.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/align.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/align.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/align.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/align.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libc-f957e64c74520dcc.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/macros.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/fixed_width_ints.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/not_x32.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/align.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/align.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/align.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/align.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/macros.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/fixed_width_ints.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/not_x32.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/b64/x86_64/align.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/gnu/align.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/linux_like/linux/align.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/libc-0.2.79/src/unix/align.rs: diff --git a/arch/toml_learning/target/debug/deps/libfiletime-727651744b3a6fd0.rlib b/arch/toml_learning/target/debug/deps/libfiletime-727651744b3a6fd0.rlib new file mode 100644 index 00000000..5228a3ad Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libfiletime-727651744b3a6fd0.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libfiletime-727651744b3a6fd0.rmeta b/arch/toml_learning/target/debug/deps/libfiletime-727651744b3a6fd0.rmeta new file mode 100644 index 00000000..b77a592e Binary files /dev/null and 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b/arch/toml_learning/target/debug/deps/libiovec-6d60102019e1348b.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/liblazy_static-c93b4732a572fb60.rlib b/arch/toml_learning/target/debug/deps/liblazy_static-c93b4732a572fb60.rlib new file mode 100644 index 00000000..c33ebabe Binary files /dev/null and b/arch/toml_learning/target/debug/deps/liblazy_static-c93b4732a572fb60.rlib differ diff --git a/arch/toml_learning/target/debug/deps/liblazy_static-c93b4732a572fb60.rmeta b/arch/toml_learning/target/debug/deps/liblazy_static-c93b4732a572fb60.rmeta new file mode 100644 index 00000000..c9218f3b Binary files /dev/null and b/arch/toml_learning/target/debug/deps/liblazy_static-c93b4732a572fb60.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/liblazycell-5309ca3a766221bf.rlib b/arch/toml_learning/target/debug/deps/liblazycell-5309ca3a766221bf.rlib new file mode 100644 index 00000000..935995ef Binary files /dev/null and b/arch/toml_learning/target/debug/deps/liblazycell-5309ca3a766221bf.rlib differ diff --git a/arch/toml_learning/target/debug/deps/liblazycell-5309ca3a766221bf.rmeta b/arch/toml_learning/target/debug/deps/liblazycell-5309ca3a766221bf.rmeta new file mode 100644 index 00000000..f313ea81 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/liblazycell-5309ca3a766221bf.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/liblibc-f957e64c74520dcc.rlib b/arch/toml_learning/target/debug/deps/liblibc-f957e64c74520dcc.rlib new file mode 100644 index 00000000..0cf271d2 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/liblibc-f957e64c74520dcc.rlib differ diff --git a/arch/toml_learning/target/debug/deps/liblibc-f957e64c74520dcc.rmeta b/arch/toml_learning/target/debug/deps/liblibc-f957e64c74520dcc.rmeta new file mode 100644 index 00000000..94ffdfe9 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/liblibc-f957e64c74520dcc.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/liblog-86f8d34791d1ea32.rlib b/arch/toml_learning/target/debug/deps/liblog-86f8d34791d1ea32.rlib new file mode 100644 index 00000000..acdd0906 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/liblog-86f8d34791d1ea32.rlib differ diff --git a/arch/toml_learning/target/debug/deps/liblog-86f8d34791d1ea32.rmeta b/arch/toml_learning/target/debug/deps/liblog-86f8d34791d1ea32.rmeta new file mode 100644 index 00000000..ca77ec92 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/liblog-86f8d34791d1ea32.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/libmio-40897f326420dab3.rlib b/arch/toml_learning/target/debug/deps/libmio-40897f326420dab3.rlib new file mode 100644 index 00000000..5bea754a Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libmio-40897f326420dab3.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libmio-40897f326420dab3.rmeta b/arch/toml_learning/target/debug/deps/libmio-40897f326420dab3.rmeta new file mode 100644 index 00000000..55576efe Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libmio-40897f326420dab3.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/libmio_extras-aecc5d72143b7262.rlib b/arch/toml_learning/target/debug/deps/libmio_extras-aecc5d72143b7262.rlib new file mode 100644 index 00000000..7fc0c216 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libmio_extras-aecc5d72143b7262.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libmio_extras-aecc5d72143b7262.rmeta b/arch/toml_learning/target/debug/deps/libmio_extras-aecc5d72143b7262.rmeta new file mode 100644 index 00000000..0e6cdff0 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libmio_extras-aecc5d72143b7262.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/libnet2-47f78eb9630d276c.rlib b/arch/toml_learning/target/debug/deps/libnet2-47f78eb9630d276c.rlib new file mode 100644 index 00000000..e6c83100 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libnet2-47f78eb9630d276c.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libnet2-47f78eb9630d276c.rmeta b/arch/toml_learning/target/debug/deps/libnet2-47f78eb9630d276c.rmeta new file mode 100644 index 00000000..98def495 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libnet2-47f78eb9630d276c.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/libnotify-460f5b0501989ba5.rlib b/arch/toml_learning/target/debug/deps/libnotify-460f5b0501989ba5.rlib new file mode 100644 index 00000000..2d827f18 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libnotify-460f5b0501989ba5.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libnotify-460f5b0501989ba5.rmeta b/arch/toml_learning/target/debug/deps/libnotify-460f5b0501989ba5.rmeta new file mode 100644 index 00000000..2ff099eb Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libnotify-460f5b0501989ba5.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/libproc_macro2-10ba1809e1dbc902.rlib b/arch/toml_learning/target/debug/deps/libproc_macro2-10ba1809e1dbc902.rlib new file mode 100644 index 00000000..55a19d23 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libproc_macro2-10ba1809e1dbc902.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libproc_macro2-10ba1809e1dbc902.rmeta b/arch/toml_learning/target/debug/deps/libproc_macro2-10ba1809e1dbc902.rmeta new file mode 100644 index 00000000..08fa8fd4 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libproc_macro2-10ba1809e1dbc902.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/libquote-af750ed0964881fc.rlib b/arch/toml_learning/target/debug/deps/libquote-af750ed0964881fc.rlib new file mode 100644 index 00000000..b5f9715b Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libquote-af750ed0964881fc.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libquote-af750ed0964881fc.rmeta b/arch/toml_learning/target/debug/deps/libquote-af750ed0964881fc.rmeta new file mode 100644 index 00000000..9fe0a6bb Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libquote-af750ed0964881fc.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/libsame_file-d6c46a96b8ab29ad.rlib b/arch/toml_learning/target/debug/deps/libsame_file-d6c46a96b8ab29ad.rlib new file mode 100644 index 00000000..61212419 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libsame_file-d6c46a96b8ab29ad.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libsame_file-d6c46a96b8ab29ad.rmeta b/arch/toml_learning/target/debug/deps/libsame_file-d6c46a96b8ab29ad.rmeta new file mode 100644 index 00000000..b203b452 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libsame_file-d6c46a96b8ab29ad.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/libserde_derive-4a4dbbd361dc80da.so b/arch/toml_learning/target/debug/deps/libserde_derive-4a4dbbd361dc80da.so new file mode 100644 index 00000000..f9969e4e Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libserde_derive-4a4dbbd361dc80da.so differ diff --git a/arch/toml_learning/target/debug/deps/libslab-f4af9e03a066116e.rlib b/arch/toml_learning/target/debug/deps/libslab-f4af9e03a066116e.rlib new file mode 100644 index 00000000..448aaa38 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libslab-f4af9e03a066116e.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libslab-f4af9e03a066116e.rmeta b/arch/toml_learning/target/debug/deps/libslab-f4af9e03a066116e.rmeta new file mode 100644 index 00000000..8e5e3f43 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libslab-f4af9e03a066116e.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/libsyn-590ded94d59e41a3.rlib b/arch/toml_learning/target/debug/deps/libsyn-590ded94d59e41a3.rlib new file mode 100644 index 00000000..7e80fbf2 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libsyn-590ded94d59e41a3.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libsyn-590ded94d59e41a3.rmeta b/arch/toml_learning/target/debug/deps/libsyn-590ded94d59e41a3.rmeta new file mode 100644 index 00000000..902070a0 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libsyn-590ded94d59e41a3.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/libunicode_xid-1640b40d9f6a97fc.rlib b/arch/toml_learning/target/debug/deps/libunicode_xid-1640b40d9f6a97fc.rlib new file mode 100644 index 00000000..a5c51c49 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libunicode_xid-1640b40d9f6a97fc.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libunicode_xid-1640b40d9f6a97fc.rmeta b/arch/toml_learning/target/debug/deps/libunicode_xid-1640b40d9f6a97fc.rmeta new file mode 100644 index 00000000..9b58c615 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libunicode_xid-1640b40d9f6a97fc.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/libwalkdir-85931a15254ccde6.rlib b/arch/toml_learning/target/debug/deps/libwalkdir-85931a15254ccde6.rlib new file mode 100644 index 00000000..0da43dda Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libwalkdir-85931a15254ccde6.rlib differ diff --git a/arch/toml_learning/target/debug/deps/libwalkdir-85931a15254ccde6.rmeta b/arch/toml_learning/target/debug/deps/libwalkdir-85931a15254ccde6.rmeta new file mode 100644 index 00000000..cc9834c3 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/libwalkdir-85931a15254ccde6.rmeta differ diff --git a/arch/toml_learning/target/debug/deps/log-86f8d34791d1ea32.d b/arch/toml_learning/target/debug/deps/log-86f8d34791d1ea32.d new file mode 100644 index 00000000..fd418a32 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/log-86f8d34791d1ea32.d @@ -0,0 +1,9 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/log-86f8d34791d1ea32.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/macros.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/serde.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/liblog-86f8d34791d1ea32.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/macros.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/serde.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/log-86f8d34791d1ea32.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/macros.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/serde.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/macros.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/log-0.4.11/src/serde.rs: diff --git a/arch/toml_learning/target/debug/deps/mio-40897f326420dab3.d b/arch/toml_learning/target/debug/deps/mio-40897f326420dab3.d new file mode 100644 index 00000000..0913e90c --- /dev/null +++ b/arch/toml_learning/target/debug/deps/mio-40897f326420dab3.d @@ -0,0 +1,36 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/mio-40897f326420dab3.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/event_imp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/io.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/poll.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/dlsym.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/epoll.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/awakener.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/eventedfd.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/io.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/ready.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/tcp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/udp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/uio.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/uds.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/token.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/lazycell.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/tcp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/udp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/channel.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/timer.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/event_loop.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/io.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/handler.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/notify.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/unix.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/udp.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libmio-40897f326420dab3.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/event_imp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/io.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/poll.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/dlsym.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/epoll.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/awakener.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/eventedfd.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/io.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/ready.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/tcp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/udp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/uio.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/uds.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/token.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/lazycell.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/tcp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/udp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/channel.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/timer.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/event_loop.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/io.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/handler.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/notify.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/unix.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/udp.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/mio-40897f326420dab3.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/event_imp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/io.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/poll.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/dlsym.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/epoll.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/awakener.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/eventedfd.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/io.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/ready.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/tcp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/udp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/uio.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/uds.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/token.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/lazycell.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/tcp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/udp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/channel.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/timer.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/event_loop.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/io.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/handler.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/notify.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/unix.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/udp.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/event_imp.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/io.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/poll.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/dlsym.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/epoll.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/awakener.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/eventedfd.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/io.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/ready.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/tcp.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/udp.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/uio.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/sys/unix/uds.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/token.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/lazycell.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/tcp.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/net/udp.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/channel.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/timer.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/event_loop.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/io.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/handler.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/notify.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/deprecated/unix.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-0.6.22/src/udp.rs: diff --git a/arch/toml_learning/target/debug/deps/mio_extras-aecc5d72143b7262.d b/arch/toml_learning/target/debug/deps/mio_extras-aecc5d72143b7262.d new file mode 100644 index 00000000..9c13ba77 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/mio_extras-aecc5d72143b7262.d @@ -0,0 +1,9 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/mio_extras-aecc5d72143b7262.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/channel.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/timer.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libmio_extras-aecc5d72143b7262.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/channel.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/timer.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/mio_extras-aecc5d72143b7262.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/channel.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/timer.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/channel.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/mio-extras-2.0.6/src/timer.rs: diff --git a/arch/toml_learning/target/debug/deps/net2-47f78eb9630d276c.d b/arch/toml_learning/target/debug/deps/net2-47f78eb9630d276c.d new file mode 100644 index 00000000..dc2a708d --- /dev/null +++ b/arch/toml_learning/target/debug/deps/net2-47f78eb9630d276c.d @@ -0,0 +1,15 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/net2-47f78eb9630d276c.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/tcp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/udp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/socket.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/ext.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/utils.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/sys/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/sys/unix/impls.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/unix.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libnet2-47f78eb9630d276c.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/tcp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/udp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/socket.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/ext.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/utils.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/sys/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/sys/unix/impls.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/unix.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/net2-47f78eb9630d276c.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/tcp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/udp.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/socket.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/ext.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/utils.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/sys/unix/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/sys/unix/impls.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/unix.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/tcp.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/udp.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/socket.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/ext.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/utils.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/sys/unix/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/sys/unix/impls.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/net2-0.2.35/src/unix.rs: diff --git a/arch/toml_learning/target/debug/deps/notify-460f5b0501989ba5.d b/arch/toml_learning/target/debug/deps/notify-460f5b0501989ba5.d new file mode 100644 index 00000000..336d4f36 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/notify-460f5b0501989ba5.d @@ -0,0 +1,12 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/notify-460f5b0501989ba5.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/inotify.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/null.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/poll.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/debounce/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/debounce/timer.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libnotify-460f5b0501989ba5.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/inotify.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/null.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/poll.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/debounce/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/debounce/timer.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/notify-460f5b0501989ba5.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/inotify.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/null.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/poll.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/debounce/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/debounce/timer.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/inotify.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/null.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/poll.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/debounce/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/notify-4.0.15/src/debounce/timer.rs: diff --git a/arch/toml_learning/target/debug/deps/proc_macro2-10ba1809e1dbc902.d b/arch/toml_learning/target/debug/deps/proc_macro2-10ba1809e1dbc902.d new file mode 100644 index 00000000..074cb004 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/proc_macro2-10ba1809e1dbc902.d @@ -0,0 +1,12 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/proc_macro2-10ba1809e1dbc902.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/marker.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/parse.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/detection.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/fallback.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/wrapper.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libproc_macro2-10ba1809e1dbc902.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/marker.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/parse.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/detection.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/fallback.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/wrapper.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/proc_macro2-10ba1809e1dbc902.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/marker.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/parse.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/detection.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/fallback.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/wrapper.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/marker.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/parse.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/detection.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/fallback.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/proc-macro2-1.0.24/src/wrapper.rs: diff --git a/arch/toml_learning/target/debug/deps/quote-af750ed0964881fc.d b/arch/toml_learning/target/debug/deps/quote-af750ed0964881fc.d new file mode 100644 index 00000000..4f085560 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/quote-af750ed0964881fc.d @@ -0,0 +1,13 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/quote-af750ed0964881fc.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/ext.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/format.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/ident_fragment.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/to_tokens.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/runtime.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/spanned.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libquote-af750ed0964881fc.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/ext.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/format.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/ident_fragment.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/to_tokens.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/runtime.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/spanned.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/quote-af750ed0964881fc.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/ext.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/format.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/ident_fragment.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/to_tokens.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/runtime.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/spanned.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/ext.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/format.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/ident_fragment.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/to_tokens.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/runtime.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/quote-1.0.7/src/spanned.rs: diff --git a/arch/toml_learning/target/debug/deps/same_file-d6c46a96b8ab29ad.d b/arch/toml_learning/target/debug/deps/same_file-d6c46a96b8ab29ad.d new file mode 100644 index 00000000..618c8f1c --- /dev/null +++ b/arch/toml_learning/target/debug/deps/same_file-d6c46a96b8ab29ad.d @@ -0,0 +1,8 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/same_file-d6c46a96b8ab29ad.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/same-file-1.0.6/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/same-file-1.0.6/src/unix.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libsame_file-d6c46a96b8ab29ad.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/same-file-1.0.6/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/same-file-1.0.6/src/unix.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/same_file-d6c46a96b8ab29ad.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/same-file-1.0.6/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/same-file-1.0.6/src/unix.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/same-file-1.0.6/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/same-file-1.0.6/src/unix.rs: diff --git a/arch/toml_learning/target/debug/deps/serde_derive-4a4dbbd361dc80da.d b/arch/toml_learning/target/debug/deps/serde_derive-4a4dbbd361dc80da.d new file mode 100644 index 00000000..2f0f7551 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/serde_derive-4a4dbbd361dc80da.d @@ -0,0 +1,19 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libserde_derive-4a4dbbd361dc80da.so: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/ast.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/attr.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/ctxt.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/case.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/check.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/symbol.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/bound.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/fragment.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/de.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/dummy.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/pretend.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/ser.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/try.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/serde_derive-4a4dbbd361dc80da.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/mod.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/ast.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/attr.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/ctxt.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/case.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/check.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/symbol.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/bound.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/fragment.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/de.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/dummy.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/pretend.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/ser.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/try.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/mod.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/ast.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/attr.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/ctxt.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/case.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/check.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/internals/symbol.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/bound.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/fragment.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/de.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/dummy.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/pretend.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/ser.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/serde_derive-1.0.117/src/try.rs: diff --git a/arch/toml_learning/target/debug/deps/slab-f4af9e03a066116e.d b/arch/toml_learning/target/debug/deps/slab-f4af9e03a066116e.d new file mode 100644 index 00000000..352059f8 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/slab-f4af9e03a066116e.d @@ -0,0 +1,7 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/slab-f4af9e03a066116e.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/slab-0.4.2/src/lib.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libslab-f4af9e03a066116e.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/slab-0.4.2/src/lib.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/slab-f4af9e03a066116e.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/slab-0.4.2/src/lib.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/slab-0.4.2/src/lib.rs: diff --git a/arch/toml_learning/target/debug/deps/syn-590ded94d59e41a3.d b/arch/toml_learning/target/debug/deps/syn-590ded94d59e41a3.d new file mode 100644 index 00000000..45b3f0bd --- /dev/null +++ b/arch/toml_learning/target/debug/deps/syn-590ded94d59e41a3.d @@ -0,0 +1,45 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/syn-590ded94d59e41a3.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/macros.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/group.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/token.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ident.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/attr.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/bigint.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/data.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/expr.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/generics.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lifetime.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lit.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/mac.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/derive.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/op.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ty.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/path.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/buffer.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ext.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/punctuated.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse_quote.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse_macro_input.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/spanned.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/../gen_helper.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/export.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/custom_keyword.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/custom_punctuation.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/sealed.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/span.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/thread.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lookahead.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/discouraged.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/verbatim.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/print.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/error.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/await.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/visit.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/clone.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libsyn-590ded94d59e41a3.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/macros.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/group.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/token.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ident.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/attr.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/bigint.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/data.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/expr.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/generics.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lifetime.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lit.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/mac.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/derive.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/op.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ty.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/path.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/buffer.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ext.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/punctuated.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse_quote.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse_macro_input.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/spanned.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/../gen_helper.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/export.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/custom_keyword.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/custom_punctuation.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/sealed.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/span.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/thread.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lookahead.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/discouraged.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/verbatim.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/print.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/error.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/await.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/visit.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/clone.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/syn-590ded94d59e41a3.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/macros.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/group.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/token.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ident.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/attr.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/bigint.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/data.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/expr.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/generics.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lifetime.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lit.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/mac.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/derive.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/op.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ty.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/path.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/buffer.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ext.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/punctuated.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse_quote.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse_macro_input.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/spanned.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/../gen_helper.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/export.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/custom_keyword.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/custom_punctuation.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/sealed.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/span.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/thread.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lookahead.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/discouraged.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/verbatim.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/print.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/error.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/await.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/visit.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/clone.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/macros.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/group.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/token.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ident.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/attr.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/bigint.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/data.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/expr.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/generics.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lifetime.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lit.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/mac.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/derive.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/op.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ty.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/path.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/buffer.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/ext.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/punctuated.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse_quote.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse_macro_input.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/spanned.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/../gen_helper.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/export.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/custom_keyword.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/custom_punctuation.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/sealed.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/span.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/thread.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/lookahead.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/parse.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/discouraged.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/verbatim.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/print.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/error.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/await.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/visit.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/syn-1.0.45/src/gen/clone.rs: diff --git a/arch/toml_learning/target/debug/deps/toml_learning-208d529ca3eead4d.d b/arch/toml_learning/target/debug/deps/toml_learning-208d529ca3eead4d.d new file mode 100644 index 00000000..a931eecd --- /dev/null +++ b/arch/toml_learning/target/debug/deps/toml_learning-208d529ca3eead4d.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-208d529ca3eead4d: src/main.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-208d529ca3eead4d.d: src/main.rs + +src/main.rs: diff --git a/arch/toml_learning/target/debug/deps/toml_learning-33399023b514f49c.d b/arch/toml_learning/target/debug/deps/toml_learning-33399023b514f49c.d new file mode 100644 index 00000000..300ef4a9 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/toml_learning-33399023b514f49c.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-33399023b514f49c: src/main.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-33399023b514f49c.d: src/main.rs + +src/main.rs: diff --git a/arch/toml_learning/target/debug/deps/toml_learning-3466204c4e7cc508 b/arch/toml_learning/target/debug/deps/toml_learning-3466204c4e7cc508 new file mode 100644 index 00000000..c0d05673 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/toml_learning-3466204c4e7cc508 differ diff --git a/arch/toml_learning/target/debug/deps/toml_learning-3466204c4e7cc508.d b/arch/toml_learning/target/debug/deps/toml_learning-3466204c4e7cc508.d new file mode 100644 index 00000000..2742feba --- /dev/null +++ b/arch/toml_learning/target/debug/deps/toml_learning-3466204c4e7cc508.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-3466204c4e7cc508: src/main.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-3466204c4e7cc508.d: src/main.rs + +src/main.rs: diff --git a/arch/toml_learning/target/debug/deps/toml_learning-6271efe665464c9f b/arch/toml_learning/target/debug/deps/toml_learning-6271efe665464c9f new file mode 100644 index 00000000..24412a62 Binary files /dev/null and b/arch/toml_learning/target/debug/deps/toml_learning-6271efe665464c9f differ diff --git a/arch/toml_learning/target/debug/deps/toml_learning-6271efe665464c9f.d b/arch/toml_learning/target/debug/deps/toml_learning-6271efe665464c9f.d new file mode 100644 index 00000000..edc973fc --- /dev/null +++ b/arch/toml_learning/target/debug/deps/toml_learning-6271efe665464c9f.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-6271efe665464c9f: src/main.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-6271efe665464c9f.d: src/main.rs + +src/main.rs: diff --git a/arch/toml_learning/target/debug/deps/toml_learning-6419956b58e4a978.d b/arch/toml_learning/target/debug/deps/toml_learning-6419956b58e4a978.d new file mode 100644 index 00000000..aff6a178 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/toml_learning-6419956b58e4a978.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-6419956b58e4a978: src/main.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-6419956b58e4a978.d: src/main.rs + +src/main.rs: diff --git a/arch/toml_learning/target/debug/deps/toml_learning-65bd0e9c59799ac6 b/arch/toml_learning/target/debug/deps/toml_learning-65bd0e9c59799ac6 new file mode 100644 index 00000000..6c87e13b Binary files /dev/null and b/arch/toml_learning/target/debug/deps/toml_learning-65bd0e9c59799ac6 differ diff --git a/arch/toml_learning/target/debug/deps/toml_learning-65bd0e9c59799ac6.d b/arch/toml_learning/target/debug/deps/toml_learning-65bd0e9c59799ac6.d new file mode 100644 index 00000000..5deda282 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/toml_learning-65bd0e9c59799ac6.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-65bd0e9c59799ac6: src/main.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-65bd0e9c59799ac6.d: src/main.rs + +src/main.rs: diff --git a/arch/toml_learning/target/debug/deps/toml_learning-925af306dd53129b b/arch/toml_learning/target/debug/deps/toml_learning-925af306dd53129b new file mode 100644 index 00000000..1ad9b84c Binary files /dev/null and b/arch/toml_learning/target/debug/deps/toml_learning-925af306dd53129b differ diff --git a/arch/toml_learning/target/debug/deps/toml_learning-925af306dd53129b.d b/arch/toml_learning/target/debug/deps/toml_learning-925af306dd53129b.d new file mode 100644 index 00000000..af142b5f --- /dev/null +++ b/arch/toml_learning/target/debug/deps/toml_learning-925af306dd53129b.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-925af306dd53129b: src/main.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-925af306dd53129b.d: src/main.rs + +src/main.rs: diff --git a/arch/toml_learning/target/debug/deps/toml_learning-c1fd577076318815.d b/arch/toml_learning/target/debug/deps/toml_learning-c1fd577076318815.d new file mode 100644 index 00000000..c5366eb1 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/toml_learning-c1fd577076318815.d @@ -0,0 +1,5 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-c1fd577076318815: src/main.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/toml_learning-c1fd577076318815.d: src/main.rs + +src/main.rs: diff --git a/arch/toml_learning/target/debug/deps/unicode_xid-1640b40d9f6a97fc.d b/arch/toml_learning/target/debug/deps/unicode_xid-1640b40d9f6a97fc.d new file mode 100644 index 00000000..11f8adb7 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/unicode_xid-1640b40d9f6a97fc.d @@ -0,0 +1,8 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/unicode_xid-1640b40d9f6a97fc.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/unicode-xid-0.2.1/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/unicode-xid-0.2.1/src/tables.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libunicode_xid-1640b40d9f6a97fc.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/unicode-xid-0.2.1/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/unicode-xid-0.2.1/src/tables.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/unicode_xid-1640b40d9f6a97fc.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/unicode-xid-0.2.1/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/unicode-xid-0.2.1/src/tables.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/unicode-xid-0.2.1/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/unicode-xid-0.2.1/src/tables.rs: diff --git a/arch/toml_learning/target/debug/deps/walkdir-85931a15254ccde6.d b/arch/toml_learning/target/debug/deps/walkdir-85931a15254ccde6.d new file mode 100644 index 00000000..82ffebe4 --- /dev/null +++ b/arch/toml_learning/target/debug/deps/walkdir-85931a15254ccde6.d @@ -0,0 +1,10 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/walkdir-85931a15254ccde6.rmeta: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/dent.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/error.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/util.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/libwalkdir-85931a15254ccde6.rlib: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/dent.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/error.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/util.rs + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/toml_learning/target/debug/deps/walkdir-85931a15254ccde6.d: /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/lib.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/dent.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/error.rs /home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/util.rs + +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/lib.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/dent.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/error.rs: +/home/penguin/.cargo/registry/src/github.com-1ecc6299db9ec823/walkdir-2.3.1/src/util.rs: diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/15txj1ueymrdqbp8.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/15txj1ueymrdqbp8.o new file mode 100644 index 00000000..3d8a406e Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/15txj1ueymrdqbp8.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/195mlpgs65v3rzs4.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/195mlpgs65v3rzs4.o new file mode 100644 index 00000000..59473cf8 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/195mlpgs65v3rzs4.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/1mucuxxdkh6spwgd.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/1mucuxxdkh6spwgd.o new file mode 100644 index 00000000..32fd4569 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/1mucuxxdkh6spwgd.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/1nphzz4461zugpp.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/1nphzz4461zugpp.o new file mode 100644 index 00000000..1d541d43 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/1nphzz4461zugpp.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/1pxk1bphbvzkxyxj.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/1pxk1bphbvzkxyxj.o new file mode 100644 index 00000000..08682abb Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/1pxk1bphbvzkxyxj.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2059hu4vttp15g1r.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2059hu4vttp15g1r.o new file mode 100644 index 00000000..de340181 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2059hu4vttp15g1r.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2a4vaa5ywz1z3vpg.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2a4vaa5ywz1z3vpg.o new file mode 100644 index 00000000..90510fb0 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2a4vaa5ywz1z3vpg.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2cdbfzo6bc2iuukp.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2cdbfzo6bc2iuukp.o new file mode 100644 index 00000000..8f5f8dca Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2cdbfzo6bc2iuukp.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2nzj5nx6ad0ey6ju.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2nzj5nx6ad0ey6ju.o new file mode 100644 index 00000000..3fc38830 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2nzj5nx6ad0ey6ju.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2o3owyjv4mcpclih.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2o3owyjv4mcpclih.o new file mode 100644 index 00000000..9871dcaf Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2o3owyjv4mcpclih.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2z8a7ez2w7l7ckta.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2z8a7ez2w7l7ckta.o new file mode 100644 index 00000000..97ced9d4 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/2z8a7ez2w7l7ckta.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/34frq95j9pr21y3x.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/34frq95j9pr21y3x.o new file mode 100644 index 00000000..ea1fb678 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/34frq95j9pr21y3x.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3aj6tlf8f2qvakq4.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3aj6tlf8f2qvakq4.o new file mode 100644 index 00000000..93760f6d Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3aj6tlf8f2qvakq4.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3fiedu4laokxdd8w.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3fiedu4laokxdd8w.o new file mode 100644 index 00000000..ff4622ef Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3fiedu4laokxdd8w.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3gpsfh69oi4hl9v3.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3gpsfh69oi4hl9v3.o new file mode 100644 index 00000000..ff2cd24c Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3gpsfh69oi4hl9v3.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3pto32xavf0aadgs.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3pto32xavf0aadgs.o new file mode 100644 index 00000000..183c85a9 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3pto32xavf0aadgs.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3qjmyjvqeu7v83mf.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3qjmyjvqeu7v83mf.o new file mode 100644 index 00000000..05f77b0e Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3qjmyjvqeu7v83mf.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3su4jk06ub2usaki.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3su4jk06ub2usaki.o new file mode 100644 index 00000000..bdc86476 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/3su4jk06ub2usaki.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/47p50b8fe0a9izp.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/47p50b8fe0a9izp.o new file mode 100644 index 00000000..2cf51b16 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/47p50b8fe0a9izp.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/4w67krvp9hcgzb9i.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/4w67krvp9hcgzb9i.o new file mode 100644 index 00000000..a4997e24 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/4w67krvp9hcgzb9i.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/51llqj723fdjj33n.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d00l6oe-zar9od-2i939sthqt0ms/51llqj723fdjj33n.o new file mode 100644 index 00000000..1ab202fa Binary files /dev/null and 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b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/15txj1ueymrdqbp8.o new file mode 100644 index 00000000..3d8a406e Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/15txj1ueymrdqbp8.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/195mlpgs65v3rzs4.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/195mlpgs65v3rzs4.o new file mode 100644 index 00000000..59473cf8 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/195mlpgs65v3rzs4.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/1mucuxxdkh6spwgd.o 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b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/2a4vaa5ywz1z3vpg.o new file mode 100644 index 00000000..90510fb0 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/2a4vaa5ywz1z3vpg.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/2cdbfzo6bc2iuukp.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/2cdbfzo6bc2iuukp.o new file mode 100644 index 00000000..8f5f8dca Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/2cdbfzo6bc2iuukp.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/2nzj5nx6ad0ey6ju.o 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b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/2z8a7ez2w7l7ckta.o new file mode 100644 index 00000000..97ced9d4 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/2z8a7ez2w7l7ckta.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/34frq95j9pr21y3x.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/34frq95j9pr21y3x.o new file mode 100644 index 00000000..ea1fb678 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/34frq95j9pr21y3x.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3aj6tlf8f2qvakq4.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3aj6tlf8f2qvakq4.o new file mode 100644 index 00000000..93760f6d Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3aj6tlf8f2qvakq4.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3fiedu4laokxdd8w.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3fiedu4laokxdd8w.o new file mode 100644 index 00000000..ff4622ef Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3fiedu4laokxdd8w.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3gpsfh69oi4hl9v3.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3gpsfh69oi4hl9v3.o new file mode 100644 index 00000000..ff2cd24c Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3gpsfh69oi4hl9v3.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3pto32xavf0aadgs.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3pto32xavf0aadgs.o new file mode 100644 index 00000000..183c85a9 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3pto32xavf0aadgs.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3qjmyjvqeu7v83mf.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3qjmyjvqeu7v83mf.o new file mode 100644 index 00000000..05f77b0e Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3qjmyjvqeu7v83mf.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3su4jk06ub2usaki.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3su4jk06ub2usaki.o new file mode 100644 index 00000000..bdc86476 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/3su4jk06ub2usaki.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/47p50b8fe0a9izp.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/47p50b8fe0a9izp.o new file mode 100644 index 00000000..2cf51b16 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/47p50b8fe0a9izp.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/4w67krvp9hcgzb9i.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/4w67krvp9hcgzb9i.o new file mode 100644 index 00000000..a4997e24 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/4w67krvp9hcgzb9i.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/51llqj723fdjj33n.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/51llqj723fdjj33n.o new file mode 100644 index 00000000..1ab202fa Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/51llqj723fdjj33n.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/53ub7immawsii09i.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/53ub7immawsii09i.o new file mode 100644 index 00000000..cba5447f Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/53ub7immawsii09i.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/5c3sbe13xzz7jhla.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/5c3sbe13xzz7jhla.o new file mode 100644 index 00000000..c8ec00c9 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/5c3sbe13xzz7jhla.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/9ty5jvbfa2a60mr.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/9ty5jvbfa2a60mr.o new file mode 100644 index 00000000..21a199dd Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/9ty5jvbfa2a60mr.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/dep-graph.bin b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/dep-graph.bin new file mode 100644 index 00000000..7687af21 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/dep-graph.bin differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/kzgljr7w9to4ebx.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/kzgljr7w9to4ebx.o new file mode 100644 index 00000000..6086ba02 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/kzgljr7w9to4ebx.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/neqaeaif4upden.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/neqaeaif4upden.o new file mode 100644 index 00000000..85607c84 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/neqaeaif4upden.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/query-cache.bin b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/query-cache.bin new file mode 100644 index 00000000..f0a1c1e2 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/query-cache.bin differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/work-products.bin b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/work-products.bin new file mode 100644 index 00000000..969aea64 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/work-products.bin differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/xgita9modz7rrsu.o b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/xgita9modz7rrsu.o new file mode 100644 index 00000000..620ced75 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq-working/xgita9modz7rrsu.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq.lock b/arch/toml_learning/target/debug/incremental/toml_learning-1500snoa8pvuc/s-fs7d6nd094-1ew2dbq.lock new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1ckdesf1y4lhv/s-fs7baiey03-1q0t5xj.lock b/arch/toml_learning/target/debug/incremental/toml_learning-1ckdesf1y4lhv/s-fs7baiey03-1q0t5xj.lock new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1nfpj976uvnj1/s-fs7bihxcvd-1foqb3v.lock b/arch/toml_learning/target/debug/incremental/toml_learning-1nfpj976uvnj1/s-fs7bihxcvd-1foqb3v.lock new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1ubccud6ulbfr/s-fs7biwdsph-x3d3ke.lock b/arch/toml_learning/target/debug/incremental/toml_learning-1ubccud6ulbfr/s-fs7biwdsph-x3d3ke.lock new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-1v4743fz0zath/s-fs7bkis5eh-xru0oo.lock b/arch/toml_learning/target/debug/incremental/toml_learning-1v4743fz0zath/s-fs7bkis5eh-xru0oo.lock new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/1w8u4f3opc9xoh89.o b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/1w8u4f3opc9xoh89.o new file mode 100644 index 00000000..c14305e6 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/1w8u4f3opc9xoh89.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/2pnlyhnkwpmpof1b.o b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/2pnlyhnkwpmpof1b.o new file mode 100644 index 00000000..e383ef75 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/2pnlyhnkwpmpof1b.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/2uylyjfccj6ozox2.o b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/2uylyjfccj6ozox2.o new file mode 100644 index 00000000..3df1abaa Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/2uylyjfccj6ozox2.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/3qplub3mg1e1j4bx.o b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/3qplub3mg1e1j4bx.o new file mode 100644 index 00000000..442ab31c Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/3qplub3mg1e1j4bx.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/5bc6ux56h4axodac.o b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/5bc6ux56h4axodac.o new file mode 100644 index 00000000..3b624883 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/5bc6ux56h4axodac.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/dep-graph.bin b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/dep-graph.bin new file mode 100644 index 00000000..ca8c908e Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/dep-graph.bin differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/query-cache.bin b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/query-cache.bin new file mode 100644 index 00000000..723f889e Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/query-cache.bin differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/work-products.bin b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/work-products.bin new file mode 100644 index 00000000..c21047b4 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx-35gxw1zzoijty/work-products.bin differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx.lock b/arch/toml_learning/target/debug/incremental/toml_learning-2nffwe5nhxfds/s-fs7i4765fy-ydv7dx.lock new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3mh15gryob52x/s-fs7bi8zsjh-163l1hn.lock b/arch/toml_learning/target/debug/incremental/toml_learning-3mh15gryob52x/s-fs7bi8zsjh-163l1hn.lock new file mode 100644 index 00000000..e69de29b diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/100f21vdr9jqosi5.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/100f21vdr9jqosi5.o new file mode 100644 index 00000000..25fbb14d Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/100f21vdr9jqosi5.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/10cjrsq9qn7olcu7.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/10cjrsq9qn7olcu7.o new file mode 100644 index 00000000..e32f4382 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/10cjrsq9qn7olcu7.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/12bhn8vdv4z6d9w.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/12bhn8vdv4z6d9w.o new file mode 100644 index 00000000..968944eb Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/12bhn8vdv4z6d9w.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/16qenbk60c43t0u8.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/16qenbk60c43t0u8.o new file mode 100644 index 00000000..2ab3f3e1 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/16qenbk60c43t0u8.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/1hzdllbmm1go9b82.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/1hzdllbmm1go9b82.o new file mode 100644 index 00000000..8a842683 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/1hzdllbmm1go9b82.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2cpgdk741pngi4em.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2cpgdk741pngi4em.o new file mode 100644 index 00000000..054f1432 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2cpgdk741pngi4em.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2fbtlxijlvxhjh6.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2fbtlxijlvxhjh6.o new file mode 100644 index 00000000..7242f79d Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2fbtlxijlvxhjh6.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2saqemtgdn7uln6p.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2saqemtgdn7uln6p.o new file mode 100644 index 00000000..aa023dbf Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2saqemtgdn7uln6p.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2w4vkilo2fdlbmmh.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2w4vkilo2fdlbmmh.o new file mode 100644 index 00000000..90e18e6b Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/2w4vkilo2fdlbmmh.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/33nxg5qrg8zjvimh.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/33nxg5qrg8zjvimh.o new file mode 100644 index 00000000..67913935 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/33nxg5qrg8zjvimh.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/349ey4wehbvj7q03.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/349ey4wehbvj7q03.o new file mode 100644 index 00000000..a2b8264b Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/349ey4wehbvj7q03.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/34souzxu5vwyzpa9.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/34souzxu5vwyzpa9.o new file mode 100644 index 00000000..9a6ed0e2 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/34souzxu5vwyzpa9.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/355j1n59ewoyysix.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/355j1n59ewoyysix.o new file mode 100644 index 00000000..5f5957ec Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/355j1n59ewoyysix.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/39mg0ru8yvxdtwgs.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/39mg0ru8yvxdtwgs.o new file mode 100644 index 00000000..a566a991 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/39mg0ru8yvxdtwgs.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/3ex2gt5but1h697h.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/3ex2gt5but1h697h.o new file mode 100644 index 00000000..40863547 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/3ex2gt5but1h697h.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/3g98y2me5vh726de.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/3g98y2me5vh726de.o new file mode 100644 index 00000000..aba73628 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/3g98y2me5vh726de.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/41iggfh5a2mq3ukn.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/41iggfh5a2mq3ukn.o new file mode 100644 index 00000000..17d6f4f2 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/41iggfh5a2mq3ukn.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/48cjzfulot6awdpr.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/48cjzfulot6awdpr.o new file mode 100644 index 00000000..d0e749c3 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/48cjzfulot6awdpr.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4a68hq4mu07kysc.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4a68hq4mu07kysc.o new file mode 100644 index 00000000..ab395e4e Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4a68hq4mu07kysc.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4av7v61ty7n7fco7.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4av7v61ty7n7fco7.o new file mode 100644 index 00000000..649d5b71 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4av7v61ty7n7fco7.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4izay1d7vp7ffuj4.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4izay1d7vp7ffuj4.o new file mode 100644 index 00000000..be2842d0 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4izay1d7vp7ffuj4.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4k1438ocqd84qpfj.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4k1438ocqd84qpfj.o new file mode 100644 index 00000000..fce51d0b Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4k1438ocqd84qpfj.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4mucx7u8skfrw2d9.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4mucx7u8skfrw2d9.o new file mode 100644 index 00000000..a63e4eae Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4mucx7u8skfrw2d9.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4ogesh4gy13v0ltt.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4ogesh4gy13v0ltt.o new file mode 100644 index 00000000..ce523c19 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4ogesh4gy13v0ltt.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4s4gtd7h7541919z.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4s4gtd7h7541919z.o new file mode 100644 index 00000000..a0afb44a Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4s4gtd7h7541919z.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4s5ekwo2lvkcrey5.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4s5ekwo2lvkcrey5.o new file mode 100644 index 00000000..0819a42c Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4s5ekwo2lvkcrey5.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4zzr950z75wqjau3.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4zzr950z75wqjau3.o new file mode 100644 index 00000000..57a28771 Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/4zzr950z75wqjau3.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/56hevwe9tb5911io.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/56hevwe9tb5911io.o new file mode 100644 index 00000000..43ae713b Binary files /dev/null and b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/56hevwe9tb5911io.o differ diff --git a/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/cqgr52lvpolc9oe.o b/arch/toml_learning/target/debug/incremental/toml_learning-3w6illj657fq/s-fs7i2n5oai-10bwocd-30u3tmmbtyog3/cqgr52lvpolc9oe.o new file mode 100644 index 00000000..813f1fb5 Binary files /dev/null and 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