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522 lines
58 KiB
C
522 lines
58 KiB
C
/**
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* \brief Component description for PDEC
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-09-28T13:45:00Z */
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#ifndef _SAMD51_PDEC_COMPONENT_H_
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#define _SAMD51_PDEC_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR PDEC */
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/* ************************************************************************** */
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/* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */
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#define PDEC_CTRLA_RESETVALUE _U_(0x00) /**< (PDEC_CTRLA) Control A Reset Value */
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#define PDEC_CTRLA_SWRST_Pos _U_(0) /**< (PDEC_CTRLA) Software Reset Position */
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#define PDEC_CTRLA_SWRST_Msk (_U_(0x1) << PDEC_CTRLA_SWRST_Pos) /**< (PDEC_CTRLA) Software Reset Mask */
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#define PDEC_CTRLA_SWRST(value) (PDEC_CTRLA_SWRST_Msk & ((value) << PDEC_CTRLA_SWRST_Pos))
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#define PDEC_CTRLA_ENABLE_Pos _U_(1) /**< (PDEC_CTRLA) Enable Position */
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#define PDEC_CTRLA_ENABLE_Msk (_U_(0x1) << PDEC_CTRLA_ENABLE_Pos) /**< (PDEC_CTRLA) Enable Mask */
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#define PDEC_CTRLA_ENABLE(value) (PDEC_CTRLA_ENABLE_Msk & ((value) << PDEC_CTRLA_ENABLE_Pos))
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#define PDEC_CTRLA_MODE_Pos _U_(2) /**< (PDEC_CTRLA) Operation Mode Position */
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#define PDEC_CTRLA_MODE_Msk (_U_(0x3) << PDEC_CTRLA_MODE_Pos) /**< (PDEC_CTRLA) Operation Mode Mask */
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#define PDEC_CTRLA_MODE(value) (PDEC_CTRLA_MODE_Msk & ((value) << PDEC_CTRLA_MODE_Pos))
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#define PDEC_CTRLA_MODE_QDEC_Val _U_(0x0) /**< (PDEC_CTRLA) QDEC operating mode */
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#define PDEC_CTRLA_MODE_HALL_Val _U_(0x1) /**< (PDEC_CTRLA) HALL operating mode */
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#define PDEC_CTRLA_MODE_COUNTER_Val _U_(0x2) /**< (PDEC_CTRLA) COUNTER operating mode */
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#define PDEC_CTRLA_MODE_QDEC (PDEC_CTRLA_MODE_QDEC_Val << PDEC_CTRLA_MODE_Pos) /**< (PDEC_CTRLA) QDEC operating mode Position */
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#define PDEC_CTRLA_MODE_HALL (PDEC_CTRLA_MODE_HALL_Val << PDEC_CTRLA_MODE_Pos) /**< (PDEC_CTRLA) HALL operating mode Position */
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#define PDEC_CTRLA_MODE_COUNTER (PDEC_CTRLA_MODE_COUNTER_Val << PDEC_CTRLA_MODE_Pos) /**< (PDEC_CTRLA) COUNTER operating mode Position */
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#define PDEC_CTRLA_RUNSTDBY_Pos _U_(6) /**< (PDEC_CTRLA) Run in Standby Position */
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#define PDEC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << PDEC_CTRLA_RUNSTDBY_Pos) /**< (PDEC_CTRLA) Run in Standby Mask */
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#define PDEC_CTRLA_RUNSTDBY(value) (PDEC_CTRLA_RUNSTDBY_Msk & ((value) << PDEC_CTRLA_RUNSTDBY_Pos))
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#define PDEC_CTRLA_CONF_Pos _U_(8) /**< (PDEC_CTRLA) PDEC Configuration Position */
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#define PDEC_CTRLA_CONF_Msk (_U_(0x7) << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) PDEC Configuration Mask */
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#define PDEC_CTRLA_CONF(value) (PDEC_CTRLA_CONF_Msk & ((value) << PDEC_CTRLA_CONF_Pos))
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#define PDEC_CTRLA_CONF_X4_Val _U_(0x0) /**< (PDEC_CTRLA) Quadrature decoder direction */
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#define PDEC_CTRLA_CONF_X4S_Val _U_(0x1) /**< (PDEC_CTRLA) Secure Quadrature decoder direction */
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#define PDEC_CTRLA_CONF_X2_Val _U_(0x2) /**< (PDEC_CTRLA) Decoder direction */
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#define PDEC_CTRLA_CONF_X2S_Val _U_(0x3) /**< (PDEC_CTRLA) Secure decoder direction */
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#define PDEC_CTRLA_CONF_AUTOC_Val _U_(0x4) /**< (PDEC_CTRLA) Auto correction mode */
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#define PDEC_CTRLA_CONF_X4 (PDEC_CTRLA_CONF_X4_Val << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) Quadrature decoder direction Position */
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#define PDEC_CTRLA_CONF_X4S (PDEC_CTRLA_CONF_X4S_Val << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) Secure Quadrature decoder direction Position */
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#define PDEC_CTRLA_CONF_X2 (PDEC_CTRLA_CONF_X2_Val << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) Decoder direction Position */
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#define PDEC_CTRLA_CONF_X2S (PDEC_CTRLA_CONF_X2S_Val << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) Secure decoder direction Position */
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#define PDEC_CTRLA_CONF_AUTOC (PDEC_CTRLA_CONF_AUTOC_Val << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) Auto correction mode Position */
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#define PDEC_CTRLA_ALOCK_Pos _U_(11) /**< (PDEC_CTRLA) Auto Lock Position */
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#define PDEC_CTRLA_ALOCK_Msk (_U_(0x1) << PDEC_CTRLA_ALOCK_Pos) /**< (PDEC_CTRLA) Auto Lock Mask */
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#define PDEC_CTRLA_ALOCK(value) (PDEC_CTRLA_ALOCK_Msk & ((value) << PDEC_CTRLA_ALOCK_Pos))
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#define PDEC_CTRLA_SWAP_Pos _U_(14) /**< (PDEC_CTRLA) PDEC Phase A and B Swap Position */
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#define PDEC_CTRLA_SWAP_Msk (_U_(0x1) << PDEC_CTRLA_SWAP_Pos) /**< (PDEC_CTRLA) PDEC Phase A and B Swap Mask */
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#define PDEC_CTRLA_SWAP(value) (PDEC_CTRLA_SWAP_Msk & ((value) << PDEC_CTRLA_SWAP_Pos))
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#define PDEC_CTRLA_PEREN_Pos _U_(15) /**< (PDEC_CTRLA) Period Enable Position */
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#define PDEC_CTRLA_PEREN_Msk (_U_(0x1) << PDEC_CTRLA_PEREN_Pos) /**< (PDEC_CTRLA) Period Enable Mask */
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#define PDEC_CTRLA_PEREN(value) (PDEC_CTRLA_PEREN_Msk & ((value) << PDEC_CTRLA_PEREN_Pos))
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#define PDEC_CTRLA_PINEN0_Pos _U_(16) /**< (PDEC_CTRLA) PDEC Input From Pin 0 Enable Position */
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#define PDEC_CTRLA_PINEN0_Msk (_U_(0x1) << PDEC_CTRLA_PINEN0_Pos) /**< (PDEC_CTRLA) PDEC Input From Pin 0 Enable Mask */
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#define PDEC_CTRLA_PINEN0(value) (PDEC_CTRLA_PINEN0_Msk & ((value) << PDEC_CTRLA_PINEN0_Pos))
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#define PDEC_CTRLA_PINEN1_Pos _U_(17) /**< (PDEC_CTRLA) PDEC Input From Pin 1 Enable Position */
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#define PDEC_CTRLA_PINEN1_Msk (_U_(0x1) << PDEC_CTRLA_PINEN1_Pos) /**< (PDEC_CTRLA) PDEC Input From Pin 1 Enable Mask */
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#define PDEC_CTRLA_PINEN1(value) (PDEC_CTRLA_PINEN1_Msk & ((value) << PDEC_CTRLA_PINEN1_Pos))
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#define PDEC_CTRLA_PINEN2_Pos _U_(18) /**< (PDEC_CTRLA) PDEC Input From Pin 2 Enable Position */
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#define PDEC_CTRLA_PINEN2_Msk (_U_(0x1) << PDEC_CTRLA_PINEN2_Pos) /**< (PDEC_CTRLA) PDEC Input From Pin 2 Enable Mask */
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#define PDEC_CTRLA_PINEN2(value) (PDEC_CTRLA_PINEN2_Msk & ((value) << PDEC_CTRLA_PINEN2_Pos))
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#define PDEC_CTRLA_PINVEN0_Pos _U_(20) /**< (PDEC_CTRLA) IO Pin 0 Invert Enable Position */
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#define PDEC_CTRLA_PINVEN0_Msk (_U_(0x1) << PDEC_CTRLA_PINVEN0_Pos) /**< (PDEC_CTRLA) IO Pin 0 Invert Enable Mask */
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#define PDEC_CTRLA_PINVEN0(value) (PDEC_CTRLA_PINVEN0_Msk & ((value) << PDEC_CTRLA_PINVEN0_Pos))
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#define PDEC_CTRLA_PINVEN1_Pos _U_(21) /**< (PDEC_CTRLA) IO Pin 1 Invert Enable Position */
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#define PDEC_CTRLA_PINVEN1_Msk (_U_(0x1) << PDEC_CTRLA_PINVEN1_Pos) /**< (PDEC_CTRLA) IO Pin 1 Invert Enable Mask */
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#define PDEC_CTRLA_PINVEN1(value) (PDEC_CTRLA_PINVEN1_Msk & ((value) << PDEC_CTRLA_PINVEN1_Pos))
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#define PDEC_CTRLA_PINVEN2_Pos _U_(22) /**< (PDEC_CTRLA) IO Pin 2 Invert Enable Position */
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#define PDEC_CTRLA_PINVEN2_Msk (_U_(0x1) << PDEC_CTRLA_PINVEN2_Pos) /**< (PDEC_CTRLA) IO Pin 2 Invert Enable Mask */
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#define PDEC_CTRLA_PINVEN2(value) (PDEC_CTRLA_PINVEN2_Msk & ((value) << PDEC_CTRLA_PINVEN2_Pos))
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#define PDEC_CTRLA_ANGULAR_Pos _U_(24) /**< (PDEC_CTRLA) Angular Counter Length Position */
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#define PDEC_CTRLA_ANGULAR_Msk (_U_(0x7) << PDEC_CTRLA_ANGULAR_Pos) /**< (PDEC_CTRLA) Angular Counter Length Mask */
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#define PDEC_CTRLA_ANGULAR(value) (PDEC_CTRLA_ANGULAR_Msk & ((value) << PDEC_CTRLA_ANGULAR_Pos))
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#define PDEC_CTRLA_MAXCMP_Pos _U_(28) /**< (PDEC_CTRLA) Maximum Consecutive Missing Pulses Position */
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#define PDEC_CTRLA_MAXCMP_Msk (_U_(0xF) << PDEC_CTRLA_MAXCMP_Pos) /**< (PDEC_CTRLA) Maximum Consecutive Missing Pulses Mask */
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#define PDEC_CTRLA_MAXCMP(value) (PDEC_CTRLA_MAXCMP_Msk & ((value) << PDEC_CTRLA_MAXCMP_Pos))
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#define PDEC_CTRLA_Msk _U_(0xF777CF4F) /**< (PDEC_CTRLA) Register Mask */
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#define PDEC_CTRLA_PINEN_Pos _U_(16) /**< (PDEC_CTRLA Position) PDEC Input From Pin x Enable */
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#define PDEC_CTRLA_PINEN_Msk (_U_(0x7) << PDEC_CTRLA_PINEN_Pos) /**< (PDEC_CTRLA Mask) PINEN */
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#define PDEC_CTRLA_PINEN(value) (PDEC_CTRLA_PINEN_Msk & ((value) << PDEC_CTRLA_PINEN_Pos))
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#define PDEC_CTRLA_PINVEN_Pos _U_(20) /**< (PDEC_CTRLA Position) IO Pin x Invert Enable */
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#define PDEC_CTRLA_PINVEN_Msk (_U_(0x7) << PDEC_CTRLA_PINVEN_Pos) /**< (PDEC_CTRLA Mask) PINVEN */
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#define PDEC_CTRLA_PINVEN(value) (PDEC_CTRLA_PINVEN_Msk & ((value) << PDEC_CTRLA_PINVEN_Pos))
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/* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W 8) Control B Clear -------- */
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#define PDEC_CTRLBCLR_RESETVALUE _U_(0x00) /**< (PDEC_CTRLBCLR) Control B Clear Reset Value */
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#define PDEC_CTRLBCLR_LUPD_Pos _U_(1) /**< (PDEC_CTRLBCLR) Lock Update Position */
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#define PDEC_CTRLBCLR_LUPD_Msk (_U_(0x1) << PDEC_CTRLBCLR_LUPD_Pos) /**< (PDEC_CTRLBCLR) Lock Update Mask */
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#define PDEC_CTRLBCLR_LUPD(value) (PDEC_CTRLBCLR_LUPD_Msk & ((value) << PDEC_CTRLBCLR_LUPD_Pos))
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#define PDEC_CTRLBCLR_CMD_Pos _U_(5) /**< (PDEC_CTRLBCLR) Command Position */
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#define PDEC_CTRLBCLR_CMD_Msk (_U_(0x7) << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Command Mask */
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#define PDEC_CTRLBCLR_CMD(value) (PDEC_CTRLBCLR_CMD_Msk & ((value) << PDEC_CTRLBCLR_CMD_Pos))
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#define PDEC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< (PDEC_CTRLBCLR) No action */
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#define PDEC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< (PDEC_CTRLBCLR) Force a counter restart or retrigger */
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#define PDEC_CTRLBCLR_CMD_UPDATE_Val _U_(0x2) /**< (PDEC_CTRLBCLR) Force update of double buffered registers */
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#define PDEC_CTRLBCLR_CMD_READSYNC_Val _U_(0x3) /**< (PDEC_CTRLBCLR) Force a read synchronization of COUNT */
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#define PDEC_CTRLBCLR_CMD_START_Val _U_(0x4) /**< (PDEC_CTRLBCLR) Start QDEC/HALL */
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#define PDEC_CTRLBCLR_CMD_STOP_Val _U_(0x5) /**< (PDEC_CTRLBCLR) Stop QDEC/HALL */
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#define PDEC_CTRLBCLR_CMD_NONE (PDEC_CTRLBCLR_CMD_NONE_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) No action Position */
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#define PDEC_CTRLBCLR_CMD_RETRIGGER (PDEC_CTRLBCLR_CMD_RETRIGGER_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Force a counter restart or retrigger Position */
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#define PDEC_CTRLBCLR_CMD_UPDATE (PDEC_CTRLBCLR_CMD_UPDATE_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Force update of double buffered registers Position */
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#define PDEC_CTRLBCLR_CMD_READSYNC (PDEC_CTRLBCLR_CMD_READSYNC_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Force a read synchronization of COUNT Position */
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#define PDEC_CTRLBCLR_CMD_START (PDEC_CTRLBCLR_CMD_START_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Start QDEC/HALL Position */
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#define PDEC_CTRLBCLR_CMD_STOP (PDEC_CTRLBCLR_CMD_STOP_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Stop QDEC/HALL Position */
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#define PDEC_CTRLBCLR_Msk _U_(0xE2) /**< (PDEC_CTRLBCLR) Register Mask */
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/* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W 8) Control B Set -------- */
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#define PDEC_CTRLBSET_RESETVALUE _U_(0x00) /**< (PDEC_CTRLBSET) Control B Set Reset Value */
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#define PDEC_CTRLBSET_LUPD_Pos _U_(1) /**< (PDEC_CTRLBSET) Lock Update Position */
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#define PDEC_CTRLBSET_LUPD_Msk (_U_(0x1) << PDEC_CTRLBSET_LUPD_Pos) /**< (PDEC_CTRLBSET) Lock Update Mask */
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#define PDEC_CTRLBSET_LUPD(value) (PDEC_CTRLBSET_LUPD_Msk & ((value) << PDEC_CTRLBSET_LUPD_Pos))
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#define PDEC_CTRLBSET_CMD_Pos _U_(5) /**< (PDEC_CTRLBSET) Command Position */
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#define PDEC_CTRLBSET_CMD_Msk (_U_(0x7) << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Command Mask */
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#define PDEC_CTRLBSET_CMD(value) (PDEC_CTRLBSET_CMD_Msk & ((value) << PDEC_CTRLBSET_CMD_Pos))
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#define PDEC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< (PDEC_CTRLBSET) No action */
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#define PDEC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< (PDEC_CTRLBSET) Force a counter restart or retrigger */
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#define PDEC_CTRLBSET_CMD_UPDATE_Val _U_(0x2) /**< (PDEC_CTRLBSET) Force update of double buffered registers */
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#define PDEC_CTRLBSET_CMD_READSYNC_Val _U_(0x3) /**< (PDEC_CTRLBSET) Force a read synchronization of COUNT */
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#define PDEC_CTRLBSET_CMD_START_Val _U_(0x4) /**< (PDEC_CTRLBSET) Start QDEC/HALL */
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#define PDEC_CTRLBSET_CMD_STOP_Val _U_(0x5) /**< (PDEC_CTRLBSET) Stop QDEC/HALL */
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#define PDEC_CTRLBSET_CMD_NONE (PDEC_CTRLBSET_CMD_NONE_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) No action Position */
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#define PDEC_CTRLBSET_CMD_RETRIGGER (PDEC_CTRLBSET_CMD_RETRIGGER_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Force a counter restart or retrigger Position */
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#define PDEC_CTRLBSET_CMD_UPDATE (PDEC_CTRLBSET_CMD_UPDATE_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Force update of double buffered registers Position */
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#define PDEC_CTRLBSET_CMD_READSYNC (PDEC_CTRLBSET_CMD_READSYNC_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Force a read synchronization of COUNT Position */
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#define PDEC_CTRLBSET_CMD_START (PDEC_CTRLBSET_CMD_START_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Start QDEC/HALL Position */
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#define PDEC_CTRLBSET_CMD_STOP (PDEC_CTRLBSET_CMD_STOP_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Stop QDEC/HALL Position */
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#define PDEC_CTRLBSET_Msk _U_(0xE2) /**< (PDEC_CTRLBSET) Register Mask */
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/* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */
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#define PDEC_EVCTRL_RESETVALUE _U_(0x00) /**< (PDEC_EVCTRL) Event Control Reset Value */
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#define PDEC_EVCTRL_EVACT_Pos _U_(0) /**< (PDEC_EVCTRL) Event Action Position */
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#define PDEC_EVCTRL_EVACT_Msk (_U_(0x3) << PDEC_EVCTRL_EVACT_Pos) /**< (PDEC_EVCTRL) Event Action Mask */
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#define PDEC_EVCTRL_EVACT(value) (PDEC_EVCTRL_EVACT_Msk & ((value) << PDEC_EVCTRL_EVACT_Pos))
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#define PDEC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< (PDEC_EVCTRL) Event action disabled */
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#define PDEC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< (PDEC_EVCTRL) Start, restart or retrigger on event */
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#define PDEC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< (PDEC_EVCTRL) Count on event */
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#define PDEC_EVCTRL_EVACT_OFF (PDEC_EVCTRL_EVACT_OFF_Val << PDEC_EVCTRL_EVACT_Pos) /**< (PDEC_EVCTRL) Event action disabled Position */
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#define PDEC_EVCTRL_EVACT_RETRIGGER (PDEC_EVCTRL_EVACT_RETRIGGER_Val << PDEC_EVCTRL_EVACT_Pos) /**< (PDEC_EVCTRL) Start, restart or retrigger on event Position */
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#define PDEC_EVCTRL_EVACT_COUNT (PDEC_EVCTRL_EVACT_COUNT_Val << PDEC_EVCTRL_EVACT_Pos) /**< (PDEC_EVCTRL) Count on event Position */
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#define PDEC_EVCTRL_EVINV_Pos _U_(2) /**< (PDEC_EVCTRL) Inverted Event Input Enable Position */
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#define PDEC_EVCTRL_EVINV_Msk (_U_(0x7) << PDEC_EVCTRL_EVINV_Pos) /**< (PDEC_EVCTRL) Inverted Event Input Enable Mask */
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#define PDEC_EVCTRL_EVINV(value) (PDEC_EVCTRL_EVINV_Msk & ((value) << PDEC_EVCTRL_EVINV_Pos))
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#define PDEC_EVCTRL_EVEI_Pos _U_(5) /**< (PDEC_EVCTRL) Event Input Enable Position */
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#define PDEC_EVCTRL_EVEI_Msk (_U_(0x7) << PDEC_EVCTRL_EVEI_Pos) /**< (PDEC_EVCTRL) Event Input Enable Mask */
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#define PDEC_EVCTRL_EVEI(value) (PDEC_EVCTRL_EVEI_Msk & ((value) << PDEC_EVCTRL_EVEI_Pos))
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#define PDEC_EVCTRL_OVFEO_Pos _U_(8) /**< (PDEC_EVCTRL) Overflow/Underflow Output Event Enable Position */
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#define PDEC_EVCTRL_OVFEO_Msk (_U_(0x1) << PDEC_EVCTRL_OVFEO_Pos) /**< (PDEC_EVCTRL) Overflow/Underflow Output Event Enable Mask */
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#define PDEC_EVCTRL_OVFEO(value) (PDEC_EVCTRL_OVFEO_Msk & ((value) << PDEC_EVCTRL_OVFEO_Pos))
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#define PDEC_EVCTRL_ERREO_Pos _U_(9) /**< (PDEC_EVCTRL) Error Output Event Enable Position */
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#define PDEC_EVCTRL_ERREO_Msk (_U_(0x1) << PDEC_EVCTRL_ERREO_Pos) /**< (PDEC_EVCTRL) Error Output Event Enable Mask */
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#define PDEC_EVCTRL_ERREO(value) (PDEC_EVCTRL_ERREO_Msk & ((value) << PDEC_EVCTRL_ERREO_Pos))
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#define PDEC_EVCTRL_DIREO_Pos _U_(10) /**< (PDEC_EVCTRL) Direction Output Event Enable Position */
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#define PDEC_EVCTRL_DIREO_Msk (_U_(0x1) << PDEC_EVCTRL_DIREO_Pos) /**< (PDEC_EVCTRL) Direction Output Event Enable Mask */
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#define PDEC_EVCTRL_DIREO(value) (PDEC_EVCTRL_DIREO_Msk & ((value) << PDEC_EVCTRL_DIREO_Pos))
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#define PDEC_EVCTRL_VLCEO_Pos _U_(11) /**< (PDEC_EVCTRL) Velocity Output Event Enable Position */
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#define PDEC_EVCTRL_VLCEO_Msk (_U_(0x1) << PDEC_EVCTRL_VLCEO_Pos) /**< (PDEC_EVCTRL) Velocity Output Event Enable Mask */
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#define PDEC_EVCTRL_VLCEO(value) (PDEC_EVCTRL_VLCEO_Msk & ((value) << PDEC_EVCTRL_VLCEO_Pos))
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#define PDEC_EVCTRL_MCEO0_Pos _U_(12) /**< (PDEC_EVCTRL) Match Channel 0 Event Output Enable Position */
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#define PDEC_EVCTRL_MCEO0_Msk (_U_(0x1) << PDEC_EVCTRL_MCEO0_Pos) /**< (PDEC_EVCTRL) Match Channel 0 Event Output Enable Mask */
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#define PDEC_EVCTRL_MCEO0(value) (PDEC_EVCTRL_MCEO0_Msk & ((value) << PDEC_EVCTRL_MCEO0_Pos))
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#define PDEC_EVCTRL_MCEO1_Pos _U_(13) /**< (PDEC_EVCTRL) Match Channel 1 Event Output Enable Position */
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#define PDEC_EVCTRL_MCEO1_Msk (_U_(0x1) << PDEC_EVCTRL_MCEO1_Pos) /**< (PDEC_EVCTRL) Match Channel 1 Event Output Enable Mask */
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#define PDEC_EVCTRL_MCEO1(value) (PDEC_EVCTRL_MCEO1_Msk & ((value) << PDEC_EVCTRL_MCEO1_Pos))
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#define PDEC_EVCTRL_Msk _U_(0x3FFF) /**< (PDEC_EVCTRL) Register Mask */
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#define PDEC_EVCTRL_MCEO_Pos _U_(12) /**< (PDEC_EVCTRL Position) Match Channel x Event Output Enable */
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#define PDEC_EVCTRL_MCEO_Msk (_U_(0x3) << PDEC_EVCTRL_MCEO_Pos) /**< (PDEC_EVCTRL Mask) MCEO */
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#define PDEC_EVCTRL_MCEO(value) (PDEC_EVCTRL_MCEO_Msk & ((value) << PDEC_EVCTRL_MCEO_Pos))
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/* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
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#define PDEC_INTENCLR_RESETVALUE _U_(0x00) /**< (PDEC_INTENCLR) Interrupt Enable Clear Reset Value */
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#define PDEC_INTENCLR_OVF_Pos _U_(0) /**< (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable Position */
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#define PDEC_INTENCLR_OVF_Msk (_U_(0x1) << PDEC_INTENCLR_OVF_Pos) /**< (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable Mask */
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#define PDEC_INTENCLR_OVF(value) (PDEC_INTENCLR_OVF_Msk & ((value) << PDEC_INTENCLR_OVF_Pos))
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#define PDEC_INTENCLR_ERR_Pos _U_(1) /**< (PDEC_INTENCLR) Error Interrupt Disable Position */
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#define PDEC_INTENCLR_ERR_Msk (_U_(0x1) << PDEC_INTENCLR_ERR_Pos) /**< (PDEC_INTENCLR) Error Interrupt Disable Mask */
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#define PDEC_INTENCLR_ERR(value) (PDEC_INTENCLR_ERR_Msk & ((value) << PDEC_INTENCLR_ERR_Pos))
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#define PDEC_INTENCLR_DIR_Pos _U_(2) /**< (PDEC_INTENCLR) Direction Interrupt Disable Position */
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#define PDEC_INTENCLR_DIR_Msk (_U_(0x1) << PDEC_INTENCLR_DIR_Pos) /**< (PDEC_INTENCLR) Direction Interrupt Disable Mask */
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#define PDEC_INTENCLR_DIR(value) (PDEC_INTENCLR_DIR_Msk & ((value) << PDEC_INTENCLR_DIR_Pos))
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#define PDEC_INTENCLR_VLC_Pos _U_(3) /**< (PDEC_INTENCLR) Velocity Interrupt Disable Position */
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#define PDEC_INTENCLR_VLC_Msk (_U_(0x1) << PDEC_INTENCLR_VLC_Pos) /**< (PDEC_INTENCLR) Velocity Interrupt Disable Mask */
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#define PDEC_INTENCLR_VLC(value) (PDEC_INTENCLR_VLC_Msk & ((value) << PDEC_INTENCLR_VLC_Pos))
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#define PDEC_INTENCLR_MC0_Pos _U_(4) /**< (PDEC_INTENCLR) Channel 0 Compare Match Disable Position */
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#define PDEC_INTENCLR_MC0_Msk (_U_(0x1) << PDEC_INTENCLR_MC0_Pos) /**< (PDEC_INTENCLR) Channel 0 Compare Match Disable Mask */
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#define PDEC_INTENCLR_MC0(value) (PDEC_INTENCLR_MC0_Msk & ((value) << PDEC_INTENCLR_MC0_Pos))
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#define PDEC_INTENCLR_MC1_Pos _U_(5) /**< (PDEC_INTENCLR) Channel 1 Compare Match Disable Position */
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#define PDEC_INTENCLR_MC1_Msk (_U_(0x1) << PDEC_INTENCLR_MC1_Pos) /**< (PDEC_INTENCLR) Channel 1 Compare Match Disable Mask */
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#define PDEC_INTENCLR_MC1(value) (PDEC_INTENCLR_MC1_Msk & ((value) << PDEC_INTENCLR_MC1_Pos))
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#define PDEC_INTENCLR_Msk _U_(0x3F) /**< (PDEC_INTENCLR) Register Mask */
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#define PDEC_INTENCLR_MC_Pos _U_(4) /**< (PDEC_INTENCLR Position) Channel x Compare Match Disable */
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#define PDEC_INTENCLR_MC_Msk (_U_(0x3) << PDEC_INTENCLR_MC_Pos) /**< (PDEC_INTENCLR Mask) MC */
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#define PDEC_INTENCLR_MC(value) (PDEC_INTENCLR_MC_Msk & ((value) << PDEC_INTENCLR_MC_Pos))
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/* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
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#define PDEC_INTENSET_RESETVALUE _U_(0x00) /**< (PDEC_INTENSET) Interrupt Enable Set Reset Value */
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#define PDEC_INTENSET_OVF_Pos _U_(0) /**< (PDEC_INTENSET) Overflow/Underflow Interrupt Enable Position */
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#define PDEC_INTENSET_OVF_Msk (_U_(0x1) << PDEC_INTENSET_OVF_Pos) /**< (PDEC_INTENSET) Overflow/Underflow Interrupt Enable Mask */
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#define PDEC_INTENSET_OVF(value) (PDEC_INTENSET_OVF_Msk & ((value) << PDEC_INTENSET_OVF_Pos))
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#define PDEC_INTENSET_ERR_Pos _U_(1) /**< (PDEC_INTENSET) Error Interrupt Enable Position */
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#define PDEC_INTENSET_ERR_Msk (_U_(0x1) << PDEC_INTENSET_ERR_Pos) /**< (PDEC_INTENSET) Error Interrupt Enable Mask */
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#define PDEC_INTENSET_ERR(value) (PDEC_INTENSET_ERR_Msk & ((value) << PDEC_INTENSET_ERR_Pos))
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#define PDEC_INTENSET_DIR_Pos _U_(2) /**< (PDEC_INTENSET) Direction Interrupt Enable Position */
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#define PDEC_INTENSET_DIR_Msk (_U_(0x1) << PDEC_INTENSET_DIR_Pos) /**< (PDEC_INTENSET) Direction Interrupt Enable Mask */
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#define PDEC_INTENSET_DIR(value) (PDEC_INTENSET_DIR_Msk & ((value) << PDEC_INTENSET_DIR_Pos))
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#define PDEC_INTENSET_VLC_Pos _U_(3) /**< (PDEC_INTENSET) Velocity Interrupt Enable Position */
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#define PDEC_INTENSET_VLC_Msk (_U_(0x1) << PDEC_INTENSET_VLC_Pos) /**< (PDEC_INTENSET) Velocity Interrupt Enable Mask */
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#define PDEC_INTENSET_VLC(value) (PDEC_INTENSET_VLC_Msk & ((value) << PDEC_INTENSET_VLC_Pos))
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#define PDEC_INTENSET_MC0_Pos _U_(4) /**< (PDEC_INTENSET) Channel 0 Compare Match Enable Position */
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#define PDEC_INTENSET_MC0_Msk (_U_(0x1) << PDEC_INTENSET_MC0_Pos) /**< (PDEC_INTENSET) Channel 0 Compare Match Enable Mask */
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#define PDEC_INTENSET_MC0(value) (PDEC_INTENSET_MC0_Msk & ((value) << PDEC_INTENSET_MC0_Pos))
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#define PDEC_INTENSET_MC1_Pos _U_(5) /**< (PDEC_INTENSET) Channel 1 Compare Match Enable Position */
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#define PDEC_INTENSET_MC1_Msk (_U_(0x1) << PDEC_INTENSET_MC1_Pos) /**< (PDEC_INTENSET) Channel 1 Compare Match Enable Mask */
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#define PDEC_INTENSET_MC1(value) (PDEC_INTENSET_MC1_Msk & ((value) << PDEC_INTENSET_MC1_Pos))
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#define PDEC_INTENSET_Msk _U_(0x3F) /**< (PDEC_INTENSET) Register Mask */
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#define PDEC_INTENSET_MC_Pos _U_(4) /**< (PDEC_INTENSET Position) Channel x Compare Match Enable */
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#define PDEC_INTENSET_MC_Msk (_U_(0x3) << PDEC_INTENSET_MC_Pos) /**< (PDEC_INTENSET Mask) MC */
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#define PDEC_INTENSET_MC(value) (PDEC_INTENSET_MC_Msk & ((value) << PDEC_INTENSET_MC_Pos))
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/* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
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#define PDEC_INTFLAG_RESETVALUE _U_(0x00) /**< (PDEC_INTFLAG) Interrupt Flag Status and Clear Reset Value */
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#define PDEC_INTFLAG_OVF_Pos _U_(0) /**< (PDEC_INTFLAG) Overflow/Underflow Position */
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#define PDEC_INTFLAG_OVF_Msk (_U_(0x1) << PDEC_INTFLAG_OVF_Pos) /**< (PDEC_INTFLAG) Overflow/Underflow Mask */
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#define PDEC_INTFLAG_OVF(value) (PDEC_INTFLAG_OVF_Msk & ((value) << PDEC_INTFLAG_OVF_Pos))
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#define PDEC_INTFLAG_ERR_Pos _U_(1) /**< (PDEC_INTFLAG) Error Position */
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#define PDEC_INTFLAG_ERR_Msk (_U_(0x1) << PDEC_INTFLAG_ERR_Pos) /**< (PDEC_INTFLAG) Error Mask */
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#define PDEC_INTFLAG_ERR(value) (PDEC_INTFLAG_ERR_Msk & ((value) << PDEC_INTFLAG_ERR_Pos))
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#define PDEC_INTFLAG_DIR_Pos _U_(2) /**< (PDEC_INTFLAG) Direction Change Position */
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#define PDEC_INTFLAG_DIR_Msk (_U_(0x1) << PDEC_INTFLAG_DIR_Pos) /**< (PDEC_INTFLAG) Direction Change Mask */
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#define PDEC_INTFLAG_DIR(value) (PDEC_INTFLAG_DIR_Msk & ((value) << PDEC_INTFLAG_DIR_Pos))
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#define PDEC_INTFLAG_VLC_Pos _U_(3) /**< (PDEC_INTFLAG) Velocity Position */
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#define PDEC_INTFLAG_VLC_Msk (_U_(0x1) << PDEC_INTFLAG_VLC_Pos) /**< (PDEC_INTFLAG) Velocity Mask */
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#define PDEC_INTFLAG_VLC(value) (PDEC_INTFLAG_VLC_Msk & ((value) << PDEC_INTFLAG_VLC_Pos))
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#define PDEC_INTFLAG_MC0_Pos _U_(4) /**< (PDEC_INTFLAG) Channel 0 Compare Match Position */
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#define PDEC_INTFLAG_MC0_Msk (_U_(0x1) << PDEC_INTFLAG_MC0_Pos) /**< (PDEC_INTFLAG) Channel 0 Compare Match Mask */
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#define PDEC_INTFLAG_MC0(value) (PDEC_INTFLAG_MC0_Msk & ((value) << PDEC_INTFLAG_MC0_Pos))
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#define PDEC_INTFLAG_MC1_Pos _U_(5) /**< (PDEC_INTFLAG) Channel 1 Compare Match Position */
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#define PDEC_INTFLAG_MC1_Msk (_U_(0x1) << PDEC_INTFLAG_MC1_Pos) /**< (PDEC_INTFLAG) Channel 1 Compare Match Mask */
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#define PDEC_INTFLAG_MC1(value) (PDEC_INTFLAG_MC1_Msk & ((value) << PDEC_INTFLAG_MC1_Pos))
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#define PDEC_INTFLAG_Msk _U_(0x3F) /**< (PDEC_INTFLAG) Register Mask */
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#define PDEC_INTFLAG_MC_Pos _U_(4) /**< (PDEC_INTFLAG Position) Channel x Compare Match */
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#define PDEC_INTFLAG_MC_Msk (_U_(0x3) << PDEC_INTFLAG_MC_Pos) /**< (PDEC_INTFLAG Mask) MC */
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#define PDEC_INTFLAG_MC(value) (PDEC_INTFLAG_MC_Msk & ((value) << PDEC_INTFLAG_MC_Pos))
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/* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */
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#define PDEC_STATUS_RESETVALUE _U_(0x40) /**< (PDEC_STATUS) Status Reset Value */
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#define PDEC_STATUS_QERR_Pos _U_(0) /**< (PDEC_STATUS) Quadrature Error Flag Position */
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#define PDEC_STATUS_QERR_Msk (_U_(0x1) << PDEC_STATUS_QERR_Pos) /**< (PDEC_STATUS) Quadrature Error Flag Mask */
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#define PDEC_STATUS_QERR(value) (PDEC_STATUS_QERR_Msk & ((value) << PDEC_STATUS_QERR_Pos))
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#define PDEC_STATUS_IDXERR_Pos _U_(1) /**< (PDEC_STATUS) Index Error Flag Position */
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#define PDEC_STATUS_IDXERR_Msk (_U_(0x1) << PDEC_STATUS_IDXERR_Pos) /**< (PDEC_STATUS) Index Error Flag Mask */
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#define PDEC_STATUS_IDXERR(value) (PDEC_STATUS_IDXERR_Msk & ((value) << PDEC_STATUS_IDXERR_Pos))
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#define PDEC_STATUS_MPERR_Pos _U_(2) /**< (PDEC_STATUS) Missing Pulse Error flag Position */
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#define PDEC_STATUS_MPERR_Msk (_U_(0x1) << PDEC_STATUS_MPERR_Pos) /**< (PDEC_STATUS) Missing Pulse Error flag Mask */
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#define PDEC_STATUS_MPERR(value) (PDEC_STATUS_MPERR_Msk & ((value) << PDEC_STATUS_MPERR_Pos))
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#define PDEC_STATUS_WINERR_Pos _U_(4) /**< (PDEC_STATUS) Window Error Flag Position */
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#define PDEC_STATUS_WINERR_Msk (_U_(0x1) << PDEC_STATUS_WINERR_Pos) /**< (PDEC_STATUS) Window Error Flag Mask */
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#define PDEC_STATUS_WINERR(value) (PDEC_STATUS_WINERR_Msk & ((value) << PDEC_STATUS_WINERR_Pos))
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#define PDEC_STATUS_HERR_Pos _U_(5) /**< (PDEC_STATUS) Hall Error Flag Position */
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#define PDEC_STATUS_HERR_Msk (_U_(0x1) << PDEC_STATUS_HERR_Pos) /**< (PDEC_STATUS) Hall Error Flag Mask */
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#define PDEC_STATUS_HERR(value) (PDEC_STATUS_HERR_Msk & ((value) << PDEC_STATUS_HERR_Pos))
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#define PDEC_STATUS_STOP_Pos _U_(6) /**< (PDEC_STATUS) Stop Position */
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#define PDEC_STATUS_STOP_Msk (_U_(0x1) << PDEC_STATUS_STOP_Pos) /**< (PDEC_STATUS) Stop Mask */
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#define PDEC_STATUS_STOP(value) (PDEC_STATUS_STOP_Msk & ((value) << PDEC_STATUS_STOP_Pos))
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#define PDEC_STATUS_DIR_Pos _U_(7) /**< (PDEC_STATUS) Direction Status Flag Position */
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#define PDEC_STATUS_DIR_Msk (_U_(0x1) << PDEC_STATUS_DIR_Pos) /**< (PDEC_STATUS) Direction Status Flag Mask */
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#define PDEC_STATUS_DIR(value) (PDEC_STATUS_DIR_Msk & ((value) << PDEC_STATUS_DIR_Pos))
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#define PDEC_STATUS_PRESCBUFV_Pos _U_(8) /**< (PDEC_STATUS) Prescaler Buffer Valid Position */
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#define PDEC_STATUS_PRESCBUFV_Msk (_U_(0x1) << PDEC_STATUS_PRESCBUFV_Pos) /**< (PDEC_STATUS) Prescaler Buffer Valid Mask */
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#define PDEC_STATUS_PRESCBUFV(value) (PDEC_STATUS_PRESCBUFV_Msk & ((value) << PDEC_STATUS_PRESCBUFV_Pos))
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#define PDEC_STATUS_FILTERBUFV_Pos _U_(9) /**< (PDEC_STATUS) Filter Buffer Valid Position */
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#define PDEC_STATUS_FILTERBUFV_Msk (_U_(0x1) << PDEC_STATUS_FILTERBUFV_Pos) /**< (PDEC_STATUS) Filter Buffer Valid Mask */
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#define PDEC_STATUS_FILTERBUFV(value) (PDEC_STATUS_FILTERBUFV_Msk & ((value) << PDEC_STATUS_FILTERBUFV_Pos))
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#define PDEC_STATUS_CCBUFV0_Pos _U_(12) /**< (PDEC_STATUS) Compare Channel 0 Buffer Valid Position */
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#define PDEC_STATUS_CCBUFV0_Msk (_U_(0x1) << PDEC_STATUS_CCBUFV0_Pos) /**< (PDEC_STATUS) Compare Channel 0 Buffer Valid Mask */
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#define PDEC_STATUS_CCBUFV0(value) (PDEC_STATUS_CCBUFV0_Msk & ((value) << PDEC_STATUS_CCBUFV0_Pos))
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#define PDEC_STATUS_CCBUFV1_Pos _U_(13) /**< (PDEC_STATUS) Compare Channel 1 Buffer Valid Position */
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#define PDEC_STATUS_CCBUFV1_Msk (_U_(0x1) << PDEC_STATUS_CCBUFV1_Pos) /**< (PDEC_STATUS) Compare Channel 1 Buffer Valid Mask */
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#define PDEC_STATUS_CCBUFV1(value) (PDEC_STATUS_CCBUFV1_Msk & ((value) << PDEC_STATUS_CCBUFV1_Pos))
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#define PDEC_STATUS_Msk _U_(0x33F7) /**< (PDEC_STATUS) Register Mask */
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#define PDEC_STATUS_CCBUFV_Pos _U_(12) /**< (PDEC_STATUS Position) Compare Channel x Buffer Valid */
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#define PDEC_STATUS_CCBUFV_Msk (_U_(0x3) << PDEC_STATUS_CCBUFV_Pos) /**< (PDEC_STATUS Mask) CCBUFV */
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#define PDEC_STATUS_CCBUFV(value) (PDEC_STATUS_CCBUFV_Msk & ((value) << PDEC_STATUS_CCBUFV_Pos))
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/* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W 8) Debug Control -------- */
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#define PDEC_DBGCTRL_RESETVALUE _U_(0x00) /**< (PDEC_DBGCTRL) Debug Control Reset Value */
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#define PDEC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (PDEC_DBGCTRL) Debug Run Mode Position */
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#define PDEC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << PDEC_DBGCTRL_DBGRUN_Pos) /**< (PDEC_DBGCTRL) Debug Run Mode Mask */
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#define PDEC_DBGCTRL_DBGRUN(value) (PDEC_DBGCTRL_DBGRUN_Msk & ((value) << PDEC_DBGCTRL_DBGRUN_Pos))
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#define PDEC_DBGCTRL_Msk _U_(0x01) /**< (PDEC_DBGCTRL) Register Mask */
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/* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) ( R/ 32) Synchronization Status -------- */
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#define PDEC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (PDEC_SYNCBUSY) Synchronization Status Reset Value */
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#define PDEC_SYNCBUSY_SWRST_Pos _U_(0) /**< (PDEC_SYNCBUSY) Software Reset Synchronization Busy Position */
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#define PDEC_SYNCBUSY_SWRST_Msk (_U_(0x1) << PDEC_SYNCBUSY_SWRST_Pos) /**< (PDEC_SYNCBUSY) Software Reset Synchronization Busy Mask */
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#define PDEC_SYNCBUSY_SWRST(value) (PDEC_SYNCBUSY_SWRST_Msk & ((value) << PDEC_SYNCBUSY_SWRST_Pos))
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#define PDEC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (PDEC_SYNCBUSY) Enable Synchronization Busy Position */
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#define PDEC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << PDEC_SYNCBUSY_ENABLE_Pos) /**< (PDEC_SYNCBUSY) Enable Synchronization Busy Mask */
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#define PDEC_SYNCBUSY_ENABLE(value) (PDEC_SYNCBUSY_ENABLE_Msk & ((value) << PDEC_SYNCBUSY_ENABLE_Pos))
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#define PDEC_SYNCBUSY_CTRLB_Pos _U_(2) /**< (PDEC_SYNCBUSY) Control B Synchronization Busy Position */
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#define PDEC_SYNCBUSY_CTRLB_Msk (_U_(0x1) << PDEC_SYNCBUSY_CTRLB_Pos) /**< (PDEC_SYNCBUSY) Control B Synchronization Busy Mask */
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#define PDEC_SYNCBUSY_CTRLB(value) (PDEC_SYNCBUSY_CTRLB_Msk & ((value) << PDEC_SYNCBUSY_CTRLB_Pos))
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#define PDEC_SYNCBUSY_STATUS_Pos _U_(3) /**< (PDEC_SYNCBUSY) Status Synchronization Busy Position */
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#define PDEC_SYNCBUSY_STATUS_Msk (_U_(0x1) << PDEC_SYNCBUSY_STATUS_Pos) /**< (PDEC_SYNCBUSY) Status Synchronization Busy Mask */
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#define PDEC_SYNCBUSY_STATUS(value) (PDEC_SYNCBUSY_STATUS_Msk & ((value) << PDEC_SYNCBUSY_STATUS_Pos))
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#define PDEC_SYNCBUSY_PRESC_Pos _U_(4) /**< (PDEC_SYNCBUSY) Prescaler Synchronization Busy Position */
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#define PDEC_SYNCBUSY_PRESC_Msk (_U_(0x1) << PDEC_SYNCBUSY_PRESC_Pos) /**< (PDEC_SYNCBUSY) Prescaler Synchronization Busy Mask */
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#define PDEC_SYNCBUSY_PRESC(value) (PDEC_SYNCBUSY_PRESC_Msk & ((value) << PDEC_SYNCBUSY_PRESC_Pos))
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#define PDEC_SYNCBUSY_FILTER_Pos _U_(5) /**< (PDEC_SYNCBUSY) Filter Synchronization Busy Position */
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#define PDEC_SYNCBUSY_FILTER_Msk (_U_(0x1) << PDEC_SYNCBUSY_FILTER_Pos) /**< (PDEC_SYNCBUSY) Filter Synchronization Busy Mask */
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#define PDEC_SYNCBUSY_FILTER(value) (PDEC_SYNCBUSY_FILTER_Msk & ((value) << PDEC_SYNCBUSY_FILTER_Pos))
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#define PDEC_SYNCBUSY_COUNT_Pos _U_(6) /**< (PDEC_SYNCBUSY) Count Synchronization Busy Position */
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#define PDEC_SYNCBUSY_COUNT_Msk (_U_(0x1) << PDEC_SYNCBUSY_COUNT_Pos) /**< (PDEC_SYNCBUSY) Count Synchronization Busy Mask */
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#define PDEC_SYNCBUSY_COUNT(value) (PDEC_SYNCBUSY_COUNT_Msk & ((value) << PDEC_SYNCBUSY_COUNT_Pos))
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#define PDEC_SYNCBUSY_CC0_Pos _U_(7) /**< (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy Position */
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#define PDEC_SYNCBUSY_CC0_Msk (_U_(0x1) << PDEC_SYNCBUSY_CC0_Pos) /**< (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy Mask */
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#define PDEC_SYNCBUSY_CC0(value) (PDEC_SYNCBUSY_CC0_Msk & ((value) << PDEC_SYNCBUSY_CC0_Pos))
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#define PDEC_SYNCBUSY_CC1_Pos _U_(8) /**< (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy Position */
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#define PDEC_SYNCBUSY_CC1_Msk (_U_(0x1) << PDEC_SYNCBUSY_CC1_Pos) /**< (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy Mask */
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#define PDEC_SYNCBUSY_CC1(value) (PDEC_SYNCBUSY_CC1_Msk & ((value) << PDEC_SYNCBUSY_CC1_Pos))
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#define PDEC_SYNCBUSY_Msk _U_(0x000001FF) /**< (PDEC_SYNCBUSY) Register Mask */
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#define PDEC_SYNCBUSY_CC_Pos _U_(7) /**< (PDEC_SYNCBUSY Position) Compare Channel x Synchronization Busy */
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#define PDEC_SYNCBUSY_CC_Msk (_U_(0x3) << PDEC_SYNCBUSY_CC_Pos) /**< (PDEC_SYNCBUSY Mask) CC */
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#define PDEC_SYNCBUSY_CC(value) (PDEC_SYNCBUSY_CC_Msk & ((value) << PDEC_SYNCBUSY_CC_Pos))
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/* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W 8) Prescaler Value -------- */
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#define PDEC_PRESC_RESETVALUE _U_(0x00) /**< (PDEC_PRESC) Prescaler Value Reset Value */
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#define PDEC_PRESC_PRESC_Pos _U_(0) /**< (PDEC_PRESC) Prescaler Value Position */
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#define PDEC_PRESC_PRESC_Msk (_U_(0xF) << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Prescaler Value Mask */
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#define PDEC_PRESC_PRESC(value) (PDEC_PRESC_PRESC_Msk & ((value) << PDEC_PRESC_PRESC_Pos))
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#define PDEC_PRESC_PRESC_DIV1_Val _U_(0x0) /**< (PDEC_PRESC) No division */
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#define PDEC_PRESC_PRESC_DIV2_Val _U_(0x1) /**< (PDEC_PRESC) Divide by 2 */
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#define PDEC_PRESC_PRESC_DIV4_Val _U_(0x2) /**< (PDEC_PRESC) Divide by 4 */
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#define PDEC_PRESC_PRESC_DIV8_Val _U_(0x3) /**< (PDEC_PRESC) Divide by 8 */
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#define PDEC_PRESC_PRESC_DIV16_Val _U_(0x4) /**< (PDEC_PRESC) Divide by 16 */
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#define PDEC_PRESC_PRESC_DIV32_Val _U_(0x5) /**< (PDEC_PRESC) Divide by 32 */
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#define PDEC_PRESC_PRESC_DIV64_Val _U_(0x6) /**< (PDEC_PRESC) Divide by 64 */
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#define PDEC_PRESC_PRESC_DIV128_Val _U_(0x7) /**< (PDEC_PRESC) Divide by 128 */
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#define PDEC_PRESC_PRESC_DIV256_Val _U_(0x8) /**< (PDEC_PRESC) Divide by 256 */
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#define PDEC_PRESC_PRESC_DIV512_Val _U_(0x9) /**< (PDEC_PRESC) Divide by 512 */
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#define PDEC_PRESC_PRESC_DIV1024_Val _U_(0xA) /**< (PDEC_PRESC) Divide by 1024 */
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#define PDEC_PRESC_PRESC_DIV1 (PDEC_PRESC_PRESC_DIV1_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) No division Position */
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#define PDEC_PRESC_PRESC_DIV2 (PDEC_PRESC_PRESC_DIV2_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 2 Position */
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#define PDEC_PRESC_PRESC_DIV4 (PDEC_PRESC_PRESC_DIV4_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 4 Position */
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#define PDEC_PRESC_PRESC_DIV8 (PDEC_PRESC_PRESC_DIV8_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 8 Position */
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#define PDEC_PRESC_PRESC_DIV16 (PDEC_PRESC_PRESC_DIV16_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 16 Position */
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#define PDEC_PRESC_PRESC_DIV32 (PDEC_PRESC_PRESC_DIV32_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 32 Position */
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#define PDEC_PRESC_PRESC_DIV64 (PDEC_PRESC_PRESC_DIV64_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 64 Position */
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#define PDEC_PRESC_PRESC_DIV128 (PDEC_PRESC_PRESC_DIV128_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 128 Position */
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#define PDEC_PRESC_PRESC_DIV256 (PDEC_PRESC_PRESC_DIV256_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 256 Position */
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#define PDEC_PRESC_PRESC_DIV512 (PDEC_PRESC_PRESC_DIV512_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 512 Position */
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#define PDEC_PRESC_PRESC_DIV1024 (PDEC_PRESC_PRESC_DIV1024_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 1024 Position */
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#define PDEC_PRESC_Msk _U_(0x0F) /**< (PDEC_PRESC) Register Mask */
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/* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W 8) Filter Value -------- */
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#define PDEC_FILTER_RESETVALUE _U_(0x00) /**< (PDEC_FILTER) Filter Value Reset Value */
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#define PDEC_FILTER_FILTER_Pos _U_(0) /**< (PDEC_FILTER) Filter Value Position */
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#define PDEC_FILTER_FILTER_Msk (_U_(0xFF) << PDEC_FILTER_FILTER_Pos) /**< (PDEC_FILTER) Filter Value Mask */
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#define PDEC_FILTER_FILTER(value) (PDEC_FILTER_FILTER_Msk & ((value) << PDEC_FILTER_FILTER_Pos))
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#define PDEC_FILTER_Msk _U_(0xFF) /**< (PDEC_FILTER) Register Mask */
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/* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W 8) Prescaler Buffer Value -------- */
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#define PDEC_PRESCBUF_RESETVALUE _U_(0x00) /**< (PDEC_PRESCBUF) Prescaler Buffer Value Reset Value */
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#define PDEC_PRESCBUF_PRESCBUF_Pos _U_(0) /**< (PDEC_PRESCBUF) Prescaler Buffer Value Position */
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#define PDEC_PRESCBUF_PRESCBUF_Msk (_U_(0xF) << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Prescaler Buffer Value Mask */
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#define PDEC_PRESCBUF_PRESCBUF(value) (PDEC_PRESCBUF_PRESCBUF_Msk & ((value) << PDEC_PRESCBUF_PRESCBUF_Pos))
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#define PDEC_PRESCBUF_PRESCBUF_DIV1_Val _U_(0x0) /**< (PDEC_PRESCBUF) No division */
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#define PDEC_PRESCBUF_PRESCBUF_DIV2_Val _U_(0x1) /**< (PDEC_PRESCBUF) Divide by 2 */
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#define PDEC_PRESCBUF_PRESCBUF_DIV4_Val _U_(0x2) /**< (PDEC_PRESCBUF) Divide by 4 */
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#define PDEC_PRESCBUF_PRESCBUF_DIV8_Val _U_(0x3) /**< (PDEC_PRESCBUF) Divide by 8 */
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#define PDEC_PRESCBUF_PRESCBUF_DIV16_Val _U_(0x4) /**< (PDEC_PRESCBUF) Divide by 16 */
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#define PDEC_PRESCBUF_PRESCBUF_DIV32_Val _U_(0x5) /**< (PDEC_PRESCBUF) Divide by 32 */
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#define PDEC_PRESCBUF_PRESCBUF_DIV64_Val _U_(0x6) /**< (PDEC_PRESCBUF) Divide by 64 */
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#define PDEC_PRESCBUF_PRESCBUF_DIV128_Val _U_(0x7) /**< (PDEC_PRESCBUF) Divide by 128 */
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#define PDEC_PRESCBUF_PRESCBUF_DIV256_Val _U_(0x8) /**< (PDEC_PRESCBUF) Divide by 256 */
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#define PDEC_PRESCBUF_PRESCBUF_DIV512_Val _U_(0x9) /**< (PDEC_PRESCBUF) Divide by 512 */
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#define PDEC_PRESCBUF_PRESCBUF_DIV1024_Val _U_(0xA) /**< (PDEC_PRESCBUF) Divide by 1024 */
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#define PDEC_PRESCBUF_PRESCBUF_DIV1 (PDEC_PRESCBUF_PRESCBUF_DIV1_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) No division Position */
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#define PDEC_PRESCBUF_PRESCBUF_DIV2 (PDEC_PRESCBUF_PRESCBUF_DIV2_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 2 Position */
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#define PDEC_PRESCBUF_PRESCBUF_DIV4 (PDEC_PRESCBUF_PRESCBUF_DIV4_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 4 Position */
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#define PDEC_PRESCBUF_PRESCBUF_DIV8 (PDEC_PRESCBUF_PRESCBUF_DIV8_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 8 Position */
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#define PDEC_PRESCBUF_PRESCBUF_DIV16 (PDEC_PRESCBUF_PRESCBUF_DIV16_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 16 Position */
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#define PDEC_PRESCBUF_PRESCBUF_DIV32 (PDEC_PRESCBUF_PRESCBUF_DIV32_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 32 Position */
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#define PDEC_PRESCBUF_PRESCBUF_DIV64 (PDEC_PRESCBUF_PRESCBUF_DIV64_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 64 Position */
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#define PDEC_PRESCBUF_PRESCBUF_DIV128 (PDEC_PRESCBUF_PRESCBUF_DIV128_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 128 Position */
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#define PDEC_PRESCBUF_PRESCBUF_DIV256 (PDEC_PRESCBUF_PRESCBUF_DIV256_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 256 Position */
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#define PDEC_PRESCBUF_PRESCBUF_DIV512 (PDEC_PRESCBUF_PRESCBUF_DIV512_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 512 Position */
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#define PDEC_PRESCBUF_PRESCBUF_DIV1024 (PDEC_PRESCBUF_PRESCBUF_DIV1024_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 1024 Position */
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#define PDEC_PRESCBUF_Msk _U_(0x0F) /**< (PDEC_PRESCBUF) Register Mask */
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/* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W 8) Filter Buffer Value -------- */
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#define PDEC_FILTERBUF_RESETVALUE _U_(0x00) /**< (PDEC_FILTERBUF) Filter Buffer Value Reset Value */
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#define PDEC_FILTERBUF_FILTERBUF_Pos _U_(0) /**< (PDEC_FILTERBUF) Filter Buffer Value Position */
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#define PDEC_FILTERBUF_FILTERBUF_Msk (_U_(0xFF) << PDEC_FILTERBUF_FILTERBUF_Pos) /**< (PDEC_FILTERBUF) Filter Buffer Value Mask */
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#define PDEC_FILTERBUF_FILTERBUF(value) (PDEC_FILTERBUF_FILTERBUF_Msk & ((value) << PDEC_FILTERBUF_FILTERBUF_Pos))
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#define PDEC_FILTERBUF_Msk _U_(0xFF) /**< (PDEC_FILTERBUF) Register Mask */
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/* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */
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#define PDEC_COUNT_RESETVALUE _U_(0x00) /**< (PDEC_COUNT) Counter Value Reset Value */
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#define PDEC_COUNT_COUNT_Pos _U_(0) /**< (PDEC_COUNT) Counter Value Position */
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#define PDEC_COUNT_COUNT_Msk (_U_(0xFFFF) << PDEC_COUNT_COUNT_Pos) /**< (PDEC_COUNT) Counter Value Mask */
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#define PDEC_COUNT_COUNT(value) (PDEC_COUNT_COUNT_Msk & ((value) << PDEC_COUNT_COUNT_Pos))
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#define PDEC_COUNT_Msk _U_(0x0000FFFF) /**< (PDEC_COUNT) Register Mask */
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/* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */
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#define PDEC_CC_RESETVALUE _U_(0x00) /**< (PDEC_CC) Channel n Compare Value Reset Value */
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#define PDEC_CC_CC_Pos _U_(0) /**< (PDEC_CC) Channel Compare Value Position */
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#define PDEC_CC_CC_Msk (_U_(0xFFFF) << PDEC_CC_CC_Pos) /**< (PDEC_CC) Channel Compare Value Mask */
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#define PDEC_CC_CC(value) (PDEC_CC_CC_Msk & ((value) << PDEC_CC_CC_Pos))
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#define PDEC_CC_Msk _U_(0x0000FFFF) /**< (PDEC_CC) Register Mask */
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/* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */
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#define PDEC_CCBUF_RESETVALUE _U_(0x00) /**< (PDEC_CCBUF) Channel Compare Buffer Value Reset Value */
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#define PDEC_CCBUF_CCBUF_Pos _U_(0) /**< (PDEC_CCBUF) Channel Compare Buffer Value Position */
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#define PDEC_CCBUF_CCBUF_Msk (_U_(0xFFFF) << PDEC_CCBUF_CCBUF_Pos) /**< (PDEC_CCBUF) Channel Compare Buffer Value Mask */
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#define PDEC_CCBUF_CCBUF(value) (PDEC_CCBUF_CCBUF_Msk & ((value) << PDEC_CCBUF_CCBUF_Pos))
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#define PDEC_CCBUF_Msk _U_(0x0000FFFF) /**< (PDEC_CCBUF) Register Mask */
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/** \brief PDEC register offsets definitions */
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#define PDEC_CTRLA_REG_OFST (0x00) /**< (PDEC_CTRLA) Control A Offset */
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#define PDEC_CTRLBCLR_REG_OFST (0x04) /**< (PDEC_CTRLBCLR) Control B Clear Offset */
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#define PDEC_CTRLBSET_REG_OFST (0x05) /**< (PDEC_CTRLBSET) Control B Set Offset */
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#define PDEC_EVCTRL_REG_OFST (0x06) /**< (PDEC_EVCTRL) Event Control Offset */
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#define PDEC_INTENCLR_REG_OFST (0x08) /**< (PDEC_INTENCLR) Interrupt Enable Clear Offset */
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#define PDEC_INTENSET_REG_OFST (0x09) /**< (PDEC_INTENSET) Interrupt Enable Set Offset */
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#define PDEC_INTFLAG_REG_OFST (0x0A) /**< (PDEC_INTFLAG) Interrupt Flag Status and Clear Offset */
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#define PDEC_STATUS_REG_OFST (0x0C) /**< (PDEC_STATUS) Status Offset */
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#define PDEC_DBGCTRL_REG_OFST (0x0F) /**< (PDEC_DBGCTRL) Debug Control Offset */
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#define PDEC_SYNCBUSY_REG_OFST (0x10) /**< (PDEC_SYNCBUSY) Synchronization Status Offset */
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#define PDEC_PRESC_REG_OFST (0x14) /**< (PDEC_PRESC) Prescaler Value Offset */
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#define PDEC_FILTER_REG_OFST (0x15) /**< (PDEC_FILTER) Filter Value Offset */
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#define PDEC_PRESCBUF_REG_OFST (0x18) /**< (PDEC_PRESCBUF) Prescaler Buffer Value Offset */
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#define PDEC_FILTERBUF_REG_OFST (0x19) /**< (PDEC_FILTERBUF) Filter Buffer Value Offset */
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#define PDEC_COUNT_REG_OFST (0x1C) /**< (PDEC_COUNT) Counter Value Offset */
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#define PDEC_CC_REG_OFST (0x20) /**< (PDEC_CC) Channel n Compare Value Offset */
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#define PDEC_CCBUF_REG_OFST (0x30) /**< (PDEC_CCBUF) Channel Compare Buffer Value Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief PDEC register API structure */
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typedef struct
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{ /* Quadrature Decodeur */
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__IO uint32_t PDEC_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */
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__IO uint8_t PDEC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */
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__IO uint8_t PDEC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */
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__IO uint16_t PDEC_EVCTRL; /**< Offset: 0x06 (R/W 16) Event Control */
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__IO uint8_t PDEC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */
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__IO uint8_t PDEC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */
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__IO uint8_t PDEC_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
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__I uint8_t Reserved1[0x01];
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__IO uint16_t PDEC_STATUS; /**< Offset: 0x0C (R/W 16) Status */
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__I uint8_t Reserved2[0x01];
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__IO uint8_t PDEC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */
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__I uint32_t PDEC_SYNCBUSY; /**< Offset: 0x10 (R/ 32) Synchronization Status */
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__IO uint8_t PDEC_PRESC; /**< Offset: 0x14 (R/W 8) Prescaler Value */
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__IO uint8_t PDEC_FILTER; /**< Offset: 0x15 (R/W 8) Filter Value */
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__I uint8_t Reserved3[0x02];
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__IO uint8_t PDEC_PRESCBUF; /**< Offset: 0x18 (R/W 8) Prescaler Buffer Value */
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__IO uint8_t PDEC_FILTERBUF; /**< Offset: 0x19 (R/W 8) Filter Buffer Value */
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__I uint8_t Reserved4[0x02];
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__IO uint32_t PDEC_COUNT; /**< Offset: 0x1C (R/W 32) Counter Value */
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__IO uint32_t PDEC_CC[2]; /**< Offset: 0x20 (R/W 32) Channel n Compare Value */
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__I uint8_t Reserved5[0x08];
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__IO uint32_t PDEC_CCBUF[2]; /**< Offset: 0x30 (R/W 32) Channel Compare Buffer Value */
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} pdec_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAMD51_PDEC_COMPONENT_H_ */
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