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< a href = "#define-members" > Macros< / a > < / div >
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< div class = "title" > conf_core.h File Reference< / div > < / div >
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< div class = "textblock" > < code > #include " clocks.h" < / code > < br / >
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< p > < a href = "conf__core_8h_source.html" > Go to the source code of this file.< / a > < / p >
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Macros< / h2 > < / td > < / tr >
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< tr class = "separator:a16a34b830edda5b571c41a0f865f7051" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a81edcdaa3908cc3d99a95047e4431405" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a81edcdaa3908cc3d99a95047e4431405" > CONF_CORE_CMCC_ENABLE< / a >       (0)< / td > < / tr >
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< tr class = "memitem:a4e846249cdbec567989afa93b6653671" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a4e846249cdbec567989afa93b6653671" > CONF_CORE_PORT_EVCTRL_0_ENABLE< / a >       (0)< / td > < / tr >
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< tr class = "memitem:ab1c71bf1f1249ce9046aca27329ae588" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#ab1c71bf1f1249ce9046aca27329ae588" > CONF_CORE_PORT_EVCTRL_1_ENABLE< / a >       (0)< / td > < / tr >
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< tr class = "memitem:a7971c1d952e35ecc50ae18de2b2c48ed" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a7971c1d952e35ecc50ae18de2b2c48ed" > CONF_CORE_PORT_EVCTRL_2_ENABLE< / a >       (0)< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_0_ENABLE< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_0_RUN_IN_STANDBY< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_0_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_0_DIV_VAL< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_0_DIVSEL< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_0_OUTPUT_ENABLE< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_0_IDC< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_1_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_1_RUN_IN_STANDBY< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_1_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_1_DIV_VAL< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_1_DIVSEL< / b >       0< / td > < / tr >
< tr class = "separator:ab2e12f8a900da42d0ca3185486aa3653" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_1_OUTPUT_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_1_IDC< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_2_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_2_RUN_IN_STANDBY< / b >       0< / td > < / tr >
< tr class = "separator:a6964718e73d3745689f7b534943215a3" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_2_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_2_DIV_VAL< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_2_DIVSEL< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_2_OUTPUT_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_2_IDC< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_3_ENABLE< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_3_RUN_IN_STANDBY< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_3_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC32K< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_3_DIV_VAL< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_3_DIVSEL< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_3_IDC< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_4_RUN_IN_STANDBY< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_4_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_4_DIV_VAL< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_4_DIVSEL< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_4_OUTPUT_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_5_RUN_IN_STANDBY< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_5_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_5_DIV_VAL< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_5_DIVSEL< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_5_OUTPUT_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_5_IDC< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_6_RUN_IN_STANDBY< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_6_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_6_DIV_VAL< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_6_DIVSEL< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_6_OUTPUT_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_6_IDC< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_7_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_7_RUN_IN_STANDBY< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_7_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_7_DIV_VAL< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_7_DIVSEL< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_7_IDC< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_8_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_8_RUN_IN_STANDBY< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_8_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_8_DIV_VAL< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_8_DIVSEL< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_8_OUTPUT_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_8_IDC< / b >       0< / td > < / tr >
< tr class = "separator:a745a2c905f215f02909859dfc840f7ae" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_9_ENABLE< / b >       0< / td > < / tr >
< tr class = "separator:aedaac2b9ad4241c252288a049f9d5e97" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_9_RUN_IN_STANDBY< / b >       0< / td > < / tr >
< tr class = "separator:a25477b98ee7a48725d2702f4925138b1" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_9_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
< tr class = "separator:a1c08dc8f723d13b8f8481525bf98316c" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_9_DIV_VAL< / b >       1< / td > < / tr >
< tr class = "separator:a9172510253cf26ab1df5f0bb29dff5a9" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_9_DIVSEL< / b >       0< / td > < / tr >
< tr class = "separator:ab611e17a201048a75894720fa71187f7" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_9_OUTPUT_ENABLE< / b >       0< / td > < / tr >
< tr class = "separator:a42b1a3b656ecc5d0353aafa430a7224f" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE< / b >       0< / td > < / tr >
< tr class = "separator:a24acebc85c7a0b46f0babaf7c7560cc6" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_9_IDC< / b >       0< / td > < / tr >
< tr class = "separator:ab7c3d2adb5d8a72db02a98d8f534d264" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_10_ENABLE< / b >       0< / td > < / tr >
< tr class = "separator:a8928d82489f83e35fc46c77937b54f42" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_10_RUN_IN_STANDBY< / b >       0< / td > < / tr >
< tr class = "separator:a823131b2633006cddc8dac02a96ed1ce" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_10_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
< tr class = "separator:a358ae9a13b446637caadbf7b4ed71098" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a34f97c15074016885aa8edb4485700d4" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a34f97c15074016885aa8edb4485700d4" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_10_DIV_VAL< / b >       1< / td > < / tr >
< tr class = "separator:a34f97c15074016885aa8edb4485700d4" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a1b92a8183fa929745c279451349bf48d" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a1b92a8183fa929745c279451349bf48d" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_10_DIVSEL< / b >       0< / td > < / tr >
< tr class = "separator:a1b92a8183fa929745c279451349bf48d" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_10_OUTPUT_ENABLE< / b >       0< / td > < / tr >
< tr class = "separator:af6137a0fb1608a3e5b5a531261d10856" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE< / b >       0< / td > < / tr >
< tr class = "separator:a487d54cb085adef1f57450b257a05a54" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_10_IDC< / b >       0< / td > < / tr >
< tr class = "separator:a1da181f6d0a2a15f56db087cf4917f68" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_11_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_11_RUN_IN_STANDBY< / b >       0< / td > < / tr >
< tr class = "separator:ab60170c3382e0f60c4ad559c1fd1e5f0" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_11_CLOCK_SOURCE< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_11_DIV_VAL< / b >       1< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_11_DIVSEL< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_11_OUTPUT_ENABLE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE< / b >       0< / td > < / tr >
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#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_GCLK_11_IDC< / b >       0< / td > < / tr >
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< tr > < td colspan = "2" > < div class = "groupHeader" > Core-Master-Clock-Configuration< / div > < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupText" > < p > Configuration options for the master clock. < / p >
< / div > < / td > < / tr >
< tr class = "memitem:ab46aa120e454ecf957efa4bd97be5bdf" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "ab46aa120e454ecf957efa4bd97be5bdf" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf" > CONF_CORE_MCLK_NVM_WAIT_STATE< / a >       0x5< / td > < / tr >
< tr class = "memdesc:ab46aa120e454ecf957efa4bd97be5bdf" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > Define the number of wait states for the master clock. < br / >
< a class = "el" href = "structCan.html" title = "CAN APB hardware registers." > Can< / a > be [0-15]. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=605" > Datasheet Reference< / a > < br / > < / td > < / tr >
< tr class = "separator:ab46aa120e454ecf957efa4bd97be5bdf" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:aa9643e96439d0d47e0684a4b11c1f529" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529" > CONF_CORE_MCLK_CPUDIV< / a >       0x1< / td > < / tr >
< tr class = "memdesc:aa9643e96439d0d47e0684a4b11c1f529" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > Define the master clock divisor. < a href = "conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:aa9643e96439d0d47e0684a4b11c1f529" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupHeader" > Core-XOSC0-Configuration< / div > < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupText" > < p > Configuration options for XOSC0. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=693" > Datasheet Reference< / a > < / p >
< / div > < / td > < / tr >
< tr class = "memitem:a61559adc856ce1dcfa046e749af63bc3" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a61559adc856ce1dcfa046e749af63bc3" > CONF_CORE_CLK_XOSC0_ENABLE< / a >       (1)< / td > < / tr >
< tr class = "memdesc:a61559adc856ce1dcfa046e749af63bc3" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > Enables or Disables the XOSC0 Clock. < a href = "conf__core_8h.html#a61559adc856ce1dcfa046e749af63bc3" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a61559adc856ce1dcfa046e749af63bc3" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:ac2ca0e9037347eb69d53a0011f989910" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#ac2ca0e9037347eb69d53a0011f989910" > CONF_CORE_CLK_XOSC0_XTALEN< / a >       (1)< / td > < / tr >
< tr class = "memdesc:ac2ca0e9037347eb69d53a0011f989910" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC0: < a href = "conf__core_8h.html#ac2ca0e9037347eb69d53a0011f989910" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:ac2ca0e9037347eb69d53a0011f989910" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:afac0686157854cc021424410ded071f1" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#afac0686157854cc021424410ded071f1" > CONF_CORE_CLK_XOSC0_RUNSTDBY< / a >       (0)< / td > < / tr >
< tr class = "memdesc:afac0686157854cc021424410ded071f1" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls how the XOSC0 behaves during standby sleep mode: < a href = "conf__core_8h.html#afac0686157854cc021424410ded071f1" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:afac0686157854cc021424410ded071f1" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a5ffaa1551b7ffb8a342b2cc5fbc5950c" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c" > CONF_CORE_CLK_XOSC0_ONDEMAND< / a >       (0)< / td > < / tr >
< tr class = "memdesc:a5ffaa1551b7ffb8a342b2cc5fbc5950c" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled, depending on peripheral clock requests. < a href = "conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a5ffaa1551b7ffb8a342b2cc5fbc5950c" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:aeea7b0d3663bb6d5ccc3218017f9a05b" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#aeea7b0d3663bb6d5ccc3218017f9a05b" > CONF_CORE_CLK_XOSC0_LOWBUFGAIN< / a >       (0)< / td > < / tr >
< tr class = "memdesc:aeea7b0d3663bb6d5ccc3218017f9a05b" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. < a href = "conf__core_8h.html#aeea7b0d3663bb6d5ccc3218017f9a05b" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:aeea7b0d3663bb6d5ccc3218017f9a05b" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a2683d3721ab44a85e60cfff0d0cbf96e" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e" > CONF_CORE_CLK_XOSC0_ENALC< / a >       (1)< / td > < / tr >
< tr class = "memdesc:a2683d3721ab44a85e60cfff0d0cbf96e" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls the XOSC0 automatic loop control: < a href = "conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a2683d3721ab44a85e60cfff0d0cbf96e" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a17cd20bb954bc137251cf7fb63889151" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a17cd20bb954bc137251cf7fb63889151" > CONF_CORE_CLK_XOSC0_CFDEN< / a >       (1)< / td > < / tr >
< tr class = "memdesc:a17cd20bb954bc137251cf7fb63889151" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls the XOSC0 clock failure detector: < a href = "conf__core_8h.html#a17cd20bb954bc137251cf7fb63889151" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a17cd20bb954bc137251cf7fb63889151" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:abe235b3b13f253acb855d15c8f33c95a" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#abe235b3b13f253acb855d15c8f33c95a" > CONF_CORE_CLK_XOSC0_SWBEN< / a >       (0)< / td > < / tr >
< tr class = "memdesc:abe235b3b13f253acb855d15c8f33c95a" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in case of clock recovery: < a href = "conf__core_8h.html#abe235b3b13f253acb855d15c8f33c95a" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:abe235b3b13f253acb855d15c8f33c95a" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:affc8201cf2340d2236ba9ca44a1e657c" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#affc8201cf2340d2236ba9ca44a1e657c" > CONF_CORE_CLK_XOSC0_STARTUP_TIME< / a >       (0x00)< / td > < / tr >
< tr class = "memdesc:affc8201cf2340d2236ba9ca44a1e657c" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > These bits select start-up time for XOSC0 according to the table below: < a href = "conf__core_8h.html#affc8201cf2340d2236ba9ca44a1e657c" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:affc8201cf2340d2236ba9ca44a1e657c" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:af6ec0afa1da472db5f1def1d1923faad" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#af6ec0afa1da472db5f1def1d1923faad" > CONF_CORE_CLK_XOSC0_FREQUENCY< / a >       12000000< / td > < / tr >
< tr class = "memdesc:af6ec0afa1da472db5f1def1d1923faad" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This is the frequency of the external clock you're using for XOSC0. This can be anything from 8MHz to 48MHz. < a href = "conf__core_8h.html#af6ec0afa1da472db5f1def1d1923faad" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:af6ec0afa1da472db5f1def1d1923faad" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupHeader" > Core-XOSC1-Configuration< / div > < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupText" > < p > Configuration options for XOSC1. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=693" > Datasheet Reference< / a > < / p >
< / div > < / td > < / tr >
< tr class = "memitem:aa54465cc56631333a22ae84ab66d5f3a" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#aa54465cc56631333a22ae84ab66d5f3a" > CONF_CORE_CLK_XOSC1_ENABLE< / a >       (0)< / td > < / tr >
< tr class = "memdesc:aa54465cc56631333a22ae84ab66d5f3a" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > Enables or Disables the XOSC1 Clock. < a href = "conf__core_8h.html#aa54465cc56631333a22ae84ab66d5f3a" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:aa54465cc56631333a22ae84ab66d5f3a" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:ae3f8741e2be4b37a46dfb49af2c2a09d" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#ae3f8741e2be4b37a46dfb49af2c2a09d" > CONF_CORE_CLK_XOSC1_XTALEN< / a >       (0)< / td > < / tr >
< tr class = "memdesc:ae3f8741e2be4b37a46dfb49af2c2a09d" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC1: < a href = "conf__core_8h.html#ae3f8741e2be4b37a46dfb49af2c2a09d" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:ae3f8741e2be4b37a46dfb49af2c2a09d" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a8bec34fdc01ac38ec0c2d13112f28aa0" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a8bec34fdc01ac38ec0c2d13112f28aa0" > CONF_CORE_CLK_XOSC1_RUNSTDBY< / a >       (0)< / td > < / tr >
< tr class = "memdesc:a8bec34fdc01ac38ec0c2d13112f28aa0" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls how the XOSC1 behaves during standby sleep mode: < a href = "conf__core_8h.html#a8bec34fdc01ac38ec0c2d13112f28aa0" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a8bec34fdc01ac38ec0c2d13112f28aa0" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:aaf561ace0fee1e373536a251ce8a9726" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#aaf561ace0fee1e373536a251ce8a9726" > CONF_CORE_CLK_XOSC1_ONDEMAND< / a >       (0)< / td > < / tr >
< tr class = "memdesc:aaf561ace0fee1e373536a251ce8a9726" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled, depending on peripheral clock requests. < a href = "conf__core_8h.html#aaf561ace0fee1e373536a251ce8a9726" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:aaf561ace0fee1e373536a251ce8a9726" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a985ebd23986d9411d3602040e33bb405" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a985ebd23986d9411d3602040e33bb405" > CONF_CORE_CLK_XOSC1_LOWBUFGAIN< / a >       (0)< / td > < / tr >
< tr class = "memdesc:a985ebd23986d9411d3602040e33bb405" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. < a href = "conf__core_8h.html#a985ebd23986d9411d3602040e33bb405" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a985ebd23986d9411d3602040e33bb405" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a3a42de5c6251540e7b8c000974acfc62" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a3a42de5c6251540e7b8c000974acfc62" > CONF_CORE_CLK_XOSC1_ENALC< / a >       (0)< / td > < / tr >
< tr class = "memdesc:a3a42de5c6251540e7b8c000974acfc62" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls the XOSC1 automatic loop control: < a href = "conf__core_8h.html#a3a42de5c6251540e7b8c000974acfc62" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a3a42de5c6251540e7b8c000974acfc62" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a924214b0f469bde71ff28fe5544466db" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a924214b0f469bde71ff28fe5544466db" > CONF_CORE_CLK_XOSC1_CFDEN< / a >       (0)< / td > < / tr >
< tr class = "memdesc:a924214b0f469bde71ff28fe5544466db" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls the XOSC1 clock failure detector: < a href = "conf__core_8h.html#a924214b0f469bde71ff28fe5544466db" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a924214b0f469bde71ff28fe5544466db" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a590b1e68a3f666bdea576a32f4e74ba0" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a590b1e68a3f666bdea576a32f4e74ba0" > CONF_CORE_CLK_XOSC1_SWBEN< / a >       (0)< / td > < / tr >
< tr class = "memdesc:a590b1e68a3f666bdea576a32f4e74ba0" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in case of clock recovery: < a href = "conf__core_8h.html#a590b1e68a3f666bdea576a32f4e74ba0" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a590b1e68a3f666bdea576a32f4e74ba0" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:ae8d2fdac3b52964174863149986db625" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#ae8d2fdac3b52964174863149986db625" > CONF_CORE_CLK_XOSC1_STARTUP_TIME< / a >       (0x00)< / td > < / tr >
< tr class = "memdesc:ae8d2fdac3b52964174863149986db625" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > These bits select start-up time for XOSC1 according to the table below: < a href = "conf__core_8h.html#ae8d2fdac3b52964174863149986db625" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:ae8d2fdac3b52964174863149986db625" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a3fc3ea49b9d78438e5a8c19a22849469" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a3fc3ea49b9d78438e5a8c19a22849469" > CONF_CORE_CLK_XOSC1_FREQUENCY< / a >       12000000< / td > < / tr >
< tr class = "memdesc:a3fc3ea49b9d78438e5a8c19a22849469" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This is the frequency of the external clock you're using for XOSC1. This can be anything from 8MHz to 48MHz. < a href = "conf__core_8h.html#a3fc3ea49b9d78438e5a8c19a22849469" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a3fc3ea49b9d78438e5a8c19a22849469" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupHeader" > Core-XOSC32K-Configuration< / div > < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupText" > < p > Configuration options for the external 32khz oscillator. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=735" > Datasheet Reference< / a > < / p >
< / div > < / td > < / tr >
< tr class = "memitem:accf341cf268c0883a3d862b98667bc9c" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#accf341cf268c0883a3d862b98667bc9c" > CONF_CORE_CLK_XOSC32K_ENABLE< / a >       (1)< / td > < / tr >
< tr class = "memdesc:accf341cf268c0883a3d862b98667bc9c" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > Enables or Disables XOSC32K. < a href = "conf__core_8h.html#accf341cf268c0883a3d862b98667bc9c" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:accf341cf268c0883a3d862b98667bc9c" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a031a77340c697036538d218724837de1" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a031a77340c697036538d218724837de1" > CONF_CORE_CLK_XOSC32K_CGM< / a >       (0x01)< / td > < / tr >
< tr class = "memdesc:a031a77340c697036538d218724837de1" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > These bits control the gain of the external crstal oscillator. < a href = "conf__core_8h.html#a031a77340c697036538d218724837de1" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a031a77340c697036538d218724837de1" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a314b78ee48f1ecf6c40f4bad7ef63d9d" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a314b78ee48f1ecf6c40f4bad7ef63d9d" > CONF_CORE_CLK_XOSC32K_STARTUP_TIME< / a >       CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us< / td > < / tr >
< tr class = "memdesc:a314b78ee48f1ecf6c40f4bad7ef63d9d" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > These bits select the startup time for the oscillator. < a href = "conf__core_8h.html#a314b78ee48f1ecf6c40f4bad7ef63d9d" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a314b78ee48f1ecf6c40f4bad7ef63d9d" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a8d70a30b50febec035af6b982daac395" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a8d70a30b50febec035af6b982daac395" > CONF_CORE_CLK_XOSC32K_ONDEMAND< / a >       (1)< / td > < / tr >
< tr class = "memdesc:a8d70a30b50febec035af6b982daac395" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls how XOSC32K behaves when a peripheral clock request is detected. < a href = "conf__core_8h.html#a8d70a30b50febec035af6b982daac395" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a8d70a30b50febec035af6b982daac395" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:adc7a2f161e9e8e54388b1f290066247e" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#adc7a2f161e9e8e54388b1f290066247e" > CONF_CORE_CLK_XOSC32K_RUNSTDBY< / a >       (0)< / td > < / tr >
< tr class = "memdesc:adc7a2f161e9e8e54388b1f290066247e" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls how XOSC32K behaves during standby sleep mode. < a href = "conf__core_8h.html#adc7a2f161e9e8e54388b1f290066247e" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:adc7a2f161e9e8e54388b1f290066247e" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a033f3571fb50a6ed02278d65ea84b45e" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a033f3571fb50a6ed02278d65ea84b45e" > CONF_CORE_CLK_XOSC32K_EN1K< / a >       (0)< / td > < / tr >
< tr class = "separator:a033f3571fb50a6ed02278d65ea84b45e" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:ae9fbb8d05dc5808f510eae4e8a629826" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#ae9fbb8d05dc5808f510eae4e8a629826" > CONF_CORE_CLK_XOSC32K_EN32K< / a >       (1)< / td > < / tr >
< tr class = "separator:ae9fbb8d05dc5808f510eae4e8a629826" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a6a65a6f4bf7e21dc2003b61a7045e24a" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a6a65a6f4bf7e21dc2003b61a7045e24a" > CONF_CORE_CLK_XOSC32K_XTALEN< / a >       (1)< / td > < / tr >
< tr class = "memdesc:a6a65a6f4bf7e21dc2003b61a7045e24a" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls the connections between the I/O pads and the external clock or crystal oscillator. < a href = "conf__core_8h.html#a6a65a6f4bf7e21dc2003b61a7045e24a" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a6a65a6f4bf7e21dc2003b61a7045e24a" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a79567f94a0f3ad2d628bcf5e1cff62d1" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a79567f94a0f3ad2d628bcf5e1cff62d1" > CONF_CORE_CLK_XOSC32K_CFDPRESC< / a >       (0)< / td > < / tr >
< tr class = "memdesc:a79567f94a0f3ad2d628bcf5e1cff62d1" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit selects the prescaler for the CLock Failure Detector: < a href = "conf__core_8h.html#a79567f94a0f3ad2d628bcf5e1cff62d1" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a79567f94a0f3ad2d628bcf5e1cff62d1" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a668d68edf9a7ac05be5b9cda247225ad" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a668d68edf9a7ac05be5b9cda247225ad" > CONF_CORE_CLK_XOSC32K_CFDEN< / a >       (0)< / td > < / tr >
< tr class = "memdesc:a668d68edf9a7ac05be5b9cda247225ad" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit selects the Clock Failulre Detector state. < a href = "conf__core_8h.html#a668d68edf9a7ac05be5b9cda247225ad" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a668d68edf9a7ac05be5b9cda247225ad" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:ac6e671eee4ca4aeb9fcbb87d52b457b5" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#ac6e671eee4ca4aeb9fcbb87d52b457b5" > CONF_CORE_CLK_XOSC32K_SWBACK< / a >       (0)< / td > < / tr >
< tr class = "memdesc:ac6e671eee4ca4aeb9fcbb87d52b457b5" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery. < a href = "conf__core_8h.html#ac6e671eee4ca4aeb9fcbb87d52b457b5" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:ac6e671eee4ca4aeb9fcbb87d52b457b5" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a42b0270d2f3c0f51c4b3d2b8ac397fda" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a42b0270d2f3c0f51c4b3d2b8ac397fda" > CONF_CORE_CLK_XOSC32K_WRTLOCK< / a >       (0)< / td > < / tr >
< tr class = "memdesc:a42b0270d2f3c0f51c4b3d2b8ac397fda" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration. < a href = "conf__core_8h.html#a42b0270d2f3c0f51c4b3d2b8ac397fda" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a42b0270d2f3c0f51c4b3d2b8ac397fda" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupHeader" > Core-DFLL48M-Configuration< / div > < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupText" > < p > Configuration options for DFLL48M < / p >
< / div > < / td > < / tr >
< tr class = "memitem:a03160c4c7871685bbde0e96f02825842" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a03160c4c7871685bbde0e96f02825842" > CONF_CORE_CLK_DFLL_ENABLE< / a >       (1)< / td > < / tr >
< tr class = "memdesc:a03160c4c7871685bbde0e96f02825842" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > Enables or Disables the DFLL48M Clock. < a href = "conf__core_8h.html#a03160c4c7871685bbde0e96f02825842" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a03160c4c7871685bbde0e96f02825842" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a55515b150245a993779a0d5f417cc828" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a55515b150245a993779a0d5f417cc828" > CONF_CORE_CLK_DFLL_ONDEMAND< / a >       (0)< / td > < / tr >
< tr class = "memdesc:a55515b150245a993779a0d5f417cc828" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > Enables or Disables on-demand operation. < a href = "conf__core_8h.html#a55515b150245a993779a0d5f417cc828" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a55515b150245a993779a0d5f417cc828" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:ab6b320dcf67ec88f534adcbf77e2ce7b" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b" > CONF_CORE_CLK_DFLL_RUNSTDBY< / a >       (0)< / td > < / tr >
< tr class = "memdesc:ab6b320dcf67ec88f534adcbf77e2ce7b" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > Enables or Disables run-in-standby operation. < a href = "conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:ab6b320dcf67ec88f534adcbf77e2ce7b" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a1f088d6654bb907ff388ced455b2dbb2" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2" > CONF_CORE_CLK_DFLL_WAITLOCK< / a >       (0)< / td > < / tr >
< tr class = "memdesc:a1f088d6654bb907ff388ced455b2dbb2" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > This bit controls the DFLL output clock, depending on the lock status: < a href = "conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a1f088d6654bb907ff388ced455b2dbb2" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a5c4e5f19e855fba0042ae119ce1be273" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a5c4e5f19e855fba0042ae119ce1be273" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_BPLKC< / b >       (0)< / td > < / tr >
< tr class = "separator:a5c4e5f19e855fba0042ae119ce1be273" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a09e3dee90c8d6a09b50e78a21d5ad7a5" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a09e3dee90c8d6a09b50e78a21d5ad7a5" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_QLDIS< / b >       (0)< / td > < / tr >
< tr class = "separator:a09e3dee90c8d6a09b50e78a21d5ad7a5" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:ae74d5c634b10eef6a79e7e55fbb2cf07" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "ae74d5c634b10eef6a79e7e55fbb2cf07" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_CCDIS< / b >       (1)< / td > < / tr >
< tr class = "separator:ae74d5c634b10eef6a79e7e55fbb2cf07" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a74344d95253ee83ec8feed88bf1ffdd5" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a74344d95253ee83ec8feed88bf1ffdd5" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_USBCRM< / b >       (1)< / td > < / tr >
< tr class = "separator:a74344d95253ee83ec8feed88bf1ffdd5" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a75b8def1d65eb508ff5c961e022e418e" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a75b8def1d65eb508ff5c961e022e418e" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_LLAW< / b >       (0)< / td > < / tr >
< tr class = "separator:a75b8def1d65eb508ff5c961e022e418e" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a6dde0ce4cb4a661b734fb1aa1f3fbf8b" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a6dde0ce4cb4a661b734fb1aa1f3fbf8b" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_STABLE_FCALIB< / b >       CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED< / td > < / tr >
< tr class = "separator:a6dde0ce4cb4a661b734fb1aa1f3fbf8b" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a4ada5f18d9f29877453b03af4711acfc" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a4ada5f18d9f29877453b03af4711acfc" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_MODE< / b >       0x01< / td > < / tr >
< tr class = "separator:a4ada5f18d9f29877453b03af4711acfc" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a89107ba362a177f2dc6929fbc4030d0f" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a89107ba362a177f2dc6929fbc4030d0f" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_DIFF_VAL< / b >       0< / td > < / tr >
< tr class = "separator:a89107ba362a177f2dc6929fbc4030d0f" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a8fb1e5e5773d953d64724376bc018327" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a8fb1e5e5773d953d64724376bc018327" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_COARSE_VAL< / b >       (0x1f / 4)< / td > < / tr >
< tr class = "separator:a8fb1e5e5773d953d64724376bc018327" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a9b135c600eaa339b864a4050888e5e15" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a9b135c600eaa339b864a4050888e5e15" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_FINE_VAL< / b >       128< / td > < / tr >
< tr class = "separator:a9b135c600eaa339b864a4050888e5e15" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a87369bb1b036d78a49c44658f1e4e157" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a87369bb1b036d78a49c44658f1e4e157" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_CSTEP_VAL< / b >       1< / td > < / tr >
< tr class = "separator:a87369bb1b036d78a49c44658f1e4e157" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a906b08d6e610a6d61aec7d373c60101d" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a906b08d6e610a6d61aec7d373c60101d" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_FSTEP_VAL< / b >       1< / td > < / tr >
< tr class = "separator:a906b08d6e610a6d61aec7d373c60101d" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a39fcdbd76df383f369f23f24c253bf67" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a39fcdbd76df383f369f23f24c253bf67" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_MUL_VAL< / b >       (48000000)< / td > < / tr >
< tr class = "separator:a39fcdbd76df383f369f23f24c253bf67" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a0d8e56832f3d1f24b98173e3a3aa0046" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046" > CONF_CORE_CLK_DFLL_GCLK_SRC< / a >       3< / td > < / tr >
< tr class = "memdesc:a0d8e56832f3d1f24b98173e3a3aa0046" > < td class = "mdescLeft" >   < / td > < td class = "mdescRight" > GCLK Source used to generate DFLL48M. < a href = "conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046" > More...< / a > < br / > < / td > < / tr >
< tr class = "separator:a0d8e56832f3d1f24b98173e3a3aa0046" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:abfec7438288095803eebaefe1338e54c" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "abfec7438288095803eebaefe1338e54c" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DFLL_OVERWRITE_CAL< / b >       0< / td > < / tr >
< tr class = "separator:abfec7438288095803eebaefe1338e54c" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupHeader" > Core-DPLL0-Configuration< / div > < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupText" > < p > Configuration Options for DPLL0. < / p >
< / div > < / td > < / tr >
< tr class = "memitem:a32837c3455721c1e932c7adcccfdf0cd" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a32837c3455721c1e932c7adcccfdf0cd" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_ENABLE< / b >       (1)< / td > < / tr >
< tr class = "separator:a32837c3455721c1e932c7adcccfdf0cd" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a2b830cd50489a764556e8b1f8e541202" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a2b830cd50489a764556e8b1f8e541202" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_ONDEMAND< / b >       (0)< / td > < / tr >
< tr class = "separator:a2b830cd50489a764556e8b1f8e541202" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a232a0f414a1c0a62a825ca70d160651a" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a232a0f414a1c0a62a825ca70d160651a" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_RUNSTDBY< / b >       (0)< / td > < / tr >
< tr class = "separator:a232a0f414a1c0a62a825ca70d160651a" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:af8301c10a83c8d93ce10a737b1c28d96" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "af8301c10a83c8d93ce10a737b1c28d96" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_LDRFRAC_VAL< / b >       0< / td > < / tr >
< tr class = "separator:af8301c10a83c8d93ce10a737b1c28d96" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a4dc011b4bae77aea3e2e78b4e58bda9f" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a4dc011b4bae77aea3e2e78b4e58bda9f" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_LDR_VAL< / b >       (119)< / td > < / tr >
< tr class = "separator:a4dc011b4bae77aea3e2e78b4e58bda9f" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a8fc4add22bc160d41a48900de8d37b9d" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a8fc4add22bc160d41a48900de8d37b9d" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_DIV_VAL< / b >       (5)< / td > < / tr >
< tr class = "separator:a8fc4add22bc160d41a48900de8d37b9d" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:adfd061b8e76628b32a3e75f8eaaa2121" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "adfd061b8e76628b32a3e75f8eaaa2121" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_DCOEN< / b >       0< / td > < / tr >
< tr class = "separator:adfd061b8e76628b32a3e75f8eaaa2121" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:ac3f9bf6a11f84f688e26c37033f442f6" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "ac3f9bf6a11f84f688e26c37033f442f6" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_DCOFILTER< / b >       CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ< / td > < / tr >
< tr class = "separator:ac3f9bf6a11f84f688e26c37033f442f6" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a36fb00b9e83f81a6ad52a639c65b14dd" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a36fb00b9e83f81a6ad52a639c65b14dd" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_LBYPASS< / b >       1< / td > < / tr >
< tr class = "separator:a36fb00b9e83f81a6ad52a639c65b14dd" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:aec55e35583b422f3fba9ddd0fe315e32" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "aec55e35583b422f3fba9ddd0fe315e32" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_LTIME< / b >       0< / td > < / tr >
< tr class = "separator:aec55e35583b422f3fba9ddd0fe315e32" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a14f2ac6af56046cd27cd670c356c2d52" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a14f2ac6af56046cd27cd670c356c2d52" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_WUF< / b >       0< / td > < / tr >
< tr class = "separator:a14f2ac6af56046cd27cd670c356c2d52" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:adcfac6cd48f945b481bd9b9c2fc14aab" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "adcfac6cd48f945b481bd9b9c2fc14aab" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_GCLK_SRC< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
< tr class = "separator:adcfac6cd48f945b481bd9b9c2fc14aab" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a8eab8998f300dc63cf9cf750a51cafa9" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a8eab8998f300dc63cf9cf750a51cafa9" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL0_REFCLK< / b >       CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0< / td > < / tr >
< tr class = "separator:a8eab8998f300dc63cf9cf750a51cafa9" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a5cd9abca6f486eaebb6ddd236960b01a" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a" > CONF_CORE_CLK_DPLL0_FILTER< / a >       0x0< / td > < / tr >
< tr class = "separator:a5cd9abca6f486eaebb6ddd236960b01a" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupHeader" > Core-DPLL1-Configuration< / div > < / td > < / tr >
< tr > < td colspan = "2" > < div class = "groupText" > < p > Configuration Options for DPLL1. < / p >
< / div > < / td > < / tr >
< tr class = "memitem:a98d3a5ebaa868e372e467d61e8f0915e" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a98d3a5ebaa868e372e467d61e8f0915e" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_ENABLE< / b >       (0)< / td > < / tr >
< tr class = "separator:a98d3a5ebaa868e372e467d61e8f0915e" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a9e78bd13faa639f138ab9ea20bd1b1dd" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a9e78bd13faa639f138ab9ea20bd1b1dd" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_ONDEMAND< / b >       (0)< / td > < / tr >
< tr class = "separator:a9e78bd13faa639f138ab9ea20bd1b1dd" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:ac2a6f39d072c0aa33b8c9c90c626f742" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "ac2a6f39d072c0aa33b8c9c90c626f742" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_RUNSTDBY< / b >       (0)< / td > < / tr >
< tr class = "separator:ac2a6f39d072c0aa33b8c9c90c626f742" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:aad9c291ed981573062103b6930f56434" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "aad9c291ed981573062103b6930f56434" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_LDRFRAC_VAL< / b >       0< / td > < / tr >
< tr class = "separator:aad9c291ed981573062103b6930f56434" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a8fb5c78ecfdc3179bc1cf0fd09b93b43" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a8fb5c78ecfdc3179bc1cf0fd09b93b43" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_LDR_VAL< / b >       (0)< / td > < / tr >
< tr class = "separator:a8fb5c78ecfdc3179bc1cf0fd09b93b43" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a420a27c14d9796b27cb4467dd9be4b25" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a420a27c14d9796b27cb4467dd9be4b25" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_DIV_VAL< / b >       (0)< / td > < / tr >
< tr class = "separator:a420a27c14d9796b27cb4467dd9be4b25" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a928c76f06226be2ce5121b60d04d7d0f" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a928c76f06226be2ce5121b60d04d7d0f" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_DCOEN< / b >       0< / td > < / tr >
< tr class = "separator:a928c76f06226be2ce5121b60d04d7d0f" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a1860168cd66107207d6bcd2a6104a953" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a1860168cd66107207d6bcd2a6104a953" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_DCOFILTER< / b >       CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ< / td > < / tr >
< tr class = "separator:a1860168cd66107207d6bcd2a6104a953" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:aa82d590e2d2bfbfff5f921600657332f" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "aa82d590e2d2bfbfff5f921600657332f" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_LBYPASS< / b >       0< / td > < / tr >
< tr class = "separator:aa82d590e2d2bfbfff5f921600657332f" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a51e32a541cfcdef0a10077488b1bda87" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a51e32a541cfcdef0a10077488b1bda87" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_LTIME< / b >       0< / td > < / tr >
< tr class = "separator:a51e32a541cfcdef0a10077488b1bda87" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a537f2fb05f6ee6cca0692bd32f2e23bb" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a537f2fb05f6ee6cca0692bd32f2e23bb" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_WUF< / b >       0< / td > < / tr >
< tr class = "separator:a537f2fb05f6ee6cca0692bd32f2e23bb" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a0780d9ac15356ac35efcc516ef288017" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a0780d9ac15356ac35efcc516ef288017" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_GCLK_SRC< / b >       GCLK_GENCTRL_SRC_XOSC0< / td > < / tr >
< tr class = "separator:a0780d9ac15356ac35efcc516ef288017" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a4ee0e9569732ce043f243a86c068b51a" > < td class = "memItemLeft" align = "right" valign = "top" > < a id = "a4ee0e9569732ce043f243a86c068b51a" > < / a >
#define  < / td > < td class = "memItemRight" valign = "bottom" > < b > CONF_CORE_CLK_DPLL1_REFCLK< / b >       CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0< / td > < / tr >
< tr class = "separator:a4ee0e9569732ce043f243a86c068b51a" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< tr class = "memitem:a9de3ab7eb7e3c001d6aa7040f6311f10" > < td class = "memItemLeft" align = "right" valign = "top" > #define  < / td > < td class = "memItemRight" valign = "bottom" > < a class = "el" href = "conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10" > CONF_CORE_CLK_DPLL1_FILTER< / a >       0x0< / td > < / tr >
< tr class = "separator:a9de3ab7eb7e3c001d6aa7040f6311f10" > < td class = "memSeparator" colspan = "2" >   < / td > < / tr >
< / table >
< a name = "details" id = "details" > < / a > < h2 class = "groupheader" > Detailed Description< / h2 >
< div class = "textblock" > < dl class = "section author" > < dt > Author< / dt > < dd > Penguin< / dd > < / dl >
< h1 > < a class = "anchor" id = "Description" > < / a >
Description< / h1 >
< p > This is the master config for the core module for this mcu. This file is < em > required< / em > for the core module to function. < / p >
< p class = "definition" > Definition in file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
< / div > < h2 class = "groupheader" > Macro Definition Documentation< / h2 >
< a id = "a03160c4c7871685bbde0e96f02825842" > < / a >
< h2 class = "memtitle" > < span class = "permalink" > < a href = "#a03160c4c7871685bbde0e96f02825842" > ◆ < / a > < / span > CONF_CORE_CLK_DFLL_ENABLE< / h2 >
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< div class = "memproto" >
< table class = "memname" >
< tr >
< td class = "memname" > #define CONF_CORE_CLK_DFLL_ENABLE      (1)< / td >
< / tr >
< / table >
< / div > < div class = "memdoc" >
< p > Enables or Disables the DFLL48M Clock. < / p >
< p > DFLL48M Enable< / p > < ul >
< li > 0 => Disables DFLL48M< / li >
< li > 1 => Enables DFLL48M < br / >
pg. 724 of datasheet < / li >
< / ul >
< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00390" > 390< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
< / div >
< / div >
< a id = "a0d8e56832f3d1f24b98173e3a3aa0046" > < / a >
< h2 class = "memtitle" > < span class = "permalink" > < a href = "#a0d8e56832f3d1f24b98173e3a3aa0046" > ◆ < / a > < / span > CONF_CORE_CLK_DFLL_GCLK_SRC< / h2 >
< div class = "memitem" >
< div class = "memproto" >
< table class = "memname" >
< tr >
< td class = "memname" > #define CONF_CORE_CLK_DFLL_GCLK_SRC      3< / td >
< / tr >
< / table >
< / div > < div class = "memdoc" >
< p > GCLK Source used to generate DFLL48M. < / p >
< p > DFLL48M GCLK Source< / p > < ul >
< li > 0 => Generic clock generator 0< / li >
< li > 1 => Generic clock generator 1< / li >
< li > 2 => Generic clock generator 2< / li >
< li > 3 => Generic clock generator 3< / li >
< li > 4 => Generic clock generator 4< / li >
< li > 5 => Generic clock generator 5< / li >
< li > 6 => Generic clock generator 6< / li >
< li > 7 => Generic clock generator 7< / li >
< li > 8 => Generic clock generator 8< / li >
< li > 9 => Generic clock generator 9< / li >
< li > 10 => Generic clock generator 10< / li >
< li > 11 => Generic clock generator 11 < / li >
< / ul >
< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00444" > 444< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
< / div >
< / div >
< a id = "a55515b150245a993779a0d5f417cc828" > < / a >
< h2 class = "memtitle" > < span class = "permalink" > < a href = "#a55515b150245a993779a0d5f417cc828" > ◆ < / a > < / span > CONF_CORE_CLK_DFLL_ONDEMAND< / h2 >
< div class = "memitem" >
< div class = "memproto" >
< table class = "memname" >
< tr >
< td class = "memname" > #define CONF_CORE_CLK_DFLL_ONDEMAND      (0)< / td >
< / tr >
< / table >
< / div > < div class = "memdoc" >
< p > Enables or Disables on-demand operation. < / p >
< p > DFLL48M On Demand Control< / p > < ul >
< li > 0 => Disables On Demand Operation< / li >
< li > 1 => Enables On Demand Operation < br / >
pg. 724 of datasheet < / li >
< / ul >
< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00398" > 398< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
< / div >
< / div >
< a id = "ab6b320dcf67ec88f534adcbf77e2ce7b" > < / a >
< h2 class = "memtitle" > < span class = "permalink" > < a href = "#ab6b320dcf67ec88f534adcbf77e2ce7b" > ◆ < / a > < / span > CONF_CORE_CLK_DFLL_RUNSTDBY< / h2 >
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< div class = "memproto" >
< table class = "memname" >
< tr >
< td class = "memname" > #define CONF_CORE_CLK_DFLL_RUNSTDBY      (0)< / td >
< / tr >
< / table >
< / div > < div class = "memdoc" >
< p > Enables or Disables run-in-standby operation. < / p >
< p > DFLL48M Run in Standby Control< / p > < ul >
< li > 0 => Disables run-in-standby operation< / li >
< li > 1 => Enables run-in-standby operation < br / >
pg. 724 of datasheet < / li >
< / ul >
< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00406" > 406< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
< / div >
< / div >
< a id = "a1f088d6654bb907ff388ced455b2dbb2" > < / a >
< h2 class = "memtitle" > < span class = "permalink" > < a href = "#a1f088d6654bb907ff388ced455b2dbb2" > ◆ < / a > < / span > CONF_CORE_CLK_DFLL_WAITLOCK< / h2 >
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< div class = "memproto" >
< table class = "memname" >
< tr >
< td class = "memname" > #define CONF_CORE_CLK_DFLL_WAITLOCK      (0)< / td >
< / tr >
< / table >
< / div > < div class = "memdoc" >
< p > This bit controls the DFLL output clock, depending on the lock status: < / p >
< p > DFLL48M Wait Lock Control< / p > < ul >
< li > 0 => Output clock before the DFLL is locked.< / li >
< li > 1 => Output clock when DFLL is locked (Fine lock). < br / >
pg. 725 of datasheet < / li >
< / ul >
< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00414" > 414< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
< / div >
< / div >
< a id = "a5cd9abca6f486eaebb6ddd236960b01a" > < / a >
< h2 class = "memtitle" > < span class = "permalink" > < a href = "#a5cd9abca6f486eaebb6ddd236960b01a" > ◆ < / a > < / span > CONF_CORE_CLK_DPLL0_FILTER< / h2 >
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< div class = "memproto" >
< table class = "memname" >
< tr >
< td class = "memname" > #define CONF_CORE_CLK_DPLL0_FILTER      0x0< / td >
< / tr >
< / table >
< / div > < div class = "memdoc" >
< p > pg. 732 of the datasheet < / p > < div class = "fragment" > < div class = "line" > FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor< / div >
< div class = "line" > 0x0 | 92.7 kHz | 0.76< / div >
< div class = "line" > 0x1 | 131 kHz | 1.08< / div >
< div class = "line" > 0x2 | 46.4 kHz | 0.38< / div >
< div class = "line" > 0x3 | 65.6 kHz | 0.54< / div >
< div class = "line" > 0x4 | 131 kHz | 0.56< / div >
< div class = "line" > 0x5 | 185 kHz | 0.79< / div >
< div class = "line" > 0x6 | 65.6 kHz | 0.28< / div >
< div class = "line" > 0x7 | 92.7 kHz | 0.39< / div >
< div class = "line" > 0x8 | 46.4 kHz | 1.49< / div >
< div class = "line" > 0x9 | 65.6 kHz | 2.11< / div >
< div class = "line" > 0xA | 23.2 kHz | 0.75< / div >
< div class = "line" > 0xB | 32.8 kHz | 1.06< / div >
< div class = "line" > 0xC | 65.6 kHz | 1.07< / div >
< div class = "line" > 0xD | 92.7 kHz | 1.51< / div >
< div class = "line" > 0xE | 32.8 kHz | 0.53< / div >
< div class = "line" > 0xF | 46.4 kHz | 0.75< / div >
< / div > <!-- fragment --> < p > When in doubt, leave this at its default. < / p >
< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00490" > 490< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
< / div >
< / div >
< a id = "a9de3ab7eb7e3c001d6aa7040f6311f10" > < / a >
< h2 class = "memtitle" > < span class = "permalink" > < a href = "#a9de3ab7eb7e3c001d6aa7040f6311f10" > ◆ < / a > < / span > CONF_CORE_CLK_DPLL1_FILTER< / h2 >
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< div class = "memproto" >
< table class = "memname" >
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< td class = "memname" > #define CONF_CORE_CLK_DPLL1_FILTER      0x0< / td >
< / tr >
< / table >
< / div > < div class = "memdoc" >
< p > pg. 732 of the datasheet < / p > < div class = "fragment" > < div class = "line" > FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor< / div >
< div class = "line" > 0x0 | 92.7 kHz | 0.76< / div >
< div class = "line" > 0x1 | 131 kHz | 1.08< / div >
< div class = "line" > 0x2 | 46.4 kHz | 0.38< / div >
< div class = "line" > 0x3 | 65.6 kHz | 0.54< / div >
< div class = "line" > 0x4 | 131 kHz | 0.56< / div >
< div class = "line" > 0x5 | 185 kHz | 0.79< / div >
< div class = "line" > 0x6 | 65.6 kHz | 0.28< / div >
< div class = "line" > 0x7 | 92.7 kHz | 0.39< / div >
< div class = "line" > 0x8 | 46.4 kHz | 1.49< / div >
< div class = "line" > 0x9 | 65.6 kHz | 2.11< / div >
< div class = "line" > 0xA | 23.2 kHz | 0.75< / div >
< div class = "line" > 0xB | 32.8 kHz | 1.06< / div >
< div class = "line" > 0xC | 65.6 kHz | 1.07< / div >
< div class = "line" > 0xD | 92.7 kHz | 1.51< / div >
< div class = "line" > 0xE | 32.8 kHz | 0.53< / div >
< div class = "line" > 0xF | 46.4 kHz | 0.75< / div >
< / div > <!-- fragment --> < p > When in doubt, leave this at its default. < / p >
< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00535" > 535< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
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< / div >
< a id = "a17cd20bb954bc137251cf7fb63889151" > < / a >
< h2 class = "memtitle" > < span class = "permalink" > < a href = "#a17cd20bb954bc137251cf7fb63889151" > ◆ < / a > < / span > CONF_CORE_CLK_XOSC0_CFDEN< / h2 >
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< td class = "memname" > #define CONF_CORE_CLK_XOSC0_CFDEN      (1)< / td >
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< / table >
< / div > < div class = "memdoc" >
< p > This bit controls the XOSC0 clock failure detector: < / p >
< p > XOSC0 Clock Failure Detector Control< / p > < ul >
< li > 0 => Clock Failure Detector is disabled.< / li >
< li > 1 => Clock Failure Detector is enabled. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722" > Datasheet Reference< / a > < / li >
< / ul >
< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00128" > 128< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
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< a id = "a61559adc856ce1dcfa046e749af63bc3" > < / a >
< h2 class = "memtitle" > < span class = "permalink" > < a href = "#a61559adc856ce1dcfa046e749af63bc3" > ◆ < / a > < / span > CONF_CORE_CLK_XOSC0_ENABLE< / h2 >
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< div class = "memproto" >
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< td class = "memname" > #define CONF_CORE_CLK_XOSC0_ENABLE      (1)< / td >
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< / table >
< / div > < div class = "memdoc" >
< p > Enables or Disables the XOSC0 Clock. < / p >
< p > XOSC0 Enable< / p > < ul >
< li > 0 => Disables XOSC0< / li >
< li > 1 => Enables XOSC0 < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723" > Datasheet Reference< / a > < / li >
< / ul >
< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00076" > 76< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
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< a id = "a2683d3721ab44a85e60cfff0d0cbf96e" > < / a >
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< p > This bit controls the XOSC0 automatic loop control: < / p >
< p > XOSC0 Automatic Loop Control< / p > < ul >
< li > 0 => The automatic loop control is disabled.< / li >
< li > 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722" > Datasheet Reference< / a > < / li >
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< td class = "memname" > #define CONF_CORE_CLK_XOSC0_FREQUENCY      12000000< / td >
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< p > This is the frequency of the external clock you're using for XOSC0. This can be anything from 8MHz to 48MHz. < / p >
< p > XOSC0 Frequency < / p >
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< p > The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. < / p >
< p > XOSC0 Low Buffer Gain Control Bit< / p > < ul >
< li > 0 => The low buffer gain of XOSC0 is disabled.< / li >
< li > 1 => The low buffer gain of XOSC0 is enabled. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722" > Datasheet Reference< / a > < / li >
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< td class = "memname" > #define CONF_CORE_CLK_XOSC0_ONDEMAND      (0)< / td >
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< p > The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled, depending on peripheral clock requests. < / p >
< p > XOSC0 On Demand Control< / p > < ul >
< li > 0 => Oscillator is always on.< / li >
< li > 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is not running if no peripheral is requesting the clock source. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722" > Datasheet Reference< / a > < / li >
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< p > This bit controls how the XOSC0 behaves during standby sleep mode: < / p >
< p > XOSC0 Run in Standby< / p > < ul >
< li > 0 => XOSC0 is not running in standby sleep mode if no peripheral requests the clock.< / li >
< li > 1 => XOSC0 is running in standby sleep mode. If ONDEMAND is 1, XOSC0 will be running when a peripheral is requesting the clock. If ONDEMAND is 0, the clock source will always be running in standby sleep mode. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723" > Datasheet Reference< / a > < / li >
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< td class = "memname" > #define CONF_CORE_CLK_XOSC0_STARTUP_TIME      (0x00)< / td >
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< p > These bits select start-up time for XOSC0 according to the table below: < / p >
< p > XOSC0 Startup Time< / p > < ul >
< li > 0x00 => 31us< / li >
< li > 0x01 => 61us< / li >
< li > 0x02 => 122us< / li >
< li > 0x03 => 244us< / li >
< li > 0x04 => 488us< / li >
< li > 0x05 => 977us< / li >
< li > 0x06 => 1953us< / li >
< li > 0x07 => 3906us< / li >
< li > 0x08 => 7813us< / li >
< li > 0x09 => 15625us< / li >
< li > 0x0A => 31250us< / li >
< li > 0x0B => 62500us< / li >
< li > 0x0C => 125000us< / li >
< li > 0x0D => 250000us< / li >
< li > 0x0E => 500000us< / li >
< li > 0x0F => 1000000us < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=721" > Datasheet Reference< / a > < / li >
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< p > This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in case of clock recovery: < / p >
< p > XOSC0 Clock Switch Enable< / p > < ul >
< li > 0 => The clock switch back is disabled.< / li >
< li > 1 => The clock switch back is enabled. This bit is reset once the XOSC0 output clock is switched back to the external clock or crystal oscillator. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722" > Datasheet Reference< / a > < / li >
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< td class = "memname" > #define CONF_CORE_CLK_XOSC0_XTALEN      (1)< / td >
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< p > This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC0: < / p >
< p > XOSC0 XTALEN< / p > < ul >
< li > 0 => External clock connected on XIN. XOUT can be used as general purpose I/O.< / li >
< li > 1 => Crystal connected to XIN/XOUT. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723" > Datasheet Reference< / a > < / li >
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< td class = "memname" > #define CONF_CORE_CLK_XOSC1_CFDEN      (0)< / td >
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< p > This bit controls the XOSC1 clock failure detector: < / p >
< p > XOSC1 Clock Failure Detector Control< / p > < ul >
< li > 0 => Clock Failure Detector is disabled.< / li >
< li > 1 => Clock Failure Detector is enabled. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722" > Datasheet Reference< / a > < / li >
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< td class = "memname" > #define CONF_CORE_CLK_XOSC1_ENABLE      (0)< / td >
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< p > Enables or Disables the XOSC1 Clock. < / p >
< p > XOSC1 Enable< / p > < ul >
< li > 0 => Disables XOSC1< / li >
< li > 1 => Enables XOSC1 < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723" > Datasheet Reference< / a > < / li >
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< td class = "memname" > #define CONF_CORE_CLK_XOSC1_ENALC      (0)< / td >
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< p > This bit controls the XOSC1 automatic loop control: < / p >
< p > XOSC1 Automatic Loop Control< / p > < ul >
< li > 0 => The automatic loop control is disabled.< / li >
< li > 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722" > Datasheet Reference< / a > < / li >
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< td class = "memname" > #define CONF_CORE_CLK_XOSC1_FREQUENCY      12000000< / td >
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< p > This is the frequency of the external clock you're using for XOSC1. This can be anything from 8MHz to 48MHz. < / p >
< p > XOSC1 Frequency < / p >
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< p > The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. < / p >
< p > XOSC1 Low Buffer Gain Control Bit< / p > < ul >
< li > 0 => The low buffer gain of XOSC1 is disabled.< / li >
< li > 1 => The low buffer gain of XOSC1 is enabled. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722" > Datasheet Reference< / a > < / li >
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< p > The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled, depending on peripheral clock requests. < / p >
< p > XOSC1 On Demand Control< / p > < ul >
< li > 0 => Oscillator is always on.< / li >
< li > 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is not running if no peripheral is requesting the clock source. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722" > Datasheet Reference< / a > < / li >
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< p > This bit controls how the XOSC1 behaves during standby sleep mode: < / p >
< p > XOSC1 Run in Standby< / p > < ul >
< li > 0 => XOSC1 is not running in standby sleep mode if no peripheral requests the clock.< / li >
< li > 1 => XOSC1 is running in standby sleep mode. If ONDEMAND is 1, XOSC1 will be running when a peripheral is requesting the clock. If ONDEMAND is 0, the clock source will always be running in standby sleep mode. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723" > Datasheet Reference< / a > < / li >
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< p > These bits select start-up time for XOSC1 according to the table below: < / p >
< p > XOSC1 Startup Time< / p > < ul >
< li > 0x00 => 31us< / li >
< li > 0x01 => 61us< / li >
< li > 0x02 => 122us< / li >
< li > 0x03 => 244us< / li >
< li > 0x04 => 488us< / li >
< li > 0x05 => 977us< / li >
< li > 0x06 => 1953us< / li >
< li > 0x07 => 3906us< / li >
< li > 0x08 => 7813us< / li >
< li > 0x09 => 15625us< / li >
< li > 0x0A => 31250us< / li >
< li > 0x0B => 62500us< / li >
< li > 0x0C => 125000us< / li >
< li > 0x0D => 250000us< / li >
< li > 0x0E => 500000us< / li >
< li > 0x0F => 1000000us < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=721" > Datasheet Reference< / a > < / li >
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< p > This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in case of clock recovery: < / p >
< p > XOSC1 Clock Switch Enable< / p > < ul >
< li > 0 => The clock switch back is disabled.< / li >
< li > 1 => The clock switch back is enabled. This bit is reset once the XOSC1 output clock is switched back to the external clock or crystal oscillator. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722" > Datasheet Reference< / a > < / li >
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< p > This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC1: < / p >
< p > XOSC1 XTALEN< / p > < ul >
< li > 0 => External clock connected on XIN. XOUT can be used as general purpose I/O.< / li >
< li > 1 => Crystal connected to XIN/XOUT. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723" > Datasheet Reference< / a > < / li >
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< p > This bit selects the Clock Failulre Detector state. < / p >
< p > XOSC32K Clock Failure Detector Control< / p > < ul >
< li > 0 => The CFD is disabled.< / li >
< li > 1 => The CFD is enabled. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750" > Datasheet Reference< / a > < / li >
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< p > This bit selects the prescaler for the CLock Failure Detector: < / p >
< p > XOSC32K Clock Failure Detector Prescaler< / p > < ul >
< li > 0 => The CFD safe clock frequency is the OSCULP32K frequency.< / li >
< li > 1 => The CFD safe clock frequency is the OSCULP32K frequency divided by 2. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750" > Datasheet Reference< / a > < / li >
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< p > These bits control the gain of the external crstal oscillator. < / p >
< p > XOSC32K Control Gain Mode< / p > < ul >
< li > 0x00 => Low Power Mode< / li >
< li > 0x01 => Standard Mode (Default)< / li >
< li > 0x02 => High Speed Mode < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748" > Datasheet Reference< / a > < / li >
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< p > XOSC32K 1KHz Output Control< / p > < ul >
< li > 0 => 1KHz output is disabled.< / li >
< li > 1 => 1KHz output is enabled. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749" > Datasheet Reference< / a > < / li >
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< p > XOSC32K 32KHz Output Control< / p > < ul >
< li > 0 => 32KHz output is disabled.< / li >
< li > 1 => 32KHz output is enabled. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749" > Datasheet Reference< / a > < / li >
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< p > Enables or Disables XOSC32K. < / p >
< p > XOSC32K Enable< / p > < ul >
< li > 0 => The oscillator is disabled.< / li >
< li > 1 => The oscillator is enabled. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749" > Datasheet Reference< / a > < / li >
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< h2 class = "memtitle" > < span class = "permalink" > < a href = "#a8d70a30b50febec035af6b982daac395" > ◆ < / a > < / span > CONF_CORE_CLK_XOSC32K_ONDEMAND< / h2 >
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< p > This bit controls how XOSC32K behaves when a peripheral clock request is detected. < / p >
< p > XOSC32K On Demand Control< / p > < ul >
< li > 0 => On Demand Control disabled< / li >
< li > 1 => On Demand Control enabled < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748" > Datasheet Reference< / a > < / li >
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< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00314" > 314< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
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< p > This bit controls how XOSC32K behaves during standby sleep mode. < / p >
< p > XOSC32K Run in Standby< / p > < ul >
< li > 0 => Run if requested by peripheral.< / li >
< li > 1 => Run if requested by peripheral OR always run depending ONDEMAND value. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748" > Datasheet Reference< / a > < / li >
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< td class = "memname" > #define CONF_CORE_CLK_XOSC32K_STARTUP_TIME      CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us< / td >
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< p > These bits select the startup time for the oscillator. < / p >
< p > XOSC32K Startup Time< / p > < ul >
< li > 0x00 => 62.592ms< / li >
< li > 0x01 => 125.092ms< / li >
< li > 0x02 => 500.092ms< / li >
< li > 0x03 => 1000.0092ms< / li >
< li > 0x04 => 2000.0092ms< / li >
< li > 0x05 => 4000.0092ms< / li >
< li > 0x06 => 8000.0092ms < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748" > Datasheet Reference< / a > < / li >
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< p > This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery. < / p >
< p > XOSC32K Clock Switch Back< / p > < ul >
< li > 0 => The clock switch is disabled.< / li >
< li > 1 => The clock switch is enabled. This bit is reset when XOSC32K output is switched back to the external clock or crystal oscillator. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750" > Datasheet Reference< / a > < / li >
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< p > This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration. < / p >
< p > XOSC32K Write Lock< / p > < ul >
< li > 0 => XOSC32K configuration is not locked.< / li >
< li > 1 => XOSC32K configuration is locked. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748" > Datasheet Reference< / a > < / li >
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< p > This bit controls the connections between the I/O pads and the external clock or crystal oscillator. < / p >
< p > XOSC32K Crystal Oscillator Enable< / p > < ul >
< li > 0 => External clock is connected on XIN32. XOUT32 can be used as general-purpose I/O.< / li >
< li > 1 => Crystal connected to XIN32/XOUT32. < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749" > Datasheet Reference< / a > < / li >
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< h2 class = "memtitle" > < span class = "permalink" > < a href = "#a81edcdaa3908cc3d99a95047e4431405" > ◆ < / a > < / span > CONF_CORE_CMCC_ENABLE< / h2 >
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< p > Define whether the CMCC (Cortex-M Cache Controller) is enabled or not.< / p > < ul >
< li > 0 => Disabled< / li >
< li > 1 => Enabled < / li >
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< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00055" > 55< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
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< p > Define whether the DMAC is enabled or not.< / p > < ul >
< li > 0 => Disabled< / li >
< li > 1 => Enabled < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=172" > Datasheet Reference< / a > < / li >
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< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00048" > 48< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
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< p > Define the master clock divisor. < / p >
< ul >
< li > 0x1 => Clock Divide by 1< / li >
< li > 0x2 => Clock Divide by 2< / li >
< li > 0x4 => Clock Divide by 4< / li >
< li > 0x8 => Clock Divide by 8< / li >
< li > 0x10 => Clock Divide by 16< / li >
< li > 0x20 => Clock Divide by 32< / li >
< li > 0x40 => Clock Divide by 64< / li >
< li > 0x80 => Clock Divide by 128 < br / >
See < a href = "https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=170" > Datasheet Reference< / a > < / li >
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< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00038" > 38< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
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< p > Currently Unused < / p >
< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00058" > 58< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
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< td class = "memname" > #define CONF_CORE_PORT_EVCTRL_1_ENABLE      (0)< / td >
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< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00060" > 60< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
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< td class = "memname" > #define CONF_CORE_PORT_EVCTRL_2_ENABLE      (0)< / td >
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< p > Currently Unused < / p >
< p class = "definition" > Definition at line < a class = "el" href = "conf__core_8h_source.html#l00062" > 62< / a > of file < a class = "el" href = "conf__core_8h_source.html" > conf_core.h< / a > .< / p >
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