conf_core.h File Reference

#include "clocks.h"

Go to the source code of this file.

Macros
#define	CONF_CORE_DMA_ENABLE   (0)
#define	CONF_CORE_CMCC_ENABLE   (0)
#define	CONF_CORE_PORT_EVCTRL_0_ENABLE   (0)
#define	CONF_CORE_PORT_EVCTRL_1_ENABLE   (0)
#define	CONF_CORE_PORT_EVCTRL_2_ENABLE   (0)
#define	CONF_CORE_GCLK_0_ENABLE   1
#define	CONF_CORE_GCLK_0_RUN_IN_STANDBY   1
#define	CONF_CORE_GCLK_0_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_GCLK_0_DIV_VAL   1
#define	CONF_CORE_GCLK_0_DIVSEL   0
#define	CONF_CORE_GCLK_0_OUTPUT_ENABLE   1
#define	CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE   1
#define	CONF_CORE_GCLK_0_IDC   1
#define	CONF_CORE_GCLK_1_ENABLE   0
#define	CONF_CORE_GCLK_1_RUN_IN_STANDBY   0
#define	CONF_CORE_GCLK_1_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_GCLK_1_DIV_VAL   1
#define	CONF_CORE_GCLK_1_DIVSEL   0
#define	CONF_CORE_GCLK_1_OUTPUT_ENABLE   0
#define	CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE   0
#define	CONF_CORE_GCLK_1_IDC   0
#define	CONF_CORE_GCLK_2_ENABLE   0
#define	CONF_CORE_GCLK_2_RUN_IN_STANDBY   0
#define	CONF_CORE_GCLK_2_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_GCLK_2_DIV_VAL   1
#define	CONF_CORE_GCLK_2_DIVSEL   0
#define	CONF_CORE_GCLK_2_OUTPUT_ENABLE   0
#define	CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE   0
#define	CONF_CORE_GCLK_2_IDC   0
#define	CONF_CORE_GCLK_3_ENABLE   1
#define	CONF_CORE_GCLK_3_RUN_IN_STANDBY   0
#define	CONF_CORE_GCLK_3_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC32K
#define	CONF_CORE_GCLK_3_DIV_VAL   1
#define	CONF_CORE_GCLK_3_DIVSEL   0
#define	CONF_CORE_GCLK_3_OUTPUT_ENABLE   0
#define	CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE   0
#define	CONF_CORE_GCLK_3_IDC   0
#define	CONF_CORE_GCLK_4_ENABLE   0
#define	CONF_CORE_GCLK_4_RUN_IN_STANDBY   0
#define	CONF_CORE_GCLK_4_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_GCLK_4_DIV_VAL   1
#define	CONF_CORE_GCLK_4_DIVSEL   1
#define	CONF_CORE_GCLK_4_OUTPUT_ENABLE   0
#define	CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE   0
#define	CONF_CORE_GCLK_4_IDC   0
#define	CONF_CORE_GCLK_5_ENABLE   0
#define	CONF_CORE_GCLK_5_RUN_IN_STANDBY   0
#define	CONF_CORE_GCLK_5_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_GCLK_5_DIV_VAL   1
#define	CONF_CORE_GCLK_5_DIVSEL   0
#define	CONF_CORE_GCLK_5_OUTPUT_ENABLE   0
#define	CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE   0
#define	CONF_CORE_GCLK_5_IDC   0
#define	CONF_CORE_GCLK_6_ENABLE   0
#define	CONF_CORE_GCLK_6_RUN_IN_STANDBY   0
#define	CONF_CORE_GCLK_6_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_GCLK_6_DIV_VAL   1
#define	CONF_CORE_GCLK_6_DIVSEL   0
#define	CONF_CORE_GCLK_6_OUTPUT_ENABLE   0
#define	CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE   0
#define	CONF_CORE_GCLK_6_IDC   0
#define	CONF_CORE_GCLK_7_ENABLE   0
#define	CONF_CORE_GCLK_7_RUN_IN_STANDBY   0
#define	CONF_CORE_GCLK_7_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_GCLK_7_DIV_VAL   1
#define	CONF_CORE_GCLK_7_DIVSEL   0
#define	CONF_CORE_GCLK_7_OUTPUT_ENABLE   0
#define	CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE   0
#define	CONF_CORE_GCLK_7_IDC   0
#define	CONF_CORE_GCLK_8_ENABLE   0
#define	CONF_CORE_GCLK_8_RUN_IN_STANDBY   0
#define	CONF_CORE_GCLK_8_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_GCLK_8_DIV_VAL   1
#define	CONF_CORE_GCLK_8_DIVSEL   0
#define	CONF_CORE_GCLK_8_OUTPUT_ENABLE   0
#define	CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE   0
#define	CONF_CORE_GCLK_8_IDC   0
#define	CONF_CORE_GCLK_9_ENABLE   0
#define	CONF_CORE_GCLK_9_RUN_IN_STANDBY   0
#define	CONF_CORE_GCLK_9_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_GCLK_9_DIV_VAL   1
#define	CONF_CORE_GCLK_9_DIVSEL   0
#define	CONF_CORE_GCLK_9_OUTPUT_ENABLE   0
#define	CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE   0
#define	CONF_CORE_GCLK_9_IDC   0
#define	CONF_CORE_GCLK_10_ENABLE   0
#define	CONF_CORE_GCLK_10_RUN_IN_STANDBY   0
#define	CONF_CORE_GCLK_10_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_GCLK_10_DIV_VAL   1
#define	CONF_CORE_GCLK_10_DIVSEL   0
#define	CONF_CORE_GCLK_10_OUTPUT_ENABLE   0
#define	CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE   0
#define	CONF_CORE_GCLK_10_IDC   0
#define	CONF_CORE_GCLK_11_ENABLE   0
#define	CONF_CORE_GCLK_11_RUN_IN_STANDBY   0
#define	CONF_CORE_GCLK_11_CLOCK_SOURCE   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_GCLK_11_DIV_VAL   1
#define	CONF_CORE_GCLK_11_DIVSEL   0
#define	CONF_CORE_GCLK_11_OUTPUT_ENABLE   0
#define	CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE   0
#define	CONF_CORE_GCLK_11_IDC   0
Core-Master-Clock-Configuration
Configuration options for the master clock.
#define	CONF_CORE_MCLK_NVM_WAIT_STATE   0x5
	Define the number of wait states for the master clock. Can be [0-15]. See Datasheet Reference
#define	CONF_CORE_MCLK_CPUDIV   0x1
	Define the master clock divisor. More...
Core-XOSC0-Configuration
Configuration options for XOSC0. See Datasheet Reference
#define	CONF_CORE_CLK_XOSC0_ENABLE   (1)
	Enables or Disables the XOSC0 Clock. More...
#define	CONF_CORE_CLK_XOSC0_XTALEN   (1)
	This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC0: More...
#define	CONF_CORE_CLK_XOSC0_RUNSTDBY   (0)
	This bit controls how the XOSC0 behaves during standby sleep mode: More...
#define	CONF_CORE_CLK_XOSC0_ONDEMAND   (0)
	The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled, depending on peripheral clock requests. More...
#define	CONF_CORE_CLK_XOSC0_LOWBUFGAIN   (0)
	The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. More...
#define	CONF_CORE_CLK_XOSC0_ENALC   (1)
	This bit controls the XOSC0 automatic loop control: More...
#define	CONF_CORE_CLK_XOSC0_CFDEN   (1)
	This bit controls the XOSC0 clock failure detector: More...
#define	CONF_CORE_CLK_XOSC0_SWBEN   (0)
	This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in case of clock recovery: More...
#define	CONF_CORE_CLK_XOSC0_STARTUP_TIME   (0x00)
	These bits select start-up time for XOSC0 according to the table below: More...
#define	CONF_CORE_CLK_XOSC0_FREQUENCY   12000000
	This is the frequency of the external clock you're using for XOSC0. This can be anything from 8MHz to 48MHz. More...
Core-XOSC1-Configuration
Configuration options for XOSC1. See Datasheet Reference
#define	CONF_CORE_CLK_XOSC1_ENABLE   (0)
	Enables or Disables the XOSC1 Clock. More...
#define	CONF_CORE_CLK_XOSC1_XTALEN   (0)
	This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC1: More...
#define	CONF_CORE_CLK_XOSC1_RUNSTDBY   (0)
	This bit controls how the XOSC1 behaves during standby sleep mode: More...
#define	CONF_CORE_CLK_XOSC1_ONDEMAND   (0)
	The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled, depending on peripheral clock requests. More...
#define	CONF_CORE_CLK_XOSC1_LOWBUFGAIN   (0)
	The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. More...
#define	CONF_CORE_CLK_XOSC1_ENALC   (0)
	This bit controls the XOSC1 automatic loop control: More...
#define	CONF_CORE_CLK_XOSC1_CFDEN   (0)
	This bit controls the XOSC1 clock failure detector: More...
#define	CONF_CORE_CLK_XOSC1_SWBEN   (0)
	This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in case of clock recovery: More...
#define	CONF_CORE_CLK_XOSC1_STARTUP_TIME   (0x00)
	These bits select start-up time for XOSC1 according to the table below: More...
#define	CONF_CORE_CLK_XOSC1_FREQUENCY   12000000
	This is the frequency of the external clock you're using for XOSC1. This can be anything from 8MHz to 48MHz. More...
Core-XOSC32K-Configuration
Configuration options for the external 32khz oscillator. See Datasheet Reference
#define	CONF_CORE_CLK_XOSC32K_ENABLE   (1)
	Enables or Disables XOSC32K. More...
#define	CONF_CORE_CLK_XOSC32K_CGM   (0x01)
	These bits control the gain of the external crstal oscillator. More...
#define	CONF_CORE_CLK_XOSC32K_STARTUP_TIME   CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
	These bits select the startup time for the oscillator. More...
#define	CONF_CORE_CLK_XOSC32K_ONDEMAND   (1)
	This bit controls how XOSC32K behaves when a peripheral clock request is detected. More...
#define	CONF_CORE_CLK_XOSC32K_RUNSTDBY   (0)
	This bit controls how XOSC32K behaves during standby sleep mode. More...
#define	CONF_CORE_CLK_XOSC32K_EN1K   (0)
#define	CONF_CORE_CLK_XOSC32K_EN32K   (1)
#define	CONF_CORE_CLK_XOSC32K_XTALEN   (1)
	This bit controls the connections between the I/O pads and the external clock or crystal oscillator. More...
#define	CONF_CORE_CLK_XOSC32K_CFDPRESC   (0)
	This bit selects the prescaler for the CLock Failure Detector: More...
#define	CONF_CORE_CLK_XOSC32K_CFDEN   (0)
	This bit selects the Clock Failulre Detector state. More...
#define	CONF_CORE_CLK_XOSC32K_SWBACK   (0)
	This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery. More...
#define	CONF_CORE_CLK_XOSC32K_WRTLOCK   (0)
	This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration. More...
Core-DFLL48M-Configuration
Configuration options for DFLL48M
#define	CONF_CORE_CLK_DFLL_ENABLE   (1)
	Enables or Disables the DFLL48M Clock. More...
#define	CONF_CORE_CLK_DFLL_ONDEMAND   (0)
	Enables or Disables on-demand operation. More...
#define	CONF_CORE_CLK_DFLL_RUNSTDBY   (0)
	Enables or Disables run-in-standby operation. More...
#define	CONF_CORE_CLK_DFLL_WAITLOCK   (0)
	This bit controls the DFLL output clock, depending on the lock status: More...
#define	CONF_CORE_CLK_DFLL_BPLKC   (0)
#define	CONF_CORE_CLK_DFLL_QLDIS   (0)
#define	CONF_CORE_CLK_DFLL_CCDIS   (1)
#define	CONF_CORE_CLK_DFLL_USBCRM   (1)
#define	CONF_CORE_CLK_DFLL_LLAW   (0)
#define	CONF_CORE_CLK_DFLL_STABLE_FCALIB   CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED
#define	CONF_CORE_CLK_DFLL_MODE   0x01
#define	CONF_CORE_CLK_DFLL_DIFF_VAL   0
#define	CONF_CORE_CLK_DFLL_COARSE_VAL   (0x1f / 4)
#define	CONF_CORE_CLK_DFLL_FINE_VAL   128
#define	CONF_CORE_CLK_DFLL_CSTEP_VAL   1
#define	CONF_CORE_CLK_DFLL_FSTEP_VAL   1
#define	CONF_CORE_CLK_DFLL_MUL_VAL   (48000000)
#define	CONF_CORE_CLK_DFLL_GCLK_SRC   3
	GCLK Source used to generate DFLL48M. More...
#define	CONF_CORE_CLK_DFLL_OVERWRITE_CAL   0
Core-DPLL0-Configuration
Configuration Options for DPLL0.
#define	CONF_CORE_CLK_DPLL0_ENABLE   (1)
#define	CONF_CORE_CLK_DPLL0_ONDEMAND   (0)
#define	CONF_CORE_CLK_DPLL0_RUNSTDBY   (0)
#define	CONF_CORE_CLK_DPLL0_LDRFRAC_VAL   0
#define	CONF_CORE_CLK_DPLL0_LDR_VAL   (119)
#define	CONF_CORE_CLK_DPLL0_DIV_VAL   (5)
#define	CONF_CORE_CLK_DPLL0_DCOEN   0
#define	CONF_CORE_CLK_DPLL0_DCOFILTER   CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
#define	CONF_CORE_CLK_DPLL0_LBYPASS   1
#define	CONF_CORE_CLK_DPLL0_LTIME   0
#define	CONF_CORE_CLK_DPLL0_WUF   0
#define	CONF_CORE_CLK_DPLL0_GCLK_SRC   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_CLK_DPLL0_REFCLK   CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
#define	CONF_CORE_CLK_DPLL0_FILTER   0x0
Core-DPLL1-Configuration
Configuration Options for DPLL1.
#define	CONF_CORE_CLK_DPLL1_ENABLE   (0)
#define	CONF_CORE_CLK_DPLL1_ONDEMAND   (0)
#define	CONF_CORE_CLK_DPLL1_RUNSTDBY   (0)
#define	CONF_CORE_CLK_DPLL1_LDRFRAC_VAL   0
#define	CONF_CORE_CLK_DPLL1_LDR_VAL   (0)
#define	CONF_CORE_CLK_DPLL1_DIV_VAL   (0)
#define	CONF_CORE_CLK_DPLL1_DCOEN   0
#define	CONF_CORE_CLK_DPLL1_DCOFILTER   CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
#define	CONF_CORE_CLK_DPLL1_LBYPASS   0
#define	CONF_CORE_CLK_DPLL1_LTIME   0
#define	CONF_CORE_CLK_DPLL1_WUF   0
#define	CONF_CORE_CLK_DPLL1_GCLK_SRC   GCLK_GENCTRL_SRC_XOSC0
#define	CONF_CORE_CLK_DPLL1_REFCLK   CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
#define	CONF_CORE_CLK_DPLL1_FILTER   0x0

Detailed Description

Author

Penguin

Description

This is the master config for the core module for this mcu. This file is required for the core module to function.

Definition in file conf_core.h.

Macro Definition Documentation

CONF_CORE_CLK_DFLL_ENABLE

#define CONF_CORE_CLK_DFLL_ENABLE   (1)

Enables or Disables the DFLL48M Clock.

DFLL48M Enable

• 0 => Disables DFLL48M
• 1 => Enables DFLL48M
  pg. 724 of datasheet

Definition at line 390 of file conf_core.h.

CONF_CORE_CLK_DFLL_GCLK_SRC

#define CONF_CORE_CLK_DFLL_GCLK_SRC   3

GCLK Source used to generate DFLL48M.

DFLL48M GCLK Source

• 0 => Generic clock generator 0
• 1 => Generic clock generator 1
• 2 => Generic clock generator 2
• 3 => Generic clock generator 3
• 4 => Generic clock generator 4
• 5 => Generic clock generator 5
• 6 => Generic clock generator 6
• 7 => Generic clock generator 7
• 8 => Generic clock generator 8
• 9 => Generic clock generator 9
• 10 => Generic clock generator 10
• 11 => Generic clock generator 11

Definition at line 444 of file conf_core.h.

CONF_CORE_CLK_DFLL_ONDEMAND

#define CONF_CORE_CLK_DFLL_ONDEMAND   (0)

Enables or Disables on-demand operation.

DFLL48M On Demand Control

• 0 => Disables On Demand Operation
• 1 => Enables On Demand Operation
  pg. 724 of datasheet

Definition at line 398 of file conf_core.h.

CONF_CORE_CLK_DFLL_RUNSTDBY

#define CONF_CORE_CLK_DFLL_RUNSTDBY   (0)

Enables or Disables run-in-standby operation.

DFLL48M Run in Standby Control

• 0 => Disables run-in-standby operation
• 1 => Enables run-in-standby operation
  pg. 724 of datasheet

Definition at line 406 of file conf_core.h.

CONF_CORE_CLK_DFLL_WAITLOCK

#define CONF_CORE_CLK_DFLL_WAITLOCK   (0)

This bit controls the DFLL output clock, depending on the lock status:

DFLL48M Wait Lock Control

• 0 => Output clock before the DFLL is locked.
• 1 => Output clock when DFLL is locked (Fine lock).
  pg. 725 of datasheet

Definition at line 414 of file conf_core.h.

CONF_CORE_CLK_DPLL0_FILTER

#define CONF_CORE_CLK_DPLL0_FILTER   0x0

pg. 732 of the datasheet

FILTER[3:0] | PLL Bandwidth (fn)    | Damping Factor
0x0         | 92.7 kHz              | 0.76
0x1         | 131 kHz               | 1.08
0x2         | 46.4 kHz              | 0.38
0x3         | 65.6 kHz              | 0.54
0x4         | 131 kHz               | 0.56
0x5         | 185 kHz               | 0.79
0x6         | 65.6 kHz              | 0.28
0x7         | 92.7 kHz              | 0.39
0x8         | 46.4 kHz              | 1.49
0x9         | 65.6 kHz              | 2.11
0xA         | 23.2 kHz              | 0.75
0xB         | 32.8 kHz              | 1.06
0xC         | 65.6 kHz              | 1.07
0xD         | 92.7 kHz              | 1.51
0xE         | 32.8 kHz              | 0.53
0xF         | 46.4 kHz              | 0.75

When in doubt, leave this at its default.

Definition at line 490 of file conf_core.h.

CONF_CORE_CLK_DPLL1_FILTER

#define CONF_CORE_CLK_DPLL1_FILTER   0x0

pg. 732 of the datasheet

FILTER[3:0] | PLL Bandwidth (fn)    | Damping Factor
0x0         | 92.7 kHz              | 0.76
0x1         | 131 kHz               | 1.08
0x2         | 46.4 kHz              | 0.38
0x3         | 65.6 kHz              | 0.54
0x4         | 131 kHz               | 0.56
0x5         | 185 kHz               | 0.79
0x6         | 65.6 kHz              | 0.28
0x7         | 92.7 kHz              | 0.39
0x8         | 46.4 kHz              | 1.49
0x9         | 65.6 kHz              | 2.11
0xA         | 23.2 kHz              | 0.75
0xB         | 32.8 kHz              | 1.06
0xC         | 65.6 kHz              | 1.07
0xD         | 92.7 kHz              | 1.51
0xE         | 32.8 kHz              | 0.53
0xF         | 46.4 kHz              | 0.75

When in doubt, leave this at its default.

Definition at line 535 of file conf_core.h.

CONF_CORE_CLK_XOSC0_CFDEN

#define CONF_CORE_CLK_XOSC0_CFDEN   (1)

This bit controls the XOSC0 clock failure detector:

XOSC0 Clock Failure Detector Control

• 0 => Clock Failure Detector is disabled.
• 1 => Clock Failure Detector is enabled.
  See Datasheet Reference

Definition at line 128 of file conf_core.h.

CONF_CORE_CLK_XOSC0_ENABLE

#define CONF_CORE_CLK_XOSC0_ENABLE   (1)

Enables or Disables the XOSC0 Clock.

XOSC0 Enable

• 0 => Disables XOSC0
• 1 => Enables XOSC0
  See Datasheet Reference

Definition at line 76 of file conf_core.h.

CONF_CORE_CLK_XOSC0_ENALC

#define CONF_CORE_CLK_XOSC0_ENALC   (1)

This bit controls the XOSC0 automatic loop control:

XOSC0 Automatic Loop Control

• 0 => The automatic loop control is disabled.
• 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation.
  See Datasheet Reference

Definition at line 120 of file conf_core.h.

CONF_CORE_CLK_XOSC0_FREQUENCY

#define CONF_CORE_CLK_XOSC0_FREQUENCY   12000000

This is the frequency of the external clock you're using for XOSC0. This can be anything from 8MHz to 48MHz.

XOSC0 Frequency

Definition at line 165 of file conf_core.h.

CONF_CORE_CLK_XOSC0_LOWBUFGAIN

#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN   (0)

The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues.

XOSC0 Low Buffer Gain Control Bit

• 0 => The low buffer gain of XOSC0 is disabled.
• 1 => The low buffer gain of XOSC0 is enabled.
  See Datasheet Reference

Definition at line 112 of file conf_core.h.

CONF_CORE_CLK_XOSC0_ONDEMAND

#define CONF_CORE_CLK_XOSC0_ONDEMAND   (0)

The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled, depending on peripheral clock requests.

XOSC0 On Demand Control

• 0 => Oscillator is always on.
• 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is not running if no peripheral is requesting the clock source.
  See Datasheet Reference

Definition at line 103 of file conf_core.h.

CONF_CORE_CLK_XOSC0_RUNSTDBY

#define CONF_CORE_CLK_XOSC0_RUNSTDBY   (0)

This bit controls how the XOSC0 behaves during standby sleep mode:

XOSC0 Run in Standby

• 0 => XOSC0 is not running in standby sleep mode if no peripheral requests the clock.
• 1 => XOSC0 is running in standby sleep mode. If ONDEMAND is 1, XOSC0 will be running when a peripheral is requesting the clock. If ONDEMAND is 0, the clock source will always be running in standby sleep mode.
  See Datasheet Reference

Definition at line 94 of file conf_core.h.

CONF_CORE_CLK_XOSC0_STARTUP_TIME

#define CONF_CORE_CLK_XOSC0_STARTUP_TIME   (0x00)

These bits select start-up time for XOSC0 according to the table below:

XOSC0 Startup Time

• 0x00 => 31us
• 0x01 => 61us
• 0x02 => 122us
• 0x03 => 244us
• 0x04 => 488us
• 0x05 => 977us
• 0x06 => 1953us
• 0x07 => 3906us
• 0x08 => 7813us
• 0x09 => 15625us
• 0x0A => 31250us
• 0x0B => 62500us
• 0x0C => 125000us
• 0x0D => 250000us
• 0x0E => 500000us
• 0x0F => 1000000us
  See Datasheet Reference

Definition at line 159 of file conf_core.h.

CONF_CORE_CLK_XOSC0_SWBEN

#define CONF_CORE_CLK_XOSC0_SWBEN   (0)

This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in case of clock recovery:

XOSC0 Clock Switch Enable

• 0 => The clock switch back is disabled.
• 1 => The clock switch back is enabled. This bit is reset once the XOSC0 output clock is switched back to the external clock or crystal oscillator.
  See Datasheet Reference

Definition at line 137 of file conf_core.h.

CONF_CORE_CLK_XOSC0_XTALEN

#define CONF_CORE_CLK_XOSC0_XTALEN   (1)

This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC0:

XOSC0 XTALEN

• 0 => External clock connected on XIN. XOUT can be used as general purpose I/O.
• 1 => Crystal connected to XIN/XOUT.
  See Datasheet Reference

Definition at line 84 of file conf_core.h.

CONF_CORE_CLK_XOSC1_CFDEN

#define CONF_CORE_CLK_XOSC1_CFDEN   (0)

This bit controls the XOSC1 clock failure detector:

XOSC1 Clock Failure Detector Control

• 0 => Clock Failure Detector is disabled.
• 1 => Clock Failure Detector is enabled.
  See Datasheet Reference

Definition at line 232 of file conf_core.h.

CONF_CORE_CLK_XOSC1_ENABLE

#define CONF_CORE_CLK_XOSC1_ENABLE   (0)

Enables or Disables the XOSC1 Clock.

XOSC1 Enable

• 0 => Disables XOSC1
• 1 => Enables XOSC1
  See Datasheet Reference

Definition at line 180 of file conf_core.h.

CONF_CORE_CLK_XOSC1_ENALC

#define CONF_CORE_CLK_XOSC1_ENALC   (0)

This bit controls the XOSC1 automatic loop control:

XOSC1 Automatic Loop Control

• 0 => The automatic loop control is disabled.
• 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation.
  See Datasheet Reference

Definition at line 224 of file conf_core.h.

CONF_CORE_CLK_XOSC1_FREQUENCY

#define CONF_CORE_CLK_XOSC1_FREQUENCY   12000000

This is the frequency of the external clock you're using for XOSC1. This can be anything from 8MHz to 48MHz.

XOSC1 Frequency

Definition at line 269 of file conf_core.h.

CONF_CORE_CLK_XOSC1_LOWBUFGAIN

#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN   (0)

The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues.

XOSC1 Low Buffer Gain Control Bit

• 0 => The low buffer gain of XOSC1 is disabled.
• 1 => The low buffer gain of XOSC1 is enabled.
  See Datasheet Reference

Definition at line 216 of file conf_core.h.

CONF_CORE_CLK_XOSC1_ONDEMAND

#define CONF_CORE_CLK_XOSC1_ONDEMAND   (0)

The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled, depending on peripheral clock requests.

XOSC1 On Demand Control

• 0 => Oscillator is always on.
• 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is not running if no peripheral is requesting the clock source.
  See Datasheet Reference

Definition at line 207 of file conf_core.h.

CONF_CORE_CLK_XOSC1_RUNSTDBY

#define CONF_CORE_CLK_XOSC1_RUNSTDBY   (0)

This bit controls how the XOSC1 behaves during standby sleep mode:

XOSC1 Run in Standby

• 0 => XOSC1 is not running in standby sleep mode if no peripheral requests the clock.
• 1 => XOSC1 is running in standby sleep mode. If ONDEMAND is 1, XOSC1 will be running when a peripheral is requesting the clock. If ONDEMAND is 0, the clock source will always be running in standby sleep mode.
  See Datasheet Reference

Definition at line 198 of file conf_core.h.

CONF_CORE_CLK_XOSC1_STARTUP_TIME

#define CONF_CORE_CLK_XOSC1_STARTUP_TIME   (0x00)

These bits select start-up time for XOSC1 according to the table below:

XOSC1 Startup Time

• 0x00 => 31us
• 0x01 => 61us
• 0x02 => 122us
• 0x03 => 244us
• 0x04 => 488us
• 0x05 => 977us
• 0x06 => 1953us
• 0x07 => 3906us
• 0x08 => 7813us
• 0x09 => 15625us
• 0x0A => 31250us
• 0x0B => 62500us
• 0x0C => 125000us
• 0x0D => 250000us
• 0x0E => 500000us
• 0x0F => 1000000us
  See Datasheet Reference

Definition at line 263 of file conf_core.h.

CONF_CORE_CLK_XOSC1_SWBEN

#define CONF_CORE_CLK_XOSC1_SWBEN   (0)

This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in case of clock recovery:

XOSC1 Clock Switch Enable

• 0 => The clock switch back is disabled.
• 1 => The clock switch back is enabled. This bit is reset once the XOSC1 output clock is switched back to the external clock or crystal oscillator.
  See Datasheet Reference

Definition at line 241 of file conf_core.h.

CONF_CORE_CLK_XOSC1_XTALEN

#define CONF_CORE_CLK_XOSC1_XTALEN   (0)

This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC1:

XOSC1 XTALEN

• 0 => External clock connected on XIN. XOUT can be used as general purpose I/O.
• 1 => Crystal connected to XIN/XOUT.
  See Datasheet Reference

Definition at line 188 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_CFDEN

#define CONF_CORE_CLK_XOSC32K_CFDEN   (0)

This bit selects the Clock Failulre Detector state.

XOSC32K Clock Failure Detector Control

• 0 => The CFD is disabled.
• 1 => The CFD is enabled.
  See Datasheet Reference

Definition at line 360 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_CFDPRESC

#define CONF_CORE_CLK_XOSC32K_CFDPRESC   (0)

This bit selects the prescaler for the CLock Failure Detector:

XOSC32K Clock Failure Detector Prescaler

• 0 => The CFD safe clock frequency is the OSCULP32K frequency.
• 1 => The CFD safe clock frequency is the OSCULP32K frequency divided by 2.
  See Datasheet Reference

Definition at line 352 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_CGM

#define CONF_CORE_CLK_XOSC32K_CGM   (0x01)

These bits control the gain of the external crstal oscillator.

XOSC32K Control Gain Mode

• 0x00 => Low Power Mode
• 0x01 => Standard Mode (Default)
• 0x02 => High Speed Mode
  See Datasheet Reference

Definition at line 293 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_EN1K

#define CONF_CORE_CLK_XOSC32K_EN1K   (0)

XOSC32K 1KHz Output Control

• 0 => 1KHz output is disabled.
• 1 => 1KHz output is enabled.
  See Datasheet Reference

Definition at line 329 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_EN32K

#define CONF_CORE_CLK_XOSC32K_EN32K   (1)

XOSC32K 32KHz Output Control

• 0 => 32KHz output is disabled.
• 1 => 32KHz output is enabled.
  See Datasheet Reference

Definition at line 336 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_ENABLE

#define CONF_CORE_CLK_XOSC32K_ENABLE   (1)

Enables or Disables XOSC32K.

XOSC32K Enable

• 0 => The oscillator is disabled.
• 1 => The oscillator is enabled.
  See Datasheet Reference

Definition at line 284 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_ONDEMAND

#define CONF_CORE_CLK_XOSC32K_ONDEMAND   (1)

This bit controls how XOSC32K behaves when a peripheral clock request is detected.

XOSC32K On Demand Control

• 0 => On Demand Control disabled
• 1 => On Demand Control enabled
  See Datasheet Reference

Definition at line 314 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_RUNSTDBY

#define CONF_CORE_CLK_XOSC32K_RUNSTDBY   (0)

This bit controls how XOSC32K behaves during standby sleep mode.

XOSC32K Run in Standby

• 0 => Run if requested by peripheral.
• 1 => Run if requested by peripheral OR always run depending ONDEMAND value.
  See Datasheet Reference

Definition at line 322 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_STARTUP_TIME

#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME   CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us

These bits select the startup time for the oscillator.

XOSC32K Startup Time

• 0x00 => 62.592ms
• 0x01 => 125.092ms
• 0x02 => 500.092ms
• 0x03 => 1000.0092ms
• 0x04 => 2000.0092ms
• 0x05 => 4000.0092ms
• 0x06 => 8000.0092ms
  See Datasheet Reference

Definition at line 306 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_SWBACK

#define CONF_CORE_CLK_XOSC32K_SWBACK   (0)

This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery.

XOSC32K Clock Switch Back

• 0 => The clock switch is disabled.
• 1 => The clock switch is enabled. This bit is reset when XOSC32K output is switched back to the external clock or crystal oscillator.
  See Datasheet Reference

Definition at line 368 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_WRTLOCK

#define CONF_CORE_CLK_XOSC32K_WRTLOCK   (0)

This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration.

XOSC32K Write Lock

• 0 => XOSC32K configuration is not locked.
• 1 => XOSC32K configuration is locked.
  See Datasheet Reference

Definition at line 376 of file conf_core.h.

CONF_CORE_CLK_XOSC32K_XTALEN

#define CONF_CORE_CLK_XOSC32K_XTALEN   (1)

This bit controls the connections between the I/O pads and the external clock or crystal oscillator.

XOSC32K Crystal Oscillator Enable

• 0 => External clock is connected on XIN32. XOUT32 can be used as general-purpose I/O.
• 1 => Crystal connected to XIN32/XOUT32.
  See Datasheet Reference

Definition at line 344 of file conf_core.h.

CONF_CORE_CMCC_ENABLE

#define CONF_CORE_CMCC_ENABLE   (0)

Define whether the CMCC (Cortex-M Cache Controller) is enabled or not.

• 0 => Disabled
• 1 => Enabled

Definition at line 55 of file conf_core.h.

CONF_CORE_DMA_ENABLE

#define CONF_CORE_DMA_ENABLE   (0)

Define whether the DMAC is enabled or not.

• 0 => Disabled
• 1 => Enabled
  See Datasheet Reference

Definition at line 48 of file conf_core.h.

CONF_CORE_MCLK_CPUDIV

#define CONF_CORE_MCLK_CPUDIV   0x1

Define the master clock divisor.

• 0x1 => Clock Divide by 1
• 0x2 => Clock Divide by 2
• 0x4 => Clock Divide by 4
• 0x8 => Clock Divide by 8
• 0x10 => Clock Divide by 16
• 0x20 => Clock Divide by 32
• 0x40 => Clock Divide by 64
• 0x80 => Clock Divide by 128
  See Datasheet Reference

Definition at line 38 of file conf_core.h.

CONF_CORE_PORT_EVCTRL_0_ENABLE

#define CONF_CORE_PORT_EVCTRL_0_ENABLE   (0)

Currently Unused

Definition at line 58 of file conf_core.h.

CONF_CORE_PORT_EVCTRL_1_ENABLE

#define CONF_CORE_PORT_EVCTRL_1_ENABLE   (0)

Currently Unused

Definition at line 60 of file conf_core.h.

CONF_CORE_PORT_EVCTRL_2_ENABLE

#define CONF_CORE_PORT_EVCTRL_2_ENABLE   (0)

Currently Unused

Definition at line 62 of file conf_core.h.