Can Struct Reference

CAN APB hardware registers. More...

#include <can.h>

Data Fields
__I CAN_CREL_Type	CREL
	Offset: 0x00 (R/ 32) Core Release.
__I CAN_ENDN_Type	ENDN
	Offset: 0x04 (R/ 32) Endian.
__IO CAN_MRCFG_Type	MRCFG
	Offset: 0x08 (R/W 32) Message RAM Configuration.
__IO CAN_DBTP_Type	DBTP
	Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler.
__IO CAN_TEST_Type	TEST
	Offset: 0x10 (R/W 32) Test.
__IO CAN_RWD_Type	RWD
	Offset: 0x14 (R/W 32) RAM Watchdog.
__IO CAN_CCCR_Type	CCCR
	Offset: 0x18 (R/W 32) CC Control.
__IO CAN_NBTP_Type	NBTP
	Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler.
__IO CAN_TSCC_Type	TSCC
	Offset: 0x20 (R/W 32) Timestamp Counter Configuration.
__I CAN_TSCV_Type	TSCV
	Offset: 0x24 (R/ 32) Timestamp Counter Value.
__IO CAN_TOCC_Type	TOCC
	Offset: 0x28 (R/W 32) Timeout Counter Configuration.
__IO CAN_TOCV_Type	TOCV
	Offset: 0x2C (R/W 32) Timeout Counter Value.
RoReg8	Reserved1 [0x10]
__I CAN_ECR_Type	ECR
	Offset: 0x40 (R/ 32) Error Counter.
__I CAN_PSR_Type	PSR
	Offset: 0x44 (R/ 32) Protocol Status.
__IO CAN_TDCR_Type	TDCR
	Offset: 0x48 (R/W 32) Extended ID Filter Configuration.
RoReg8	Reserved2 [0x4]
__IO CAN_IR_Type	IR
	Offset: 0x50 (R/W 32) Interrupt.
__IO CAN_IE_Type	IE
	Offset: 0x54 (R/W 32) Interrupt Enable.
__IO CAN_ILS_Type	ILS
	Offset: 0x58 (R/W 32) Interrupt Line Select.
__IO CAN_ILE_Type	ILE
	Offset: 0x5C (R/W 32) Interrupt Line Enable.
RoReg8	Reserved3 [0x20]
__IO CAN_GFC_Type	GFC
	Offset: 0x80 (R/W 32) Global Filter Configuration.
__IO CAN_SIDFC_Type	SIDFC
	Offset: 0x84 (R/W 32) Standard ID Filter Configuration.
__IO CAN_XIDFC_Type	XIDFC
	Offset: 0x88 (R/W 32) Extended ID Filter Configuration.
RoReg8	Reserved4 [0x4]
__IO CAN_XIDAM_Type	XIDAM
	Offset: 0x90 (R/W 32) Extended ID AND Mask.
__I CAN_HPMS_Type	HPMS
	Offset: 0x94 (R/ 32) High Priority Message Status.
__IO CAN_NDAT1_Type	NDAT1
	Offset: 0x98 (R/W 32) New Data 1.
__IO CAN_NDAT2_Type	NDAT2
	Offset: 0x9C (R/W 32) New Data 2.
__IO CAN_RXF0C_Type	RXF0C
	Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration.
__I CAN_RXF0S_Type	RXF0S
	Offset: 0xA4 (R/ 32) Rx FIFO 0 Status.
__IO CAN_RXF0A_Type	RXF0A
	Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge.
__IO CAN_RXBC_Type	RXBC
	Offset: 0xAC (R/W 32) Rx Buffer Configuration.
__IO CAN_RXF1C_Type	RXF1C
	Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration.
__I CAN_RXF1S_Type	RXF1S
	Offset: 0xB4 (R/ 32) Rx FIFO 1 Status.
__IO CAN_RXF1A_Type	RXF1A
	Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge.
__IO CAN_RXESC_Type	RXESC
	Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration.
__IO CAN_TXBC_Type	TXBC
	Offset: 0xC0 (R/W 32) Tx Buffer Configuration.
__I CAN_TXFQS_Type	TXFQS
	Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status.
__IO CAN_TXESC_Type	TXESC
	Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration.
__I CAN_TXBRP_Type	TXBRP
	Offset: 0xCC (R/ 32) Tx Buffer Request Pending.
__IO CAN_TXBAR_Type	TXBAR
	Offset: 0xD0 (R/W 32) Tx Buffer Add Request.
__IO CAN_TXBCR_Type	TXBCR
	Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request.
__I CAN_TXBTO_Type	TXBTO
	Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred.
__I CAN_TXBCF_Type	TXBCF
	Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished.
__IO CAN_TXBTIE_Type	TXBTIE
	Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable.
__IO CAN_TXBCIE_Type	TXBCIE
	Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable.
RoReg8	Reserved5 [0x8]
__IO CAN_TXEFC_Type	TXEFC
	Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration.
__I CAN_TXEFS_Type	TXEFS
	Offset: 0xF4 (R/ 32) Tx Event FIFO Status.
__IO CAN_TXEFA_Type	TXEFA
	Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge.

Detailed Description

CAN APB hardware registers.

Definition at line 3034 of file can.h.

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The documentation for this struct was generated from the following file:

• /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/can.h