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348 lines
9.2 KiB
C
348 lines
9.2 KiB
C
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/**
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* \file
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*
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* \brief SAM TC
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*
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* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <hpl_pwm.h>
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#include <hpl_tc_config.h>
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#include <hpl_timer.h>
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#include <utils.h>
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#include <utils_assert.h>
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#include <hpl_tc_base.h>
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#ifndef CONF_TC0_ENABLE
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#define CONF_TC0_ENABLE 0
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#endif
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#ifndef CONF_TC1_ENABLE
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#define CONF_TC1_ENABLE 0
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#endif
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#ifndef CONF_TC2_ENABLE
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#define CONF_TC2_ENABLE 0
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#endif
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#ifndef CONF_TC3_ENABLE
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#define CONF_TC3_ENABLE 0
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#endif
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#ifndef CONF_TC4_ENABLE
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#define CONF_TC4_ENABLE 0
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#endif
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#ifndef CONF_TC5_ENABLE
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#define CONF_TC5_ENABLE 0
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#endif
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#ifndef CONF_TC6_ENABLE
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#define CONF_TC6_ENABLE 0
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#endif
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#ifndef CONF_TC7_ENABLE
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#define CONF_TC7_ENABLE 0
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#endif
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/**
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* \brief Macro is used to fill usart configuration structure based on its
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* number
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*
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* \param[in] n The number of structures
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*/
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#define TC_CONFIGURATION(n) \
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{ \
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n, TC##n##_IRQn, \
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TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC) \
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| (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos) \
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| TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos), \
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(CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \
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| (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \
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| (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \
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(CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1, \
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}
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/**
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* \brief TC configuration type
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*/
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struct tc_configuration {
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uint8_t number;
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IRQn_Type irq;
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hri_tc_ctrla_reg_t ctrl_a;
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hri_tc_evctrl_reg_t event_ctrl;
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hri_tc_dbgctrl_reg_t dbg_ctrl;
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hri_tccount8_per_reg_t per;
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hri_tccount32_cc_reg_t cc0;
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hri_tccount32_cc_reg_t cc1;
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};
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/**
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* \brief Array of TC configurations
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*/
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static struct tc_configuration _tcs[] = {
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#if CONF_TC0_ENABLE == 1
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TC_CONFIGURATION(0),
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#endif
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#if CONF_TC1_ENABLE == 1
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TC_CONFIGURATION(1),
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#endif
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#if CONF_TC2_ENABLE == 1
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TC_CONFIGURATION(2),
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#endif
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#if CONF_TC3_ENABLE == 1
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TC_CONFIGURATION(3),
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#endif
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#if CONF_TC4_ENABLE == 1
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TC_CONFIGURATION(4),
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#endif
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#if CONF_TC5_ENABLE == 1
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TC_CONFIGURATION(5),
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#endif
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#if CONF_TC6_ENABLE == 1
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TC_CONFIGURATION(6),
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#endif
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#if CONF_TC7_ENABLE == 1
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TC_CONFIGURATION(7),
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#endif
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};
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static struct _timer_device *_tc0_dev = NULL;
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static int8_t get_tc_index(const void *const hw);
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static void _tc_init_irq_param(const void *const hw, void *dev);
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static inline uint8_t _get_hardware_offset(const void *const hw);
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/**
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* \brief Initialize TC
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*/
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int32_t _timer_init(struct _timer_device *const device, void *const hw)
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{
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int8_t i = get_tc_index(hw);
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device->hw = hw;
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ASSERT(ARRAY_SIZE(_tcs));
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if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) {
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if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) {
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hri_tc_clear_CTRLA_ENABLE_bit(hw);
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hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE);
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}
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hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST);
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}
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hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
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hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a);
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hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl);
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hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl);
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hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MFRQ);
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if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
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hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0);
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hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
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} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) {
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hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0);
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hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1);
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} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) {
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hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0);
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hri_tccount8_write_CC_reg(hw, 1, (uint8_t)_tcs[i].cc1);
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hri_tccount8_write_PER_reg(hw, _tcs[i].per);
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}
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hri_tc_set_INTEN_OVF_bit(hw);
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_tc_init_irq_param(hw, (void *)device);
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NVIC_DisableIRQ(_tcs[i].irq);
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NVIC_ClearPendingIRQ(_tcs[i].irq);
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NVIC_EnableIRQ(_tcs[i].irq);
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return ERR_NONE;
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}
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/**
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* \brief De-initialize TC
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*/
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void _timer_deinit(struct _timer_device *const device)
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{
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void *const hw = device->hw;
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int8_t i = get_tc_index(hw);
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ASSERT(ARRAY_SIZE(_tcs));
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NVIC_DisableIRQ(_tcs[i].irq);
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hri_tc_clear_CTRLA_ENABLE_bit(hw);
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hri_tc_set_CTRLA_SWRST_bit(hw);
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}
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/**
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* \brief Start hardware timer
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*/
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void _timer_start(struct _timer_device *const device)
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{
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hri_tc_set_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Stop hardware timer
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*/
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void _timer_stop(struct _timer_device *const device)
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{
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hri_tc_clear_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Set timer period
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*/
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void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles)
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{
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void *const hw = device->hw;
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if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
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hri_tccount32_write_CC_reg(hw, 0, clock_cycles);
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} else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
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hri_tccount16_write_CC_reg(hw, 0, (uint16_t)clock_cycles);
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} else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
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hri_tccount8_write_PER_reg(hw, clock_cycles);
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}
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}
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/**
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* \brief Retrieve timer period
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*/
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uint32_t _timer_get_period(const struct _timer_device *const device)
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{
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void *const hw = device->hw;
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if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
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return hri_tccount32_read_CC_reg(hw, 0);
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} else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
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return hri_tccount16_read_CC_reg(hw, 0);
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} else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) {
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return hri_tccount8_read_PER_reg(hw);
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}
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return 0;
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}
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/**
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* \brief Check if timer is running
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*/
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bool _timer_is_started(const struct _timer_device *const device)
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{
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return hri_tc_get_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Retrieve timer helper functions
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*/
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struct _timer_hpl_interface *_tc_get_timer(void)
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{
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return NULL;
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}
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/**
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* \brief Retrieve pwm helper functions
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*/
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struct _pwm_hpl_interface *_tc_get_pwm(void)
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{
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return NULL;
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}
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/**
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* \brief Set timer IRQ
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*
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* \param[in] hw The pointer to hardware instance
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*/
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void _timer_set_irq(struct _timer_device *const device)
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{
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void *const hw = device->hw;
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int8_t i = get_tc_index(hw);
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ASSERT(ARRAY_SIZE(_tcs));
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_irq_set(_tcs[i].irq);
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}
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/**
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* \internal TC interrupt handler for Timer
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*
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* \param[in] instance TC instance number
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*/
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static void tc_interrupt_handler(struct _timer_device *device)
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{
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void *const hw = device->hw;
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if (hri_tc_get_interrupt_OVF_bit(hw)) {
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hri_tc_clear_interrupt_OVF_bit(hw);
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device->timer_cb.period_expired(device);
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}
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}
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/**
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* \brief TC interrupt handler
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*/
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void TC0_Handler(void)
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{
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tc_interrupt_handler(_tc0_dev);
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}
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/**
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* \internal Retrieve TC index
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*
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* \param[in] hw The pointer to hardware instance
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*
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* \return The index of TC configuration
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*/
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static int8_t get_tc_index(const void *const hw)
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{
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uint8_t index = _get_hardware_offset(hw);
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uint8_t i;
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for (i = 0; i < ARRAY_SIZE(_tcs); i++) {
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if (_tcs[i].number == index) {
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return i;
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}
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}
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ASSERT(false);
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return -1;
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}
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/**
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* \brief Init irq param with the given tc hardware instance
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*/
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static void _tc_init_irq_param(const void *const hw, void *dev)
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{
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if (hw == TC0) {
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_tc0_dev = (struct _timer_device *)dev;
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}
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}
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/**
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* \internal Retrieve TC hardware index
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*
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* \param[in] hw The pointer to hardware instance
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*/
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static inline uint8_t _get_hardware_offset(const void *const hw)
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{
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/* List of available TC modules. */
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Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
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/* Find index for TC instance. */
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for (uint32_t i = 0; i < TC_INST_NUM; i++) {
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if ((uint32_t)hw == (uint32_t)tc_modules[i]) {
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return i;
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}
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}
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return 0;
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}
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