init
adragott
4 years ago
commit
66011ce043
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@ -0,0 +1 @@
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src/*
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@ -0,0 +1,511 @@
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################################################################################
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# Automatically-generated file. Do not edit!
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################################################################################
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SHELL := cmd.exe
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RM := rm -rf
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USER_OBJS :=
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LIBS :=
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PROJ :=
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O_SRCS :=
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C_SRCS :=
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S_SRCS :=
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S_UPPER_SRCS :=
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OBJ_SRCS :=
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ASM_SRCS :=
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PREPROCESSING_SRCS :=
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OBJS :=
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OBJS_AS_ARGS :=
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C_DEPS :=
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C_DEPS_AS_ARGS :=
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EXECUTABLES :=
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OUTPUT_FILE_PATH :=
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OUTPUT_FILE_PATH_AS_ARGS :=
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AVR_APP_PATH :=$$$AVR_APP_PATH$$$
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QUOTE := "
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ADDITIONAL_DEPENDENCIES:=
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OUTPUT_FILE_DEP:=
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LIB_DEP:=
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LINKER_SCRIPT_DEP:=
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# Every subdirectory with source files must be described here
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SUBDIRS := \
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../src/ \
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../src/ASF/ \
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../src/ASF/common2/ \
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../src/ASF/common2/services/ \
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../src/ASF/common2/services/delay/ \
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../src/ASF/common2/services/delay/sam0/ \
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../src/ASF/common/ \
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../src/ASF/common/boards/ \
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../src/ASF/common/utils/ \
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../src/ASF/common/utils/interrupt/ \
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../src/ASF/sam0/ \
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../src/ASF/sam0/boards/ \
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../src/ASF/sam0/boards/samd21_xplained_pro/ \
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../src/ASF/sam0/drivers/ \
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../src/ASF/sam0/drivers/adc/ \
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../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/ \
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../src/ASF/sam0/drivers/extint/ \
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../src/ASF/sam0/drivers/extint/extint_sam_d_r_h/ \
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../src/ASF/sam0/drivers/port/ \
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../src/ASF/sam0/drivers/port/quick_start/ \
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../src/ASF/sam0/drivers/sercom/ \
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../src/ASF/sam0/drivers/sercom/usart/ \
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../src/ASF/sam0/drivers/sercom/usart/quick_start/ \
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../src/ASF/sam0/drivers/sercom/usart/quick_start_callback/ \
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../src/ASF/sam0/drivers/sercom/usart/quick_start_dma/ \
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../src/ASF/sam0/drivers/sercom/usart/quick_start_lin/ \
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../src/ASF/sam0/drivers/system/ \
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../src/ASF/sam0/drivers/system/clock/ \
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../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/ \
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../src/ASF/sam0/drivers/system/interrupt/ \
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../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/ \
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../src/ASF/sam0/drivers/system/pinmux/ \
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../src/ASF/sam0/drivers/system/pinmux/quick_start/ \
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../src/ASF/sam0/drivers/system/power/ \
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../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/ \
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../src/ASF/sam0/drivers/system/reset/ \
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../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/ \
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../src/ASF/sam0/drivers/tcc/ \
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../src/ASF/sam0/drivers/tcc/quick_start/ \
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../src/ASF/sam0/drivers/tcc/quick_start_buffering/ \
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../src/ASF/sam0/drivers/tcc/quick_start_callback/ \
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../src/ASF/sam0/drivers/tcc/quick_start_dma/ \
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../src/ASF/sam0/drivers/tcc/quick_start_faultn/ \
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../src/ASF/sam0/drivers/tcc/quick_start_faultx/ \
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../src/ASF/sam0/drivers/tcc/quick_start_timer/ \
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../src/ASF/sam0/utils/ \
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../src/ASF/sam0/utils/cmsis/ \
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../src/ASF/sam0/utils/cmsis/samd21/ \
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../src/ASF/sam0/utils/cmsis/samd21/include/ \
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../src/ASF/sam0/utils/cmsis/samd21/include/component/ \
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../src/ASF/sam0/utils/cmsis/samd21/include/instance/ \
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../src/ASF/sam0/utils/cmsis/samd21/include/pio/ \
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../src/ASF/sam0/utils/cmsis/samd21/source/ \
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../src/ASF/sam0/utils/cmsis/samd21/source/gcc/ \
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../src/ASF/sam0/utils/header_files/ \
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../src/ASF/sam0/utils/linker_scripts/ \
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../src/ASF/sam0/utils/linker_scripts/samd21/ \
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../src/ASF/sam0/utils/linker_scripts/samd21/gcc/ \
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../src/ASF/sam0/utils/make/ \
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../src/ASF/sam0/utils/preprocessor/ \
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../src/ASF/sam0/utils/syscalls/ \
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../src/ASF/sam0/utils/syscalls/gcc/ \
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../src/ASF/thirdparty/ \
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../src/ASF/thirdparty/CMSIS/ \
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../src/ASF/thirdparty/CMSIS/Include/ \
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../src/ASF/thirdparty/CMSIS/Lib/ \
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../src/ASF/thirdparty/CMSIS/Lib/GCC/ \
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../src/config/ \
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../src/drivers \
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../src/devices
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# Add inputs and outputs from these tool invocations to the build variables
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C_SRCS += \
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../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c \
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../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.c \
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../src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.c \
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../src/ASF/sam0/drivers/sercom/sercom.c \
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../src/devices/motor.c \
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../src/drivers/p_adc.c \
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../src/ASF/sam0/drivers/tcc/tcc.c \
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../src/ASF/sam0/drivers/tcc/tcc_callback.c \
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../src/drivers/p_io.c \
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../src/drivers/p_usart.c \
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../src/ASF/sam0/drivers/sercom/usart/usart.c \
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../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c \
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../src/ASF/sam0/drivers/sercom/sercom_interrupt.c \
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../src/ASF/sam0/drivers/extint/extint_callback.c \
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../src/ASF/common2/services/delay/sam0/systick_counter.c \
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../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \
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../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c \
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../src/ASF/sam0/drivers/port/port.c \
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../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c \
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../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c \
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../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c \
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../src/ASF/sam0/drivers/system/pinmux/pinmux.c \
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../src/ASF/sam0/drivers/system/system.c \
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../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c \
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../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c \
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../src/ASF/sam0/utils/syscalls/gcc/syscalls.c \
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../src/main.c
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PREPROCESSING_SRCS +=
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ASM_SRCS +=
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OBJS += \
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src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
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src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.o \
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src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.o \
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src/ASF/sam0/drivers/sercom/sercom.o \
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src/devices/motor.o \
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src/drivers/p_adc.o \
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src/ASF/sam0/drivers/tcc/tcc.o \
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src/ASF/sam0/drivers/tcc/tcc_callback.o \
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src/drivers/p_io.o \
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src/drivers/p_usart.o \
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src/ASF/sam0/drivers/sercom/usart/usart.o \
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src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
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src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
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src/ASF/sam0/drivers/extint/extint_callback.o \
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src/ASF/common2/services/delay/sam0/systick_counter.o \
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src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
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src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
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src/ASF/sam0/drivers/port/port.o \
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src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
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src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
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src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
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src/ASF/sam0/drivers/system/pinmux/pinmux.o \
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src/ASF/sam0/drivers/system/system.o \
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src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
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src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
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src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
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src/main.o
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OBJS_AS_ARGS += \
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src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
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src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.o \
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src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.o \
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src/ASF/sam0/drivers/sercom/sercom.o \
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src/devices/motor.o \
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src/drivers/p_adc.o \
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src/ASF/sam0/drivers/tcc/tcc.o \
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src/ASF/sam0/drivers/tcc/tcc_callback.o \
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src/drivers/p_io.o \
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src/drivers/p_usart.o \
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src/ASF/sam0/drivers/sercom/usart/usart.o \
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src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
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src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
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src/ASF/sam0/drivers/extint/extint_callback.o \
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src/ASF/common2/services/delay/sam0/systick_counter.o \
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src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
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src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
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src/ASF/sam0/drivers/port/port.o \
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src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
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src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
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src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
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src/ASF/sam0/drivers/system/pinmux/pinmux.o \
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src/ASF/sam0/drivers/system/system.o \
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src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
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src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
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src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
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src/main.o
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C_DEPS += \
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src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
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src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.d \
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src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.d \
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src/ASF/sam0/drivers/sercom/sercom.d \
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src/devices/motor.d \
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src/drivers/p_adc.d \
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||||
src/ASF/sam0/drivers/tcc/tcc.d \
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||||
src/ASF/sam0/drivers/tcc/tcc_callback.d \
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||||
src/drivers/p_io.d \
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src/drivers/p_usart.d \
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||||
src/ASF/sam0/drivers/sercom/usart/usart.d \
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||||
src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
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||||
src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
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||||
src/ASF/sam0/drivers/extint/extint_callback.d \
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||||
src/ASF/common2/services/delay/sam0/systick_counter.d \
|
||||
src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
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||||
src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
|
||||
src/ASF/sam0/drivers/port/port.d \
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
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||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
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src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
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src/ASF/sam0/drivers/system/pinmux/pinmux.d \
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||||
src/ASF/sam0/drivers/system/system.d \
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||||
src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
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||||
src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
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||||
src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
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src/main.d
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C_DEPS_AS_ARGS += \
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src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
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||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.d \
|
||||
src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.d \
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||||
src/ASF/sam0/drivers/sercom/sercom.d \
|
||||
src/devices/motor.d \
|
||||
src/drivers/p_adc.d \
|
||||
src/ASF/sam0/drivers/tcc/tcc.d \
|
||||
src/ASF/sam0/drivers/tcc/tcc_callback.d \
|
||||
src/drivers/p_io.d \
|
||||
src/drivers/p_usart.d \
|
||||
src/ASF/sam0/drivers/sercom/usart/usart.d \
|
||||
src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
|
||||
src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
|
||||
src/ASF/sam0/drivers/extint/extint_callback.d \
|
||||
src/ASF/common2/services/delay/sam0/systick_counter.d \
|
||||
src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
|
||||
src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
|
||||
src/ASF/sam0/drivers/port/port.d \
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
|
||||
src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
|
||||
src/ASF/sam0/drivers/system/pinmux/pinmux.d \
|
||||
src/ASF/sam0/drivers/system/system.d \
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
|
||||
src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
|
||||
src/main.d
|
||||
|
||||
OUTPUT_FILE_PATH +=ePenguin-Boaty-Testbed.elf
|
||||
|
||||
OUTPUT_FILE_PATH_AS_ARGS +=ePenguin-Boaty-Testbed.elf
|
||||
|
||||
ADDITIONAL_DEPENDENCIES:=
|
||||
|
||||
OUTPUT_FILE_DEP:= ./makedep.mk
|
||||
|
||||
LIB_DEP+=
|
||||
|
||||
LINKER_SCRIPT_DEP+= \
|
||||
../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
|
||||
|
||||
|
||||
# AVR32/GNU C Compiler
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o: ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.o: ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.o: ../src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/sercom/sercom.o: ../src/ASF/sam0/drivers/sercom/sercom.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/devices/motor.o: ../src/devices/motor.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/drivers/p_adc.o: ../src/drivers/p_adc.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/tcc/tcc.o: ../src/ASF/sam0/drivers/tcc/tcc.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/tcc/tcc_callback.o: ../src/ASF/sam0/drivers/tcc/tcc_callback.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/drivers/p_io.o: ../src/drivers/p_io.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/drivers/p_usart.o: ../src/drivers/p_usart.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/sercom/usart/usart.o: ../src/ASF/sam0/drivers/sercom/usart/usart.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o: ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/sercom/sercom_interrupt.o: ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/extint/extint_callback.o: ../src/ASF/sam0/drivers/extint/extint_callback.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/common2/services/delay/sam0/systick_counter.o: ../src/ASF/common2/services/delay/sam0/systick_counter.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/boards/samd21_xplained_pro/board_init.o: ../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/port/port.o: ../src/ASF/sam0/drivers/port/port.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/system/interrupt/system_interrupt.o: ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/system/pinmux/pinmux.o: ../src/ASF/sam0/drivers/system/pinmux/pinmux.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/system/system.o: ../src/ASF/sam0/drivers/system/system.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/utils/syscalls/gcc/syscalls.o: ../src/ASF/sam0/utils/syscalls/gcc/syscalls.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/main.o: ../src/main.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/devices" -I"../src/drivers" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
# AVR32/GNU Preprocessing Assembler
|
||||
|
||||
|
||||
|
||||
# AVR32/GNU Assembler
|
||||
|
||||
|
||||
|
||||
|
||||
ifneq ($(MAKECMDGOALS),clean)
|
||||
ifneq ($(strip $(C_DEPS)),)
|
||||
-include $(C_DEPS)
|
||||
endif
|
||||
endif
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
|
||||
# All Target
|
||||
all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
|
||||
|
||||
$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
|
||||
@echo Building target: $@
|
||||
@echo Invoking: ARM/GNU Linker : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="ePenguin-Boaty-Testbed.map" -Wl,--start-group -larm_cortexM0l_math -lm -Wl,--end-group -L"../src/ASF/thirdparty/CMSIS/Lib/GCC" -Wl,--gc-sections -mcpu=cortex-m0plus -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
|
||||
@echo Finished building target: $@
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O binary "ePenguin-Boaty-Testbed.elf" "ePenguin-Boaty-Testbed.bin"
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature "ePenguin-Boaty-Testbed.elf" "ePenguin-Boaty-Testbed.hex"
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O binary "ePenguin-Boaty-Testbed.elf" "ePenguin-Boaty-Testbed.eep" || exit 0
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objdump.exe" -h -S "ePenguin-Boaty-Testbed.elf" > "ePenguin-Boaty-Testbed.lss"
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature "ePenguin-Boaty-Testbed.elf" "ePenguin-Boaty-Testbed.srec"
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-size.exe" "ePenguin-Boaty-Testbed.elf"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
# Other Targets
|
||||
clean:
|
||||
-$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)
|
||||
-$(RM) $(C_DEPS_AS_ARGS)
|
||||
rm -rf "ePenguin-Boaty-Testbed.elf" "ePenguin-Boaty-Testbed.a" "ePenguin-Boaty-Testbed.hex" "ePenguin-Boaty-Testbed.bin" "ePenguin-Boaty-Testbed.lss" "ePenguin-Boaty-Testbed.eep" "ePenguin-Boaty-Testbed.map" "ePenguin-Boaty-Testbed.srec"
|
||||
|
||||
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,58 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit or delete the file
|
||||
################################################################################
|
||||
|
||||
src\ASF\sam0\drivers\adc\adc_sam_d_r_h\adc.c
|
||||
|
||||
src\ASF\sam0\drivers\adc\adc_sam_d_r_h\adc_callback.c
|
||||
|
||||
src\ASF\sam0\drivers\extint\extint_sam_d_r_h\extint.c
|
||||
|
||||
src\ASF\sam0\drivers\sercom\sercom.c
|
||||
|
||||
src\devices\motor.c
|
||||
|
||||
src\drivers\p_adc.c
|
||||
|
||||
src\ASF\sam0\drivers\tcc\tcc.c
|
||||
|
||||
src\ASF\sam0\drivers\tcc\tcc_callback.c
|
||||
|
||||
src\drivers\p_io.c
|
||||
|
||||
src\drivers\p_usart.c
|
||||
|
||||
src\ASF\sam0\drivers\sercom\usart\usart.c
|
||||
|
||||
src\ASF\sam0\drivers\sercom\usart\usart_interrupt.c
|
||||
|
||||
src\ASF\sam0\drivers\sercom\sercom_interrupt.c
|
||||
|
||||
src\ASF\sam0\drivers\extint\extint_callback.c
|
||||
|
||||
src\ASF\common2\services\delay\sam0\systick_counter.c
|
||||
|
||||
src\ASF\common\utils\interrupt\interrupt_sam_nvic.c
|
||||
|
||||
src\ASF\sam0\boards\samd21_xplained_pro\board_init.c
|
||||
|
||||
src\ASF\sam0\drivers\port\port.c
|
||||
|
||||
src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\clock.c
|
||||
|
||||
src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\gclk.c
|
||||
|
||||
src\ASF\sam0\drivers\system\interrupt\system_interrupt.c
|
||||
|
||||
src\ASF\sam0\drivers\system\pinmux\pinmux.c
|
||||
|
||||
src\ASF\sam0\drivers\system\system.c
|
||||
|
||||
src\ASF\sam0\utils\cmsis\samd21\source\gcc\startup_samd21.c
|
||||
|
||||
src\ASF\sam0\utils\cmsis\samd21\source\system_samd21.c
|
||||
|
||||
src\ASF\sam0\utils\syscalls\gcc\syscalls.c
|
||||
|
||||
src\main.c
|
||||
|
||||
@ -0,0 +1 @@
|
||||
src/*
|
||||
@ -0,0 +1,499 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
SHELL := cmd.exe
|
||||
RM := rm -rf
|
||||
|
||||
USER_OBJS :=
|
||||
|
||||
LIBS :=
|
||||
PROJ :=
|
||||
|
||||
O_SRCS :=
|
||||
C_SRCS :=
|
||||
S_SRCS :=
|
||||
S_UPPER_SRCS :=
|
||||
OBJ_SRCS :=
|
||||
ASM_SRCS :=
|
||||
PREPROCESSING_SRCS :=
|
||||
OBJS :=
|
||||
OBJS_AS_ARGS :=
|
||||
C_DEPS :=
|
||||
C_DEPS_AS_ARGS :=
|
||||
EXECUTABLES :=
|
||||
OUTPUT_FILE_PATH :=
|
||||
OUTPUT_FILE_PATH_AS_ARGS :=
|
||||
AVR_APP_PATH :=$$$AVR_APP_PATH$$$
|
||||
QUOTE := "
|
||||
ADDITIONAL_DEPENDENCIES:=
|
||||
OUTPUT_FILE_DEP:=
|
||||
LIB_DEP:=
|
||||
LINKER_SCRIPT_DEP:=
|
||||
|
||||
# Every subdirectory with source files must be described here
|
||||
SUBDIRS := \
|
||||
../src/ \
|
||||
../src/ASF/ \
|
||||
../src/ASF/common2/ \
|
||||
../src/ASF/common2/services/ \
|
||||
../src/ASF/common2/services/delay/ \
|
||||
../src/ASF/common2/services/delay/sam0/ \
|
||||
../src/ASF/common/ \
|
||||
../src/ASF/common/boards/ \
|
||||
../src/ASF/common/utils/ \
|
||||
../src/ASF/common/utils/interrupt/ \
|
||||
../src/ASF/sam0/ \
|
||||
../src/ASF/sam0/boards/ \
|
||||
../src/ASF/sam0/boards/samd21_xplained_pro/ \
|
||||
../src/ASF/sam0/drivers/ \
|
||||
../src/ASF/sam0/drivers/adc/ \
|
||||
../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/ \
|
||||
../src/ASF/sam0/drivers/extint/ \
|
||||
../src/ASF/sam0/drivers/extint/extint_sam_d_r_h/ \
|
||||
../src/ASF/sam0/drivers/port/ \
|
||||
../src/ASF/sam0/drivers/port/quick_start/ \
|
||||
../src/ASF/sam0/drivers/sercom/ \
|
||||
../src/ASF/sam0/drivers/sercom/usart/ \
|
||||
../src/ASF/sam0/drivers/sercom/usart/quick_start/ \
|
||||
../src/ASF/sam0/drivers/sercom/usart/quick_start_callback/ \
|
||||
../src/ASF/sam0/drivers/sercom/usart/quick_start_dma/ \
|
||||
../src/ASF/sam0/drivers/sercom/usart/quick_start_lin/ \
|
||||
../src/ASF/sam0/drivers/system/ \
|
||||
../src/ASF/sam0/drivers/system/clock/ \
|
||||
../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/ \
|
||||
../src/ASF/sam0/drivers/system/interrupt/ \
|
||||
../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/ \
|
||||
../src/ASF/sam0/drivers/system/pinmux/ \
|
||||
../src/ASF/sam0/drivers/system/pinmux/quick_start/ \
|
||||
../src/ASF/sam0/drivers/system/power/ \
|
||||
../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/ \
|
||||
../src/ASF/sam0/drivers/system/reset/ \
|
||||
../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/ \
|
||||
../src/ASF/sam0/drivers/tcc/ \
|
||||
../src/ASF/sam0/drivers/tcc/quick_start/ \
|
||||
../src/ASF/sam0/drivers/tcc/quick_start_buffering/ \
|
||||
../src/ASF/sam0/drivers/tcc/quick_start_callback/ \
|
||||
../src/ASF/sam0/drivers/tcc/quick_start_dma/ \
|
||||
../src/ASF/sam0/drivers/tcc/quick_start_faultn/ \
|
||||
../src/ASF/sam0/drivers/tcc/quick_start_faultx/ \
|
||||
../src/ASF/sam0/drivers/tcc/quick_start_timer/ \
|
||||
../src/ASF/sam0/utils/ \
|
||||
../src/ASF/sam0/utils/cmsis/ \
|
||||
../src/ASF/sam0/utils/cmsis/samd21/ \
|
||||
../src/ASF/sam0/utils/cmsis/samd21/include/ \
|
||||
../src/ASF/sam0/utils/cmsis/samd21/include/component/ \
|
||||
../src/ASF/sam0/utils/cmsis/samd21/include/instance/ \
|
||||
../src/ASF/sam0/utils/cmsis/samd21/include/pio/ \
|
||||
../src/ASF/sam0/utils/cmsis/samd21/source/ \
|
||||
../src/ASF/sam0/utils/cmsis/samd21/source/gcc/ \
|
||||
../src/ASF/sam0/utils/header_files/ \
|
||||
../src/ASF/sam0/utils/linker_scripts/ \
|
||||
../src/ASF/sam0/utils/linker_scripts/samd21/ \
|
||||
../src/ASF/sam0/utils/linker_scripts/samd21/gcc/ \
|
||||
../src/ASF/sam0/utils/make/ \
|
||||
../src/ASF/sam0/utils/preprocessor/ \
|
||||
../src/ASF/sam0/utils/syscalls/ \
|
||||
../src/ASF/sam0/utils/syscalls/gcc/ \
|
||||
../src/ASF/thirdparty/ \
|
||||
../src/ASF/thirdparty/CMSIS/ \
|
||||
../src/ASF/thirdparty/CMSIS/Include/ \
|
||||
../src/ASF/thirdparty/CMSIS/Lib/ \
|
||||
../src/ASF/thirdparty/CMSIS/Lib/GCC/ \
|
||||
../src/config/ \
|
||||
../src/drivers \
|
||||
../src/devices
|
||||
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c \
|
||||
../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.c \
|
||||
../src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.c \
|
||||
../src/ASF/sam0/drivers/sercom/sercom.c \
|
||||
../src/drivers/p_adc.c \
|
||||
../src/ASF/sam0/drivers/tcc/tcc.c \
|
||||
../src/ASF/sam0/drivers/tcc/tcc_callback.c \
|
||||
../src/drivers/p_io.c \
|
||||
../src/drivers/p_usart.c \
|
||||
../src/ASF/sam0/drivers/sercom/usart/usart.c \
|
||||
../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c \
|
||||
../src/ASF/sam0/drivers/sercom/sercom_interrupt.c \
|
||||
../src/ASF/sam0/drivers/extint/extint_callback.c \
|
||||
../src/ASF/common2/services/delay/sam0/systick_counter.c \
|
||||
../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \
|
||||
../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c \
|
||||
../src/ASF/sam0/drivers/port/port.c \
|
||||
../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c \
|
||||
../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c \
|
||||
../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c \
|
||||
../src/ASF/sam0/drivers/system/pinmux/pinmux.c \
|
||||
../src/ASF/sam0/drivers/system/system.c \
|
||||
../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c \
|
||||
../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c \
|
||||
../src/ASF/sam0/utils/syscalls/gcc/syscalls.c \
|
||||
../src/main.c
|
||||
|
||||
|
||||
PREPROCESSING_SRCS +=
|
||||
|
||||
|
||||
ASM_SRCS +=
|
||||
|
||||
|
||||
OBJS += \
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.o \
|
||||
src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.o \
|
||||
src/ASF/sam0/drivers/sercom/sercom.o \
|
||||
src/drivers/p_adc.o \
|
||||
src/ASF/sam0/drivers/tcc/tcc.o \
|
||||
src/ASF/sam0/drivers/tcc/tcc_callback.o \
|
||||
src/drivers/p_io.o \
|
||||
src/drivers/p_usart.o \
|
||||
src/ASF/sam0/drivers/sercom/usart/usart.o \
|
||||
src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
|
||||
src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
|
||||
src/ASF/sam0/drivers/extint/extint_callback.o \
|
||||
src/ASF/common2/services/delay/sam0/systick_counter.o \
|
||||
src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
|
||||
src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
|
||||
src/ASF/sam0/drivers/port/port.o \
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
|
||||
src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
|
||||
src/ASF/sam0/drivers/system/pinmux/pinmux.o \
|
||||
src/ASF/sam0/drivers/system/system.o \
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
|
||||
src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
|
||||
src/main.o
|
||||
|
||||
OBJS_AS_ARGS += \
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.o \
|
||||
src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.o \
|
||||
src/ASF/sam0/drivers/sercom/sercom.o \
|
||||
src/drivers/p_adc.o \
|
||||
src/ASF/sam0/drivers/tcc/tcc.o \
|
||||
src/ASF/sam0/drivers/tcc/tcc_callback.o \
|
||||
src/drivers/p_io.o \
|
||||
src/drivers/p_usart.o \
|
||||
src/ASF/sam0/drivers/sercom/usart/usart.o \
|
||||
src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
|
||||
src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
|
||||
src/ASF/sam0/drivers/extint/extint_callback.o \
|
||||
src/ASF/common2/services/delay/sam0/systick_counter.o \
|
||||
src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
|
||||
src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
|
||||
src/ASF/sam0/drivers/port/port.o \
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
|
||||
src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
|
||||
src/ASF/sam0/drivers/system/pinmux/pinmux.o \
|
||||
src/ASF/sam0/drivers/system/system.o \
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
|
||||
src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
|
||||
src/main.o
|
||||
|
||||
C_DEPS += \
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.d \
|
||||
src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.d \
|
||||
src/ASF/sam0/drivers/sercom/sercom.d \
|
||||
src/drivers/p_adc.d \
|
||||
src/ASF/sam0/drivers/tcc/tcc.d \
|
||||
src/ASF/sam0/drivers/tcc/tcc_callback.d \
|
||||
src/drivers/p_io.d \
|
||||
src/drivers/p_usart.d \
|
||||
src/ASF/sam0/drivers/sercom/usart/usart.d \
|
||||
src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
|
||||
src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
|
||||
src/ASF/sam0/drivers/extint/extint_callback.d \
|
||||
src/ASF/common2/services/delay/sam0/systick_counter.d \
|
||||
src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
|
||||
src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
|
||||
src/ASF/sam0/drivers/port/port.d \
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
|
||||
src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
|
||||
src/ASF/sam0/drivers/system/pinmux/pinmux.d \
|
||||
src/ASF/sam0/drivers/system/system.d \
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
|
||||
src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
|
||||
src/main.d
|
||||
|
||||
C_DEPS_AS_ARGS += \
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.d \
|
||||
src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.d \
|
||||
src/ASF/sam0/drivers/sercom/sercom.d \
|
||||
src/drivers/p_adc.d \
|
||||
src/ASF/sam0/drivers/tcc/tcc.d \
|
||||
src/ASF/sam0/drivers/tcc/tcc_callback.d \
|
||||
src/drivers/p_io.d \
|
||||
src/drivers/p_usart.d \
|
||||
src/ASF/sam0/drivers/sercom/usart/usart.d \
|
||||
src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
|
||||
src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
|
||||
src/ASF/sam0/drivers/extint/extint_callback.d \
|
||||
src/ASF/common2/services/delay/sam0/systick_counter.d \
|
||||
src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
|
||||
src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
|
||||
src/ASF/sam0/drivers/port/port.d \
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
|
||||
src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
|
||||
src/ASF/sam0/drivers/system/pinmux/pinmux.d \
|
||||
src/ASF/sam0/drivers/system/system.d \
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
|
||||
src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
|
||||
src/main.d
|
||||
|
||||
OUTPUT_FILE_PATH +=ePenguin-Boaty-Testbed.elf
|
||||
|
||||
OUTPUT_FILE_PATH_AS_ARGS +=ePenguin-Boaty-Testbed.elf
|
||||
|
||||
ADDITIONAL_DEPENDENCIES:=
|
||||
|
||||
OUTPUT_FILE_DEP:= ./makedep.mk
|
||||
|
||||
LIB_DEP+=
|
||||
|
||||
LINKER_SCRIPT_DEP+= \
|
||||
../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
|
||||
|
||||
|
||||
# AVR32/GNU C Compiler
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o: ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.o: ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.o: ../src/ASF/sam0/drivers/extint/extint_sam_d_r_h/extint.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/sercom/sercom.o: ../src/ASF/sam0/drivers/sercom/sercom.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/drivers/p_adc.o: ../src/drivers/p_adc.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/tcc/tcc.o: ../src/ASF/sam0/drivers/tcc/tcc.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/tcc/tcc_callback.o: ../src/ASF/sam0/drivers/tcc/tcc_callback.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/drivers/p_io.o: ../src/drivers/p_io.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/drivers/p_usart.o: ../src/drivers/p_usart.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/sercom/usart/usart.o: ../src/ASF/sam0/drivers/sercom/usart/usart.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o: ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/sercom/sercom_interrupt.o: ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/extint/extint_callback.o: ../src/ASF/sam0/drivers/extint/extint_callback.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/common2/services/delay/sam0/systick_counter.o: ../src/ASF/common2/services/delay/sam0/systick_counter.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/boards/samd21_xplained_pro/board_init.o: ../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/port/port.o: ../src/ASF/sam0/drivers/port/port.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/system/interrupt/system_interrupt.o: ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/system/pinmux/pinmux.o: ../src/ASF/sam0/drivers/system/pinmux/pinmux.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/drivers/system/system.o: ../src/ASF/sam0/drivers/system/system.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/ASF/sam0/utils/syscalls/gcc/syscalls.o: ../src/ASF/sam0/utils/syscalls/gcc/syscalls.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
src/main.o: ../src/main.c
|
||||
@echo Building file: $<
|
||||
@echo Invoking: ARM/GNU C Compiler : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=true -DEXTINT_CALLBACK_MODE=true -DUSART_CALLBACK_MODE=true -DTCC_ASYNC=true -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/extint" -I"../src/ASF/sam0/drivers/extint/extint_sam_d_r_h" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/ASF/sam0/drivers/tcc" -I"../src/drivers" -I"../src/devices" -Os -fdata-sections -ffunction-sections -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
# AVR32/GNU Preprocessing Assembler
|
||||
|
||||
|
||||
|
||||
# AVR32/GNU Assembler
|
||||
|
||||
|
||||
|
||||
|
||||
ifneq ($(MAKECMDGOALS),clean)
|
||||
ifneq ($(strip $(C_DEPS)),)
|
||||
-include $(C_DEPS)
|
||||
endif
|
||||
endif
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
|
||||
# All Target
|
||||
all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
|
||||
|
||||
$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
|
||||
@echo Building target: $@
|
||||
@echo Invoking: ARM/GNU Linker : 6.3.1
|
||||
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="ePenguin-Boaty-Testbed.map" --specs=nano.specs -Wl,--start-group -larm_cortexM0l_math -lm -Wl,--end-group -L"../src/ASF/thirdparty/CMSIS/Lib/GCC" -Wl,--gc-sections -mcpu=cortex-m0plus -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
|
||||
@echo Finished building target: $@
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O binary "ePenguin-Boaty-Testbed.elf" "ePenguin-Boaty-Testbed.bin"
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature "ePenguin-Boaty-Testbed.elf" "ePenguin-Boaty-Testbed.hex"
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O binary "ePenguin-Boaty-Testbed.elf" "ePenguin-Boaty-Testbed.eep" || exit 0
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objdump.exe" -h -S "ePenguin-Boaty-Testbed.elf" > "ePenguin-Boaty-Testbed.lss"
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature "ePenguin-Boaty-Testbed.elf" "ePenguin-Boaty-Testbed.srec"
|
||||
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-size.exe" "ePenguin-Boaty-Testbed.elf"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
# Other Targets
|
||||
clean:
|
||||
-$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)
|
||||
-$(RM) $(C_DEPS_AS_ARGS)
|
||||
rm -rf "ePenguin-Boaty-Testbed.elf" "ePenguin-Boaty-Testbed.a" "ePenguin-Boaty-Testbed.hex" "ePenguin-Boaty-Testbed.bin" "ePenguin-Boaty-Testbed.lss" "ePenguin-Boaty-Testbed.eep" "ePenguin-Boaty-Testbed.map" "ePenguin-Boaty-Testbed.srec"
|
||||
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
File diff suppressed because it is too large
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,224 @@
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
S9030B29C8
|
||||
@ -0,0 +1,56 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit or delete the file
|
||||
################################################################################
|
||||
|
||||
src\ASF\sam0\drivers\adc\adc_sam_d_r_h\adc.c
|
||||
|
||||
src\ASF\sam0\drivers\adc\adc_sam_d_r_h\adc_callback.c
|
||||
|
||||
src\ASF\sam0\drivers\extint\extint_sam_d_r_h\extint.c
|
||||
|
||||
src\ASF\sam0\drivers\sercom\sercom.c
|
||||
|
||||
src\drivers\p_adc.c
|
||||
|
||||
src\ASF\sam0\drivers\tcc\tcc.c
|
||||
|
||||
src\ASF\sam0\drivers\tcc\tcc_callback.c
|
||||
|
||||
src\drivers\p_io.c
|
||||
|
||||
src\drivers\p_usart.c
|
||||
|
||||
src\ASF\sam0\drivers\sercom\usart\usart.c
|
||||
|
||||
src\ASF\sam0\drivers\sercom\usart\usart_interrupt.c
|
||||
|
||||
src\ASF\sam0\drivers\sercom\sercom_interrupt.c
|
||||
|
||||
src\ASF\sam0\drivers\extint\extint_callback.c
|
||||
|
||||
src\ASF\common2\services\delay\sam0\systick_counter.c
|
||||
|
||||
src\ASF\common\utils\interrupt\interrupt_sam_nvic.c
|
||||
|
||||
src\ASF\sam0\boards\samd21_xplained_pro\board_init.c
|
||||
|
||||
src\ASF\sam0\drivers\port\port.c
|
||||
|
||||
src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\clock.c
|
||||
|
||||
src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\gclk.c
|
||||
|
||||
src\ASF\sam0\drivers\system\interrupt\system_interrupt.c
|
||||
|
||||
src\ASF\sam0\drivers\system\pinmux\pinmux.c
|
||||
|
||||
src\ASF\sam0\drivers\system\system.c
|
||||
|
||||
src\ASF\sam0\utils\cmsis\samd21\source\gcc\startup_samd21.c
|
||||
|
||||
src\ASF\sam0\utils\cmsis\samd21\source\system_samd21.c
|
||||
|
||||
src\ASF\sam0\utils\syscalls\gcc\syscalls.c
|
||||
|
||||
src\main.c
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,450 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Standard board header file.
|
||||
*
|
||||
* This file includes the appropriate board header file according to the
|
||||
* defined board (parameter BOARD).
|
||||
*
|
||||
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
/**
|
||||
* \defgroup group_common_boards Generic board support
|
||||
*
|
||||
* The generic board support module includes board-specific definitions
|
||||
* and function prototypes, such as the board initialization function.
|
||||
*
|
||||
* \{
|
||||
*/
|
||||
|
||||
#include "compiler.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*! \name Base Boards
|
||||
*/
|
||||
//! @{
|
||||
#define EVK1100 1 //!< AT32UC3A EVK1100 board.
|
||||
#define EVK1101 2 //!< AT32UC3B EVK1101 board.
|
||||
#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board.
|
||||
#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.
|
||||
#define EVK1105 5 //!< AT32UC3A EVK1105 board.
|
||||
#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.
|
||||
#define UC3L_EK 7 //!< AT32UC3L-EK board.
|
||||
#define XPLAIN 8 //!< ATxmega128A1 Xplain board.
|
||||
#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.
|
||||
#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.
|
||||
#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.
|
||||
#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.
|
||||
#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.
|
||||
#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.
|
||||
#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.
|
||||
#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.
|
||||
#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
|
||||
#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board.
|
||||
#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board.
|
||||
#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board.
|
||||
#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.
|
||||
#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.
|
||||
#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.
|
||||
#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.
|
||||
#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.
|
||||
#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.
|
||||
#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards.
|
||||
#define RZ600 31 //!< AT32UC3A RZ600 MCU board.
|
||||
#define SAM3S_EK 32 //!< SAM3S-EK board.
|
||||
#define SAM3U_EK 33 //!< SAM3U-EK board.
|
||||
#define SAM3X_EK 34 //!< SAM3X-EK board.
|
||||
#define SAM3N_EK 35 //!< SAM3N-EK board.
|
||||
#define SAM3S_EK2 36 //!< SAM3S-EK2 board.
|
||||
#define SAM4S_EK 37 //!< SAM4S-EK board.
|
||||
#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.
|
||||
#define STK600_MEGA 39 //!< STK600 MEGA board.
|
||||
#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.
|
||||
#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.
|
||||
#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.
|
||||
#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.
|
||||
#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board.
|
||||
#define SAM4L_EK 45 //!< SAM4L-EK board.
|
||||
#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board.
|
||||
#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board.
|
||||
#define STK600_RC032X 48 //!< STK600 with RC032X routing card board.
|
||||
#define SAM4S_EK2 49 //!< SAM4S-EK2 board.
|
||||
#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board.
|
||||
#define SAM4E_EK 51 //!< SAM4E-EK board.
|
||||
#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board.
|
||||
#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board.
|
||||
#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board.
|
||||
#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit.
|
||||
#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit.
|
||||
#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit.
|
||||
#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board.
|
||||
#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board.
|
||||
#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board.
|
||||
#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board.
|
||||
#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board.
|
||||
#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB.
|
||||
#define SAM4C_EK 64 //!< SAM4C-EK board.
|
||||
#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board.
|
||||
#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board.
|
||||
#define SAM4CP16BMB 67 //!< SAM4CP16BMB board.
|
||||
#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board.
|
||||
#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board.
|
||||
#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board.
|
||||
#define SAM4CMP_DB 71 //!< SAM4CMP demo board.
|
||||
#define SAM4CMS_DB 72 //!< SAM4CMS demo board.
|
||||
#define ATPL230AMB 73 //!< ATPL230AMB board.
|
||||
#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board.
|
||||
#define SAMG55_XPLAINED_PRO 75 //!< SAMG55 Xplained Pro board.
|
||||
#define SAML21_XPLAINED_PRO 76 //!< SAM L21 Xplained Pro board.
|
||||
#define SAMD10_XPLAINED_MINI 77 //!< SAM D10 Xplained Mini board.
|
||||
#define SAMDA1_XPLAINED_PRO 78 //!< SAM DA1 Xplained Pro board.
|
||||
#define SAMW25_XPLAINED_PRO 79 //!< SAMW25 Xplained Pro board.
|
||||
#define SAMC21_XPLAINED_PRO 80 //!< SAM C21 Xplained Pro board.
|
||||
#define SAMV71_XPLAINED_ULTRA 81 //!< SAMV71 Xplained Ultra board.
|
||||
#define ATMEGA328P_XPLAINED_MINI 82 //!< ATMEGA328P Xplained MINI board.
|
||||
#define ATMEGA328PB_XPLAINED_MINI 83 //!< ATMEGA328PB Xplained MINI board.
|
||||
#define SAMB11_XPLAINED_PRO 84 //!< SAM B11 Xplained Pro board.
|
||||
#define SAME70_XPLAINED 85 //!< SAME70 Xplained board.
|
||||
#define SAML22_XPLAINED_PRO 86 //!< SAM L22 Xplained Pro board.
|
||||
#define SAML22_XPLAINED_PRO_B 87 //!< SAM L22 Xplained Pro board.
|
||||
#define SAMR21ZLL_EK 88 //!< SAMR21ZLL-EK board.
|
||||
#define ATMEGA168PB_XPLAINED_MINI 89 //!< ATMEGA168PB Xplained MINI board.
|
||||
#define ATMEGA324PB_XPLAINED_PRO 90 //!< ATMEGA324PB Xplained Pro board.
|
||||
#define SAMB11ZR_XPLAINED_PRO 92 //!< SAM B11 ZR Xplained Pro board.
|
||||
#define SAMR30_XPLAINED_PRO 93 //!< SAM R30 Xplained Pro board.
|
||||
#define SAMHA1G16A_XPLAINED_PRO 94 //!< SAM HA1G16A Xplained Pro board.
|
||||
#define SAMR34_XPLAINED_PRO 95 //!< SAM R34 Xplained Pro board.
|
||||
#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices.
|
||||
#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family.
|
||||
#define USER_BOARD 99 //!< User-reserved board (if any).
|
||||
#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader).
|
||||
#define SAMB11ZR_SENSOR_TAG 101 //!< SAMB11ZR sensor tag board
|
||||
#define SAMR30_MODULE_XPLAINED_PRO 102 //!< SAM R30 Module Xplained Pro board.
|
||||
#define SAMR21G18_MODULE 103 //!< SAMR21G18-MR210UA Module.
|
||||
#define SAMR21B18_MODULE 104 //!< SAMR21B18-MZ210PA Module.
|
||||
//! @}
|
||||
|
||||
/*! \name Extension Boards
|
||||
*/
|
||||
//! @{
|
||||
#define EXT1102 1 //!< AT32UC3B EXT1102 board
|
||||
#define MC300 2 //!< AT32UC3 MC300 board
|
||||
#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1
|
||||
#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2
|
||||
#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board
|
||||
#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board
|
||||
#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"
|
||||
#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600
|
||||
#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600
|
||||
#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600
|
||||
#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard
|
||||
#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board
|
||||
#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
|
||||
//! @}
|
||||
|
||||
#if BOARD == EVK1100
|
||||
# include "evk1100/evk1100.h"
|
||||
#elif BOARD == EVK1101
|
||||
# include "evk1101/evk1101.h"
|
||||
#elif BOARD == UC3C_EK
|
||||
# include "uc3c_ek/uc3c_ek.h"
|
||||
#elif BOARD == EVK1104
|
||||
# include "evk1104/evk1104.h"
|
||||
#elif BOARD == EVK1105
|
||||
# include "evk1105/evk1105.h"
|
||||
#elif BOARD == STK600_RCUC3L0
|
||||
# include "stk600/rcuc3l0/stk600_rcuc3l0.h"
|
||||
#elif BOARD == UC3L_EK
|
||||
# include "uc3l_ek/uc3l_ek.h"
|
||||
#elif BOARD == STK600_RCUC3L4
|
||||
# include "stk600/rcuc3l4/stk600_rcuc3l4.h"
|
||||
#elif BOARD == XPLAIN
|
||||
# include "xplain/xplain.h"
|
||||
#elif BOARD == STK600_MEGA
|
||||
/*No header-file to include*/
|
||||
#elif BOARD == STK600_MEGA_RF
|
||||
# include "stk600.h"
|
||||
#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
|
||||
# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
|
||||
#elif BOARD == ATMEGA256RFR2_ZIGBIT
|
||||
# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
|
||||
#elif BOARD == STK600_RC032X
|
||||
# include "stk600/rc032x/stk600_rc032x.h"
|
||||
#elif BOARD == STK600_RC044X
|
||||
# include "stk600/rc044x/stk600_rc044x.h"
|
||||
#elif BOARD == STK600_RC064X
|
||||
# include "stk600/rc064x/stk600_rc064x.h"
|
||||
#elif BOARD == STK600_RC100X
|
||||
# include "stk600/rc100x/stk600_rc100x.h"
|
||||
#elif BOARD == UC3_A3_XPLAINED
|
||||
# include "uc3_a3_xplained/uc3_a3_xplained.h"
|
||||
#elif BOARD == UC3_L0_XPLAINED
|
||||
# include "uc3_l0_xplained/uc3_l0_xplained.h"
|
||||
#elif BOARD == STK600_RCUC3B0
|
||||
# include "stk600/rcuc3b0/stk600_rcuc3b0.h"
|
||||
#elif BOARD == STK600_RCUC3D
|
||||
# include "stk600/rcuc3d/stk600_rcuc3d.h"
|
||||
#elif BOARD == STK600_RCUC3C0
|
||||
# include "stk600/rcuc3c0/stk600_rcuc3c0.h"
|
||||
#elif BOARD == SAMG53_XPLAINED_PRO
|
||||
# include "samg53_xplained_pro/samg53_xplained_pro.h"
|
||||
#elif BOARD == SAMG55_XPLAINED_PRO
|
||||
# include "samg55_xplained_pro/samg55_xplained_pro.h"
|
||||
#elif BOARD == XMEGA_B1_XPLAINED
|
||||
# include "xmega_b1_xplained/xmega_b1_xplained.h"
|
||||
#elif BOARD == STK600_RC064X_LCDX
|
||||
# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
|
||||
#elif BOARD == STK600_RC100X_LCDX
|
||||
# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
|
||||
#elif BOARD == XMEGA_A1_XPLAINED
|
||||
# include "xmega_a1_xplained/xmega_a1_xplained.h"
|
||||
#elif BOARD == XMEGA_A1U_XPLAINED_PRO
|
||||
# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
|
||||
#elif BOARD == UC3_L0_XPLAINED_BC
|
||||
# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
|
||||
#elif BOARD == SAM3S_EK
|
||||
# include "sam3s_ek/sam3s_ek.h"
|
||||
# include "system_sam3s.h"
|
||||
#elif BOARD == SAM3S_EK2
|
||||
# include "sam3s_ek2/sam3s_ek2.h"
|
||||
# include "system_sam3sd8.h"
|
||||
#elif BOARD == SAM3U_EK
|
||||
# include "sam3u_ek/sam3u_ek.h"
|
||||
# include "system_sam3u.h"
|
||||
#elif BOARD == SAM3X_EK
|
||||
# include "sam3x_ek/sam3x_ek.h"
|
||||
# include "system_sam3x.h"
|
||||
#elif BOARD == SAM3N_EK
|
||||
# include "sam3n_ek/sam3n_ek.h"
|
||||
# include "system_sam3n.h"
|
||||
#elif BOARD == SAM4S_EK
|
||||
# include "sam4s_ek/sam4s_ek.h"
|
||||
# include "system_sam4s.h"
|
||||
#elif BOARD == SAM4S_WPIR_RD
|
||||
# include "sam4s_wpir_rd/sam4s_wpir_rd.h"
|
||||
# include "system_sam4s.h"
|
||||
#elif BOARD == SAM4S_XPLAINED
|
||||
# include "sam4s_xplained/sam4s_xplained.h"
|
||||
# include "system_sam4s.h"
|
||||
#elif BOARD == SAM4S_EK2
|
||||
# include "sam4s_ek2/sam4s_ek2.h"
|
||||
# include "system_sam4s.h"
|
||||
#elif BOARD == MEGA_1284P_XPLAINED
|
||||
/*No header-file to include*/
|
||||
#elif BOARD == ARDUINO_DUE_X
|
||||
# include "arduino_due_x/arduino_due_x.h"
|
||||
# include "system_sam3x.h"
|
||||
#elif BOARD == SAM4L_EK
|
||||
# include "sam4l_ek/sam4l_ek.h"
|
||||
#elif BOARD == SAM4E_EK
|
||||
# include "sam4e_ek/sam4e_ek.h"
|
||||
#elif BOARD == SAMD20_XPLAINED_PRO
|
||||
# include "samd20_xplained_pro/samd20_xplained_pro.h"
|
||||
#elif BOARD == SAMD21_XPLAINED_PRO
|
||||
# include "samd21_xplained_pro/samd21_xplained_pro.h"
|
||||
#elif BOARD == SAMR21_XPLAINED_PRO
|
||||
# include "samr21_xplained_pro/samr21_xplained_pro.h"
|
||||
#elif BOARD == SAMR30_XPLAINED_PRO && defined(__SAMR30G18A__)
|
||||
# include "samr30_xplained_pro/samr30_xplained_pro.h"
|
||||
#elif BOARD == SAMR30_MODULE_XPLAINED_PRO && defined(__SAMR30E18A__)
|
||||
# include "samr30_module_xplained_pro/samr30_module_xplained_pro.h"
|
||||
#elif BOARD == SAMR21ZLL_EK
|
||||
# include "samr21zll_ek/samr21zll_ek.h"
|
||||
#elif BOARD == SAMD11_XPLAINED_PRO
|
||||
# include "samd11_xplained_pro/samd11_xplained_pro.h"
|
||||
#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__)
|
||||
# include "saml21_xplained_pro/saml21_xplained_pro.h"
|
||||
#elif BOARD == SAML22_XPLAINED_PRO
|
||||
# include "saml22_xplained_pro/saml22_xplained_pro.h"
|
||||
#elif BOARD == SAML22_XPLAINED_PRO_B
|
||||
# include "saml22_xplained_pro_b/saml22_xplained_pro_b.h"
|
||||
#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__)
|
||||
# include "saml21_xplained_pro_b/saml21_xplained_pro.h"
|
||||
#elif BOARD == SAMD10_XPLAINED_MINI
|
||||
# include "samd10_xplained_mini/samd10_xplained_mini.h"
|
||||
#elif BOARD == SAMDA1_XPLAINED_PRO
|
||||
# include "samda1_xplained_pro/samda1_xplained_pro.h"
|
||||
#elif BOARD == SAMHA1G16A_XPLAINED_PRO
|
||||
# include "samha1g16a_xplained_pro/samha1g16a_xplained_pro.h"
|
||||
#elif BOARD == SAMC21_XPLAINED_PRO
|
||||
# include "samc21_xplained_pro/samc21_xplained_pro.h"
|
||||
#elif BOARD == SAM4N_XPLAINED_PRO
|
||||
# include "sam4n_xplained_pro/sam4n_xplained_pro.h"
|
||||
#elif BOARD == SAMW25_XPLAINED_PRO
|
||||
# include "samw25_xplained_pro/samw25_xplained_pro.h"
|
||||
#elif BOARD == SAMV71_XPLAINED_ULTRA
|
||||
# include "samv71_xplained_ultra/samv71_xplained_ultra.h"
|
||||
#elif BOARD == MEGA1284P_XPLAINED_BC
|
||||
# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
|
||||
#elif BOARD == UC3_L0_QT600
|
||||
# include "uc3_l0_qt600/uc3_l0_qt600.h"
|
||||
#elif BOARD == XMEGA_A3BU_XPLAINED
|
||||
# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
|
||||
#elif BOARD == XMEGA_E5_XPLAINED
|
||||
# include "xmega_e5_xplained/xmega_e5_xplained.h"
|
||||
#elif BOARD == UC3B_BOARD_CONTROLLER
|
||||
# include "uc3b_board_controller/uc3b_board_controller.h"
|
||||
#elif BOARD == RZ600
|
||||
# include "rz600/rz600.h"
|
||||
#elif BOARD == STK600_RCUC3A0
|
||||
# include "stk600/rcuc3a0/stk600_rcuc3a0.h"
|
||||
#elif BOARD == ATXMEGA128A1_QT600
|
||||
# include "atxmega128a1_qt600/atxmega128a1_qt600.h"
|
||||
#elif BOARD == STK600_RCUC3L3
|
||||
# include "stk600/rcuc3l3/stk600_rcuc3l3.h"
|
||||
#elif BOARD == SAM4S_XPLAINED_PRO
|
||||
# include "sam4s_xplained_pro/sam4s_xplained_pro.h"
|
||||
#elif BOARD == SAM4L_XPLAINED_PRO
|
||||
# include "sam4l_xplained_pro/sam4l_xplained_pro.h"
|
||||
#elif BOARD == SAM4L8_XPLAINED_PRO
|
||||
# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
|
||||
#elif BOARD == SAM4C_EK
|
||||
# include "sam4c_ek/sam4c_ek.h"
|
||||
#elif BOARD == SAM4CMP_DB
|
||||
# include "sam4cmp_db/sam4cmp_db.h"
|
||||
#elif BOARD == SAM4CMS_DB
|
||||
# include "sam4cms_db/sam4cms_db.h"
|
||||
#elif BOARD == SAM4CP16BMB
|
||||
# include "sam4cp16bmb/sam4cp16bmb.h"
|
||||
#elif BOARD == ATPL230AMB
|
||||
# include "atpl230amb/atpl230amb.h"
|
||||
#elif BOARD == XMEGA_C3_XPLAINED
|
||||
# include "xmega_c3_xplained/xmega_c3_xplained.h"
|
||||
#elif BOARD == XMEGA_RF233_ZIGBIT
|
||||
# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
|
||||
#elif BOARD == XMEGA_A3_REB_CBB
|
||||
# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
|
||||
#elif BOARD == ATMEGARFX_RCB
|
||||
# include "atmegarfx_rcb/atmegarfx_rcb.h"
|
||||
#elif BOARD == RCB256RFR2_XPRO
|
||||
# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
|
||||
#elif BOARD == XMEGA_RF212B_ZIGBIT
|
||||
# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
|
||||
#elif BOARD == SAM4E_XPLAINED_PRO
|
||||
# include "sam4e_xplained_pro/sam4e_xplained_pro.h"
|
||||
#elif BOARD == ATMEGA328P_XPLAINED_MINI
|
||||
# include "atmega328p_xplained_mini/atmega328p_xplained_mini.h"
|
||||
#elif BOARD == ATMEGA328PB_XPLAINED_MINI
|
||||
# include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h"
|
||||
#elif BOARD == SAMB11_XPLAINED_PRO
|
||||
# include "samb11_xplained_pro/samb11_xplained_pro.h"
|
||||
#elif BOARD == SAME70_XPLAINED
|
||||
# include "same70_xplained/same70_xplained.h"
|
||||
#elif BOARD == ATMEGA168PB_XPLAINED_MINI
|
||||
# include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h"
|
||||
#elif BOARD == ATMEGA324PB_XPLAINED_PRO
|
||||
# include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h"
|
||||
#elif BOARD == SAMB11ZR_XPLAINED_PRO
|
||||
# include "samb11zr_xplained_pro/samb11zr_xplained_pro.h"
|
||||
#elif BOARD == SIMULATOR_XMEGA_A1
|
||||
# include "simulator/xmega_a1/simulator_xmega_a1.h"
|
||||
#elif BOARD == AVR_SIMULATOR_UC3
|
||||
# include "avr_simulator_uc3/avr_simulator_uc3.h"
|
||||
#elif BOARD == SAMR21G18_MODULE
|
||||
# include "samr21g18_module/samr21g18_module.h"
|
||||
#elif BOARD == SAMR21B18_MODULE
|
||||
# include "samr21b18_module/samr21b18_module.h"
|
||||
#elif BOARD == SAMR34_XPLAINED_PRO && defined(__SAMR34J18B__)
|
||||
# include "samr34_xplained_pro/samr34_xplained_pro.h"
|
||||
#elif BOARD == USER_BOARD
|
||||
// User-reserved area: #include the header file of your board here (if any).
|
||||
# include "user_board.h"
|
||||
#elif BOARD == DUMMY_BOARD
|
||||
# include "dummy/dummy_board.h"
|
||||
#elif BOARD == SAMB11ZR_SENSOR_TAG
|
||||
# include "samb11zr_sensor_tag/samb11zr_sensor_tag.h"
|
||||
#else
|
||||
# error No known Atmel board defined
|
||||
#endif
|
||||
|
||||
#if (defined EXT_BOARD)
|
||||
# if EXT_BOARD == MC300
|
||||
# include "mc300/mc300.h"
|
||||
# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
|
||||
(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
|
||||
(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
|
||||
(EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \
|
||||
(EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
|
||||
(EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
|
||||
# include "sensors_xplained/sensors_xplained.h"
|
||||
# elif EXT_BOARD == RZ600_AT86RF231
|
||||
# include "at86rf231/at86rf231.h"
|
||||
# elif EXT_BOARD == RZ600_AT86RF230B
|
||||
# include "at86rf230b/at86rf230b.h"
|
||||
# elif EXT_BOARD == RZ600_AT86RF212
|
||||
# include "at86rf212/at86rf212.h"
|
||||
# elif EXT_BOARD == SECURITY_XPLAINED
|
||||
# include "security_xplained.h"
|
||||
# elif EXT_BOARD == USER_EXT_BOARD
|
||||
// User-reserved area: #include the header file of your extension board here
|
||||
// (if any).
|
||||
# endif
|
||||
#endif
|
||||
|
||||
|
||||
#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
|
||||
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
|
||||
|
||||
/*! \brief This function initializes the board target resources
|
||||
*
|
||||
* This function should be called to ensure proper initialization of the target
|
||||
* board hardware connected to the part.
|
||||
*/
|
||||
extern void board_init(void);
|
||||
|
||||
#endif // #ifdef __AVR32_ABI_COMPILER__
|
||||
#else
|
||||
/*! \brief This function initializes the board target resources
|
||||
*
|
||||
* This function should be called to ensure proper initialization of the target
|
||||
* board hardware connected to the part.
|
||||
*/
|
||||
extern void board_init(void);
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \}
|
||||
*/
|
||||
|
||||
#endif // _BOARD_H_
|
||||
@ -0,0 +1,132 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Global interrupt management for 8- and 32-bit AVR
|
||||
*
|
||||
* Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef UTILS_INTERRUPT_H
|
||||
#define UTILS_INTERRUPT_H
|
||||
|
||||
#include <parts.h>
|
||||
|
||||
#if XMEGA || MEGA
|
||||
# include "interrupt/interrupt_avr8.h"
|
||||
#elif UC3
|
||||
# include "interrupt/interrupt_avr32.h"
|
||||
#elif SAM || SAMB
|
||||
# include "interrupt/interrupt_sam_nvic.h"
|
||||
#else
|
||||
# error Unsupported device.
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \defgroup interrupt_group Global interrupt management
|
||||
*
|
||||
* This is a driver for global enabling and disabling of interrupts.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/**
|
||||
* \def CONFIG_INTERRUPT_FORCE_INTC
|
||||
* \brief Force usage of the ASF INTC driver
|
||||
*
|
||||
* Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
|
||||
* This is useful to ensure compatibility across compilers and shall be used only when required
|
||||
* by the application needs.
|
||||
*/
|
||||
# define CONFIG_INTERRUPT_FORCE_INTC
|
||||
#endif
|
||||
|
||||
//! \name Global interrupt flags
|
||||
//@{
|
||||
/**
|
||||
* \typedef irqflags_t
|
||||
* \brief Type used for holding state of interrupt flag
|
||||
*/
|
||||
|
||||
/**
|
||||
* \def cpu_irq_enable
|
||||
* \brief Enable interrupts globally
|
||||
*/
|
||||
|
||||
/**
|
||||
* \def cpu_irq_disable
|
||||
* \brief Disable interrupts globally
|
||||
*/
|
||||
|
||||
/**
|
||||
* \fn irqflags_t cpu_irq_save(void)
|
||||
* \brief Get and clear the global interrupt flags
|
||||
*
|
||||
* Use in conjunction with \ref cpu_irq_restore.
|
||||
*
|
||||
* \return Current state of interrupt flags.
|
||||
*
|
||||
* \note This function leaves interrupts disabled.
|
||||
*/
|
||||
|
||||
/**
|
||||
* \fn void cpu_irq_restore(irqflags_t flags)
|
||||
* \brief Restore global interrupt flags
|
||||
*
|
||||
* Use in conjunction with \ref cpu_irq_save.
|
||||
*
|
||||
* \param flags State to set interrupt flag to.
|
||||
*/
|
||||
|
||||
/**
|
||||
* \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
|
||||
* \brief Check if interrupts are globally enabled in supplied flags
|
||||
*
|
||||
* \param flags Currents state of interrupt flags.
|
||||
*
|
||||
* \return True if interrupts are enabled.
|
||||
*/
|
||||
|
||||
/**
|
||||
* \def cpu_irq_is_enabled
|
||||
* \brief Check if interrupts are globally enabled
|
||||
*
|
||||
* \return True if interrupts are enabled.
|
||||
*/
|
||||
//@}
|
||||
|
||||
//! @}
|
||||
|
||||
/**
|
||||
* \ingroup interrupt_group
|
||||
* \defgroup interrupt_deprecated_group Deprecated interrupt definitions
|
||||
*/
|
||||
|
||||
#endif /* UTILS_INTERRUPT_H */
|
||||
@ -0,0 +1,76 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#include "interrupt_sam_nvic.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
/* Deprecated - global flag to determine the global interrupt state. Required by
|
||||
* QTouch library, however new applications should use cpu_irq_is_enabled()
|
||||
* which probes the true global interrupt state from the CPU special registers.
|
||||
*/
|
||||
volatile bool g_interrupt_enabled = true;
|
||||
#endif
|
||||
|
||||
void cpu_irq_enter_critical(void)
|
||||
{
|
||||
if (cpu_irq_critical_section_counter == 0) {
|
||||
if (cpu_irq_is_enabled()) {
|
||||
cpu_irq_disable();
|
||||
cpu_irq_prev_interrupt_state = true;
|
||||
} else {
|
||||
/* Make sure the to save the prev state as false */
|
||||
cpu_irq_prev_interrupt_state = false;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
cpu_irq_critical_section_counter++;
|
||||
}
|
||||
|
||||
void cpu_irq_leave_critical(void)
|
||||
{
|
||||
/* Check if the user is trying to leave a critical section when not in a critical section */
|
||||
Assert(cpu_irq_critical_section_counter > 0);
|
||||
|
||||
cpu_irq_critical_section_counter--;
|
||||
|
||||
/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
|
||||
was enabled when entering critical state */
|
||||
if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
|
||||
cpu_irq_enable();
|
||||
}
|
||||
}
|
||||
|
||||
@ -0,0 +1,179 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef UTILS_INTERRUPT_INTERRUPT_H
|
||||
#define UTILS_INTERRUPT_INTERRUPT_H
|
||||
|
||||
#include <compiler.h>
|
||||
#include <parts.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \weakgroup interrupt_group
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \name Interrupt Service Routine definition
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Define service routine
|
||||
*
|
||||
* \note For NVIC devices the interrupt service routines are predefined to
|
||||
* add to vector table in binary generation, so there is no service
|
||||
* register at run time. The routine collections are in exceptions.h.
|
||||
*
|
||||
* Usage:
|
||||
* \code
|
||||
ISR(foo_irq_handler)
|
||||
{
|
||||
// Function definition
|
||||
...
|
||||
}
|
||||
\endcode
|
||||
*
|
||||
* \param func Name for the function.
|
||||
*/
|
||||
# define ISR(func) \
|
||||
void func (void)
|
||||
|
||||
/**
|
||||
* \brief Initialize interrupt vectors
|
||||
*
|
||||
* For NVIC the interrupt vectors are put in vector table. So nothing
|
||||
* to do to initialize them, except defined the vector function with
|
||||
* right name.
|
||||
*
|
||||
* This must be called prior to \ref irq_register_handler.
|
||||
*/
|
||||
# define irq_initialize_vectors() \
|
||||
do { \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* \brief Register handler for interrupt
|
||||
*
|
||||
* For NVIC the interrupt vectors are put in vector table. So nothing
|
||||
* to do to register them, except defined the vector function with
|
||||
* right name.
|
||||
*
|
||||
* Usage:
|
||||
* \code
|
||||
irq_initialize_vectors();
|
||||
irq_register_handler(foo_irq_handler);
|
||||
\endcode
|
||||
*
|
||||
* \note The function \a func must be defined with the \ref ISR macro.
|
||||
* \note The functions prototypes can be found in the device exception header
|
||||
* files (exceptions.h).
|
||||
*/
|
||||
# define irq_register_handler(int_num, int_prio) \
|
||||
NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \
|
||||
NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \
|
||||
NVIC_EnableIRQ( (IRQn_Type)int_num); \
|
||||
|
||||
//@}
|
||||
|
||||
# define cpu_irq_enable() \
|
||||
do { \
|
||||
g_interrupt_enabled = true; \
|
||||
__DMB(); \
|
||||
__enable_irq(); \
|
||||
} while (0)
|
||||
# define cpu_irq_disable() \
|
||||
do { \
|
||||
__disable_irq(); \
|
||||
__DMB(); \
|
||||
g_interrupt_enabled = false; \
|
||||
} while (0)
|
||||
|
||||
typedef uint32_t irqflags_t;
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern volatile bool g_interrupt_enabled;
|
||||
#endif
|
||||
|
||||
#define cpu_irq_is_enabled() (__get_PRIMASK() == 0)
|
||||
|
||||
static volatile uint32_t cpu_irq_critical_section_counter;
|
||||
static volatile bool cpu_irq_prev_interrupt_state;
|
||||
|
||||
static inline irqflags_t cpu_irq_save(void)
|
||||
{
|
||||
volatile irqflags_t flags = cpu_irq_is_enabled();
|
||||
cpu_irq_disable();
|
||||
return flags;
|
||||
}
|
||||
|
||||
static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
|
||||
{
|
||||
return (flags);
|
||||
}
|
||||
|
||||
static inline void cpu_irq_restore(irqflags_t flags)
|
||||
{
|
||||
if (cpu_irq_is_enabled_flags(flags))
|
||||
cpu_irq_enable();
|
||||
}
|
||||
|
||||
void cpu_irq_enter_critical(void);
|
||||
void cpu_irq_leave_critical(void);
|
||||
|
||||
/**
|
||||
* \weakgroup interrupt_deprecated_group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define Enable_global_interrupt() cpu_irq_enable()
|
||||
#define Disable_global_interrupt() cpu_irq_disable()
|
||||
#define Is_global_interrupt_enabled() cpu_irq_is_enabled()
|
||||
|
||||
//@}
|
||||
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* UTILS_INTERRUPT_INTERRUPT_H */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,91 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Common Delay Service
|
||||
*
|
||||
* Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef DELAY_H_INCLUDED
|
||||
#define DELAY_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup group_common_services_delay Busy-Wait Delay Routines
|
||||
*
|
||||
* This module provides simple loop-based delay routines for those
|
||||
* applications requiring a brief wait during execution. Common for
|
||||
* API ver. 2.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef SYSTICK_MODE
|
||||
#include "sam0/systick_counter.h"
|
||||
#endif
|
||||
#ifdef CYCLE_MODE
|
||||
#include "sam0/cycle_counter.h"
|
||||
#endif
|
||||
|
||||
void delay_init(void);
|
||||
|
||||
/**
|
||||
* \def delay_s
|
||||
* \brief Delay in at least specified number of seconds.
|
||||
* \param delay Delay in seconds
|
||||
*/
|
||||
#define delay_s(delay) ((delay) ? cpu_delay_s(delay) : cpu_delay_us(1))
|
||||
|
||||
/**
|
||||
* \def delay_ms
|
||||
* \brief Delay in at least specified number of milliseconds.
|
||||
* \param delay Delay in milliseconds
|
||||
*/
|
||||
#define delay_ms(delay) ((delay) ? cpu_delay_ms(delay) : cpu_delay_us(1))
|
||||
|
||||
/**
|
||||
* \def delay_us
|
||||
* \brief Delay in at least specified number of microseconds.
|
||||
* \param delay Delay in microseconds
|
||||
*/
|
||||
#define delay_us(delay) ((delay) ? cpu_delay_us(delay) : cpu_delay_us(1))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DELAY_H_INCLUDED */
|
||||
@ -0,0 +1,86 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief ARM functions for busy-wait delay loops
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#include "delay.h"
|
||||
|
||||
/**
|
||||
* Value used to calculate ms delay. Default to be used with a 8MHz clock;
|
||||
*/
|
||||
static uint32_t cycles_per_ms = 8000000UL / 1000;
|
||||
static uint32_t cycles_per_us = 8000000UL / 1000000;
|
||||
|
||||
/**
|
||||
* \brief Initialize the delay driver.
|
||||
*
|
||||
* This must be called during start up to initialize the delay routine with
|
||||
* the current used main clock. It must run any time the main CPU clock is changed.
|
||||
*/
|
||||
void delay_init(void)
|
||||
{
|
||||
cycles_per_ms = system_gclk_gen_get_hz(0);
|
||||
cycles_per_ms /= 1000;
|
||||
cycles_per_us = cycles_per_ms / 1000;
|
||||
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Delay loop to delay at least n number of microseconds
|
||||
*
|
||||
* \param n Number of microseconds to wait
|
||||
*/
|
||||
void delay_cycles_us(
|
||||
uint32_t n)
|
||||
{
|
||||
while (n--) {
|
||||
/* Devide up to blocks of 10u */
|
||||
delay_cycles(cycles_per_us);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Delay loop to delay at least n number of milliseconds
|
||||
*
|
||||
* \param n Number of milliseconds to wait
|
||||
*/
|
||||
void delay_cycles_ms(
|
||||
uint32_t n)
|
||||
{
|
||||
while (n--) {
|
||||
/* Devide up to blocks of 1ms */
|
||||
delay_cycles(cycles_per_ms);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,103 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief ARM functions for busy-wait delay loops
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef CYCLE_COUNTER_H_INCLUDED
|
||||
#define CYCLE_COUNTER_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
#include <clock.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \name Convenience functions for busy-wait delay loops
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Delay loop to delay n number of cycles
|
||||
* Delay program execution for at least the specified number of CPU cycles.
|
||||
*
|
||||
* \param n Number of cycles to delay
|
||||
*/
|
||||
static inline void delay_cycles(
|
||||
const uint32_t n)
|
||||
{
|
||||
if (n > 0) {
|
||||
SysTick->LOAD = n;
|
||||
SysTick->VAL = 0;
|
||||
|
||||
while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
void delay_cycles_us(uint32_t n);
|
||||
|
||||
void delay_cycles_ms(uint32_t n);
|
||||
|
||||
/**
|
||||
* \brief Delay program execution for at least the specified number of microseconds.
|
||||
*
|
||||
* \param delay number of microseconds to wait
|
||||
*/
|
||||
#define cpu_delay_us(delay) delay_cycles_us(delay)
|
||||
|
||||
/**
|
||||
* \brief Delay program execution for at least the specified number of milliseconds.
|
||||
*
|
||||
* \param delay number of milliseconds to wait
|
||||
*/
|
||||
#define cpu_delay_ms(delay) delay_cycles_ms(delay)
|
||||
|
||||
/**
|
||||
* \brief Delay program execution for at least the specified number of seconds.
|
||||
*
|
||||
* \param delay number of seconds to wait
|
||||
*/
|
||||
#define cpu_delay_s(delay) delay_cycles_ms(1000 * delay)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CYCLE_COUNTER_H_INCLUDED */
|
||||
@ -0,0 +1,80 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM D21 Xplained Pro board initialization
|
||||
*
|
||||
* Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <board.h>
|
||||
#include <conf_board.h>
|
||||
#include <port.h>
|
||||
|
||||
#if defined(__GNUC__)
|
||||
void board_init(void) WEAK __attribute__((alias("system_board_init")));
|
||||
#elif defined(__ICCARM__)
|
||||
void board_init(void);
|
||||
# pragma weak board_init=system_board_init
|
||||
#endif
|
||||
|
||||
void system_board_init(void)
|
||||
{
|
||||
struct port_config pin_conf;
|
||||
port_get_config_defaults(&pin_conf);
|
||||
|
||||
/* Configure LEDs as outputs, turn them off */
|
||||
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
|
||||
port_pin_set_config(LED_0_PIN, &pin_conf);
|
||||
port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
|
||||
|
||||
/* Set buttons as inputs */
|
||||
pin_conf.direction = PORT_PIN_DIR_INPUT;
|
||||
pin_conf.input_pull = PORT_PIN_PULL_UP;
|
||||
port_pin_set_config(BUTTON_0_PIN, &pin_conf);
|
||||
|
||||
#ifdef CONF_BOARD_AT86RFX
|
||||
port_get_config_defaults(&pin_conf);
|
||||
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
|
||||
port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
|
||||
port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
|
||||
port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
|
||||
port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
|
||||
port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
|
||||
port_pin_set_output_level(AT86RFX_SPI_SCK, true);
|
||||
port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
|
||||
port_pin_set_output_level(AT86RFX_SPI_CS, true);
|
||||
port_pin_set_output_level(AT86RFX_RST_PIN, true);
|
||||
port_pin_set_output_level(AT86RFX_SLP_PIN, true);
|
||||
pin_conf.direction = PORT_PIN_DIR_INPUT;
|
||||
port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
|
||||
#endif
|
||||
}
|
||||
@ -0,0 +1,699 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM D21 Xplained Pro board definition
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
|
||||
#define SAMD21_XPLAINED_PRO_H_INCLUDED
|
||||
|
||||
#include <conf_board.h>
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \ingroup group_common_boards
|
||||
* \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
void system_board_init(void);
|
||||
|
||||
/**
|
||||
* \defgroup samd21_xplained_pro_features_group Features
|
||||
*
|
||||
* Symbols that describe features and capabilities of the board.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Name string macro */
|
||||
#define BOARD_NAME "SAMD21_XPLAINED_PRO"
|
||||
|
||||
/** \name Resonator definitions
|
||||
* @{ */
|
||||
#define BOARD_FREQ_SLCK_XTAL (32768U)
|
||||
#define BOARD_FREQ_SLCK_BYPASS (32768U)
|
||||
#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
|
||||
#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
|
||||
#define BOARD_MCK CHIP_FREQ_CPU_MAX
|
||||
#define BOARD_OSC_STARTUP_US 15625
|
||||
/** @} */
|
||||
|
||||
/** \name LED0 definitions
|
||||
* @{ */
|
||||
#define LED0_PIN PIN_PB30
|
||||
#define LED0_ACTIVE false
|
||||
#define LED0_INACTIVE !LED0_ACTIVE
|
||||
/** @} */
|
||||
|
||||
/** \name SW0 definitions
|
||||
* @{ */
|
||||
#define SW0_PIN PIN_PA15
|
||||
#define SW0_ACTIVE false
|
||||
#define SW0_INACTIVE !SW0_ACTIVE
|
||||
#define SW0_EIC_PIN PIN_PA15A_EIC_EXTINT15
|
||||
#define SW0_EIC_MUX MUX_PA15A_EIC_EXTINT15
|
||||
#define SW0_EIC_PINMUX PINMUX_PA15A_EIC_EXTINT15
|
||||
#define SW0_EIC_LINE 15
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \name LED #0 definitions
|
||||
*
|
||||
* Wrapper macros for LED0, to ensure common naming across all Xplained Pro
|
||||
* boards.
|
||||
*
|
||||
* @{ */
|
||||
#define LED_0_NAME "LED0 (yellow)"
|
||||
#define LED_0_PIN LED0_PIN
|
||||
#define LED_0_ACTIVE LED0_ACTIVE
|
||||
#define LED_0_INACTIVE LED0_INACTIVE
|
||||
#define LED0_GPIO LED0_PIN
|
||||
#define LED0 LED0_PIN
|
||||
|
||||
#define LED_0_PWM4CTRL_MODULE TCC0
|
||||
#define LED_0_PWM4CTRL_CHANNEL 0
|
||||
#define LED_0_PWM4CTRL_OUTPUT 0
|
||||
#define LED_0_PWM4CTRL_PIN PIN_PB30E_TCC0_WO0
|
||||
#define LED_0_PWM4CTRL_MUX MUX_PB30E_TCC0_WO0
|
||||
#define LED_0_PWM4CTRL_PINMUX PINMUX_PB30E_TCC0_WO0
|
||||
/** @} */
|
||||
|
||||
/** Number of on-board LEDs */
|
||||
#define LED_COUNT 1
|
||||
|
||||
/**
|
||||
* \name Serialflash definitions
|
||||
*
|
||||
* On board Serialflash definitions.
|
||||
*
|
||||
* @{ */
|
||||
#define SERIALFLASH_SPI_MODULE SERCOM5
|
||||
#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
|
||||
#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
|
||||
#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED
|
||||
#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
|
||||
#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
|
||||
#define SERIALFLASH_SPI_CS PIN_PA13
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \name Button #0 definitions
|
||||
*
|
||||
* Wrapper macros for SW0, to ensure common naming across all Xplained Pro
|
||||
* boards.
|
||||
*
|
||||
* @{ */
|
||||
#define BUTTON_0_NAME "SW0"
|
||||
#define BUTTON_0_PIN SW0_PIN
|
||||
#define BUTTON_0_ACTIVE SW0_ACTIVE
|
||||
#define BUTTON_0_INACTIVE SW0_INACTIVE
|
||||
#define BUTTON_0_EIC_PIN SW0_EIC_PIN
|
||||
#define BUTTON_0_EIC_MUX SW0_EIC_MUX
|
||||
#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
|
||||
#define BUTTON_0_EIC_LINE SW0_EIC_LINE
|
||||
/** @} */
|
||||
|
||||
/** Number of on-board buttons */
|
||||
#define BUTTON_COUNT 1
|
||||
|
||||
/** \name Extension header #1 pin definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT1_PIN_3 PIN_PB00
|
||||
#define EXT1_PIN_4 PIN_PB01
|
||||
#define EXT1_PIN_5 PIN_PB06
|
||||
#define EXT1_PIN_6 PIN_PB07
|
||||
#define EXT1_PIN_7 PIN_PB02
|
||||
#define EXT1_PIN_8 PIN_PB03
|
||||
#define EXT1_PIN_9 PIN_PB04
|
||||
#define EXT1_PIN_10 PIN_PB05
|
||||
#define EXT1_PIN_11 PIN_PA08
|
||||
#define EXT1_PIN_12 PIN_PA09
|
||||
#define EXT1_PIN_13 PIN_PB09
|
||||
#define EXT1_PIN_14 PIN_PB08
|
||||
#define EXT1_PIN_15 PIN_PA05
|
||||
#define EXT1_PIN_16 PIN_PA06
|
||||
#define EXT1_PIN_17 PIN_PA04
|
||||
#define EXT1_PIN_18 PIN_PA07
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #1 pin definitions by function
|
||||
* @{
|
||||
*/
|
||||
#define EXT1_PIN_ADC_0 EXT1_PIN_3
|
||||
#define EXT1_PIN_ADC_1 EXT1_PIN_4
|
||||
#define EXT1_PIN_GPIO_0 EXT1_PIN_5
|
||||
#define EXT1_PIN_GPIO_1 EXT1_PIN_6
|
||||
#define EXT1_PIN_PWM_0 EXT1_PIN_7
|
||||
#define EXT1_PIN_PWM_1 EXT1_PIN_8
|
||||
#define EXT1_PIN_IRQ EXT1_PIN_9
|
||||
#define EXT1_PIN_I2C_SDA EXT1_PIN_11
|
||||
#define EXT1_PIN_I2C_SCL EXT1_PIN_12
|
||||
#define EXT1_PIN_UART_RX EXT1_PIN_13
|
||||
#define EXT1_PIN_UART_TX EXT1_PIN_14
|
||||
#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
|
||||
#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
|
||||
#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
|
||||
#define EXT1_PIN_SPI_MISO EXT1_PIN_17
|
||||
#define EXT1_PIN_SPI_SCK EXT1_PIN_18
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #1 ADC definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT1_ADC_MODULE ADC
|
||||
#define EXT1_ADC_0_CHANNEL 8
|
||||
#define EXT1_ADC_0_PIN PIN_PB00B_ADC_AIN8
|
||||
#define EXT1_ADC_0_MUX MUX_PB00B_ADC_AIN8
|
||||
#define EXT1_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8
|
||||
#define EXT1_ADC_1_CHANNEL 9
|
||||
#define EXT1_ADC_1_PIN PIN_PB01B_ADC_AIN9
|
||||
#define EXT1_ADC_1_MUX MUX_PB01B_ADC_AIN9
|
||||
#define EXT1_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #1 PWM definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT1_PWM_MODULE TC6
|
||||
#define EXT1_PWM_0_CHANNEL 0
|
||||
#define EXT1_PWM_0_PIN PIN_PB02E_TC6_WO0
|
||||
#define EXT1_PWM_0_MUX MUX_PB02E_TC6_WO0
|
||||
#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC6_WO0
|
||||
#define EXT1_PWM_1_CHANNEL 1
|
||||
#define EXT1_PWM_1_PIN PIN_PB03E_TC6_WO1
|
||||
#define EXT1_PWM_1_MUX MUX_PB03E_TC6_WO1
|
||||
#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC6_WO1
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #1 IRQ/External interrupt definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT1_IRQ_MODULE EIC
|
||||
#define EXT1_IRQ_INPUT 4
|
||||
#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4
|
||||
#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4
|
||||
#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #1 I2C definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT1_I2C_MODULE SERCOM2
|
||||
#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
|
||||
#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #1 UART definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT1_UART_MODULE SERCOM4
|
||||
#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
|
||||
#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0
|
||||
#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1
|
||||
#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
|
||||
#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
|
||||
#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
|
||||
#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #1 SPI definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT1_SPI_MODULE SERCOM0
|
||||
#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
|
||||
#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3
|
||||
#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
|
||||
#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #2 pin definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT2_PIN_3 PIN_PA10
|
||||
#define EXT2_PIN_4 PIN_PA11
|
||||
#define EXT2_PIN_5 PIN_PA20
|
||||
#define EXT2_PIN_6 PIN_PA21
|
||||
#define EXT2_PIN_7 PIN_PB12
|
||||
#define EXT2_PIN_8 PIN_PB13
|
||||
#define EXT2_PIN_9 PIN_PB14
|
||||
#define EXT2_PIN_10 PIN_PB15
|
||||
#define EXT2_PIN_11 PIN_PA08
|
||||
#define EXT2_PIN_12 PIN_PA09
|
||||
#define EXT2_PIN_13 PIN_PB11
|
||||
#define EXT2_PIN_14 PIN_PB10
|
||||
#define EXT2_PIN_15 PIN_PA17
|
||||
#define EXT2_PIN_16 PIN_PA18
|
||||
#define EXT2_PIN_17 PIN_PA16
|
||||
#define EXT2_PIN_18 PIN_PA19
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #2 pin definitions by function
|
||||
* @{
|
||||
*/
|
||||
#define EXT2_PIN_ADC_0 EXT2_PIN_3
|
||||
#define EXT2_PIN_ADC_1 EXT2_PIN_4
|
||||
#define EXT2_PIN_GPIO_0 EXT2_PIN_5
|
||||
#define EXT2_PIN_GPIO_1 EXT2_PIN_6
|
||||
#define EXT2_PIN_PWM_0 EXT2_PIN_7
|
||||
#define EXT2_PIN_PWM_1 EXT2_PIN_8
|
||||
#define EXT2_PIN_IRQ EXT2_PIN_9
|
||||
#define EXT2_PIN_I2C_SDA EXT2_PIN_11
|
||||
#define EXT2_PIN_I2C_SCL EXT2_PIN_12
|
||||
#define EXT2_PIN_UART_RX EXT2_PIN_13
|
||||
#define EXT2_PIN_UART_TX EXT2_PIN_14
|
||||
#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10
|
||||
#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15
|
||||
#define EXT2_PIN_SPI_MOSI EXT2_PIN_16
|
||||
#define EXT2_PIN_SPI_MISO EXT2_PIN_17
|
||||
#define EXT2_PIN_SPI_SCK EXT2_PIN_18
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #2 ADC definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT2_ADC_MODULE ADC
|
||||
#define EXT2_ADC_0_CHANNEL 18
|
||||
#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18
|
||||
#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18
|
||||
#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18
|
||||
#define EXT2_ADC_1_CHANNEL 19
|
||||
#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19
|
||||
#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19
|
||||
#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #2 PWM definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT2_PWM_MODULE TC4
|
||||
#define EXT2_PWM_0_CHANNEL 0
|
||||
#define EXT2_PWM_0_PIN PIN_PB12E_TC4_WO0
|
||||
#define EXT2_PWM_0_MUX MUX_PB12E_TC4_WO0
|
||||
#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC4_WO0
|
||||
#define EXT2_PWM_1_CHANNEL 1
|
||||
#define EXT2_PWM_1_PIN PIN_PB13E_TC4_WO1
|
||||
#define EXT2_PWM_1_MUX MUX_PB13E_TC4_WO1
|
||||
#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC4_WO1
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #2 PWM for Control definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT2_PWM4CTRL_MODULE TCC0
|
||||
#define EXT2_PWM4CTRL_0_CHANNEL 2
|
||||
#define EXT2_PWM4CTRL_0_OUTPUT 6
|
||||
#define EXT2_PWM4CTRL_0_PIN PIN_PB12F_TCC0_WO6
|
||||
#define EXT2_PWM4CTRL_0_MUX MUX_PB12F_TCC0_WO6
|
||||
#define EXT2_PWM4CTRL_0_PINMUX PINMUX_PB12F_TCC0_WO6
|
||||
#define EXT2_PWM4CTRL_1_CHANNEL 3
|
||||
#define EXT2_PWM4CTRL_1_OUTPUT 7
|
||||
#define EXT2_PWM4CTRL_1_PIN PIN_PB13F_TCC0_WO7
|
||||
#define EXT2_PWM4CTRL_1_MUX MUX_PB13F_TCC0_WO7
|
||||
#define EXT2_PWM4CTRL_1_PINMUX PINMUX_PB13F_TCC0_WO7
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #2 IRQ/External interrupt definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT2_IRQ_MODULE EIC
|
||||
#define EXT2_IRQ_INPUT 14
|
||||
#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14
|
||||
#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14
|
||||
#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #2 I2C definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT2_I2C_MODULE SERCOM2
|
||||
#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
|
||||
#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #2 UART definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT2_UART_MODULE SERCOM4
|
||||
#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
|
||||
#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_PB12C_SERCOM4_PAD0
|
||||
#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_PB13C_SERCOM4_PAD1
|
||||
#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
|
||||
#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
|
||||
#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
|
||||
#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #2 SPI definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT2_SPI_MODULE SERCOM1
|
||||
#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
|
||||
#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
|
||||
#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
|
||||
#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
|
||||
#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
|
||||
#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
|
||||
#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #3 pin definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT3_PIN_3 PIN_PA02
|
||||
#define EXT3_PIN_4 PIN_PA03
|
||||
#define EXT3_PIN_5 PIN_PB30
|
||||
#define EXT3_PIN_6 PIN_PA15
|
||||
#define EXT3_PIN_7 PIN_PA12
|
||||
#define EXT3_PIN_8 PIN_PA13
|
||||
#define EXT3_PIN_9 PIN_PA28
|
||||
#define EXT3_PIN_10 PIN_PA27
|
||||
#define EXT3_PIN_11 PIN_PA08
|
||||
#define EXT3_PIN_12 PIN_PA09
|
||||
#define EXT3_PIN_13 PIN_PB11
|
||||
#define EXT3_PIN_14 PIN_PB10
|
||||
#define EXT3_PIN_15 PIN_PB17
|
||||
#define EXT3_PIN_16 PIN_PB22
|
||||
#define EXT3_PIN_17 PIN_PB16
|
||||
#define EXT3_PIN_18 PIN_PB23
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #3 pin definitions by function
|
||||
* @{
|
||||
*/
|
||||
#define EXT3_PIN_ADC_0 EXT3_PIN_3
|
||||
#define EXT3_PIN_ADC_1 EXT3_PIN_4
|
||||
#define EXT3_PIN_GPIO_0 EXT3_PIN_5
|
||||
#define EXT3_PIN_GPIO_1 EXT3_PIN_6
|
||||
#define EXT3_PIN_PWM_0 EXT3_PIN_7
|
||||
#define EXT3_PIN_PWM_1 EXT3_PIN_8
|
||||
#define EXT3_PIN_IRQ EXT3_PIN_9
|
||||
#define EXT3_PIN_I2C_SDA EXT3_PIN_11
|
||||
#define EXT3_PIN_I2C_SCL EXT3_PIN_12
|
||||
#define EXT3_PIN_UART_RX EXT3_PIN_13
|
||||
#define EXT3_PIN_UART_TX EXT3_PIN_14
|
||||
#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10
|
||||
#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
|
||||
#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
|
||||
#define EXT3_PIN_SPI_MISO EXT3_PIN_17
|
||||
#define EXT3_PIN_SPI_SCK EXT3_PIN_18
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #3 ADC definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT3_ADC_MODULE ADC
|
||||
#define EXT3_ADC_0_CHANNEL 0
|
||||
#define EXT3_ADC_0_PIN PIN_PA02B_ADC_AIN0
|
||||
#define EXT3_ADC_0_MUX MUX_PA02B_ADC_AIN0
|
||||
#define EXT3_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0
|
||||
#define EXT3_ADC_1_CHANNEL 1
|
||||
#define EXT3_ADC_1_PIN PIN_PA03B_ADC_AIN1
|
||||
#define EXT3_ADC_1_MUX MUX_PA03B_ADC_AIN1
|
||||
#define EXT3_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #3 PWM for Control definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT3_PWM4CTRL_MODULE TCC2
|
||||
#define EXT3_PWM4CTRL_0_CHANNEL 0
|
||||
#define EXT3_PWM4CTRL_0_OUTPUT 0
|
||||
#define EXT3_PWM4CTRL_0_PIN PIN_PA12E_TCC2_WO0
|
||||
#define EXT3_PWM4CTRL_0_MUX MUX_PA12E_TCC2_WO0
|
||||
#define EXT3_PWM4CTRL_0_PINMUX PINMUX_PA12E_TCC2_WO0
|
||||
#define EXT3_PWM4CTRL_1_CHANNEL 1
|
||||
#define EXT3_PWM4CTRL_1_OUTPUT 1
|
||||
#define EXT3_PWM4CTRL_1_PIN PIN_PA13E_TCC2_WO1
|
||||
#define EXT3_PWM4CTRL_1_MUX MUX_PA13E_TCC2_WO1
|
||||
#define EXT3_PWM4CTRL_1_PINMUX PINMUX_PA13E_TCC2_WO1
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #3 IRQ/External interrupt definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT3_IRQ_MODULE EIC
|
||||
#define EXT3_IRQ_INPUT 8
|
||||
#define EXT3_IRQ_PIN PIN_PA28A_EIC_EXTINT8
|
||||
#define EXT3_IRQ_MUX MUX_PA28A_EIC_EXTINT8
|
||||
#define EXT3_IRQ_PINMUX PINMUX_PA28A_EIC_EXTINT8
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #3 I2C definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT3_I2C_MODULE SERCOM2
|
||||
#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
|
||||
#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #3 UART definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT3_UART_MODULE SERCOM4
|
||||
#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
|
||||
#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
|
||||
#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
|
||||
#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2
|
||||
#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3
|
||||
#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
|
||||
#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #3 SPI definitions
|
||||
* @{
|
||||
*/
|
||||
#define EXT3_SPI_MODULE SERCOM5
|
||||
#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
|
||||
#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
|
||||
#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1
|
||||
#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
|
||||
#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
|
||||
#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
|
||||
#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** \name Extension header #3 Dataflash
|
||||
* @{
|
||||
*/
|
||||
#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
|
||||
#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
|
||||
#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
|
||||
#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
|
||||
#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
|
||||
#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
|
||||
/** @} */
|
||||
|
||||
/** \name USB definitions
|
||||
* @{
|
||||
*/
|
||||
#define USB_ID
|
||||
#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
|
||||
#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
|
||||
#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
|
||||
#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
|
||||
#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
|
||||
#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
|
||||
#define USB_VBUS_PIN PIN_PA14
|
||||
#define USB_VBUS_EIC_LINE 14
|
||||
#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14
|
||||
#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14
|
||||
#define USB_ID_PIN PIN_PA03
|
||||
#define USB_ID_EIC_LINE 3
|
||||
#define USB_ID_EIC_MUX MUX_PA03A_EIC_EXTINT3
|
||||
#define USB_ID_EIC_PINMUX PINMUX_PA03A_EIC_EXTINT3
|
||||
/** @} */
|
||||
|
||||
/** \name Embedded debugger GPIO interface definitions
|
||||
* @{
|
||||
*/
|
||||
#define EDBG_GPIO0_PIN PIN_PA27
|
||||
#define EDBG_GPIO1_PIN PIN_PA28
|
||||
#define EDBG_GPIO2_PIN PIN_PA20
|
||||
#define EDBG_GPIO3_PIN PIN_PA21
|
||||
/** @} */
|
||||
|
||||
/** \name Embedded debugger USART interface definitions
|
||||
* @{
|
||||
*/
|
||||
#define EDBG_UART_MODULE -1 /* Not available on this board */
|
||||
#define EDBG_UART_RX_PIN -1 /* Not available on this board */
|
||||
#define EDBG_UART_RX_MUX -1 /* Not available on this board */
|
||||
#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
|
||||
#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
|
||||
#define EDBG_UART_TX_PIN -1 /* Not available on this board */
|
||||
#define EDBG_UART_TX_MUX -1 /* Not available on this board */
|
||||
#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
|
||||
#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
|
||||
/** @} */
|
||||
|
||||
/** \name Embedded debugger I2C interface definitions
|
||||
* @{
|
||||
*/
|
||||
#define EDBG_I2C_MODULE SERCOM2
|
||||
#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
|
||||
#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** \name Embedded debugger SPI interface definitions
|
||||
* @{
|
||||
*/
|
||||
#define EDBG_SPI_MODULE SERCOM5
|
||||
#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
|
||||
#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
|
||||
#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
|
||||
#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
|
||||
#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
|
||||
#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
|
||||
#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** \name Embedded debugger CDC Gateway USART interface definitions
|
||||
* @{
|
||||
*/
|
||||
#define EDBG_CDC_MODULE SERCOM3
|
||||
#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
|
||||
#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0
|
||||
#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1
|
||||
#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
|
||||
#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
|
||||
#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX
|
||||
#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
|
||||
/** \name 802.15.4 TRX Interface definitions
|
||||
* @{
|
||||
*/
|
||||
#ifndef EXT2_CONFIG
|
||||
#define AT86RFX_SPI EXT1_SPI_MODULE
|
||||
#define AT86RFX_RST_PIN EXT1_PIN_7
|
||||
#define AT86RFX_MISC_PIN EXT1_PIN_12
|
||||
#define AT86RFX_IRQ_PIN EXT1_PIN_9
|
||||
#define AT86RFX_SLP_PIN EXT1_PIN_10
|
||||
#define AT86RFX_SPI_CS EXT1_PIN_15
|
||||
#define AT86RFX_SPI_MOSI EXT1_PIN_16
|
||||
#define AT86RFX_SPI_MISO EXT1_PIN_17
|
||||
#define AT86RFX_SPI_SCK EXT1_PIN_18
|
||||
#define AT86RFX_CSD EXT1_PIN_5
|
||||
#define AT86RFX_CPS EXT1_PIN_8
|
||||
|
||||
#define AT86RFX_SPI_SERCOM_MUX_SETTING EXT1_SPI_SERCOM_MUX_SETTING
|
||||
#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 EXT1_SPI_SERCOM_PINMUX_PAD0
|
||||
#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
|
||||
#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 EXT1_SPI_SERCOM_PINMUX_PAD2
|
||||
#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 EXT1_SPI_SERCOM_PINMUX_PAD3
|
||||
|
||||
#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT
|
||||
#define AT86RFX_IRQ_PINMUX EXT1_IRQ_PINMUX
|
||||
|
||||
|
||||
#endif
|
||||
/** Enables the transceiver main interrupt. */
|
||||
#define ENABLE_TRX_IRQ() \
|
||||
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
|
||||
|
||||
/** Disables the transceiver main interrupt. */
|
||||
#define DISABLE_TRX_IRQ() \
|
||||
extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
|
||||
|
||||
/** Clears the transceiver main interrupt. */
|
||||
#define CLEAR_TRX_IRQ() \
|
||||
extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
|
||||
|
||||
/*
|
||||
* This macro saves the trx interrupt status and disables the trx interrupt.
|
||||
*/
|
||||
#define ENTER_TRX_REGION() \
|
||||
{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
|
||||
|
||||
/*
|
||||
* This macro restores the transceiver interrupt status
|
||||
*/
|
||||
#define LEAVE_TRX_REGION() \
|
||||
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \brief Turns off the specified LEDs.
|
||||
*
|
||||
* \param led_gpio LED to turn off (LEDx_GPIO).
|
||||
*
|
||||
* \note The pins of the specified LEDs are set to GPIO output mode.
|
||||
*/
|
||||
#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
|
||||
|
||||
/**
|
||||
* \brief Turns on the specified LEDs.
|
||||
*
|
||||
* \param led_gpio LED to turn on (LEDx_GPIO).
|
||||
*
|
||||
* \note The pins of the specified LEDs are set to GPIO output mode.
|
||||
*/
|
||||
#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
|
||||
|
||||
/**
|
||||
* \brief Toggles the specified LEDs.
|
||||
*
|
||||
* \param led_gpio LED to toggle (LEDx_GPIO).
|
||||
*
|
||||
* \note The pins of the specified LEDs are set to GPIO output mode.
|
||||
*/
|
||||
#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SAMD21_XPLAINED_PRO_H_INCLUDED */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,172 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Peripheral Analog-to-Digital Converter Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef ADC_CALLBACK_H_INCLUDED
|
||||
#define ADC_CALLBACK_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup asfdoc_sam0_adc_group
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <adc.h>
|
||||
|
||||
/**
|
||||
* Enum for the possible types of ADC asynchronous jobs that may be issued to
|
||||
* the driver.
|
||||
*/
|
||||
enum adc_job_type {
|
||||
/** Asynchronous ADC read into a user provided buffer */
|
||||
ADC_JOB_READ_BUFFER,
|
||||
};
|
||||
|
||||
/**
|
||||
* \name Callback Management
|
||||
* @{
|
||||
*/
|
||||
void adc_register_callback(
|
||||
struct adc_module *const module,
|
||||
adc_callback_t callback_func,
|
||||
enum adc_callback callback_type);
|
||||
|
||||
void adc_unregister_callback(
|
||||
struct adc_module *module,
|
||||
enum adc_callback callback_type);
|
||||
|
||||
/**
|
||||
* \brief Enables callback.
|
||||
*
|
||||
* Enables the callback function registered by \ref
|
||||
* adc_register_callback. The callback function will be called from the
|
||||
* interrupt handler when the conditions for the callback type are met.
|
||||
*
|
||||
* \param[in] module Pointer to ADC software instance struct
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*
|
||||
* \return Status of the operation.
|
||||
* \retval STATUS_OK If operation was completed
|
||||
* \retval STATUS_ERR_INVALID If operation was not completed,
|
||||
* due to invalid callback_type
|
||||
*
|
||||
*/
|
||||
static inline void adc_enable_callback(
|
||||
struct adc_module *const module,
|
||||
enum adc_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
|
||||
/* Enable callback */
|
||||
module->enabled_callback_mask |= (1 << callback_type);
|
||||
|
||||
/* Enable window interrupt if this is a window callback */
|
||||
if (callback_type == ADC_CALLBACK_WINDOW) {
|
||||
adc_enable_interrupt(module, ADC_INTERRUPT_WINDOW);
|
||||
}
|
||||
/* Enable overrun interrupt if error callback is registered */
|
||||
if (callback_type == ADC_CALLBACK_ERROR) {
|
||||
adc_enable_interrupt(module, ADC_INTERRUPT_OVERRUN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disables callback.
|
||||
*
|
||||
* Disables the callback function registered by the \ref
|
||||
* adc_register_callback.
|
||||
*
|
||||
* \param[in] module Pointer to ADC software instance struct
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*
|
||||
* \return Status of the operation.
|
||||
* \retval STATUS_OK If operation was completed
|
||||
* \retval STATUS_ERR_INVALID If operation was not completed,
|
||||
* due to invalid callback_type
|
||||
*
|
||||
*/
|
||||
static inline void adc_disable_callback(
|
||||
struct adc_module *const module,
|
||||
enum adc_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
|
||||
/* Disable callback */
|
||||
module->enabled_callback_mask &= ~(1 << callback_type);
|
||||
|
||||
/* Disable window interrupt if this is a window callback */
|
||||
if (callback_type == ADC_CALLBACK_WINDOW) {
|
||||
adc_disable_interrupt(module, ADC_INTERRUPT_WINDOW);
|
||||
}
|
||||
/* Disable overrun interrupt if this is the error callback */
|
||||
if (callback_type == ADC_CALLBACK_ERROR) {
|
||||
adc_disable_interrupt(module, ADC_INTERRUPT_OVERRUN);
|
||||
}
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* \name Job Management
|
||||
* @{
|
||||
*/
|
||||
enum status_code adc_read_buffer_job(
|
||||
struct adc_module *const module_inst,
|
||||
uint16_t *buffer,
|
||||
uint16_t samples);
|
||||
|
||||
enum status_code adc_get_job_status(
|
||||
struct adc_module *module_inst,
|
||||
enum adc_job_type type);
|
||||
|
||||
void adc_abort_job(
|
||||
struct adc_module *module_inst,
|
||||
enum adc_job_type type);
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ADC_CALLBACK_H_INCLUDED */
|
||||
@ -0,0 +1,726 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Peripheral Analog-to-Digital Converter Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#include "adc.h"
|
||||
|
||||
#if SAMD20
|
||||
/* The Die revision D number */
|
||||
#define REVISON_D_NUM 3
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Initializes an ADC configuration structure to defaults
|
||||
*
|
||||
* Initializes a given ADC configuration struct to a set of known default
|
||||
* values. This function should be called on any new instance of the
|
||||
* configuration struct before being modified by the user application.
|
||||
*
|
||||
* The default configuration is as follows:
|
||||
* \li GCLK generator 0 (GCLK main) clock source
|
||||
* \li 1V from internal bandgap reference
|
||||
* \li Div 4 clock prescaler
|
||||
* \li 12-bit resolution
|
||||
* \li Window monitor disabled
|
||||
* \li No gain
|
||||
* \li Positive input on ADC PIN 0
|
||||
* \li Negative input on ADC PIN 1
|
||||
* \li Averaging disabled
|
||||
* \li Oversampling disabled
|
||||
* \li Right adjust data
|
||||
* \li Single-ended mode
|
||||
* \li Free running disabled
|
||||
* \li All events (input and generation) disabled
|
||||
* \li Sleep operation disabled
|
||||
* \li No reference compensation
|
||||
* \li No gain/offset correction
|
||||
* \li No added sampling time
|
||||
* \li Pin scan mode disabled
|
||||
*
|
||||
* \param[out] config Pointer to configuration struct to initialize to
|
||||
* default values
|
||||
*/
|
||||
void adc_get_config_defaults(struct adc_config *const config)
|
||||
{
|
||||
Assert(config);
|
||||
config->clock_source = GCLK_GENERATOR_0;
|
||||
config->reference = ADC_REFERENCE_INT1V;
|
||||
config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4;
|
||||
config->resolution = ADC_RESOLUTION_12BIT;
|
||||
config->window.window_mode = ADC_WINDOW_MODE_DISABLE;
|
||||
config->window.window_upper_value = 0;
|
||||
config->window.window_lower_value = 0;
|
||||
config->gain_factor = ADC_GAIN_FACTOR_1X;
|
||||
#if SAMR21
|
||||
config->positive_input = ADC_POSITIVE_INPUT_PIN6 ;
|
||||
#else
|
||||
config->positive_input = ADC_POSITIVE_INPUT_PIN0 ;
|
||||
#endif
|
||||
config->negative_input = ADC_NEGATIVE_INPUT_GND ;
|
||||
config->accumulate_samples = ADC_ACCUMULATE_DISABLE;
|
||||
config->divide_result = ADC_DIVIDE_RESULT_DISABLE;
|
||||
config->left_adjust = false;
|
||||
config->differential_mode = false;
|
||||
config->freerunning = false;
|
||||
config->event_action = ADC_EVENT_ACTION_DISABLED;
|
||||
config->run_in_standby = false;
|
||||
config->reference_compensation_enable = false;
|
||||
config->correction.correction_enable = false;
|
||||
config->correction.gain_correction = ADC_GAINCORR_RESETVALUE;
|
||||
config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE;
|
||||
config->sample_length = 0;
|
||||
config->pin_scan.offset_start_scan = 0;
|
||||
config->pin_scan.inputs_to_scan = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Sets the ADC window mode
|
||||
*
|
||||
* Sets the ADC window mode to a given mode and value range.
|
||||
*
|
||||
* \param[in] module_inst Pointer to the ADC software instance struct
|
||||
* \param[in] window_mode Window monitor mode to set
|
||||
* \param[in] window_lower_value Lower window monitor threshold value
|
||||
* \param[in] window_upper_value Upper window monitor threshold value
|
||||
*/
|
||||
void adc_set_window_mode(
|
||||
struct adc_module *const module_inst,
|
||||
const enum adc_window_mode window_mode,
|
||||
const int16_t window_lower_value,
|
||||
const int16_t window_upper_value)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module_inst);
|
||||
Assert(module_inst->hw);
|
||||
|
||||
Adc *const adc_module = module_inst->hw;
|
||||
|
||||
while (adc_is_syncing(module_inst)) {
|
||||
/* Wait for synchronization */
|
||||
}
|
||||
|
||||
/* Set window mode */
|
||||
adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos;
|
||||
|
||||
while (adc_is_syncing(module_inst)) {
|
||||
/* Wait for synchronization */
|
||||
}
|
||||
|
||||
/* Set lower window monitor threshold value */
|
||||
adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos;
|
||||
|
||||
while (adc_is_syncing(module_inst)) {
|
||||
/* Wait for synchronization */
|
||||
}
|
||||
|
||||
/* Set upper window monitor threshold value */
|
||||
adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos;
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal Configure MUX settings for the analog pins
|
||||
*
|
||||
* This function will set the given ADC input pins
|
||||
* to the analog function in the pinmux, giving
|
||||
* the ADC access to the analog signal
|
||||
*
|
||||
* \param [in] pin AINxx pin to configure
|
||||
*/
|
||||
static inline void _adc_configure_ain_pin(uint32_t pin)
|
||||
{
|
||||
#define PIN_INVALID_ADC_AIN 0xFFFFUL
|
||||
|
||||
/* Pinmapping table for AINxx -> GPIO pin number */
|
||||
const uint32_t pinmapping[] = {
|
||||
#if (SAMD20E) || (SAMD21E)|| (SAMDA1E)
|
||||
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
|
||||
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
|
||||
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
|
||||
#elif (SAMD20G) || (SAMD21G)|| (SAMDA1G)
|
||||
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
|
||||
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
|
||||
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
|
||||
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
|
||||
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
|
||||
#elif (SAMD20J) || (SAMD21J)|| (SAMDA1J)
|
||||
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
|
||||
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
|
||||
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
|
||||
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
|
||||
PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9,
|
||||
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
|
||||
PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
|
||||
PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
|
||||
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
|
||||
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
|
||||
#elif SAMR21E
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
#elif SAMR21G
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
|
||||
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
#elif (SAMD09C) || (SAMD10C) || (SAMD11C)
|
||||
PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
#elif (SAMD09D)
|
||||
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
|
||||
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
|
||||
PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
|
||||
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
#elif (SAMD10DS) || (SAMD10DU) || (SAMD11DS) || (SAMD11DU)
|
||||
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
|
||||
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
|
||||
PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
|
||||
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
#elif (SAMD10DM) || (SAMD11DM)
|
||||
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
|
||||
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
|
||||
PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
|
||||
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
|
||||
PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
#elif (SAMHA1G) || (SAMHA0G)
|
||||
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
|
||||
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_PB03B_ADC_AIN11,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
|
||||
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
|
||||
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
|
||||
#elif (SAMHA1E) || (SAMHA0E)
|
||||
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
|
||||
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
|
||||
#else
|
||||
# error ADC pin mappings are not defined for this device.
|
||||
#endif
|
||||
};
|
||||
|
||||
uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
|
||||
|
||||
if (pin <= ADC_EXTCHANNEL_MSB) {
|
||||
pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
|
||||
|
||||
Assert(pin_map_result != PIN_INVALID_ADC_AIN);
|
||||
|
||||
struct system_pinmux_config config;
|
||||
system_pinmux_get_config_defaults(&config);
|
||||
|
||||
/* Analog functions are all on MUX setting B */
|
||||
config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
|
||||
config.mux_position = 1;
|
||||
|
||||
system_pinmux_pin_set_config(pin_map_result, &config);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal Writes an ADC configuration to the hardware module
|
||||
*
|
||||
* Writes out a given ADC module configuration to the hardware module.
|
||||
*
|
||||
* \param[out] module_inst Pointer to the ADC software instance struct
|
||||
* \param[in] config Pointer to configuration struct
|
||||
*
|
||||
* \return Status of the configuration procedure
|
||||
* \retval STATUS_OK The configuration was successful
|
||||
* \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
|
||||
*/
|
||||
static enum status_code _adc_set_config(
|
||||
struct adc_module *const module_inst,
|
||||
struct adc_config *const config)
|
||||
{
|
||||
uint8_t adjres = 0;
|
||||
uint32_t resolution = ADC_RESOLUTION_16BIT;
|
||||
enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
|
||||
#if SAMD20
|
||||
uint8_t revision_num = ((REG_DSU_DID & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos);
|
||||
#endif
|
||||
|
||||
/* Get the hardware module pointer */
|
||||
Adc *const adc_module = module_inst->hw;
|
||||
|
||||
/* Configure GCLK channel and enable clock */
|
||||
struct system_gclk_chan_config gclk_chan_conf;
|
||||
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
|
||||
gclk_chan_conf.source_generator = config->clock_source;
|
||||
system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
|
||||
system_gclk_chan_enable(ADC_GCLK_ID);
|
||||
|
||||
/* Setup pinmuxing for analog inputs */
|
||||
if (config->pin_scan.inputs_to_scan != 0) {
|
||||
uint8_t offset = config->pin_scan.offset_start_scan;
|
||||
uint8_t start_pin =
|
||||
offset +(uint8_t)config->positive_input;
|
||||
uint8_t end_pin =
|
||||
start_pin + config->pin_scan.inputs_to_scan;
|
||||
|
||||
while (start_pin < end_pin) {
|
||||
_adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
|
||||
start_pin++;
|
||||
offset++;
|
||||
}
|
||||
_adc_configure_ain_pin(config->negative_input);
|
||||
} else {
|
||||
_adc_configure_ain_pin(config->positive_input);
|
||||
_adc_configure_ain_pin(config->negative_input);
|
||||
}
|
||||
|
||||
/* Configure run in standby */
|
||||
adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
|
||||
|
||||
/* Configure reference */
|
||||
adc_module->REFCTRL.reg =
|
||||
(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
|
||||
(config->reference);
|
||||
|
||||
/* Set adjusting result and number of samples */
|
||||
switch (config->resolution) {
|
||||
|
||||
case ADC_RESOLUTION_CUSTOM:
|
||||
adjres = config->divide_result;
|
||||
accumulate = config->accumulate_samples;
|
||||
/* 16-bit result register */
|
||||
resolution = ADC_RESOLUTION_16BIT;
|
||||
break;
|
||||
|
||||
case ADC_RESOLUTION_13BIT:
|
||||
/* Increase resolution by 1 bit */
|
||||
adjres = ADC_DIVIDE_RESULT_2;
|
||||
accumulate = ADC_ACCUMULATE_SAMPLES_4;
|
||||
/* 16-bit result register */
|
||||
resolution = ADC_RESOLUTION_16BIT;
|
||||
break;
|
||||
|
||||
case ADC_RESOLUTION_14BIT:
|
||||
/* Increase resolution by 2 bit */
|
||||
adjres = ADC_DIVIDE_RESULT_4;
|
||||
accumulate = ADC_ACCUMULATE_SAMPLES_16;
|
||||
/* 16-bit result register */
|
||||
resolution = ADC_RESOLUTION_16BIT;
|
||||
break;
|
||||
#if SAMD20
|
||||
/* See $35.1.8 for ADC errata of SAM D20.
|
||||
The revisions before D have this issue.*/
|
||||
case ADC_RESOLUTION_15BIT:
|
||||
/* Increase resolution by 3 bit */
|
||||
if(revision_num < REVISON_D_NUM) {
|
||||
adjres = ADC_DIVIDE_RESULT_8;
|
||||
} else {
|
||||
adjres = ADC_DIVIDE_RESULT_2;
|
||||
}
|
||||
accumulate = ADC_ACCUMULATE_SAMPLES_64;
|
||||
/* 16-bit result register */
|
||||
resolution = ADC_RESOLUTION_16BIT;
|
||||
break;
|
||||
|
||||
case ADC_RESOLUTION_16BIT:
|
||||
if(revision_num < REVISON_D_NUM) {
|
||||
/* Increase resolution by 4 bit */
|
||||
adjres = ADC_DIVIDE_RESULT_16;
|
||||
} else {
|
||||
adjres = ADC_DIVIDE_RESULT_DISABLE;
|
||||
}
|
||||
accumulate = ADC_ACCUMULATE_SAMPLES_256;
|
||||
/* 16-bit result register */
|
||||
resolution = ADC_RESOLUTION_16BIT;
|
||||
break;
|
||||
#else
|
||||
case ADC_RESOLUTION_15BIT:
|
||||
/* Increase resolution by 3 bit */
|
||||
adjres = ADC_DIVIDE_RESULT_2;
|
||||
accumulate = ADC_ACCUMULATE_SAMPLES_64;
|
||||
/* 16-bit result register */
|
||||
resolution = ADC_RESOLUTION_16BIT;
|
||||
break;
|
||||
|
||||
case ADC_RESOLUTION_16BIT:
|
||||
/* Increase resolution by 4 bit */
|
||||
adjres = ADC_DIVIDE_RESULT_DISABLE;
|
||||
accumulate = ADC_ACCUMULATE_SAMPLES_256;
|
||||
/* 16-bit result register */
|
||||
resolution = ADC_RESOLUTION_16BIT;
|
||||
break;
|
||||
#endif
|
||||
case ADC_RESOLUTION_8BIT:
|
||||
/* 8-bit result register */
|
||||
resolution = ADC_RESOLUTION_8BIT;
|
||||
break;
|
||||
case ADC_RESOLUTION_10BIT:
|
||||
/* 10-bit result register */
|
||||
resolution = ADC_RESOLUTION_10BIT;
|
||||
break;
|
||||
case ADC_RESOLUTION_12BIT:
|
||||
/* 12-bit result register */
|
||||
resolution = ADC_RESOLUTION_12BIT;
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Unknown. Abort. */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
|
||||
|
||||
/* Check validity of sample length value */
|
||||
if (config->sample_length > 63) {
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
} else {
|
||||
/* Configure sample length */
|
||||
adc_module->SAMPCTRL.reg =
|
||||
(config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos);
|
||||
}
|
||||
|
||||
while (adc_is_syncing(module_inst)) {
|
||||
/* Wait for synchronization */
|
||||
}
|
||||
|
||||
/* Configure CTRLB */
|
||||
adc_module->CTRLB.reg =
|
||||
config->clock_prescaler |
|
||||
resolution |
|
||||
(config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
|
||||
(config->freerunning << ADC_CTRLB_FREERUN_Pos) |
|
||||
(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
|
||||
(config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
|
||||
|
||||
/* Check validity of window thresholds */
|
||||
if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
|
||||
switch (resolution) {
|
||||
case ADC_RESOLUTION_8BIT:
|
||||
if (config->differential_mode &&
|
||||
(config->window.window_lower_value > 127 ||
|
||||
config->window.window_lower_value < -128 ||
|
||||
config->window.window_upper_value > 127 ||
|
||||
config->window.window_upper_value < -128)) {
|
||||
/* Invalid value */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
} else if (config->window.window_lower_value > 255 ||
|
||||
config->window.window_upper_value > 255){
|
||||
/* Invalid value */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
break;
|
||||
case ADC_RESOLUTION_10BIT:
|
||||
if (config->differential_mode &&
|
||||
(config->window.window_lower_value > 511 ||
|
||||
config->window.window_lower_value < -512 ||
|
||||
config->window.window_upper_value > 511 ||
|
||||
config->window.window_upper_value < -512)) {
|
||||
/* Invalid value */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
} else if (config->window.window_lower_value > 1023 ||
|
||||
config->window.window_upper_value > 1023){
|
||||
/* Invalid value */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
break;
|
||||
case ADC_RESOLUTION_12BIT:
|
||||
if (config->differential_mode &&
|
||||
(config->window.window_lower_value > 2047 ||
|
||||
config->window.window_lower_value < -2048 ||
|
||||
config->window.window_upper_value > 2047 ||
|
||||
config->window.window_upper_value < -2048)) {
|
||||
/* Invalid value */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
} else if (config->window.window_lower_value > 4095 ||
|
||||
config->window.window_upper_value > 4095){
|
||||
/* Invalid value */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
break;
|
||||
case ADC_RESOLUTION_16BIT:
|
||||
if (config->differential_mode &&
|
||||
(config->window.window_lower_value > 32767 ||
|
||||
config->window.window_lower_value < -32768 ||
|
||||
config->window.window_upper_value > 32767 ||
|
||||
config->window.window_upper_value < -32768)) {
|
||||
/* Invalid value */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
} else if (config->window.window_lower_value > 65535 ||
|
||||
config->window.window_upper_value > 65535){
|
||||
/* Invalid value */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
while (adc_is_syncing(module_inst)) {
|
||||
/* Wait for synchronization */
|
||||
}
|
||||
|
||||
/* Configure window mode */
|
||||
adc_module->WINCTRL.reg = config->window.window_mode;
|
||||
|
||||
while (adc_is_syncing(module_inst)) {
|
||||
/* Wait for synchronization */
|
||||
}
|
||||
|
||||
/* Configure lower threshold */
|
||||
adc_module->WINLT.reg =
|
||||
config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
|
||||
|
||||
while (adc_is_syncing(module_inst)) {
|
||||
/* Wait for synchronization */
|
||||
}
|
||||
|
||||
/* Configure lower threshold */
|
||||
adc_module->WINUT.reg = config->window.window_upper_value <<
|
||||
ADC_WINUT_WINUT_Pos;
|
||||
|
||||
uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
|
||||
if (inputs_to_scan > 0) {
|
||||
/*
|
||||
* Number of input sources included is the value written to INPUTSCAN
|
||||
* plus 1.
|
||||
*/
|
||||
inputs_to_scan--;
|
||||
}
|
||||
|
||||
if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
|
||||
config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
|
||||
/* Invalid number of input pins or input offset */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
while (adc_is_syncing(module_inst)) {
|
||||
/* Wait for synchronization */
|
||||
}
|
||||
|
||||
/* Configure pin scan mode and positive and negative input pins */
|
||||
adc_module->INPUTCTRL.reg =
|
||||
config->gain_factor |
|
||||
(config->pin_scan.offset_start_scan <<
|
||||
ADC_INPUTCTRL_INPUTOFFSET_Pos) |
|
||||
(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
|
||||
config->negative_input |
|
||||
config->positive_input;
|
||||
|
||||
/* Configure events */
|
||||
adc_module->EVCTRL.reg = config->event_action;
|
||||
|
||||
/* Disable all interrupts */
|
||||
adc_module->INTENCLR.reg =
|
||||
(1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) |
|
||||
(1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos);
|
||||
|
||||
if (config->correction.correction_enable){
|
||||
/* Make sure gain_correction value is valid */
|
||||
if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
} else {
|
||||
/* Set gain correction value */
|
||||
adc_module->GAINCORR.reg = config->correction.gain_correction <<
|
||||
ADC_GAINCORR_GAINCORR_Pos;
|
||||
}
|
||||
|
||||
/* Make sure offset correction value is valid */
|
||||
if (config->correction.offset_correction > 2047 ||
|
||||
config->correction.offset_correction < -2048) {
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
} else {
|
||||
/* Set offset correction value */
|
||||
adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
|
||||
ADC_OFFSETCORR_OFFSETCORR_Pos;
|
||||
}
|
||||
}
|
||||
|
||||
/* Load in the fixed device ADC calibration constants */
|
||||
adc_module->CALIB.reg =
|
||||
ADC_CALIB_BIAS_CAL(
|
||||
(*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)
|
||||
) |
|
||||
ADC_CALIB_LINEARITY_CAL(
|
||||
(*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)
|
||||
);
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initializes the ADC channel sequence
|
||||
*
|
||||
* Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one
|
||||
* automatically after a conversion done, causing the next conversion
|
||||
* to be done with the positive input equal to MUXPOS + INPUTOFFSET,
|
||||
* it is scanning continuously one by one even ADC channels are not continuous.
|
||||
*
|
||||
* Initializes the ADC channel sequence by the sequence of pin_array.
|
||||
*
|
||||
* \param[in] pin_array The array of the Mux selection for the positive ADC input
|
||||
* \param[in] size The size of pin_array
|
||||
*/
|
||||
void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size)
|
||||
{
|
||||
for (int i = 0; i < size; i++) {
|
||||
_adc_configure_ain_pin(pin_array[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initializes the ADC
|
||||
*
|
||||
* Initializes the ADC device struct and the hardware module based on the
|
||||
* given configuration struct values.
|
||||
*
|
||||
* \param[out] module_inst Pointer to the ADC software instance struct
|
||||
* \param[in] hw Pointer to the ADC module instance
|
||||
* \param[in] config Pointer to the configuration struct
|
||||
*
|
||||
* \return Status of the initialization procedure.
|
||||
* \retval STATUS_OK The initialization was successful
|
||||
* \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
|
||||
* \retval STATUS_BUSY The module is busy with a reset operation
|
||||
* \retval STATUS_ERR_DENIED The module is enabled
|
||||
*/
|
||||
enum status_code adc_init(
|
||||
struct adc_module *const module_inst,
|
||||
Adc *hw,
|
||||
struct adc_config *config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module_inst);
|
||||
Assert(hw);
|
||||
Assert(config);
|
||||
|
||||
/* Associate the software module instance with the hardware module */
|
||||
module_inst->hw = hw;
|
||||
|
||||
/* Turn on the digital interface clock */
|
||||
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
|
||||
|
||||
if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
|
||||
/* We are in the middle of a reset. Abort. */
|
||||
return STATUS_BUSY;
|
||||
}
|
||||
|
||||
if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
|
||||
/* Module must be disabled before initialization. Abort. */
|
||||
return STATUS_ERR_DENIED;
|
||||
}
|
||||
|
||||
/* Store the selected reference for later use */
|
||||
module_inst->reference = config->reference;
|
||||
|
||||
/* Make sure bandgap is enabled if requested by the config */
|
||||
if (module_inst->reference == ADC_REFERENCE_INT1V) {
|
||||
system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
|
||||
}
|
||||
|
||||
#if ADC_CALLBACK_MODE == true
|
||||
for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
|
||||
module_inst->callback[i] = NULL;
|
||||
};
|
||||
|
||||
module_inst->registered_callback_mask = 0;
|
||||
module_inst->enabled_callback_mask = 0;
|
||||
module_inst->remaining_conversions = 0;
|
||||
module_inst->job_status = STATUS_OK;
|
||||
|
||||
_adc_instances[0] = module_inst;
|
||||
|
||||
if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
|
||||
!config->freerunning) {
|
||||
module_inst->software_trigger = true;
|
||||
} else {
|
||||
module_inst->software_trigger = false;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Write configuration to module */
|
||||
return _adc_set_config(module_inst, config);
|
||||
}
|
||||
@ -0,0 +1,247 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Peripheral Analog-to-Digital Converter Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#include "adc_callback.h"
|
||||
|
||||
struct adc_module *_adc_instances[ADC_INST_NUM];
|
||||
|
||||
static void _adc_interrupt_handler(const uint8_t instance)
|
||||
{
|
||||
struct adc_module *module = _adc_instances[instance];
|
||||
|
||||
/* get interrupt flags and mask out enabled callbacks */
|
||||
uint32_t flags = module->hw->INTFLAG.reg & module->hw->INTENSET.reg;
|
||||
|
||||
if (flags & ADC_INTFLAG_RESRDY) {
|
||||
/* clear interrupt flag */
|
||||
module->hw->INTFLAG.reg = ADC_INTFLAG_RESRDY;
|
||||
|
||||
while (adc_is_syncing(module)) {
|
||||
/* Wait for synchronization */
|
||||
}
|
||||
|
||||
/* store ADC result in job buffer */
|
||||
*(module->job_buffer++) = module->hw->RESULT.reg;
|
||||
|
||||
if (--module->remaining_conversions > 0) {
|
||||
if (module->software_trigger == true) {
|
||||
adc_start_conversion(module);
|
||||
}
|
||||
} else {
|
||||
adc_disable_interrupt(module, ADC_INTERRUPT_RESULT_READY);
|
||||
if (module->job_status == STATUS_BUSY) {
|
||||
/* job is complete. update status,disable interrupt
|
||||
*and call callback */
|
||||
module->job_status = STATUS_OK;
|
||||
|
||||
if ((module->enabled_callback_mask &
|
||||
(1 << ADC_CALLBACK_READ_BUFFER)) &&
|
||||
(module->registered_callback_mask &
|
||||
(1 << ADC_CALLBACK_READ_BUFFER))) {
|
||||
(module->callback[ADC_CALLBACK_READ_BUFFER])(module);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (flags & ADC_INTFLAG_WINMON) {
|
||||
module->hw->INTFLAG.reg = ADC_INTFLAG_WINMON;
|
||||
if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_WINDOW)) &&
|
||||
(module->registered_callback_mask & (1 << ADC_CALLBACK_WINDOW))) {
|
||||
(module->callback[ADC_CALLBACK_WINDOW])(module);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (flags & ADC_INTFLAG_OVERRUN) {
|
||||
module->hw->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
|
||||
if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_ERROR)) &&
|
||||
(module->registered_callback_mask & (1 << ADC_CALLBACK_ERROR))) {
|
||||
(module->callback[ADC_CALLBACK_ERROR])(module);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/** Interrupt handler for the ADC module. */
|
||||
void ADC_Handler(void)
|
||||
{
|
||||
_adc_interrupt_handler(0);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Registers a callback
|
||||
*
|
||||
* Registers a callback function which is implemented by the user.
|
||||
*
|
||||
* \note The callback must be enabled by for the interrupt handler to call it
|
||||
* when the condition for the callback is met.
|
||||
*
|
||||
* \param[in] module Pointer to ADC software instance struct
|
||||
* \param[in] callback_func Pointer to callback function
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*
|
||||
*/
|
||||
void adc_register_callback(
|
||||
struct adc_module *const module,
|
||||
adc_callback_t callback_func,
|
||||
enum adc_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(callback_func);
|
||||
|
||||
/* Register callback function */
|
||||
module->callback[callback_type] = callback_func;
|
||||
|
||||
/* Set the bit corresponding to the callback_type */
|
||||
module->registered_callback_mask |= (1 << callback_type);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Unregisters a callback
|
||||
*
|
||||
* Unregisters a callback function which is implemented by the user.
|
||||
*
|
||||
* \param[in] module Pointer to ADC software instance struct
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*
|
||||
*/
|
||||
void adc_unregister_callback(
|
||||
struct adc_module *const module,
|
||||
enum adc_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
|
||||
/* Unregister callback function */
|
||||
module->callback[callback_type] = NULL;
|
||||
|
||||
/* Clear the bit corresponding to the callback_type */
|
||||
module->registered_callback_mask &= ~(1 << callback_type);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Read multiple samples from ADC
|
||||
*
|
||||
* Read \c samples samples from the ADC into the buffer \c buffer.
|
||||
* If there is no hardware trigger defined (event action) the
|
||||
* driver will retrigger the ADC conversion whenever a conversion
|
||||
* is complete until \c samples samples has been acquired. To avoid
|
||||
* jitter in the sampling frequency using an event trigger is advised.
|
||||
*
|
||||
* \param[in] module_inst Pointer to the ADC software instance struct
|
||||
* \param[in] samples Number of samples to acquire
|
||||
* \param[out] buffer Buffer to store the ADC samples
|
||||
*
|
||||
* \return Status of the job start.
|
||||
* \retval STATUS_OK The conversion job was started successfully and is
|
||||
* in progress
|
||||
* \retval STATUS_BUSY The ADC is already busy with another job
|
||||
*/
|
||||
enum status_code adc_read_buffer_job(
|
||||
struct adc_module *const module_inst,
|
||||
uint16_t *buffer,
|
||||
uint16_t samples)
|
||||
{
|
||||
Assert(module_inst);
|
||||
Assert(samples);
|
||||
Assert(buffer);
|
||||
|
||||
if(module_inst->remaining_conversions != 0 ||
|
||||
module_inst->job_status == STATUS_BUSY){
|
||||
return STATUS_BUSY;
|
||||
}
|
||||
|
||||
module_inst->job_status = STATUS_BUSY;
|
||||
module_inst->remaining_conversions = samples;
|
||||
module_inst->job_buffer = buffer;
|
||||
|
||||
adc_enable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
|
||||
|
||||
if(module_inst->software_trigger == true) {
|
||||
adc_start_conversion(module_inst);
|
||||
}
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Gets the status of a job
|
||||
*
|
||||
* Gets the status of an ongoing or the last job.
|
||||
*
|
||||
* \param [in] module_inst Pointer to the ADC software instance struct
|
||||
* \param [in] type Type of job to get status
|
||||
*
|
||||
* \return Status of the job.
|
||||
*/
|
||||
enum status_code adc_get_job_status(
|
||||
struct adc_module *module_inst,
|
||||
enum adc_job_type type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module_inst);
|
||||
|
||||
if (type == ADC_JOB_READ_BUFFER ) {
|
||||
return module_inst->job_status;
|
||||
} else {
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Aborts an ongoing job
|
||||
*
|
||||
* Aborts an ongoing job.
|
||||
*
|
||||
* \param [in] module_inst Pointer to the ADC software instance struct
|
||||
* \param [in] type Type of job to abort
|
||||
*/
|
||||
void adc_abort_job(
|
||||
struct adc_module *module_inst,
|
||||
enum adc_job_type type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module_inst);
|
||||
|
||||
if (type == ADC_JOB_READ_BUFFER) {
|
||||
/* Disable interrupt */
|
||||
adc_disable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
|
||||
/* Mark job as aborted */
|
||||
module_inst->job_status = STATUS_ABORTED;
|
||||
module_inst->remaining_conversions = 0;
|
||||
}
|
||||
}
|
||||
|
||||
@ -0,0 +1,718 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM ADC functionality
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef ADC_FEATURE_H_INCLUDED
|
||||
#define ADC_FEATURE_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup asfdoc_sam0_adc_group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if ADC_CALLBACK_MODE == true
|
||||
# include <system_interrupt.h>
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern struct adc_module *_adc_instances[ADC_INST_NUM];
|
||||
#endif
|
||||
|
||||
/** Forward definition of the device instance. */
|
||||
struct adc_module;
|
||||
|
||||
/** Type of the callback functions. */
|
||||
typedef void (*adc_callback_t)(struct adc_module *const module);
|
||||
|
||||
/**
|
||||
* \brief ADC Callback enum
|
||||
*
|
||||
* Callback types for ADC callback driver.
|
||||
*
|
||||
*/
|
||||
enum adc_callback {
|
||||
/** Callback for buffer received */
|
||||
ADC_CALLBACK_READ_BUFFER,
|
||||
/** Callback when window is hit */
|
||||
ADC_CALLBACK_WINDOW,
|
||||
/** Callback for error */
|
||||
ADC_CALLBACK_ERROR,
|
||||
# if !defined(__DOXYGEN__)
|
||||
/** Number of available callbacks */
|
||||
ADC_CALLBACK_N,
|
||||
# endif
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief ADC reference voltage enum
|
||||
*
|
||||
* Enum for the possible reference voltages for the ADC.
|
||||
*
|
||||
*/
|
||||
enum adc_reference {
|
||||
/** 1.0V voltage reference */
|
||||
ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V,
|
||||
/** 1/1.48V<SUB>CC</SUB> reference */
|
||||
ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
|
||||
/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */
|
||||
ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
|
||||
/** External reference A */
|
||||
ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA,
|
||||
/** External reference B */
|
||||
ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC clock prescaler enum
|
||||
*
|
||||
* Enum for the possible clock prescaler values for the ADC.
|
||||
*
|
||||
*/
|
||||
enum adc_clock_prescaler {
|
||||
/** ADC clock division factor 4 */
|
||||
ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4,
|
||||
/** ADC clock division factor 8 */
|
||||
ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8,
|
||||
/** ADC clock division factor 16 */
|
||||
ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16,
|
||||
/** ADC clock division factor 32 */
|
||||
ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32,
|
||||
/** ADC clock division factor 64 */
|
||||
ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64,
|
||||
/** ADC clock division factor 128 */
|
||||
ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
|
||||
/** ADC clock division factor 256 */
|
||||
ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
|
||||
/** ADC clock division factor 512 */
|
||||
ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC resolution enum
|
||||
*
|
||||
* Enum for the possible resolution values for the ADC.
|
||||
*
|
||||
*/
|
||||
enum adc_resolution {
|
||||
/** ADC 12-bit resolution */
|
||||
ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT,
|
||||
/** ADC 16-bit resolution using oversampling and decimation */
|
||||
ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT,
|
||||
/** ADC 10-bit resolution */
|
||||
ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT,
|
||||
/** ADC 8-bit resolution */
|
||||
ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT,
|
||||
/** ADC 13-bit resolution using oversampling and decimation */
|
||||
ADC_RESOLUTION_13BIT,
|
||||
/** ADC 14-bit resolution using oversampling and decimation */
|
||||
ADC_RESOLUTION_14BIT,
|
||||
/** ADC 15-bit resolution using oversampling and decimation */
|
||||
ADC_RESOLUTION_15BIT,
|
||||
/** ADC 16-bit result register for use with averaging. When using this mode
|
||||
* the ADC result register will be set to 16-bit wide, and the number of
|
||||
* samples to accumulate and the division factor is configured by the
|
||||
* \ref adc_config.accumulate_samples and \ref adc_config.divide_result
|
||||
* members in the configuration struct.
|
||||
*/
|
||||
ADC_RESOLUTION_CUSTOM,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC window monitor mode enum
|
||||
*
|
||||
* Enum for the possible window monitor modes for the ADC.
|
||||
*
|
||||
*/
|
||||
enum adc_window_mode {
|
||||
/** No window mode */
|
||||
ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE,
|
||||
/** RESULT > WINLT */
|
||||
ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1,
|
||||
/** RESULT < WINUT */
|
||||
ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2,
|
||||
/** WINLT < RESULT < WINUT */
|
||||
ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3,
|
||||
/** !(WINLT < RESULT < WINUT) */
|
||||
ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC gain factor selection enum
|
||||
*
|
||||
* Enum for the possible gain factor values for the ADC.
|
||||
*
|
||||
*/
|
||||
enum adc_gain_factor {
|
||||
/** 1x gain */
|
||||
ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X,
|
||||
/** 2x gain */
|
||||
ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X,
|
||||
/** 4x gain */
|
||||
ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X,
|
||||
/** 8x gain */
|
||||
ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X,
|
||||
/** 16x gain */
|
||||
ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X,
|
||||
/** 1/2x gain */
|
||||
ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC event action enum
|
||||
*
|
||||
* Enum for the possible actions to take on an incoming event.
|
||||
*
|
||||
*/
|
||||
enum adc_event_action {
|
||||
/** Event action disabled */
|
||||
ADC_EVENT_ACTION_DISABLED = 0,
|
||||
/** Flush ADC and start conversion */
|
||||
ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI,
|
||||
/** Start conversion */
|
||||
ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC positive MUX input selection enum
|
||||
*
|
||||
* Enum for the possible positive MUX input selections for the ADC.
|
||||
*
|
||||
*/
|
||||
enum adc_positive_input {
|
||||
/** ADC0 pin */
|
||||
ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0,
|
||||
/** ADC1 pin */
|
||||
ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1,
|
||||
/** ADC2 pin */
|
||||
ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2,
|
||||
/** ADC3 pin */
|
||||
ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3,
|
||||
/** ADC4 pin */
|
||||
ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4,
|
||||
/** ADC5 pin */
|
||||
ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5,
|
||||
/** ADC6 pin */
|
||||
ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6,
|
||||
/** ADC7 pin */
|
||||
ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7,
|
||||
/** ADC8 pin */
|
||||
ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8,
|
||||
/** ADC9 pin */
|
||||
ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9,
|
||||
/** ADC10 pin */
|
||||
ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10,
|
||||
/** ADC11 pin */
|
||||
ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11,
|
||||
/** ADC12 pin */
|
||||
ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12,
|
||||
/** ADC13 pin */
|
||||
ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13,
|
||||
/** ADC14 pin */
|
||||
ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14,
|
||||
/** ADC15 pin */
|
||||
ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15,
|
||||
/** ADC16 pin */
|
||||
ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16,
|
||||
/** ADC17 pin */
|
||||
ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17,
|
||||
/** ADC18 pin */
|
||||
ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18,
|
||||
/** ADC19 pin */
|
||||
ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19,
|
||||
/** Temperature reference */
|
||||
ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP,
|
||||
/** Bandgap voltage */
|
||||
ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP,
|
||||
/** 1/4 scaled core supply */
|
||||
ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
|
||||
/** 1/4 scaled I/O supply */
|
||||
ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
|
||||
/** DAC input */
|
||||
ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC negative Multiplexer(MUX) input selection enum
|
||||
*
|
||||
* Enum for the possible negative Multiplexer(MUX) input selections for the ADC.
|
||||
*
|
||||
*/
|
||||
enum adc_negative_input {
|
||||
/** ADC0 pin */
|
||||
ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0,
|
||||
/** ADC1 pin */
|
||||
ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1,
|
||||
/** ADC2 pin */
|
||||
ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2,
|
||||
/** ADC3 pin */
|
||||
ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3,
|
||||
/** ADC4 pin */
|
||||
ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4,
|
||||
/** ADC5 pin */
|
||||
ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5,
|
||||
/** ADC6 pin */
|
||||
ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6,
|
||||
/** ADC7 pin */
|
||||
ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7,
|
||||
/** Internal ground */
|
||||
ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND,
|
||||
/** I/O ground */
|
||||
ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC number of accumulated samples enum
|
||||
*
|
||||
* Enum for the possible numbers of ADC samples to accumulate.
|
||||
* This setting is only used when the \ref ADC_RESOLUTION_CUSTOM
|
||||
* resolution setting is used.
|
||||
*
|
||||
*/
|
||||
enum adc_accumulate_samples {
|
||||
/** No averaging */
|
||||
ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1,
|
||||
/** Average 2 samples */
|
||||
ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2,
|
||||
/** Average 4 samples */
|
||||
ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4,
|
||||
/** Average 8 samples */
|
||||
ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8,
|
||||
/** Average 16 samples */
|
||||
ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16,
|
||||
/** Average 32 samples */
|
||||
ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32,
|
||||
/** Average 64 samples */
|
||||
ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64,
|
||||
/** Average 128 samples */
|
||||
ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128,
|
||||
/** Average 256 samples */
|
||||
ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256,
|
||||
/** Average 512 samples */
|
||||
ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512,
|
||||
/** Average 1024 samples */
|
||||
ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC possible dividers for the result register
|
||||
*
|
||||
* Enum for the possible division factors to use when accumulating
|
||||
* multiple samples. To keep the same resolution for the averaged
|
||||
* result and the actual input value, the division factor must
|
||||
* be equal to the number of samples accumulated. This setting is only
|
||||
* used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
|
||||
*/
|
||||
enum adc_divide_result {
|
||||
/** Don't divide result register after accumulation */
|
||||
ADC_DIVIDE_RESULT_DISABLE = 0,
|
||||
/** Divide result register by 2 after accumulation */
|
||||
ADC_DIVIDE_RESULT_2 = 1,
|
||||
/** Divide result register by 4 after accumulation */
|
||||
ADC_DIVIDE_RESULT_4 = 2,
|
||||
/** Divide result register by 8 after accumulation */
|
||||
ADC_DIVIDE_RESULT_8 = 3,
|
||||
/** Divide result register by 16 after accumulation */
|
||||
ADC_DIVIDE_RESULT_16 = 4,
|
||||
/** Divide result register by 32 after accumulation */
|
||||
ADC_DIVIDE_RESULT_32 = 5,
|
||||
/** Divide result register by 64 after accumulation */
|
||||
ADC_DIVIDE_RESULT_64 = 6,
|
||||
/** Divide result register by 128 after accumulation */
|
||||
ADC_DIVIDE_RESULT_128 = 7,
|
||||
};
|
||||
|
||||
#if ADC_CALLBACK_MODE == true
|
||||
/**
|
||||
* Enum for the possible ADC interrupt flags.
|
||||
*/
|
||||
enum adc_interrupt_flag {
|
||||
/** ADC result ready */
|
||||
ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
|
||||
/** Window monitor match */
|
||||
ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON,
|
||||
/** ADC result overwritten before read */
|
||||
ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN,
|
||||
};
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief ADC oversampling and decimation enum
|
||||
*
|
||||
* Enum for the possible numbers of bits resolution can be increased by when
|
||||
* using oversampling and decimation.
|
||||
*
|
||||
*/
|
||||
enum adc_oversampling_and_decimation {
|
||||
/** Don't use oversampling and decimation mode */
|
||||
ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
|
||||
/** 1-bit resolution increase */
|
||||
ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
|
||||
/** 2-bit resolution increase */
|
||||
ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
|
||||
/** 3-bit resolution increase */
|
||||
ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
|
||||
/** 4-bit resolution increase */
|
||||
ADC_OVERSAMPLING_AND_DECIMATION_4BIT
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Window monitor configuration structure
|
||||
*
|
||||
* Window monitor configuration structure.
|
||||
*/
|
||||
struct adc_window_config {
|
||||
/** Selected window mode */
|
||||
enum adc_window_mode window_mode;
|
||||
/** Lower window value */
|
||||
int32_t window_lower_value;
|
||||
/** Upper window value */
|
||||
int32_t window_upper_value;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC event enable/disable structure.
|
||||
*
|
||||
* Event flags for the ADC module. This is used to enable and
|
||||
* disable events via \ref adc_enable_events() and \ref adc_disable_events().
|
||||
*/
|
||||
struct adc_events {
|
||||
/** Enable event generation on conversion done */
|
||||
bool generate_event_on_conversion_done;
|
||||
/** Enable event generation on window monitor */
|
||||
bool generate_event_on_window_monitor;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Gain and offset correction configuration structure
|
||||
*
|
||||
* Gain and offset correction configuration structure.
|
||||
* Part of the \ref adc_config struct and will be initialized by
|
||||
* \ref adc_get_config_defaults.
|
||||
*/
|
||||
struct adc_correction_config {
|
||||
/**
|
||||
* Enables correction for gain and offset based on values of gain_correction and
|
||||
* offset_correction if set to true
|
||||
*/
|
||||
bool correction_enable;
|
||||
/**
|
||||
* This value defines how the ADC conversion result is compensated for gain
|
||||
* error before written to the result register. This is a fractional value,
|
||||
* 1-bit integer plus an 11-bit fraction, therefore
|
||||
* 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
|
||||
* \c 0b010000000000 to \c 0b111111111111.
|
||||
*/
|
||||
uint16_t gain_correction;
|
||||
/**
|
||||
* This value defines how the ADC conversion result is compensated for
|
||||
* offset error before written to the result register. This is a 12-bit
|
||||
* value in two's complement format.
|
||||
*/
|
||||
int16_t offset_correction;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Pin scan configuration structure
|
||||
*
|
||||
* Pin scan configuration structure. Part of the \ref adc_config struct and will
|
||||
* be initialized by \ref adc_get_config_defaults.
|
||||
*/
|
||||
struct adc_pin_scan_config {
|
||||
/**
|
||||
* Offset (relative to selected positive input) of the first input pin to be
|
||||
* used in pin scan mode
|
||||
*/
|
||||
uint8_t offset_start_scan;
|
||||
/**
|
||||
* Number of input pins to scan in pin scan mode. A value below two will
|
||||
* disable pin scan mode.
|
||||
*/
|
||||
uint8_t inputs_to_scan;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC configuration structure
|
||||
*
|
||||
* Configuration structure for an ADC instance. This structure should be
|
||||
* initialized by the \ref adc_get_config_defaults()
|
||||
* function before being modified by the user application.
|
||||
*/
|
||||
struct adc_config {
|
||||
/** GCLK generator used to clock the peripheral */
|
||||
enum gclk_generator clock_source;
|
||||
/** Voltage reference */
|
||||
enum adc_reference reference;
|
||||
/** Clock prescaler */
|
||||
enum adc_clock_prescaler clock_prescaler;
|
||||
/** Result resolution */
|
||||
enum adc_resolution resolution;
|
||||
/** Gain factor */
|
||||
enum adc_gain_factor gain_factor;
|
||||
/** Positive Multiplexer (MUX) input */
|
||||
enum adc_positive_input positive_input;
|
||||
/** Negative MUX input. For singled-ended conversion mode, the negative
|
||||
* input must be connected to ground. This ground could be the internal
|
||||
* GND, IOGND or an external ground connected to a pin. */
|
||||
enum adc_negative_input negative_input;
|
||||
/** Number of ADC samples to accumulate when using the
|
||||
* \c ADC_RESOLUTION_CUSTOM mode. Note: if the result width increases,
|
||||
* result resolution will be changed accordingly.
|
||||
*/
|
||||
enum adc_accumulate_samples accumulate_samples;
|
||||
/** Division ration when using the ADC_RESOLUTION_CUSTOM mode */
|
||||
enum adc_divide_result divide_result;
|
||||
/** Left adjusted result */
|
||||
bool left_adjust;
|
||||
/** Enables differential mode if true.
|
||||
* if false, ADC will run in singled-ended mode. */
|
||||
bool differential_mode;
|
||||
/** Enables free running mode if true */
|
||||
bool freerunning;
|
||||
/** Enables ADC in standby sleep mode if true */
|
||||
bool run_in_standby;
|
||||
/**
|
||||
* Enables reference buffer offset compensation if true.
|
||||
* This will increase the accuracy of the gain stage, but decreases the input
|
||||
* impedance; therefore the startup time of the reference must be increased.
|
||||
*/
|
||||
bool reference_compensation_enable;
|
||||
/**
|
||||
* This value (0-63) control the ADC sampling time in number of half ADC
|
||||
* prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
|
||||
* controlling the ADC input impedance. Sampling time is set according to
|
||||
* the formula:
|
||||
* Sample time = (sample_length+1) * (ADCclk / 2).
|
||||
*/
|
||||
uint8_t sample_length;
|
||||
/** Window monitor configuration structure */
|
||||
struct adc_window_config window;
|
||||
/** Gain and offset correction configuration structure */
|
||||
struct adc_correction_config correction;
|
||||
/** Event action to take on incoming event */
|
||||
enum adc_event_action event_action;
|
||||
/** Pin scan configuration structure */
|
||||
struct adc_pin_scan_config pin_scan;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief ADC software device instance structure.
|
||||
*
|
||||
* ADC software instance structure, used to retain software state information
|
||||
* of an associated hardware module instance.
|
||||
*
|
||||
* \note The fields of this structure should not be altered by the user
|
||||
* application; they are reserved for module-internal use only.
|
||||
*/
|
||||
struct adc_module {
|
||||
#if !defined(__DOXYGEN__)
|
||||
/** Pointer to ADC hardware module */
|
||||
Adc *hw;
|
||||
/** Keep reference configuration so we know when enable is called */
|
||||
enum adc_reference reference;
|
||||
# if ADC_CALLBACK_MODE == true
|
||||
/** Array to store callback functions */
|
||||
adc_callback_t callback[ADC_CALLBACK_N];
|
||||
/** Pointer to buffer used for ADC results */
|
||||
volatile uint16_t *job_buffer;
|
||||
/** Remaining number of conversions in current job */
|
||||
volatile uint16_t remaining_conversions;
|
||||
/** Bit mask for callbacks registered */
|
||||
uint8_t registered_callback_mask;
|
||||
/** Bit mask for callbacks enabled */
|
||||
uint8_t enabled_callback_mask;
|
||||
/** Holds the status of the ongoing or last conversion job */
|
||||
volatile enum status_code job_status;
|
||||
/** If software triggering is needed */
|
||||
bool software_trigger;
|
||||
# endif
|
||||
#endif
|
||||
};
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/**
|
||||
* \brief Determines if the hardware module(s) are currently synchronizing to the bus.
|
||||
*
|
||||
* Checks to see if the underlying hardware peripheral module(s) are currently
|
||||
* synchronizing across multiple clock domains to the hardware bus. This
|
||||
* function can be used to delay further operations on a module until such time
|
||||
* that it is ready, to prevent blocking delays for synchronization in the
|
||||
* user application.
|
||||
*
|
||||
* \param[in] module_inst Pointer to the ADC software instance struct
|
||||
*
|
||||
* \return Synchronization status of the underlying hardware module(s).
|
||||
*
|
||||
* \retval true if the module synchronization is ongoing
|
||||
* \retval false if the module has completed synchronization
|
||||
*/
|
||||
static inline bool adc_is_syncing(
|
||||
struct adc_module *const module_inst)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module_inst);
|
||||
|
||||
Adc *const adc_module = module_inst->hw;
|
||||
|
||||
if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \name ADC Gain and Pin Scan Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Sets ADC gain factor
|
||||
*
|
||||
* Sets the ADC gain factor to a specified gain setting.
|
||||
*
|
||||
* \param[in] module_inst Pointer to the ADC software instance struct
|
||||
* \param[in] gain_factor Gain factor value to set
|
||||
*/
|
||||
static inline void adc_set_gain(
|
||||
struct adc_module *const module_inst,
|
||||
const enum adc_gain_factor gain_factor)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module_inst);
|
||||
Assert(module_inst->hw);
|
||||
|
||||
Adc *const adc_module = module_inst->hw;
|
||||
|
||||
while (adc_is_syncing(module_inst)) {
|
||||
/* Wait for synchronization */
|
||||
}
|
||||
|
||||
/* Set new gain factor */
|
||||
adc_module->INPUTCTRL.reg =
|
||||
(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) |
|
||||
(gain_factor);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Sets the ADC pin scan mode
|
||||
*
|
||||
* Configures the pin scan mode of the ADC module. In pin scan mode, the first
|
||||
* conversion will start at the configured positive input + start_offset. When
|
||||
* a conversion is done, a conversion will start on the next input, until
|
||||
* \c inputs_to_scan number of conversions are made.
|
||||
*
|
||||
* \param[in] module_inst Pointer to the ADC software instance struct
|
||||
* \param[in] inputs_to_scan Number of input pins to perform a conversion on
|
||||
* (must be two or more)
|
||||
* \param[in] start_offset Offset of first pin to scan (relative to
|
||||
* configured positive input)
|
||||
*
|
||||
* \return Status of the pin scan configuration set request.
|
||||
*
|
||||
* \retval STATUS_OK Pin scan mode has been set successfully
|
||||
* \retval STATUS_ERR_INVALID_ARG Number of input pins to scan or offset has
|
||||
* an invalid value
|
||||
*/
|
||||
static inline enum status_code adc_set_pin_scan_mode(
|
||||
struct adc_module *const module_inst,
|
||||
uint8_t inputs_to_scan,
|
||||
const uint8_t start_offset)
|
||||
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module_inst);
|
||||
Assert(module_inst->hw);
|
||||
|
||||
Adc *const adc_module = module_inst->hw;
|
||||
|
||||
if (inputs_to_scan > 0) {
|
||||
/*
|
||||
* Number of input sources included is the value written to INPUTSCAN
|
||||
* plus 1.
|
||||
*/
|
||||
inputs_to_scan--;
|
||||
}
|
||||
|
||||
if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
|
||||
start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
|
||||
/* Invalid number of input pins */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
while (adc_is_syncing(module_inst)) {
|
||||
/* Wait for synchronization */
|
||||
}
|
||||
|
||||
/* Set pin scan mode */
|
||||
adc_module->INPUTCTRL.reg =
|
||||
(adc_module->INPUTCTRL.reg &
|
||||
~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) |
|
||||
(start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
|
||||
(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos);
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disables pin scan mode
|
||||
*
|
||||
* Disables pin scan mode. The next conversion will be made on only one pin
|
||||
* (the configured positive input pin).
|
||||
*
|
||||
* \param[in] module_inst Pointer to the ADC software instance struct
|
||||
*/
|
||||
static inline void adc_disable_pin_scan_mode(
|
||||
struct adc_module *const module_inst)
|
||||
{
|
||||
/* Disable pin scan mode */
|
||||
adc_set_pin_scan_mode(module_inst, 0, 0);
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* ADC_FEATURE_H_INCLUDED */
|
||||
|
||||
@ -0,0 +1,699 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM External Interrupt Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef EXTINT_H_INCLUDED
|
||||
#define EXTINT_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \defgroup asfdoc_sam0_extint_group SAM External Interrupt (EXTINT) Driver
|
||||
*
|
||||
* This driver for Atmel® | SMART ARM®-based microcontrollers provides
|
||||
* an interface for the configuration and management of external interrupts
|
||||
* generated by the physical device pins, including edge detection.
|
||||
* The following driver API modes are covered by this
|
||||
* manual:
|
||||
*
|
||||
* - Polled APIs
|
||||
* \if EXTINT_CALLBACK_MODE
|
||||
* - Callback APIs
|
||||
* \endif
|
||||
*
|
||||
* The following peripheral is used by this module:
|
||||
* - EIC (External Interrupt Controller)
|
||||
*
|
||||
* The following devices can use this module:
|
||||
* - Atmel | SMART SAM D20/D21
|
||||
* - Atmel | SMART SAM R21
|
||||
* - Atmel | SMART SAM D09/D10/D11
|
||||
* - Atmel | SMART SAM L21/L22
|
||||
* - Atmel | SMART SAM DA1
|
||||
* - Atmel | SMART SAM C20/C21
|
||||
* - Atmel | SMART SAM HA1
|
||||
* - Atmel | SMART SAM R34/R35
|
||||
*
|
||||
* The outline of this documentation is as follows:
|
||||
* - \ref asfdoc_sam0_extint_prerequisites
|
||||
* - \ref asfdoc_sam0_extint_module_overview
|
||||
* - \ref asfdoc_sam0_extint_special_considerations
|
||||
* - \ref asfdoc_sam0_extint_extra_info
|
||||
* - \ref asfdoc_sam0_extint_examples
|
||||
* - \ref asfdoc_sam0_extint_api_overview
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_extint_prerequisites Prerequisites
|
||||
*
|
||||
* There are no prerequisites for this module.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_extint_module_overview Module Overview
|
||||
*
|
||||
* The External Interrupt (EXTINT) module provides a method of asynchronously
|
||||
* detecting rising edge, falling edge, or specific level detection on individual
|
||||
* I/O pins of a device. This detection can then be used to trigger a software
|
||||
* interrupt or event, or polled for later use if required. External interrupts
|
||||
* can also optionally be used to automatically wake up the device from sleep
|
||||
* mode, allowing the device to conserve power while still being able to react
|
||||
* to an external stimulus in a timely manner.
|
||||
*
|
||||
* \subsection asfdoc_sam0_extint_logical_channels Logical Channels
|
||||
* The External Interrupt module contains a number of logical channels, each of
|
||||
* which is capable of being individually configured for a given pin routing,
|
||||
* detection mode, and filtering/wake up characteristics.
|
||||
*
|
||||
* Each individual logical external interrupt channel may be routed to a single
|
||||
* physical device I/O pin in order to detect a particular edge or level of the
|
||||
* incoming signal.
|
||||
*
|
||||
* \subsection asfdoc_sam0_extint_module_overview_nmi_chanel NMI Channels
|
||||
*
|
||||
* One or more Non Maskable Interrupt (NMI) channels are provided within each
|
||||
* physical External Interrupt Controller module, allowing a single physical pin
|
||||
* of the device to fire a single NMI interrupt in response to a particular
|
||||
* edge or level stimulus. An NMI cannot, as the name suggests, be disabled in
|
||||
* firmware and will take precedence over any in-progress interrupt sources.
|
||||
*
|
||||
* NMIs can be used to implement critical device features such as forced
|
||||
* software reset or other functionality where the action should be executed in
|
||||
* preference to all other running code with a minimum amount of latency.
|
||||
*
|
||||
* \subsection asfdoc_sam0_extint_module_overview_filtering Input Filtering and Detection
|
||||
*
|
||||
* To reduce the possibility of noise or other transient signals causing
|
||||
* unwanted device wake-ups, interrupts, and/or events via an external interrupt
|
||||
* channel. A hardware signal filter can be enabled on individual channels. This
|
||||
* filter provides a Majority-of-Three voter filter on the incoming signal, so
|
||||
* that the input state is considered to be the majority vote of three
|
||||
* subsequent samples of the pin input buffer. The possible sampled input and
|
||||
* resulting filtered output when the filter is enabled is shown in
|
||||
* \ref asfdoc_sam0_extint_filter_table "the table below".
|
||||
*
|
||||
* \anchor asfdoc_sam0_extint_filter_table
|
||||
* <table>
|
||||
* <caption>Sampled Input and Resulting Filtered Output</caption>
|
||||
* <tr>
|
||||
* <th>Input Sample 1</th>
|
||||
* <th>Input Sample 2</th>
|
||||
* <th>Input Sample 3</th>
|
||||
* <th>Filtered Output</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>0</td> <td>0</td> <td>0</td> <td>0</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>0</td> <td>0</td> <td>1</td> <td>0</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>0</td> <td>1</td> <td>0</td> <td>0</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>0</td> <td>1</td> <td>1</td> <td>1</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>1</td> <td>0</td> <td>0</td> <td>0</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>1</td> <td>0</td> <td>1</td> <td>1</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>1</td> <td>1</td> <td>0</td> <td>1</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>1</td> <td>1</td> <td>1</td> <td>1</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*
|
||||
* \subsection asfdoc_sam0_extint_module_overview_events Events and Interrupts
|
||||
*
|
||||
* Channel detection states may be polled inside the application for synchronous
|
||||
* detection, or events and interrupts may be used for asynchronous behavior.
|
||||
* Each channel can be configured to give an asynchronous hardware event (which
|
||||
* may in turn trigger actions in other hardware modules) or an asynchronous
|
||||
* software interrupt.
|
||||
*
|
||||
* \note The connection of events between modules requires the use of the
|
||||
* \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
|
||||
* to route output event of one module to the input event of another.
|
||||
* For more information on event routing, refer to the event driver
|
||||
* documentation.
|
||||
*
|
||||
* \subsection asfdoc_sam0_extint_module_overview_physical Physical Connection
|
||||
*
|
||||
* \ref asfdoc_sam0_extint_int_connections "The diagram below" shows how this
|
||||
* module is interconnected within the device.
|
||||
*
|
||||
* \anchor asfdoc_sam0_extint_int_connections
|
||||
* \dot
|
||||
* digraph overview {
|
||||
* node [label="Port Pad" shape=square] pad;
|
||||
*
|
||||
* subgraph driver {
|
||||
* node [label="Peripheral MUX" shape=trapezium] pinmux;
|
||||
* node [label="EIC Module" shape=ellipse] eic;
|
||||
* node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
|
||||
* }
|
||||
*
|
||||
* pinmux -> eic;
|
||||
* pad -> pinmux;
|
||||
* pinmux -> peripherals;
|
||||
* }
|
||||
* \enddot
|
||||
*
|
||||
* \section asfdoc_sam0_extint_special_considerations Special Considerations
|
||||
*
|
||||
* Not all devices support disabling of the NMI channel(s) detection mode - see
|
||||
* your device datasheet.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_extint_extra_info Extra Information
|
||||
*
|
||||
* For extra information, see \ref asfdoc_sam0_extint_extra. This includes:
|
||||
* - \ref asfdoc_sam0_extint_extra_acronyms
|
||||
* - \ref asfdoc_sam0_extint_extra_dependencies
|
||||
* - \ref asfdoc_sam0_extint_extra_errata
|
||||
* - \ref asfdoc_sam0_extint_extra_history
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_extint_examples Examples
|
||||
*
|
||||
* For a list of examples related to this driver, see
|
||||
* \ref asfdoc_sam0_extint_exqsg.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_extint_api_overview API Overview
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <pinmux.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief External interrupt edge detection configuration enum.
|
||||
*
|
||||
* Enum for the possible signal edge detection modes of the External
|
||||
* Interrupt Controller module.
|
||||
*/
|
||||
enum extint_detect {
|
||||
/** No edge detection. Not allowed as a NMI detection mode on some
|
||||
* devices. */
|
||||
EXTINT_DETECT_NONE = 0,
|
||||
/** Detect rising signal edges */
|
||||
EXTINT_DETECT_RISING = 1,
|
||||
/** Detect falling signal edges */
|
||||
EXTINT_DETECT_FALLING = 2,
|
||||
/** Detect both signal edges */
|
||||
EXTINT_DETECT_BOTH = 3,
|
||||
/** Detect high signal levels */
|
||||
EXTINT_DETECT_HIGH = 4,
|
||||
/** Detect low signal levels */
|
||||
EXTINT_DETECT_LOW = 5,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief External interrupt internal pull configuration enum.
|
||||
*
|
||||
* Enum for the possible pin internal pull configurations.
|
||||
*
|
||||
* \note Disabling the internal pull resistor is not recommended if the driver
|
||||
* is used in interrupt (callback) mode, due the possibility of floating
|
||||
* inputs generating continuous interrupts.
|
||||
*/
|
||||
enum extint_pull {
|
||||
/** Internal pull-up resistor is enabled on the pin */
|
||||
EXTINT_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP,
|
||||
/** Internal pull-down resistor is enabled on the pin */
|
||||
EXTINT_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
|
||||
/** Internal pull resistor is disconnected from the pin */
|
||||
EXTINT_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
|
||||
};
|
||||
|
||||
/** The EIC is clocked by GCLK_EIC. */
|
||||
#define EXTINT_CLK_GCLK 0
|
||||
/** The EIC is clocked by CLK_ULP32K. */
|
||||
#define EXTINT_CLK_ULP32K 1
|
||||
|
||||
/**
|
||||
* \brief External Interrupt Controller channel configuration structure.
|
||||
*
|
||||
* Configuration structure for the edge detection mode of an external
|
||||
* interrupt channel.
|
||||
*/
|
||||
struct extint_chan_conf {
|
||||
/** GPIO pin the NMI should be connected to */
|
||||
uint32_t gpio_pin;
|
||||
/** MUX position the GPIO pin should be configured to */
|
||||
uint32_t gpio_pin_mux;
|
||||
/** Internal pull to enable on the input pin */
|
||||
enum extint_pull gpio_pin_pull;
|
||||
#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35)
|
||||
/** Enable asynchronous edge detection. */
|
||||
bool enable_async_edge_detection;
|
||||
#else
|
||||
/** Wake up the device if the channel interrupt fires during sleep mode */
|
||||
bool wake_if_sleeping;
|
||||
#endif
|
||||
/** Filter the raw input signal to prevent noise from triggering an
|
||||
* interrupt accidentally, using a three sample majority filter */
|
||||
bool filter_input_signal;
|
||||
/** Edge detection mode to use */
|
||||
enum extint_detect detection_criteria;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief External Interrupt event enable/disable structure.
|
||||
*
|
||||
* Event flags for the \ref extint_enable_events() and
|
||||
* \ref extint_disable_events().
|
||||
*/
|
||||
struct extint_events {
|
||||
/** If \c true, an event will be generated when an external interrupt
|
||||
* channel detection state changes */
|
||||
bool generate_event_on_detect[32 * EIC_INST_NUM];
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief External Interrupt Controller NMI configuration structure.
|
||||
*
|
||||
* Configuration structure for the edge detection mode of an external
|
||||
* interrupt NMI channel.
|
||||
*/
|
||||
struct extint_nmi_conf {
|
||||
/** GPIO pin the NMI should be connected to */
|
||||
uint32_t gpio_pin;
|
||||
/** MUX position the GPIO pin should be configured to */
|
||||
uint32_t gpio_pin_mux;
|
||||
/** Internal pull to enable on the input pin */
|
||||
enum extint_pull gpio_pin_pull;
|
||||
/** Filter the raw input signal to prevent noise from triggering an
|
||||
* interrupt accidentally, using a three sample majority filter */
|
||||
bool filter_input_signal;
|
||||
/** Edge detection mode to use. Not all devices support all possible
|
||||
* detection modes for NMIs.
|
||||
*/
|
||||
enum extint_detect detection_criteria;
|
||||
#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35)
|
||||
/** Enable asynchronous edge detection. */
|
||||
bool enable_async_edge_detection;
|
||||
#endif
|
||||
};
|
||||
|
||||
#if EXTINT_CALLBACK_MODE == true
|
||||
/** Type definition for an EXTINT module callback function */
|
||||
typedef void (*extint_callback_t)(void);
|
||||
|
||||
#ifndef EIC_NUMBER_OF_INTERRUPTS
|
||||
# define EIC_NUMBER_OF_INTERRUPTS 16
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
/** \internal
|
||||
* Internal EXTINT module device instance structure definition.
|
||||
*/
|
||||
struct _extint_module
|
||||
{
|
||||
# if EXTINT_CALLBACK_MODE == true
|
||||
/** Asynchronous channel callback table, for user-registered handlers */
|
||||
extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS];
|
||||
# else
|
||||
/** Dummy value to ensure the struct has at least one member */
|
||||
uint8_t _dummy;
|
||||
# endif
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Retrieves the base EIC module address from a given channel number.
|
||||
*
|
||||
* Retrieves the base address of a EIC hardware module associated with the
|
||||
* given external interrupt channel.
|
||||
*
|
||||
* \param[in] channel External interrupt channel index to convert
|
||||
*
|
||||
* \return Base address of the associated EIC module.
|
||||
*/
|
||||
static inline Eic * _extint_get_eic_from_channel(
|
||||
const uint8_t channel)
|
||||
{
|
||||
uint8_t eic_index = (channel / 32);
|
||||
|
||||
if (eic_index < EIC_INST_NUM) {
|
||||
/* Array of available EICs */
|
||||
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
|
||||
|
||||
return eics[eic_index];
|
||||
} else {
|
||||
Assert(false);
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieves the base EIC module address from a given NMI channel number.
|
||||
*
|
||||
* Retrieves the base address of a EIC hardware module associated with the
|
||||
* given non-maskable external interrupt channel.
|
||||
*
|
||||
* \param[in] nmi_channel Non-Maskable interrupt channel index to convert
|
||||
*
|
||||
* \return Base address of the associated EIC module.
|
||||
*/
|
||||
static inline Eic * _extint_get_eic_from_nmi(
|
||||
const uint8_t nmi_channel)
|
||||
{
|
||||
uint8_t eic_index = nmi_channel;
|
||||
|
||||
if (eic_index < EIC_INST_NUM) {
|
||||
/* Array of available EICs */
|
||||
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
|
||||
|
||||
return eics[eic_index];
|
||||
} else {
|
||||
Assert(false);
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/** \name Event Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
void extint_enable_events(
|
||||
struct extint_events *const events);
|
||||
|
||||
void extint_disable_events(
|
||||
struct extint_events *const events);
|
||||
|
||||
/** @} */
|
||||
|
||||
/** \name Configuration and Initialization (Channel)
|
||||
* @{
|
||||
*/
|
||||
|
||||
void extint_chan_get_config_defaults(
|
||||
struct extint_chan_conf *const config);
|
||||
|
||||
void extint_chan_set_config(
|
||||
const uint8_t channel,
|
||||
const struct extint_chan_conf *const config);
|
||||
|
||||
/** @} */
|
||||
|
||||
/** \name Configuration and Initialization (NMI)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initializes an External Interrupt NMI channel configuration structure to defaults.
|
||||
*
|
||||
* Initializes a given External Interrupt NMI channel configuration structure
|
||||
* to a set of known default values. This function should be called on all new
|
||||
* instances of these configuration structures before being modified by the
|
||||
* user application.
|
||||
*
|
||||
* The default configuration is as follows:
|
||||
* \li Input filtering disabled
|
||||
* \li Detect falling edges of a signal
|
||||
* \li Asynchronous edge detection is disabled
|
||||
*
|
||||
* \param[out] config Configuration structure to initialize to default values
|
||||
*/
|
||||
static inline void extint_nmi_get_config_defaults(
|
||||
struct extint_nmi_conf *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(config);
|
||||
|
||||
/* Default configuration values */
|
||||
config->gpio_pin = 0;
|
||||
config->gpio_pin_mux = 0;
|
||||
config->gpio_pin_pull = EXTINT_PULL_UP;
|
||||
config->filter_input_signal = false;
|
||||
config->detection_criteria = EXTINT_DETECT_FALLING;
|
||||
#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35)
|
||||
config->enable_async_edge_detection = false;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
enum status_code extint_nmi_set_config(
|
||||
const uint8_t nmi_channel,
|
||||
const struct extint_nmi_conf *const config);
|
||||
|
||||
/** @} */
|
||||
|
||||
/** \name Detection testing and clearing (channel)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Retrieves the edge detection state of a configured channel.
|
||||
*
|
||||
* Reads the current state of a configured channel, and determines
|
||||
* if the detection criteria of the channel has been met.
|
||||
*
|
||||
* \param[in] channel External Interrupt channel index to check
|
||||
*
|
||||
* \return Status of the requested channel's edge detection state.
|
||||
* \retval true If the channel's edge/level detection criteria was met
|
||||
* \retval false If the channel has not detected its configured criteria
|
||||
*/
|
||||
static inline bool extint_chan_is_detected(
|
||||
const uint8_t channel)
|
||||
{
|
||||
Eic *const eic_module = _extint_get_eic_from_channel(channel);
|
||||
uint32_t eic_mask = (1UL << (channel % 32));
|
||||
|
||||
return (eic_module->INTFLAG.reg & eic_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Clears the edge detection state of a configured channel.
|
||||
*
|
||||
* Clears the current state of a configured channel, readying it for
|
||||
* the next level or edge detection.
|
||||
*
|
||||
* \param[in] channel External Interrupt channel index to check
|
||||
*/
|
||||
static inline void extint_chan_clear_detected(
|
||||
const uint8_t channel)
|
||||
{
|
||||
Eic *const eic_module = _extint_get_eic_from_channel(channel);
|
||||
uint32_t eic_mask = (1UL << (channel % 32));
|
||||
|
||||
eic_module->INTFLAG.reg = eic_mask;
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/** \name Detection Testing and Clearing (NMI)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Retrieves the edge detection state of a configured NMI channel.
|
||||
*
|
||||
* Reads the current state of a configured NMI channel, and determines
|
||||
* if the detection criteria of the NMI channel has been met.
|
||||
*
|
||||
* \param[in] nmi_channel External Interrupt NMI channel index to check
|
||||
*
|
||||
* \return Status of the requested NMI channel's edge detection state.
|
||||
* \retval true If the NMI channel's edge/level detection criteria was met
|
||||
* \retval false If the NMI channel has not detected its configured criteria
|
||||
*/
|
||||
static inline bool extint_nmi_is_detected(
|
||||
const uint8_t nmi_channel)
|
||||
{
|
||||
Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
|
||||
|
||||
return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Clears the edge detection state of a configured NMI channel.
|
||||
*
|
||||
* Clears the current state of a configured NMI channel, readying it for
|
||||
* the next level or edge detection.
|
||||
*
|
||||
* \param[in] nmi_channel External Interrupt NMI channel index to check
|
||||
*/
|
||||
static inline void extint_nmi_clear_detected(
|
||||
const uint8_t nmi_channel)
|
||||
{
|
||||
Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
|
||||
|
||||
eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI;
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
#if EXTINT_CALLBACK_MODE == true
|
||||
# include "extint_callback.h"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_extint_extra Extra Information for EXTINT Driver
|
||||
*
|
||||
* \section asfdoc_sam0_extint_extra_acronyms Acronyms
|
||||
* The table below presents the acronyms used in this module:
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Acronym</th>
|
||||
* <th>Description</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>EIC</td>
|
||||
* <td>External Interrupt Controller</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>MUX</td>
|
||||
* <td>Multiplexer</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>NMI</td>
|
||||
* <td>Non-Maskable Interrupt</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_extint_extra_dependencies Dependencies
|
||||
* This driver has the following dependencies:
|
||||
*
|
||||
* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_extint_extra_errata Errata
|
||||
* There are no errata related to this driver.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_extint_extra_history Module History
|
||||
* An overview of the module history is presented in the table below, with
|
||||
* details on the enhancements and fixes made to the module since its first
|
||||
* release. The current version of this corresponds to the newest version in
|
||||
* the table.
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Changelog</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>
|
||||
* \li Driver updated to follow driver type convention
|
||||
* \li Removed \c %extint_reset(), \c %extint_disable() and
|
||||
* \c extint_enable() functions. Added internal function
|
||||
* \c %_system_extint_init().
|
||||
* \li Added configuration EXTINT_CLOCK_SOURCE in conf_extint.h
|
||||
* \li Removed configuration EXTINT_CALLBACKS_MAX in conf_extint.h, and
|
||||
* added channel parameter in the register functions
|
||||
* \c %extint_register_callback() and \c %extint_unregister_callback()
|
||||
* </td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Updated interrupt handler to clear interrupt flag before calling
|
||||
* callback function</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Updated initialization function to also enable the digital interface
|
||||
* clock to the module if it is disabled</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Initial Release</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_extint_exqsg Examples for EXTINT Driver
|
||||
*
|
||||
* This is a list of the available Quick Start guides (QSGs) and example
|
||||
* applications for \ref asfdoc_sam0_extint_group.
|
||||
* QSGs are simple examples with step-by-step instructions to configure and
|
||||
* use this driver in a selection of use cases. Note that a QSG can be compiled
|
||||
* as a standalone application or be added to the user application.
|
||||
*
|
||||
* - \subpage asfdoc_sam0_extint_basic_use_case
|
||||
* \if EXTINT_CALLBACK_MODE
|
||||
* - \subpage asfdoc_sam0_extint_callback_use_case
|
||||
* \endif
|
||||
*
|
||||
* \page asfdoc_sam0_extint_document_revision_history Document Revision History
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Doc. Rev.</th>
|
||||
* <th>Date</th>
|
||||
* <th>Comments</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42112E</td>
|
||||
* <td>12/2015</td>
|
||||
* <td>Added support for SAM L21/L22, SAM C21, SAM D09, and SAM DA1</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42112D</td>
|
||||
* <td>12/2014</td>
|
||||
* <td>Added support for SAM R21 and SAM D10/D11</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42112C</td>
|
||||
* <td>01/2014</td>
|
||||
* <td>Added support for SAM D21</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42112B</td>
|
||||
* <td>06/2013</td>
|
||||
* <td>Added additional documentation on the event system. Corrected
|
||||
* documentation typos.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42112A</td>
|
||||
* <td>06/2013</td>
|
||||
* <td>Initial release</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*/
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,222 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM External Interrupt Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#include "extint.h"
|
||||
#include "extint_callback.h"
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Internal driver device instance struct, declared in the main module driver.
|
||||
*/
|
||||
extern struct _extint_module _extint_dev;
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* This is the number of the channel whose callback is currently running.
|
||||
*/
|
||||
uint8_t _current_channel;
|
||||
|
||||
/**
|
||||
* \brief Registers an asynchronous callback function with the driver.
|
||||
*
|
||||
* Registers an asynchronous callback with the EXTINT driver, fired when a
|
||||
* channel detects the configured channel detection criteria
|
||||
* (e.g. edge or level). Callbacks are fired once for each detected channel.
|
||||
*
|
||||
* \note NMI channel callbacks cannot be registered via this function; the
|
||||
* device's NMI interrupt should be hooked directly in the user
|
||||
* application and the NMI flags manually cleared via
|
||||
* \ref extint_nmi_clear_detected().
|
||||
*
|
||||
* \param[in] callback Pointer to the callback function to register
|
||||
* \param[in] channel Logical channel to register callback for
|
||||
* \param[in] type Type of callback function to register
|
||||
*
|
||||
* \return Status of the registration operation.
|
||||
* \retval STATUS_OK The callback was registered successfully
|
||||
* \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
|
||||
* \retval STATUS_ERR_ALREADY_INITIALIZED Callback function has been
|
||||
* registered, need unregister first
|
||||
*/
|
||||
enum status_code extint_register_callback(
|
||||
const extint_callback_t callback,
|
||||
const uint8_t channel,
|
||||
const enum extint_callback_type type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(callback);
|
||||
|
||||
if (type != EXTINT_CALLBACK_TYPE_DETECT) {
|
||||
Assert(false);
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
if (_extint_dev.callbacks[channel] == NULL) {
|
||||
_extint_dev.callbacks[channel] = callback;
|
||||
return STATUS_OK;
|
||||
} else if (_extint_dev.callbacks[channel] == callback) {
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
return STATUS_ERR_ALREADY_INITIALIZED;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Unregisters an asynchronous callback function with the driver.
|
||||
*
|
||||
* Unregisters an asynchronous callback with the EXTINT driver, removing it
|
||||
* from the internal callback registration table.
|
||||
*
|
||||
* \param[in] callback Pointer to the callback function to unregister
|
||||
* \param[in] channel Logical channel to unregister callback for
|
||||
* \param[in] type Type of callback function to unregister
|
||||
*
|
||||
* \return Status of the de-registration operation.
|
||||
* \retval STATUS_OK The callback was unregistered successfully
|
||||
* \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
|
||||
* \retval STATUS_ERR_BAD_ADDRESS No matching entry was found in the
|
||||
* registration table
|
||||
*/
|
||||
enum status_code extint_unregister_callback(
|
||||
const extint_callback_t callback,
|
||||
const uint8_t channel,
|
||||
const enum extint_callback_type type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(callback);
|
||||
|
||||
if (type != EXTINT_CALLBACK_TYPE_DETECT) {
|
||||
Assert(false);
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
if (_extint_dev.callbacks[channel] == callback) {
|
||||
_extint_dev.callbacks[channel] = NULL;
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
return STATUS_ERR_BAD_ADDRESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enables asynchronous callback generation for a given channel and type.
|
||||
*
|
||||
* Enables asynchronous callbacks for a given logical external interrupt channel
|
||||
* and type. This must be called before an external interrupt channel will
|
||||
* generate callback events.
|
||||
*
|
||||
* \param[in] channel Logical channel to enable callback generation for
|
||||
* \param[in] type Type of callback function callbacks to enable
|
||||
*
|
||||
* \return Status of the callback enable operation.
|
||||
* \retval STATUS_OK The callback was enabled successfully
|
||||
* \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
|
||||
*/
|
||||
enum status_code extint_chan_enable_callback(
|
||||
const uint8_t channel,
|
||||
const enum extint_callback_type type)
|
||||
{
|
||||
if (type == EXTINT_CALLBACK_TYPE_DETECT) {
|
||||
Eic *const eic = _extint_get_eic_from_channel(channel);
|
||||
|
||||
eic->INTENSET.reg = (1UL << channel);
|
||||
}
|
||||
else {
|
||||
Assert(false);
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disables asynchronous callback generation for a given channel and type.
|
||||
*
|
||||
* Disables asynchronous callbacks for a given logical external interrupt
|
||||
* channel and type.
|
||||
*
|
||||
* \param[in] channel Logical channel to disable callback generation for
|
||||
* \param[in] type Type of callback function callbacks to disable
|
||||
*
|
||||
* \return Status of the callback disable operation.
|
||||
* \retval STATUS_OK The callback was disabled successfully
|
||||
* \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
|
||||
*/
|
||||
enum status_code extint_chan_disable_callback(
|
||||
const uint8_t channel,
|
||||
const enum extint_callback_type type)
|
||||
{
|
||||
if (type == EXTINT_CALLBACK_TYPE_DETECT) {
|
||||
Eic *const eic = _extint_get_eic_from_channel(channel);
|
||||
|
||||
eic->INTENCLR.reg = (1UL << channel);
|
||||
}
|
||||
else {
|
||||
Assert(false);
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Find what channel caused the callback.
|
||||
*
|
||||
* Can be used in an EXTINT callback function to find what channel caused
|
||||
* the callback in case the same callback is used by multiple channels.
|
||||
*
|
||||
* \return Channel number.
|
||||
*/
|
||||
uint8_t extint_get_current_channel(void)
|
||||
{
|
||||
return _current_channel;
|
||||
}
|
||||
|
||||
/** Handler for the EXTINT hardware module interrupt. */
|
||||
void EIC_Handler(void)
|
||||
{
|
||||
/* Find any triggered channels, run associated callback handlers */
|
||||
for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) {
|
||||
if (extint_chan_is_detected(_current_channel)) {
|
||||
/* Clear flag */
|
||||
extint_chan_clear_detected(_current_channel);
|
||||
/* Find any associated callback entries in the callback table */
|
||||
if (_extint_dev.callbacks[_current_channel] != NULL) {
|
||||
/* Run the registered callback */
|
||||
_extint_dev.callbacks[_current_channel]();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,98 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM External Interrupt Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef EXTINT_CALLBACK_H_INCLUDED
|
||||
#define EXTINT_CALLBACK_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup asfdoc_sam0_extint_group
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** \name Callback Configuration and Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Enum for the possible callback types for the EXTINT module. */
|
||||
enum extint_callback_type
|
||||
{
|
||||
/** Callback type for when an external interrupt detects the configured
|
||||
* channel criteria (i.e. edge or level detection)
|
||||
*/
|
||||
EXTINT_CALLBACK_TYPE_DETECT,
|
||||
};
|
||||
|
||||
enum status_code extint_register_callback(
|
||||
const extint_callback_t callback,
|
||||
const uint8_t channel,
|
||||
const enum extint_callback_type type);
|
||||
|
||||
enum status_code extint_unregister_callback(
|
||||
const extint_callback_t callback,
|
||||
const uint8_t channel,
|
||||
const enum extint_callback_type type);
|
||||
|
||||
uint8_t extint_get_current_channel(void);
|
||||
|
||||
/** @} */
|
||||
|
||||
/** \name Callback Enabling and Disabling (Channel)
|
||||
* @{
|
||||
*/
|
||||
|
||||
enum status_code extint_chan_enable_callback(
|
||||
const uint8_t channel,
|
||||
const enum extint_callback_type type);
|
||||
|
||||
enum status_code extint_chan_disable_callback(
|
||||
const uint8_t channel,
|
||||
const enum extint_callback_type type);
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,415 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM External Interrupt Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#include <system.h>
|
||||
#include <system_interrupt.h>
|
||||
#include <extint.h>
|
||||
#include <conf_extint.h>
|
||||
|
||||
#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__)
|
||||
# warning EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0.
|
||||
|
||||
/** Configuration option, setting the EIC clock source which can be used for
|
||||
* EIC edge detection or filtering. This option may be overridden in the module
|
||||
* configuration header file \c conf_extint.h.
|
||||
*/
|
||||
# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Internal driver device instance struct.
|
||||
*/
|
||||
struct _extint_module _extint_dev;
|
||||
|
||||
/**
|
||||
* \brief Determin if the general clock is required
|
||||
*
|
||||
* \param[in] filter_input_signal Filter the raw input signal to prevent noise
|
||||
* \param[in] detection_criteria Edge detection mode to use (\ref extint_detect)
|
||||
*/
|
||||
#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \
|
||||
((filter_input_signal) ? true : (\
|
||||
(EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\
|
||||
(EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\
|
||||
(EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false))))
|
||||
|
||||
static void _extint_enable(void);
|
||||
static void _extint_disable(void);
|
||||
|
||||
/**
|
||||
* \brief Determines if the hardware module(s) are currently synchronizing to the bus.
|
||||
*
|
||||
* Checks to see if the underlying hardware peripheral module(s) are currently
|
||||
* synchronizing across multiple clock domains to the hardware bus, This
|
||||
* function can be used to delay further operations on a module until such time
|
||||
* that it is ready, to prevent blocking delays for synchronization in the
|
||||
* user application.
|
||||
*
|
||||
* \return Synchronization status of the underlying hardware module(s).
|
||||
*
|
||||
* \retval true If the module synchronization is ongoing
|
||||
* \retval false If the module has completed synchronization
|
||||
*/
|
||||
static inline bool extint_is_syncing(void)
|
||||
{
|
||||
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
|
||||
|
||||
for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
|
||||
if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
/**
|
||||
* \internal
|
||||
* \brief Initializes and enables the External Interrupt driver.
|
||||
*
|
||||
* Enable the clocks used by External Interrupt driver.
|
||||
*
|
||||
* Resets the External Interrupt driver, resetting all hardware
|
||||
* module registers to their power-on defaults, then enable it for further use.
|
||||
*
|
||||
* Reset the callback list if callback mode is used.
|
||||
*
|
||||
* This function must be called before attempting to use any NMI or standard
|
||||
* external interrupt channel functions.
|
||||
*
|
||||
* \note When SYSTEM module is used, this function will be invoked by
|
||||
* \ref system_init() automatically if the module is included.
|
||||
*/
|
||||
void _system_extint_init(void);
|
||||
void _system_extint_init(void)
|
||||
{
|
||||
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
|
||||
|
||||
/* Turn on the digital interface clock */
|
||||
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC);
|
||||
|
||||
/* Configure the generic clock for the module and enable it */
|
||||
struct system_gclk_chan_config gclk_chan_conf;
|
||||
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
|
||||
gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE;
|
||||
system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf);
|
||||
|
||||
/* Enable the clock anyway, since when needed it will be requested
|
||||
* by External Interrupt driver */
|
||||
system_gclk_chan_enable(EIC_GCLK_ID);
|
||||
|
||||
/* Reset all EIC hardware modules. */
|
||||
for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
|
||||
eics[i]->CTRL.reg |= EIC_CTRL_SWRST;
|
||||
}
|
||||
|
||||
while (extint_is_syncing()) {
|
||||
/* Wait for all hardware modules to complete synchronization */
|
||||
}
|
||||
|
||||
/* Reset the software module */
|
||||
#if EXTINT_CALLBACK_MODE == true
|
||||
/* Clear callback registration table */
|
||||
for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) {
|
||||
_extint_dev.callbacks[j] = NULL;
|
||||
}
|
||||
system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC);
|
||||
#endif
|
||||
|
||||
/* Enables the driver for further use */
|
||||
_extint_enable();
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* \brief Enables the External Interrupt driver.
|
||||
*
|
||||
* Enables EIC modules.
|
||||
* Registered callback list will not be affected if callback mode is used.
|
||||
*/
|
||||
void _extint_enable(void)
|
||||
{
|
||||
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
|
||||
|
||||
/* Enable all EIC hardware modules. */
|
||||
for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
|
||||
eics[i]->CTRL.reg |= EIC_CTRL_ENABLE;
|
||||
}
|
||||
|
||||
while (extint_is_syncing()) {
|
||||
/* Wait for all hardware modules to complete synchronization */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* \brief Disables the External Interrupt driver.
|
||||
*
|
||||
* Disables EIC modules that were previously started via a call to
|
||||
* \ref _extint_enable().
|
||||
* Registered callback list will not be affected if callback mode is used.
|
||||
*/
|
||||
void _extint_disable(void)
|
||||
{
|
||||
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
|
||||
|
||||
/* Disable all EIC hardware modules. */
|
||||
for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
|
||||
eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE;
|
||||
}
|
||||
|
||||
while (extint_is_syncing()) {
|
||||
/* Wait for all hardware modules to complete synchronization */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initializes an External Interrupt channel configuration structure to defaults.
|
||||
*
|
||||
* Initializes a given External Interrupt channel configuration structure to a
|
||||
* set of known default values. This function should be called on all new
|
||||
* instances of these configuration structures before being modified by the
|
||||
* user application.
|
||||
*
|
||||
* The default configuration is as follows:
|
||||
* \li Wake the device if an edge detection occurs whilst in sleep
|
||||
* \li Input filtering disabled
|
||||
* \li Internal pull-up enabled
|
||||
* \li Detect falling edges of a signal
|
||||
*
|
||||
* \param[out] config Configuration structure to initialize to default values
|
||||
*/
|
||||
void extint_chan_get_config_defaults(
|
||||
struct extint_chan_conf *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(config);
|
||||
|
||||
/* Default configuration values */
|
||||
config->gpio_pin = 0;
|
||||
config->gpio_pin_mux = 0;
|
||||
config->gpio_pin_pull = EXTINT_PULL_UP;
|
||||
config->wake_if_sleeping = true;
|
||||
config->filter_input_signal = false;
|
||||
config->detection_criteria = EXTINT_DETECT_FALLING;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Writes an External Interrupt channel configuration to the hardware module.
|
||||
*
|
||||
* Writes out a given configuration of an External Interrupt channel
|
||||
* configuration to the hardware module. If the channel is already configured,
|
||||
* the new configuration will replace the existing one.
|
||||
*
|
||||
* \param[in] channel External Interrupt channel to configure
|
||||
* \param[in] config Configuration settings for the channel
|
||||
|
||||
*/
|
||||
void extint_chan_set_config(
|
||||
const uint8_t channel,
|
||||
const struct extint_chan_conf *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(config);
|
||||
/* Sanity check clock requirements */
|
||||
Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
|
||||
_extint_is_gclk_required(config->filter_input_signal,
|
||||
config->detection_criteria)));
|
||||
|
||||
struct system_pinmux_config pinmux_config;
|
||||
system_pinmux_get_config_defaults(&pinmux_config);
|
||||
|
||||
pinmux_config.mux_position = config->gpio_pin_mux;
|
||||
pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
|
||||
pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
|
||||
system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
|
||||
|
||||
/* Get a pointer to the module hardware instance */
|
||||
Eic *const EIC_module = _extint_get_eic_from_channel(channel);
|
||||
|
||||
uint32_t config_pos = (4 * (channel % 8));
|
||||
uint32_t new_config;
|
||||
|
||||
/* Determine the channel's new edge detection configuration */
|
||||
new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos);
|
||||
|
||||
/* Enable the hardware signal filter if requested in the config */
|
||||
if (config->filter_input_signal) {
|
||||
new_config |= EIC_CONFIG_FILTEN0;
|
||||
}
|
||||
|
||||
/* Clear the existing and set the new channel configuration */
|
||||
EIC_module->CONFIG[channel / 8].reg
|
||||
= (EIC_module->CONFIG[channel / 8].reg &
|
||||
~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) |
|
||||
(new_config << config_pos);
|
||||
|
||||
/* Set the channel's new wake up mode setting */
|
||||
if (config->wake_if_sleeping) {
|
||||
EIC_module->WAKEUP.reg |= (1UL << channel);
|
||||
} else {
|
||||
EIC_module->WAKEUP.reg &= ~(1UL << channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Writes an External Interrupt NMI channel configuration to the hardware module.
|
||||
*
|
||||
* Writes out a given configuration of an External Interrupt NMI channel
|
||||
* configuration to the hardware module. If the channel is already configured,
|
||||
* the new configuration will replace the existing one.
|
||||
*
|
||||
* \param[in] nmi_channel External Interrupt NMI channel to configure
|
||||
* \param[in] config Configuration settings for the channel
|
||||
*
|
||||
* \returns Status code indicating the success or failure of the request.
|
||||
* \retval STATUS_OK Configuration succeeded
|
||||
* \retval STATUS_ERR_PIN_MUX_INVALID An invalid pinmux value was supplied
|
||||
* \retval STATUS_ERR_BAD_FORMAT An invalid detection mode was requested
|
||||
*/
|
||||
enum status_code extint_nmi_set_config(
|
||||
const uint8_t nmi_channel,
|
||||
const struct extint_nmi_conf *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(config);
|
||||
/* Sanity check clock requirements */
|
||||
Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
|
||||
_extint_is_gclk_required(config->filter_input_signal,
|
||||
config->detection_criteria)));
|
||||
|
||||
struct system_pinmux_config pinmux_config;
|
||||
system_pinmux_get_config_defaults(&pinmux_config);
|
||||
|
||||
pinmux_config.mux_position = config->gpio_pin_mux;
|
||||
pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
|
||||
pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
|
||||
pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
|
||||
system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
|
||||
|
||||
/* Get a pointer to the module hardware instance */
|
||||
Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel);
|
||||
|
||||
uint32_t new_config;
|
||||
|
||||
/* Determine the NMI's new edge detection configuration */
|
||||
new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos);
|
||||
|
||||
/* Enable the hardware signal filter if requested in the config */
|
||||
if (config->filter_input_signal) {
|
||||
new_config |= EIC_NMICTRL_NMIFILTEN;
|
||||
}
|
||||
|
||||
/* Disable EIC and general clock to configure NMI */
|
||||
_extint_disable();
|
||||
system_gclk_chan_disable(EIC_GCLK_ID);
|
||||
|
||||
EIC_module->NMICTRL.reg = new_config;
|
||||
|
||||
/* Enable the general clock and EIC after configure NMI */
|
||||
system_gclk_chan_enable(EIC_GCLK_ID);
|
||||
_extint_enable();
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enables an External Interrupt event output.
|
||||
*
|
||||
* Enables one or more output events from the External Interrupt module. See
|
||||
* \ref extint_events "here" for a list of events this module supports.
|
||||
*
|
||||
* \note Events cannot be altered while the module is enabled.
|
||||
*
|
||||
* \param[in] events Struct containing flags of events to enable
|
||||
*/
|
||||
void extint_enable_events(
|
||||
struct extint_events *const events)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(events);
|
||||
|
||||
/* Array of available EICs. */
|
||||
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
|
||||
|
||||
/* Update the event control register for each physical EIC instance */
|
||||
for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
|
||||
uint32_t event_mask = 0;
|
||||
|
||||
/* Create an enable mask for the current EIC module */
|
||||
for (uint32_t j = 0; j < 32; j++) {
|
||||
if (events->generate_event_on_detect[(32 * i) + j]) {
|
||||
event_mask |= (1UL << j);
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable the masked events */
|
||||
eics[i]->EVCTRL.reg |= event_mask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disables an External Interrupt event output.
|
||||
*
|
||||
* Disables one or more output events from the External Interrupt module. See
|
||||
* \ref extint_events "here" for a list of events this module supports.
|
||||
*
|
||||
* \note Events cannot be altered while the module is enabled.
|
||||
*
|
||||
* \param[in] events Struct containing flags of events to disable
|
||||
*/
|
||||
void extint_disable_events(
|
||||
struct extint_events *const events)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(events);
|
||||
|
||||
/* Array of available EICs. */
|
||||
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
|
||||
|
||||
/* Update the event control register for each physical EIC instance */
|
||||
for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
|
||||
uint32_t event_mask = 0;
|
||||
|
||||
/* Create a disable mask for the current EIC module */
|
||||
for (uint32_t j = 0; j < 32; j++) {
|
||||
if (events->generate_event_on_detect[(32 * i) + j]) {
|
||||
event_mask |= (1UL << j);
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable the masked events */
|
||||
eics[i]->EVCTRL.reg &= ~event_mask;
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,99 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM GPIO Port Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#include <port.h>
|
||||
|
||||
/**
|
||||
* \brief Writes a Port pin configuration to the hardware module.
|
||||
*
|
||||
* Writes out a given configuration of a Port pin configuration to the hardware
|
||||
* module.
|
||||
*
|
||||
* \note If the pin direction is set as an output, the pull-up/pull-down input
|
||||
* configuration setting is ignored.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to configure
|
||||
* \param[in] config Configuration settings for the pin
|
||||
*/
|
||||
void port_pin_set_config(
|
||||
const uint8_t gpio_pin,
|
||||
const struct port_config *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(config);
|
||||
|
||||
struct system_pinmux_config pinmux_config;
|
||||
system_pinmux_get_config_defaults(&pinmux_config);
|
||||
|
||||
pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
|
||||
pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
|
||||
pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
|
||||
pinmux_config.powersave = config->powersave;
|
||||
|
||||
system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Writes a Port group configuration group to the hardware module.
|
||||
*
|
||||
* Writes out a given configuration of a Port group configuration to the
|
||||
* hardware module.
|
||||
*
|
||||
* \note If the pin direction is set as an output, the pull-up/pull-down input
|
||||
* configuration setting is ignored.
|
||||
*
|
||||
* \param[out] port Base of the PORT module to write to
|
||||
* \param[in] mask Mask of the port pin(s) to configure
|
||||
* \param[in] config Configuration settings for the pin group
|
||||
*/
|
||||
void port_group_set_config(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const struct port_config *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(port);
|
||||
Assert(config);
|
||||
|
||||
struct system_pinmux_config pinmux_config;
|
||||
system_pinmux_get_config_defaults(&pinmux_config);
|
||||
|
||||
pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
|
||||
pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
|
||||
pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
|
||||
pinmux_config.powersave = config->powersave;
|
||||
|
||||
system_pinmux_group_set_config(port, mask, &pinmux_config);
|
||||
}
|
||||
@ -0,0 +1,785 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM GPIO Port Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef PORT_H_INCLUDED
|
||||
#define PORT_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \defgroup asfdoc_sam0_port_group SAM Port (PORT) Driver
|
||||
*
|
||||
* This driver for Atmel® | SMART ARM®-based microcontrollers provides
|
||||
* an interface for the configuration and management of the device's General
|
||||
* Purpose Input/Output (GPIO) pin functionality, for manual pin state reading
|
||||
* and writing.
|
||||
*
|
||||
* The following peripheral is used by this module:
|
||||
* - PORT (GPIO Management)
|
||||
*
|
||||
* The following devices can use this module:
|
||||
* - Atmel | SMART SAM D20/D21
|
||||
* - Atmel | SMART SAM R21
|
||||
* - Atmel | SMART SAM D09/D10/D11
|
||||
* - Atmel | SMART SAM L21/L22
|
||||
* - Atmel | SMART SAM DA1
|
||||
* - Atmel | SMART SAM C20/C21
|
||||
* - Atmel | SMART SAM HA1
|
||||
* - Atmel | SMART SAM R30
|
||||
* - Atmel | SMART SAM R34
|
||||
* - Atmel | SMART SAM R35
|
||||
*
|
||||
* The outline of this documentation is as follows:
|
||||
* - \ref asfdoc_sam0_port_prerequisites
|
||||
* - \ref asfdoc_sam0_port_module_overview
|
||||
* - \ref asfdoc_sam0_port_special_considerations
|
||||
* - \ref asfdoc_sam0_port_extra_info
|
||||
* - \ref asfdoc_sam0_port_examples
|
||||
* - \ref asfdoc_sam0_port_api_overview
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_port_prerequisites Prerequisites
|
||||
*
|
||||
* There are no prerequisites for this module.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_port_module_overview Module Overview
|
||||
*
|
||||
* The device GPIO (PORT) module provides an interface between the user
|
||||
* application logic and external hardware peripherals, when general pin state
|
||||
* manipulation is required. This driver provides an easy-to-use interface to
|
||||
* the physical pin input samplers and output drivers, so that pins can be read
|
||||
* from or written to for general purpose external hardware control.
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_features Driver Feature Macro Definition
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Driver Feature Macro</th>
|
||||
* <th>Supported devices</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>FEATURE_PORT_INPUT_EVENT</td>
|
||||
* <td>SAM L21/L22/C20/C21/R30/R34/R35</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
* \note The specific features are only available in the driver when the
|
||||
* selected device supports those features.
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins
|
||||
* SAM devices use two naming conventions for the I/O pins in the device; one
|
||||
* physical and one logical. Each physical pin on a device package is assigned
|
||||
* both a physical port and pin identifier (e.g. "PORTA.0") as well as a
|
||||
* monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
|
||||
* former is used to map physical pins to their physical internal device module
|
||||
* counterparts, for simplicity the design of this driver uses the logical GPIO
|
||||
* numbers instead.
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_module_overview_physical Physical Connection
|
||||
*
|
||||
* \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how
|
||||
* this module is interconnected within the device.
|
||||
*
|
||||
* \anchor asfdoc_sam0_port_module_int_connections
|
||||
* \dot
|
||||
* digraph overview {
|
||||
* node [label="Port Pad" shape=square] pad;
|
||||
*
|
||||
* subgraph driver {
|
||||
* node [label="Peripheral MUX" shape=trapezium] pinmux;
|
||||
* node [label="GPIO Module" shape=ellipse] gpio;
|
||||
* node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
|
||||
* }
|
||||
*
|
||||
* pinmux -> gpio;
|
||||
* pad -> pinmux;
|
||||
* pinmux -> peripherals;
|
||||
* }
|
||||
* \enddot
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_port_special_considerations Special Considerations
|
||||
*
|
||||
* The SAM port pin input sampler can be disabled when the pin is configured
|
||||
* in pure output mode to save power; reading the pin state of a pin configured
|
||||
* in output-only mode will read the logical output state that was last set.
|
||||
*
|
||||
* \section asfdoc_sam0_port_extra_info Extra Information
|
||||
*
|
||||
* For extra information, see \ref asfdoc_sam0_port_extra. This includes:
|
||||
* - \ref asfdoc_sam0_port_extra_acronyms
|
||||
* - \ref asfdoc_sam0_port_extra_dependencies
|
||||
* - \ref asfdoc_sam0_port_extra_errata
|
||||
* - \ref asfdoc_sam0_port_extra_history
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_port_examples Examples
|
||||
*
|
||||
* For a list of examples related to this driver, see
|
||||
* \ref asfdoc_sam0_port_exqsg.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_port_api_overview API Overview
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <pinmux.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \name Driver Feature Definition
|
||||
* Define port features set according to different device family.
|
||||
* @{
|
||||
*/
|
||||
#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
|
||||
/** Event input control feature support for PORT group. */
|
||||
# define FEATURE_PORT_INPUT_EVENT
|
||||
#endif
|
||||
/*@}*/
|
||||
|
||||
/** \name PORT Alias Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Convenience definition for GPIO module group A on the device (if
|
||||
* available). */
|
||||
#if (PORT_GROUPS > 0) || defined(__DOXYGEN__)
|
||||
# define PORTA PORT->Group[0]
|
||||
#endif
|
||||
|
||||
#if (PORT_GROUPS > 1) || defined(__DOXYGEN__)
|
||||
/** Convenience definition for GPIO module group B on the device (if
|
||||
* available). */
|
||||
# define PORTB PORT->Group[1]
|
||||
#endif
|
||||
|
||||
#if (PORT_GROUPS > 2) || defined(__DOXYGEN__)
|
||||
/** Convenience definition for GPIO module group C on the device (if
|
||||
* available). */
|
||||
# define PORTC PORT->Group[2]
|
||||
#endif
|
||||
|
||||
#if (PORT_GROUPS > 3) || defined(__DOXYGEN__)
|
||||
/** Convenience definition for GPIO module group D on the device (if
|
||||
* available). */
|
||||
# define PORTD PORT->Group[3]
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \brief Port pin direction configuration enum.
|
||||
*
|
||||
* Enum for the possible pin direction settings of the port pin configuration
|
||||
* structure, to indicate the direction the pin should use.
|
||||
*/
|
||||
enum port_pin_dir {
|
||||
/** The pin's input buffer should be enabled, so that the pin state can
|
||||
* be read */
|
||||
PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT,
|
||||
/** The pin's output buffer should be enabled, so that the pin state can
|
||||
* be set */
|
||||
PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
|
||||
/** The pin's output and input buffers should be enabled, so that the pin
|
||||
* state can be set and read back */
|
||||
PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Port pin input pull configuration enum.
|
||||
*
|
||||
* Enum for the possible pin pull settings of the port pin configuration
|
||||
* structure, to indicate the type of logic level pull the pin should use.
|
||||
*/
|
||||
enum port_pin_pull {
|
||||
/** No logical pull should be applied to the pin */
|
||||
PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
|
||||
/** Pin should be pulled up when idle */
|
||||
PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP,
|
||||
/** Pin should be pulled down when idle */
|
||||
PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
|
||||
};
|
||||
|
||||
#ifdef FEATURE_PORT_INPUT_EVENT
|
||||
/**
|
||||
* \brief Port input event action.
|
||||
*
|
||||
* List of port input events action on pin.
|
||||
*/
|
||||
enum port_input_event_action {
|
||||
/** Event out to pin */
|
||||
PORT_INPUT_EVENT_ACTION_OUT = 0,
|
||||
/** Set output register of pin on event */
|
||||
PORT_INPUT_EVENT_ACTION_SET,
|
||||
/** Clear output register pin on event */
|
||||
PORT_INPUT_EVENT_ACTION_CLR,
|
||||
/** Toggle output register pin on event */
|
||||
PORT_INPUT_EVENT_ACTION_TGL,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Port input event.
|
||||
*
|
||||
* List of port input events.
|
||||
*/
|
||||
enum port_input_event{
|
||||
/** Port input event 0 */
|
||||
PORT_INPUT_EVENT_0 = 0,
|
||||
/** Port input event 1 */
|
||||
PORT_INPUT_EVENT_1 = 1,
|
||||
/** Port input event 2 */
|
||||
PORT_INPUT_EVENT_2 = 2,
|
||||
/** Port input event 3 */
|
||||
PORT_INPUT_EVENT_3 = 3,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Port input event configuration structure.
|
||||
*
|
||||
* Configuration structure for a port input event.
|
||||
*/
|
||||
struct port_input_event_config{
|
||||
/** Port input event action */
|
||||
enum port_input_event_action action;
|
||||
/** GPIO pin */
|
||||
uint8_t gpio_pin;
|
||||
};
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Port pin configuration structure.
|
||||
*
|
||||
* Configuration structure for a port pin instance. This structure should be
|
||||
* initialized by the \ref port_get_config_defaults() function before being
|
||||
* modified by the user application.
|
||||
*/
|
||||
struct port_config {
|
||||
/** Port buffer input/output direction */
|
||||
enum port_pin_dir direction;
|
||||
|
||||
/** Port pull-up/pull-down for input pins */
|
||||
enum port_pin_pull input_pull;
|
||||
|
||||
/** Enable lowest possible powerstate on the pin
|
||||
*
|
||||
* \note All other configurations will be ignored, the pin will be disabled.
|
||||
*/
|
||||
bool powersave;
|
||||
};
|
||||
|
||||
/** \name State Reading/Writing (Physical Group Orientated)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Retrieves the PORT module group instance from a given GPIO pin number.
|
||||
*
|
||||
* Retrieves the PORT module group instance associated with a given logical
|
||||
* GPIO pin number.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to convert
|
||||
*
|
||||
* \return Base address of the associated PORT module.
|
||||
*/
|
||||
static inline PortGroup* port_get_group_from_gpio_pin(
|
||||
const uint8_t gpio_pin)
|
||||
{
|
||||
return system_pinmux_get_group_from_gpio_pin(gpio_pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieves the state of a group of port pins that are configured as inputs.
|
||||
*
|
||||
* Reads the current logic level of a port module's pins and returns the
|
||||
* current levels as a bitmask.
|
||||
*
|
||||
* \param[in] port Base of the PORT module to read from
|
||||
* \param[in] mask Mask of the port pin(s) to read
|
||||
*
|
||||
* \return Status of the port pin(s) input buffers.
|
||||
*/
|
||||
static inline uint32_t port_group_get_input_level(
|
||||
const PortGroup *const port,
|
||||
const uint32_t mask)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(port);
|
||||
|
||||
return (port->IN.reg & mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieves the state of a group of port pins that are configured as outputs.
|
||||
*
|
||||
* Reads the current logical output level of a port module's pins and returns
|
||||
* the current levels as a bitmask.
|
||||
*
|
||||
* \param[in] port Base of the PORT module to read from
|
||||
* \param[in] mask Mask of the port pin(s) to read
|
||||
*
|
||||
* \return Status of the port pin(s) output buffers.
|
||||
*/
|
||||
static inline uint32_t port_group_get_output_level(
|
||||
const PortGroup *const port,
|
||||
const uint32_t mask)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(port);
|
||||
|
||||
return (port->OUT.reg & mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Sets the state of a group of port pins that are configured as outputs.
|
||||
*
|
||||
* Sets the current output level of a port module's pins to a given logic
|
||||
* level.
|
||||
*
|
||||
* \param[out] port Base of the PORT module to write to
|
||||
* \param[in] mask Mask of the port pin(s) to change
|
||||
* \param[in] level_mask Mask of the port level(s) to set
|
||||
*/
|
||||
static inline void port_group_set_output_level(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const uint32_t level_mask)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(port);
|
||||
|
||||
port->OUTSET.reg = (mask & level_mask);
|
||||
port->OUTCLR.reg = (mask & ~level_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Toggles the state of a group of port pins that are configured as an outputs.
|
||||
*
|
||||
* Toggles the current output levels of a port module's pins.
|
||||
*
|
||||
* \param[out] port Base of the PORT module to write to
|
||||
* \param[in] mask Mask of the port pin(s) to toggle
|
||||
*/
|
||||
static inline void port_group_toggle_output_level(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(port);
|
||||
|
||||
port->OUTTGL.reg = mask;
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/** \name Configuration and Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initializes a Port pin/group configuration structure to defaults.
|
||||
*
|
||||
* Initializes a given Port pin/group configuration structure to a set of
|
||||
* known default values. This function should be called on all new
|
||||
* instances of these configuration structures before being modified by the
|
||||
* user application.
|
||||
*
|
||||
* The default configuration is as follows:
|
||||
* \li Input mode with internal pull-up enabled
|
||||
*
|
||||
* \param[out] config Configuration structure to initialize to default values
|
||||
*/
|
||||
static inline void port_get_config_defaults(
|
||||
struct port_config *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(config);
|
||||
|
||||
/* Default configuration values */
|
||||
config->direction = PORT_PIN_DIR_INPUT;
|
||||
config->input_pull = PORT_PIN_PULL_UP;
|
||||
config->powersave = false;
|
||||
}
|
||||
|
||||
void port_pin_set_config(
|
||||
const uint8_t gpio_pin,
|
||||
const struct port_config *const config);
|
||||
|
||||
void port_group_set_config(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const struct port_config *const config);
|
||||
|
||||
/** @} */
|
||||
|
||||
/** \name State Reading/Writing (Logical Pin Orientated)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Retrieves the state of a port pin that is configured as an input.
|
||||
*
|
||||
* Reads the current logic level of a port pin and returns the current
|
||||
* level as a Boolean value.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to read
|
||||
*
|
||||
* \return Status of the port pin's input buffer.
|
||||
*/
|
||||
static inline bool port_pin_get_input_level(
|
||||
const uint8_t gpio_pin)
|
||||
{
|
||||
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
|
||||
uint32_t pin_mask = (1UL << (gpio_pin % 32));
|
||||
|
||||
return (port_base->IN.reg & pin_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieves the state of a port pin that is configured as an output.
|
||||
*
|
||||
* Reads the current logical output level of a port pin and returns the current
|
||||
* level as a Boolean value.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to read
|
||||
*
|
||||
* \return Status of the port pin's output buffer.
|
||||
*/
|
||||
static inline bool port_pin_get_output_level(
|
||||
const uint8_t gpio_pin)
|
||||
{
|
||||
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
|
||||
uint32_t pin_mask = (1UL << (gpio_pin % 32));
|
||||
|
||||
return (port_base->OUT.reg & pin_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Sets the state of a port pin that is configured as an output.
|
||||
*
|
||||
* Sets the current output level of a port pin to a given logic level.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to write to
|
||||
* \param[in] level Logical level to set the given pin to
|
||||
*/
|
||||
static inline void port_pin_set_output_level(
|
||||
const uint8_t gpio_pin,
|
||||
const bool level)
|
||||
{
|
||||
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
|
||||
uint32_t pin_mask = (1UL << (gpio_pin % 32));
|
||||
|
||||
/* Set the pin to high or low atomically based on the requested level */
|
||||
if (level) {
|
||||
port_base->OUTSET.reg = pin_mask;
|
||||
} else {
|
||||
port_base->OUTCLR.reg = pin_mask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Toggles the state of a port pin that is configured as an output.
|
||||
*
|
||||
* Toggles the current output level of a port pin.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to toggle
|
||||
*/
|
||||
static inline void port_pin_toggle_output_level(
|
||||
const uint8_t gpio_pin)
|
||||
{
|
||||
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
|
||||
uint32_t pin_mask = (1UL << (gpio_pin % 32));
|
||||
|
||||
/* Toggle pin output level */
|
||||
port_base->OUTTGL.reg = pin_mask;
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef FEATURE_PORT_INPUT_EVENT
|
||||
|
||||
/** \name Port Input Event
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Enable the port event input.
|
||||
*
|
||||
* Enable the port event input with the given pin and event.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin
|
||||
* \param[in] n Port input event
|
||||
*
|
||||
* \retval STATUS_ERR_INVALID_ARG Invalid parameter
|
||||
* \retval STATUS_OK Successfully
|
||||
*/
|
||||
static inline enum status_code port_enable_input_event(
|
||||
const uint8_t gpio_pin,
|
||||
const enum port_input_event n)
|
||||
{
|
||||
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
|
||||
switch (n) {
|
||||
case PORT_INPUT_EVENT_0:
|
||||
port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
|
||||
break;
|
||||
case PORT_INPUT_EVENT_1:
|
||||
port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
|
||||
break;
|
||||
case PORT_INPUT_EVENT_2:
|
||||
port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
|
||||
break;
|
||||
case PORT_INPUT_EVENT_3:
|
||||
port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
|
||||
break;
|
||||
default:
|
||||
Assert(false);
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable the port event input.
|
||||
*
|
||||
* Disable the port event input with the given pin and event.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin
|
||||
* \param[in] gpio_pin Port input event
|
||||
*
|
||||
* \retval STATUS_ERR_INVALID_ARG Invalid parameter
|
||||
* \retval STATUS_OK Successfully
|
||||
*/
|
||||
static inline enum status_code port_disable_input_event(
|
||||
const uint8_t gpio_pin,
|
||||
const enum port_input_event n)
|
||||
{
|
||||
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
|
||||
switch (n) {
|
||||
case PORT_INPUT_EVENT_0:
|
||||
port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
|
||||
break;
|
||||
case PORT_INPUT_EVENT_1:
|
||||
port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
|
||||
break;
|
||||
case PORT_INPUT_EVENT_2:
|
||||
port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
|
||||
break;
|
||||
case PORT_INPUT_EVENT_3:
|
||||
port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
|
||||
break;
|
||||
default:
|
||||
Assert(false);
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the default configuration for port input event.
|
||||
*
|
||||
* Fills a configuration structure with the default configuration for port input event:
|
||||
* - Event output to pin
|
||||
* - Event action to be executed on PIN 0
|
||||
*
|
||||
* \param[out] config Configuration structure to fill with default values
|
||||
*/
|
||||
static inline void port_input_event_get_config_defaults(
|
||||
struct port_input_event_config *const config)
|
||||
{
|
||||
Assert(config);
|
||||
config->action = PORT_INPUT_EVENT_ACTION_OUT;
|
||||
config->gpio_pin = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Configure port input event.
|
||||
*
|
||||
* Configures port input event with the given configuration settings.
|
||||
*
|
||||
* \param[in] config Port input even configuration structure containing the new config
|
||||
*
|
||||
* \retval STATUS_ERR_INVALID_ARG Invalid parameter
|
||||
* \retval STATUS_OK Successfully
|
||||
*/
|
||||
|
||||
static inline enum status_code port_input_event_set_config(
|
||||
const enum port_input_event n,
|
||||
struct port_input_event_config *const config)
|
||||
{
|
||||
Assert(config);
|
||||
PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin);
|
||||
uint8_t pin_index = config->gpio_pin % 32;
|
||||
struct port_config pin_conf;
|
||||
|
||||
port_get_config_defaults(&pin_conf);
|
||||
/* Configure the GPIO pin as outputs*/
|
||||
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
|
||||
port_pin_set_config(config->gpio_pin, &pin_conf);
|
||||
|
||||
switch (n) {
|
||||
case PORT_INPUT_EVENT_0:
|
||||
port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
|
||||
| PORT_EVCTRL_PID0(pin_index);
|
||||
break;
|
||||
case PORT_INPUT_EVENT_1:
|
||||
port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action)
|
||||
| PORT_EVCTRL_PID1(pin_index);
|
||||
break;
|
||||
case PORT_INPUT_EVENT_2:
|
||||
port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action)
|
||||
| PORT_EVCTRL_PID2(pin_index);
|
||||
break;
|
||||
case PORT_INPUT_EVENT_3:
|
||||
port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action)
|
||||
| PORT_EVCTRL_PID3(pin_index);
|
||||
break;
|
||||
default:
|
||||
Assert(false);
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_port_extra Extra Information for PORT Driver
|
||||
*
|
||||
* \section asfdoc_sam0_port_extra_acronyms Acronyms
|
||||
* Below is a table listing the acronyms used in this module, along with their
|
||||
* intended meanings.
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Acronym</th>
|
||||
* <th>Description</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>GPIO</td>
|
||||
* <td>General Purpose Input/Output</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>MUX</td>
|
||||
* <td>Multiplexer</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_port_extra_dependencies Dependencies
|
||||
* This driver has the following dependencies:
|
||||
*
|
||||
* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_port_extra_errata Errata
|
||||
* There are no errata related to this driver.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_port_extra_history Module History
|
||||
* An overview of the module history is presented in the table below, with
|
||||
* details on the enhancements and fixes made to the module since its first
|
||||
* release. The current version of this corresponds to the newest version in
|
||||
* the table.
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Changelog</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Added input event feature</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Initial release</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_port_exqsg Examples for PORT Driver
|
||||
*
|
||||
* This is a list of the available Quick Start guides (QSGs) and example
|
||||
* applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with
|
||||
* step-by-step instructions to configure and use this driver in a selection of
|
||||
* use cases. Note that a QSG can be compiled as a standalone application or be
|
||||
* added to the user application.
|
||||
*
|
||||
* - \subpage asfdoc_sam0_port_basic_use_case
|
||||
*
|
||||
* \page asfdoc_sam0_port_document_revision_history Document Revision History
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Doc. Rev.</td>
|
||||
* <th>Date</td>
|
||||
* <th>Comments</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42113E</td>
|
||||
* <td>12/2015</td>
|
||||
* <td>Added input event feature.
|
||||
* Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30/R34 and SAM DA1.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42113D</td>
|
||||
* <td>12/2014</td>
|
||||
* <td>Added support for SAM R21 and SAM D10/D11</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42113C</td>
|
||||
* <td>01/2014</td>
|
||||
* <td>Added support for SAM D21</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42113B</td>
|
||||
* <td>06/2013</td>
|
||||
* <td>Corrected documentation typos</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42113A</td>
|
||||
* <td>06/2013</td>
|
||||
* <td>Initial document release</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*/
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,98 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM GPIO Port Driver Quick Start
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_port_basic_use_case Quick Start Guide for PORT - Basic
|
||||
*
|
||||
* In this use case, the PORT module is configured for:
|
||||
* \li One pin in input mode, with pull-up enabled
|
||||
* \li One pin in output mode
|
||||
*
|
||||
* This use case sets up the PORT to read the current state of a GPIO pin set as
|
||||
* an input, and mirrors the opposite logical state on a pin configured as an
|
||||
* output.
|
||||
*
|
||||
* \section asfdoc_sam0_port_basic_use_case_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_basic_use_case_setup_prereq Prerequisites
|
||||
* There are no special setup requirements for this use-case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_basic_use_case_setup_code Code
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_port_basic.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_port_basic.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_basic_use_case_setup_flow Workflow
|
||||
* -# Create a PORT module pin configuration struct, which can be filled out to
|
||||
* adjust the configuration of a single port pin.
|
||||
* \snippet qs_port_basic.c setup_1
|
||||
* -# Initialize the pin configuration struct with the module's default values.
|
||||
* \snippet qs_port_basic.c setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Adjust the configuration struct to request an input pin.
|
||||
* \snippet qs_port_basic.c setup_3
|
||||
* -# Configure push button pin with the initialized pin configuration struct, to enable
|
||||
* the input sampler on the pin.
|
||||
* \snippet qs_port_basic.c setup_4
|
||||
* -# Adjust the configuration struct to request an output pin.
|
||||
* \snippet qs_port_basic.c setup_5
|
||||
* \note The existing configuration struct may be re-used, as long as any
|
||||
* values that have been altered from the default settings are taken
|
||||
* into account by the user application.
|
||||
*
|
||||
* -# Configure LED pin with the initialized pin configuration struct, to enable
|
||||
* the output driver on the pin.
|
||||
* \snippet qs_port_basic.c setup_6
|
||||
*
|
||||
* \section asfdoc_sam0_port_basic_use_case_use_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_basic_use_case_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_port_basic.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_port_basic_use_case_flow Workflow
|
||||
* -# Read in the current input sampler state of push button pin, which has been
|
||||
* configured as an input in the use-case setup code.
|
||||
* \snippet qs_port_basic.c main_1
|
||||
* -# Write the inverted pin level state to LED pin, which has been configured as
|
||||
* an output in the use-case setup code.
|
||||
* \snippet qs_port_basic.c main_2
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
@ -0,0 +1,280 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Serial Peripheral Interface Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#include "sercom.h"
|
||||
|
||||
#define SHIFT 32
|
||||
#define BAUD_INT_MAX 8192
|
||||
#define BAUD_FP_MAX 8
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
/**
|
||||
* \internal Configuration structure to save current gclk status.
|
||||
*/
|
||||
struct _sercom_conf {
|
||||
/* Status of gclk generator initialization */
|
||||
bool generator_is_set;
|
||||
/* Sercom gclk generator used */
|
||||
enum gclk_generator generator_source;
|
||||
};
|
||||
|
||||
static struct _sercom_conf _sercom_config;
|
||||
|
||||
|
||||
/**
|
||||
* \internal Calculate 64 bit division, ref can be found in
|
||||
* http://en.wikipedia.org/wiki/Division_algorithm#Long_division
|
||||
*/
|
||||
static uint64_t long_division(uint64_t n, uint64_t d)
|
||||
{
|
||||
int32_t i;
|
||||
uint64_t q = 0, r = 0, bit_shift;
|
||||
for (i = 63; i >= 0; i--) {
|
||||
bit_shift = (uint64_t)1 << i;
|
||||
|
||||
r = r << 1;
|
||||
|
||||
if (n & bit_shift) {
|
||||
r |= 0x01;
|
||||
}
|
||||
|
||||
if (r >= d) {
|
||||
r = r - d;
|
||||
q |= bit_shift;
|
||||
}
|
||||
}
|
||||
|
||||
return q;
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal Calculate synchronous baudrate value (SPI/UART)
|
||||
*/
|
||||
enum status_code _sercom_get_sync_baud_val(
|
||||
const uint32_t baudrate,
|
||||
const uint32_t external_clock,
|
||||
uint16_t *const baudvalue)
|
||||
{
|
||||
/* Baud value variable */
|
||||
uint16_t baud_calculated = 0;
|
||||
uint32_t clock_value = external_clock;
|
||||
|
||||
|
||||
/* Check if baudrate is outside of valid range */
|
||||
if (baudrate > (external_clock / 2)) {
|
||||
/* Return with error code */
|
||||
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
|
||||
}
|
||||
|
||||
/* Calculate BAUD value from clock frequency and baudrate */
|
||||
clock_value = external_clock / 2;
|
||||
while (clock_value >= baudrate) {
|
||||
clock_value = clock_value - baudrate;
|
||||
baud_calculated++;
|
||||
}
|
||||
baud_calculated = baud_calculated - 1;
|
||||
|
||||
/* Check if BAUD value is more than 255, which is maximum
|
||||
* for synchronous mode */
|
||||
if (baud_calculated > 0xFF) {
|
||||
/* Return with an error code */
|
||||
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
|
||||
} else {
|
||||
*baudvalue = baud_calculated;
|
||||
return STATUS_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal Calculate asynchronous baudrate value (UART)
|
||||
*/
|
||||
enum status_code _sercom_get_async_baud_val(
|
||||
const uint32_t baudrate,
|
||||
const uint32_t peripheral_clock,
|
||||
uint16_t *const baudval,
|
||||
enum sercom_asynchronous_operation_mode mode,
|
||||
enum sercom_asynchronous_sample_num sample_num)
|
||||
{
|
||||
/* Temporary variables */
|
||||
uint64_t ratio = 0;
|
||||
uint64_t scale = 0;
|
||||
uint64_t baud_calculated = 0;
|
||||
uint8_t baud_fp;
|
||||
uint32_t baud_int = 0;
|
||||
uint64_t temp1;
|
||||
|
||||
/* Check if the baudrate is outside of valid range */
|
||||
if ((baudrate * sample_num) > peripheral_clock) {
|
||||
/* Return with error code */
|
||||
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
|
||||
}
|
||||
|
||||
if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
|
||||
/* Calculate the BAUD value */
|
||||
temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
|
||||
ratio = long_division(temp1, peripheral_clock);
|
||||
scale = ((uint64_t)1 << SHIFT) - ratio;
|
||||
baud_calculated = (65536 * scale) >> SHIFT;
|
||||
} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
|
||||
temp1 = ((uint64_t)baudrate * sample_num);
|
||||
baud_int = long_division( peripheral_clock, temp1);
|
||||
if(baud_int > BAUD_INT_MAX) {
|
||||
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
|
||||
}
|
||||
temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
|
||||
baud_fp = temp1 - 8 * baud_int;
|
||||
baud_calculated = baud_int | (baud_fp << 13);
|
||||
}
|
||||
|
||||
*baudval = baud_calculated;
|
||||
return STATUS_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Set GCLK channel to generator.
|
||||
*
|
||||
* This will set the appropriate GCLK channel to the requested GCLK generator.
|
||||
* This will set the generator for all SERCOM instances, and the user will thus
|
||||
* only be able to set the same generator that has previously been set, if any.
|
||||
*
|
||||
* After the generator has been set the first time, the generator can be changed
|
||||
* using the \c force_change flag.
|
||||
*
|
||||
* \param[in] generator_source The generator to use for SERCOM.
|
||||
* \param[in] force_change Force change the generator.
|
||||
*
|
||||
* \return Status code indicating the GCLK generator change operation.
|
||||
* \retval STATUS_OK If the generator update request was
|
||||
* successful.
|
||||
* \retval STATUS_ERR_ALREADY_INITIALIZED If a generator was already configured
|
||||
* and the new configuration was not
|
||||
* forced.
|
||||
*/
|
||||
enum status_code sercom_set_gclk_generator(
|
||||
const enum gclk_generator generator_source,
|
||||
const bool force_change)
|
||||
{
|
||||
/* Check if valid option */
|
||||
if (!_sercom_config.generator_is_set || force_change) {
|
||||
/* Create and fill a GCLK configuration structure for the new config */
|
||||
struct system_gclk_chan_config gclk_chan_conf;
|
||||
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
|
||||
gclk_chan_conf.source_generator = generator_source;
|
||||
system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
|
||||
system_gclk_chan_enable(SERCOM_GCLK_ID);
|
||||
|
||||
/* Save config */
|
||||
_sercom_config.generator_source = generator_source;
|
||||
_sercom_config.generator_is_set = true;
|
||||
|
||||
return STATUS_OK;
|
||||
} else if (generator_source == _sercom_config.generator_source) {
|
||||
/* Return status OK if same config */
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/* Return invalid config to already initialized GCLK */
|
||||
return STATUS_ERR_ALREADY_INITIALIZED;
|
||||
}
|
||||
|
||||
/** \internal
|
||||
* Creates a switch statement case entry to convert a SERCOM instance and pad
|
||||
* index to the default SERCOM pad MUX setting.
|
||||
*/
|
||||
#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \
|
||||
case (uintptr_t)SERCOM##n: \
|
||||
switch (pad) { \
|
||||
case 0: \
|
||||
return SERCOM##n##_PAD0_DEFAULT; \
|
||||
case 1: \
|
||||
return SERCOM##n##_PAD1_DEFAULT; \
|
||||
case 2: \
|
||||
return SERCOM##n##_PAD2_DEFAULT; \
|
||||
case 3: \
|
||||
return SERCOM##n##_PAD3_DEFAULT; \
|
||||
} \
|
||||
break;
|
||||
|
||||
/**
|
||||
* \internal Gets the default PAD pinout for a given SERCOM.
|
||||
*
|
||||
* Returns the pinmux settings for the given SERCOM and pad. This is used
|
||||
* for default configuration of pins.
|
||||
*
|
||||
* \param[in] sercom_module Pointer to the SERCOM module
|
||||
* \param[in] pad PAD to get default pinout for
|
||||
*
|
||||
* \returns The default pinmux for the given SERCOM instance and PAD
|
||||
*
|
||||
*/
|
||||
uint32_t _sercom_get_default_pad(
|
||||
Sercom *const sercom_module,
|
||||
const uint8_t pad)
|
||||
{
|
||||
switch ((uintptr_t)sercom_module) {
|
||||
/* Auto-generate a lookup table for the default SERCOM pad defaults */
|
||||
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
|
||||
}
|
||||
|
||||
Assert(false);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Find index of given instance.
|
||||
*
|
||||
* \param[in] sercom_instance Instance pointer.
|
||||
*
|
||||
* \return Index of given instance.
|
||||
*/
|
||||
uint8_t _sercom_get_sercom_inst_index(
|
||||
Sercom *const sercom_instance)
|
||||
{
|
||||
/* Save all available SERCOM instances for compare */
|
||||
Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
|
||||
|
||||
/* Find index for sercom instance */
|
||||
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
|
||||
if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
/* Invalid data given */
|
||||
Assert(false);
|
||||
return 0;
|
||||
}
|
||||
@ -0,0 +1,108 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Serial Peripheral Interface Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef SERCOM_H_INCLUDED
|
||||
#define SERCOM_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
#include <system.h>
|
||||
#include <clock.h>
|
||||
#include <system_interrupt.h>
|
||||
#include "sercom_pinout.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* SERCOM modules should share same slow GCLK channel ID */
|
||||
#define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW
|
||||
|
||||
#if (0x1ff >= REV_SERCOM)
|
||||
# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1
|
||||
#elif (0x400 >= REV_SERCOM)
|
||||
# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2
|
||||
#else
|
||||
# error "Unknown SYNCBUSY scheme for this SERCOM revision"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief sercom asynchronous operation mode
|
||||
*
|
||||
* Select sercom asynchronous operation mode
|
||||
*/
|
||||
enum sercom_asynchronous_operation_mode {
|
||||
SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0,
|
||||
SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief sercom asynchronous samples per bit
|
||||
*
|
||||
* Select number of samples per bit
|
||||
*/
|
||||
enum sercom_asynchronous_sample_num {
|
||||
SERCOM_ASYNC_SAMPLE_NUM_3 = 3,
|
||||
SERCOM_ASYNC_SAMPLE_NUM_8 = 8,
|
||||
SERCOM_ASYNC_SAMPLE_NUM_16 = 16,
|
||||
};
|
||||
|
||||
enum status_code sercom_set_gclk_generator(
|
||||
const enum gclk_generator generator_source,
|
||||
const bool force_change);
|
||||
|
||||
enum status_code _sercom_get_sync_baud_val(
|
||||
const uint32_t baudrate,
|
||||
const uint32_t external_clock,
|
||||
uint16_t *const baudval);
|
||||
|
||||
enum status_code _sercom_get_async_baud_val(
|
||||
const uint32_t baudrate,
|
||||
const uint32_t peripheral_clock,
|
||||
uint16_t *const baudval,
|
||||
enum sercom_asynchronous_operation_mode mode,
|
||||
enum sercom_asynchronous_sample_num sample_num);
|
||||
|
||||
uint32_t _sercom_get_default_pad(
|
||||
Sercom *const sercom_module,
|
||||
const uint8_t pad);
|
||||
|
||||
uint8_t _sercom_get_sercom_inst_index(
|
||||
Sercom *const sercom_instance);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__SERCOM_H_INCLUDED
|
||||
@ -0,0 +1,131 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Serial Peripheral Interface Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#include "sercom_interrupt.h"
|
||||
|
||||
void *_sercom_instances[SERCOM_INST_NUM];
|
||||
|
||||
/** Save status of initialized handlers */
|
||||
static bool _handler_table_initialized = false;
|
||||
|
||||
/** Void pointers for saving device instance structures */
|
||||
static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance);
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Default interrupt handler.
|
||||
*
|
||||
* \param[in] instance SERCOM instance used.
|
||||
*/
|
||||
static void _sercom_default_handler(
|
||||
const uint8_t instance)
|
||||
{
|
||||
Assert(false);
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Saves the given callback handler.
|
||||
*
|
||||
* \param[in] instance Instance index.
|
||||
* \param[in] interrupt_handler Pointer to instance callback handler.
|
||||
*/
|
||||
void _sercom_set_handler(
|
||||
const uint8_t instance,
|
||||
const sercom_handler_t interrupt_handler)
|
||||
{
|
||||
/* Initialize handlers with default handler and device instances with 0 */
|
||||
if (_handler_table_initialized == false) {
|
||||
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
|
||||
_sercom_interrupt_handlers[i] = &_sercom_default_handler;
|
||||
_sercom_instances[i] = NULL;
|
||||
}
|
||||
|
||||
_handler_table_initialized = true;
|
||||
}
|
||||
|
||||
/* Save interrupt handler */
|
||||
_sercom_interrupt_handlers[instance] = interrupt_handler;
|
||||
}
|
||||
|
||||
|
||||
/** \internal
|
||||
* Converts a given SERCOM index to its interrupt vector index.
|
||||
*/
|
||||
#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \
|
||||
SYSTEM_INTERRUPT_MODULE_SERCOM##n,
|
||||
|
||||
/** \internal
|
||||
* Generates a SERCOM interrupt handler function for a given SERCOM index.
|
||||
*/
|
||||
#define _SERCOM_INTERRUPT_HANDLER(n, unused) \
|
||||
void SERCOM##n##_Handler(void) \
|
||||
{ \
|
||||
_sercom_interrupt_handlers[n](n); \
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Returns the system interrupt vector.
|
||||
*
|
||||
* \param[in] sercom_instance Instance pointer
|
||||
*
|
||||
* \return Enum of system interrupt vector
|
||||
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM0
|
||||
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM1
|
||||
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM2
|
||||
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM3
|
||||
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM4
|
||||
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM5
|
||||
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
|
||||
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
|
||||
*/
|
||||
enum system_interrupt_vector _sercom_get_interrupt_vector(
|
||||
Sercom *const sercom_instance)
|
||||
{
|
||||
const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
|
||||
{
|
||||
MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
|
||||
};
|
||||
|
||||
/* Retrieve the index of the SERCOM being requested */
|
||||
uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
|
||||
|
||||
/* Get the vector number from the lookup table for the requested SERCOM */
|
||||
return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
|
||||
}
|
||||
|
||||
/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
|
||||
MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)
|
||||
@ -0,0 +1,62 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Serial Peripheral Interface Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef SERCOM_INTERRUPT_H_INCLUDED
|
||||
#define SERCOM_INTERRUPT_H_INCLUDED
|
||||
|
||||
#include "sercom.h"
|
||||
#include <system_interrupt.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Look-up table for device instances */
|
||||
extern void *_sercom_instances[SERCOM_INST_NUM];
|
||||
|
||||
typedef void (*sercom_handler_t)(uint8_t instance);
|
||||
|
||||
enum system_interrupt_vector _sercom_get_interrupt_vector(
|
||||
Sercom *const sercom_instance);
|
||||
|
||||
void _sercom_set_handler(
|
||||
const uint8_t instance,
|
||||
const sercom_handler_t interrupt_handler);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SERCOM_INTERRUPT_H_INCLUDED */
|
||||
@ -0,0 +1,612 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM SERCOM Module Pinout Definitions
|
||||
*
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef SERCOM_PINOUT_H_INCLUDED
|
||||
#define SERCOM_PINOUT_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#if SAMR21E
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
# if SAM_PART_IS_DEFINED(SAMR21E19A)
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
|
||||
# else
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA27F_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA28F_SERCOM3_PAD1
|
||||
#endif
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3
|
||||
|
||||
/* SERCOM4 */
|
||||
# if SAM_PART_IS_DEFINED(SAMR21E19A)
|
||||
#define SERCOM4_PAD0_DEFAULT PINMUX_PB08D_SERCOM4_PAD0
|
||||
#define SERCOM4_PAD1_DEFAULT PINMUX_PB09D_SERCOM4_PAD1
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
|
||||
# else
|
||||
#define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0
|
||||
#define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3
|
||||
# endif
|
||||
|
||||
/* SERCOM5 */
|
||||
#define SERCOM5_PAD0_DEFAULT PINMUX_PB30D_SERCOM5_PAD0
|
||||
#define SERCOM5_PAD1_DEFAULT PINMUX_PB31D_SERCOM5_PAD1
|
||||
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
|
||||
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
|
||||
|
||||
#elif SAMR21G
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
|
||||
|
||||
/* SERCOM4 */
|
||||
#define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0
|
||||
#define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3
|
||||
|
||||
/* SERCOM5 */
|
||||
#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0
|
||||
#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1
|
||||
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
|
||||
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
|
||||
|
||||
#elif (SAMD09)
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA08D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA09D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA30C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA31C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA24C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA25C_SERCOM1_PAD3
|
||||
|
||||
#elif (SAMD10DS) || (SAMD10DM) || (SAMD10DU) || (SAMD11DS) || (SAMD11DM) || (SAMD11DU)
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA22C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA23C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA16D_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA25D_SERCOM2_PAD3
|
||||
|
||||
#elif (SAMD10C) || (SAMD11C)
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA08D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA09D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA30C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA31C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA24C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA25C_SERCOM1_PAD3
|
||||
|
||||
#elif SAM_PART_IS_DEFINED(SAMD21E15L) || SAM_PART_IS_DEFINED(SAMD21E16L)
|
||||
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3
|
||||
|
||||
#elif (SAML22N)
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA10C_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA11C_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA20D_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA21D_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PB02C_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PB21C_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PB00C_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PB01C_SERCOM3_PAD3
|
||||
|
||||
/* SERCOM4 */
|
||||
#define SERCOM4_PAD0_DEFAULT PINMUX_PA12C_SERCOM4_PAD0
|
||||
#define SERCOM4_PAD1_DEFAULT PINMUX_PA13C_SERCOM4_PAD1
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14C_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15C_SERCOM4_PAD3
|
||||
|
||||
/* SERCOM5 */
|
||||
#define SERCOM5_PAD0_DEFAULT PINMUX_PB30D_SERCOM5_PAD0
|
||||
#define SERCOM5_PAD1_DEFAULT PINMUX_PB31D_SERCOM5_PAD1
|
||||
#define SERCOM5_PAD2_DEFAULT PINMUX_PB22D_SERCOM5_PAD2
|
||||
#define SERCOM5_PAD3_DEFAULT PINMUX_PB23D_SERCOM5_PAD3
|
||||
#elif (SAML22J) || (SAML22G)
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA10C_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA11C_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA20D_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA21D_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA12D_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA13D_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA14D_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA15D_SERCOM3_PAD3
|
||||
#elif (SAMC20E) || (SAMC21E)
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3
|
||||
|
||||
#elif (SAMC20G) || (SAMC21G)
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3
|
||||
|
||||
#ifdef ID_SERCOM4
|
||||
/* SERCOM4 */
|
||||
#define SERCOM4_PAD0_DEFAULT PINMUX_PB08D_SERCOM4_PAD0
|
||||
#define SERCOM4_PAD1_DEFAULT PINMUX_PB09D_SERCOM4_PAD1
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PB10D_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3
|
||||
#endif
|
||||
|
||||
#ifdef ID_SERCOM5
|
||||
/* SERCOM5 */
|
||||
#define SERCOM5_PAD0_DEFAULT PINMUX_PB02D_SERCOM5_PAD0
|
||||
#define SERCOM5_PAD1_DEFAULT PINMUX_PB03D_SERCOM5_PAD1
|
||||
#define SERCOM5_PAD2_DEFAULT PINMUX_PB22D_SERCOM5_PAD2
|
||||
#define SERCOM5_PAD3_DEFAULT PINMUX_PB23D_SERCOM5_PAD3
|
||||
#endif
|
||||
|
||||
#elif (SAMC20J) || (SAMC21J)
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3
|
||||
|
||||
#ifdef ID_SERCOM4
|
||||
/* SERCOM4 */
|
||||
#define SERCOM4_PAD0_DEFAULT PINMUX_PB08D_SERCOM4_PAD0
|
||||
#define SERCOM4_PAD1_DEFAULT PINMUX_PB09D_SERCOM4_PAD1
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PB10D_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3
|
||||
#endif
|
||||
|
||||
#ifdef ID_SERCOM5
|
||||
/* SERCOM5 */
|
||||
#define SERCOM5_PAD0_DEFAULT PINMUX_PB02D_SERCOM5_PAD0
|
||||
#define SERCOM5_PAD1_DEFAULT PINMUX_PB03D_SERCOM5_PAD1
|
||||
#define SERCOM5_PAD2_DEFAULT PINMUX_PB00D_SERCOM5_PAD2
|
||||
#define SERCOM5_PAD3_DEFAULT PINMUX_PB01D_SERCOM5_PAD3
|
||||
#endif
|
||||
|
||||
#elif (SAMDA1)
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
|
||||
|
||||
#if (SAMDA1E)
|
||||
/* SERCOM4 */
|
||||
#define SERCOM4_PAD0_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM4_PAD1_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
|
||||
#else
|
||||
/* SERCOM4 */
|
||||
#define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0
|
||||
#define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
|
||||
#endif
|
||||
|
||||
/* SERCOM5 */
|
||||
#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0
|
||||
#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1
|
||||
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
|
||||
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
|
||||
|
||||
#elif (SAMHA1E) || (SAMHA0E)
|
||||
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
|
||||
|
||||
/* SERCOM4 */
|
||||
#define SERCOM4_PAD0_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3
|
||||
|
||||
/* SERCOM5 */
|
||||
#define SERCOM5_PAD0_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM5_PAD1_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM5_PAD2_DEFAULT PINMUX_PA20C_SERCOM5_PAD2
|
||||
#define SERCOM5_PAD3_DEFAULT 0 /* No available pin */
|
||||
|
||||
#elif (SAMHA1G) || (SAMHA0G)
|
||||
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA10C_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA11C_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
|
||||
|
||||
/* SERCOM4 */
|
||||
#define SERCOM4_PAD0_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM4_PAD1_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PB10D_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3
|
||||
|
||||
/* SERCOM5 */
|
||||
#define SERCOM5_PAD0_DEFAULT PINMUX_PB16C_SERCOM5_PAD0
|
||||
#define SERCOM5_PAD1_DEFAULT PINMUX_PB17C_SERCOM5_PAD1
|
||||
#define SERCOM5_PAD2_DEFAULT PINMUX_PA20C_SERCOM5_PAD2
|
||||
#define SERCOM5_PAD3_DEFAULT PINMUX_PA21C_SERCOM5_PAD3
|
||||
|
||||
#elif (SAML21E) || (SAMR34) || (SAMR35)
|
||||
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
|
||||
|
||||
#if !SAM_PART_IS_DEFINED(SAML21E18A)
|
||||
/* SERCOM4 */
|
||||
#define SERCOM4_PAD0_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM4_PAD1_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
|
||||
|
||||
/* SERCOM5 */
|
||||
#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0
|
||||
#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1
|
||||
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
|
||||
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
|
||||
#endif
|
||||
|
||||
#elif (SAMR30E)
|
||||
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM0_PAD1_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#define SERCOM1_PAD0_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM1_PAD1_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM2_PAD3_DEFAULT 0 /* No available pin */
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
|
||||
|
||||
/* SERCOM4 */
|
||||
#define SERCOM4_PAD0_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM4_PAD1_DEFAULT 0 /* No available pin */
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
|
||||
|
||||
/* SERCOM5 */
|
||||
#define SERCOM5_PAD0_DEFAULT 0
|
||||
#define SERCOM5_PAD1_DEFAULT 0
|
||||
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
|
||||
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
|
||||
|
||||
#else
|
||||
/* SERCOM0 */
|
||||
#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
|
||||
#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
|
||||
#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
|
||||
#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
|
||||
|
||||
/* SERCOM1 */
|
||||
#if SAM_PART_IS_DEFINED(SAMD21G15L) || SAM_PART_IS_DEFINED(SAMD21G16L)
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3
|
||||
#else
|
||||
#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0
|
||||
#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1
|
||||
#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
|
||||
#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
|
||||
#endif
|
||||
|
||||
/* SERCOM2 */
|
||||
#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
|
||||
#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
|
||||
#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2
|
||||
#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3
|
||||
|
||||
/* SERCOM3 */
|
||||
#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
|
||||
#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
|
||||
#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
|
||||
#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
|
||||
|
||||
#if !(SAMD20E || SAMD21E)
|
||||
/* SERCOM4 */
|
||||
#define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0
|
||||
#define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1
|
||||
#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
|
||||
#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
|
||||
|
||||
/* SERCOM5 */
|
||||
#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0
|
||||
#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1
|
||||
#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
|
||||
#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif /* SERCOM_PINOUT_H_INCLUDED */
|
||||
@ -0,0 +1,106 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM USART Quick Start
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_sercom_usart_basic_use_case Quick Start Guide for SERCOM USART - Basic
|
||||
*
|
||||
* This quick start will echo back characters typed into the terminal. In this
|
||||
* use case the USART will be configured with the following settings:
|
||||
* - Asynchronous mode
|
||||
* - 9600 Baudrate
|
||||
* - 8-bits, No Parity and one Stop Bit
|
||||
* - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_usart_basic_use_case_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_usart_basic_use_case_prereq Prerequisites
|
||||
* There are no special setup requirements for this use-case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_basic_use_case_setup_code Code
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_usart_basic_use.c module_inst
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_usart_basic_use.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_usart_basic_use.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_basic_use_case_setup_flow Workflow
|
||||
* -# Create a module software instance structure for the USART module to store
|
||||
* the USART driver state while it is in use.
|
||||
* \snippet qs_usart_basic_use.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Configure the USART module.
|
||||
* -# Create a USART module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical USART peripheral.
|
||||
* \snippet qs_usart_basic_use.c setup_config
|
||||
* -# Initialize the USART configuration struct with the module's default values.
|
||||
* \snippet qs_usart_basic_use.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Alter the USART settings to configure the physical pinout, baudrate, and
|
||||
* other relevant parameters.
|
||||
* \snippet qs_usart_basic_use.c setup_change_config
|
||||
* -# Configure the USART module with the desired settings, retrying while the
|
||||
* driver is busy until the configuration is stressfully set.
|
||||
* \snippet qs_usart_basic_use.c setup_set_config
|
||||
* -# Enable the USART module.
|
||||
* \snippet qs_usart_basic_use.c setup_enable
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_usart_basic_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_basic_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_usart_basic_use.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_basic_use_case_main_flow Workflow
|
||||
* -# Send a string to the USART to show the demo is running, blocking until
|
||||
* all characters have been sent.
|
||||
* \snippet qs_usart_basic_use.c main_send_string
|
||||
* -# Enter an infinite loop to continuously echo received values on the USART.
|
||||
* \snippet qs_usart_basic_use.c main_loop
|
||||
* -# Perform a blocking read of the USART, storing the received character into
|
||||
* the previously declared temporary variable.
|
||||
* \snippet qs_usart_basic_use.c main_read
|
||||
* -# Echo the received variable back to the USART via a blocking write.
|
||||
* \snippet qs_usart_basic_use.c main_write
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
@ -0,0 +1,120 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM USART Quick Start
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_sercom_usart_callback_use_case Quick Start Guide for SERCOM USART - Callback
|
||||
*
|
||||
* This quick start will echo back characters typed into the terminal, using
|
||||
* asynchronous TX and RX callbacks from the USART peripheral. In this use case
|
||||
* the USART will be configured with the following settings:
|
||||
* - Asynchronous mode
|
||||
* - 9600 Baudrate
|
||||
* - 8-bits, No Parity and one Stop Bit
|
||||
* - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_usart_callback_use_case_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_usart_callback_use_case_prereq Prerequisites
|
||||
* There are no special setup requirements for this use-case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_callback_use_case_setup_code Code
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_usart_callback.c module_inst
|
||||
* \snippet qs_usart_callback.c rx_buffer_var
|
||||
*
|
||||
* Copy-paste the following callback function code to your user application:
|
||||
* \snippet qs_usart_callback.c callback_funcs
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_usart_callback.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_usart_callback.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_callback_use_case_setup_flow Workflow
|
||||
* -# Create a module software instance structure for the USART module to store
|
||||
* the USART driver state while it is in use.
|
||||
* \snippet qs_usart_callback.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Configure the USART module.
|
||||
* -# Create a USART module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical USART peripheral.
|
||||
* \snippet qs_usart_callback.c setup_config
|
||||
* -# Initialize the USART configuration struct with the module's default values.
|
||||
* \snippet qs_usart_callback.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Alter the USART settings to configure the physical pinout, baudrate, and
|
||||
* other relevant parameters.
|
||||
* \snippet qs_usart_callback.c setup_change_config
|
||||
* -# Configure the USART module with the desired settings, retrying while the
|
||||
* driver is busy until the configuration is stressfully set.
|
||||
* \snippet qs_usart_callback.c setup_set_config
|
||||
* -# Enable the USART module.
|
||||
* \snippet qs_usart_callback.c setup_enable
|
||||
* -# Configure the USART callbacks.
|
||||
* -# Register the TX and RX callback functions with the driver.
|
||||
* \snippet qs_usart_callback.c setup_register_callbacks
|
||||
* -# Enable the TX and RX callbacks so that they will be called by the driver
|
||||
* when appropriate.
|
||||
* \snippet qs_usart_callback.c setup_enable_callbacks
|
||||
*
|
||||
* \section asfdoc_sam0_usart_callback_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_callback_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_usart_callback.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_callback_use_case_main_flow Workflow
|
||||
* -# Enable global interrupts, so that the callbacks can be fired.
|
||||
* \snippet qs_usart_callback.c enable_global_interrupts
|
||||
* -# Send a string to the USART to show the demo is running, blocking until
|
||||
* all characters have been sent.
|
||||
* \snippet qs_usart_callback.c main_send_string
|
||||
* -# Enter an infinite loop to continuously echo received values on the USART.
|
||||
* \snippet qs_usart_callback.c main_loop
|
||||
* -# Perform an asynchronous read of the USART, which will fire the registered
|
||||
* callback when characters are received.
|
||||
* \snippet qs_usart_callback.c main_read
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#include <asf.h>
|
||||
#include <conf_clocks.h>
|
||||
|
||||
@ -0,0 +1,208 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Quick Start Guide for Using Usart driver with DMA
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_sercom_usart_dma_use_case Quick Start Guide for Using DMA with SERCOM USART
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAM D21 Xplained Pro
|
||||
* - SAM R21 Xplained Pro
|
||||
* - SAM D11 Xplained Pro
|
||||
* - SAM DA1 Xplained Pro
|
||||
* - SAM HA1G16A Xplained Pro
|
||||
* - SAM L21 Xplained Pro
|
||||
* - SAM L22 Xplained Pro
|
||||
* - SAM C21 Xplained Pro
|
||||
*
|
||||
* This quick start will receive eight bytes of data from the PC terminal and transmit back the string
|
||||
* to the terminal through DMA. In this use case the USART will be configured with the following
|
||||
* settings:
|
||||
* - Asynchronous mode
|
||||
* - 9600 Baudrate
|
||||
* - 8-bits, No Parity and one Stop Bit
|
||||
* - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_usart_dma_use_case_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_usart_dma_use_case_prereq Prerequisites
|
||||
* There are no special setup requirements for this use-case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_dma_use_case_setup_code Code
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_usart_dma_use.c module_inst
|
||||
* \snippet qs_usart_dma_use.c dma_resource
|
||||
* \snippet qs_usart_dma_use.c usart_buffer
|
||||
* \snippet qs_usart_dma_use.c transfer_descriptor
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_usart_dma_use.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_usart_dma_use.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_dma_use_case_setup_flow Workflow
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_inst Create variables
|
||||
* -# Create a module software instance structure for the USART module to store
|
||||
* the USART driver state while it is in use.
|
||||
* \snippet qs_usart_dma_use.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Create module software instance structures for DMA resources to store
|
||||
* the DMA resource state while it is in use.
|
||||
* \snippet qs_usart_dma_use.c dma_resource
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Create a buffer to store the data to be transferred /received.
|
||||
* \snippet qs_usart_dma_use.c usart_buffer
|
||||
* -# Create DMA transfer descriptors for RX/TX.
|
||||
* \snippet qs_usart_dma_use.c transfer_descriptor
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_usart Configure the USART
|
||||
* -# Create a USART module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical USART peripheral.
|
||||
* \snippet qs_usart_dma_use.c setup_config
|
||||
* -# Initialize the USART configuration struct with the module's default values.
|
||||
* \snippet qs_usart_dma_use.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Alter the USART settings to configure the physical pinout, baudrate, and
|
||||
* other relevant parameters.
|
||||
* \snippet qs_usart_dma_use.c setup_change_config
|
||||
* -# Configure the USART module with the desired settings, retrying while the
|
||||
* driver is busy until the configuration is stressfully set.
|
||||
* \snippet qs_usart_dma_use.c setup_set_config
|
||||
* -# Enable the USART module.
|
||||
* \snippet qs_usart_dma_use.c setup_enable
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_dma Configure DMA
|
||||
* -# Create a callback function of receiver done.
|
||||
* \snippet qs_usart_dma_use.c transfer_done_rx
|
||||
*
|
||||
* -# Create a callback function of transmission done.
|
||||
* \snippet qs_usart_dma_use.c transfer_done_tx
|
||||
*
|
||||
* -# Create a DMA resource configuration structure, which can be filled out to
|
||||
* adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_usart_dma_use.c setup_rx_1
|
||||
*
|
||||
* -# Initialize the DMA resource configuration struct with the module's
|
||||
* default values.
|
||||
* \snippet qs_usart_dma_use.c setup_rx_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Set extra configurations for the DMA resource. It is using peripheral
|
||||
* trigger. SERCOM TX empty trigger causes a beat transfer in
|
||||
* this example.
|
||||
* \snippet qs_usart_dma_use.c setup_rx_3
|
||||
*
|
||||
* -# Allocate a DMA resource with the configurations.
|
||||
* \snippet qs_usart_dma_use.c setup_rx_4
|
||||
*
|
||||
* -# Create a DMA transfer descriptor configuration structure, which can be
|
||||
* filled out to adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_usart_dma_use.c setup_rx_5
|
||||
*
|
||||
* -# Initialize the DMA transfer descriptor configuration struct with the module's
|
||||
* default values.
|
||||
* \snippet qs_usart_dma_use.c setup_rx_6
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Set the specific parameters for a DMA transfer with transfer size, source
|
||||
* address, and destination address.
|
||||
* \snippet qs_usart_dma_use.c setup_rx_7
|
||||
*
|
||||
* -# Create the DMA transfer descriptor.
|
||||
* \snippet qs_usart_dma_use.c setup_rx_8
|
||||
*
|
||||
* -# Create a DMA resource configuration structure for TX, which can be filled
|
||||
* out to adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_usart_dma_use.c setup_tx_1
|
||||
*
|
||||
* -# Initialize the DMA resource configuration struct with the module's
|
||||
* default values.
|
||||
* \snippet qs_usart_dma_use.c setup_tx_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Set extra configurations for the DMA resource. It is using peripheral
|
||||
* trigger. SERCOM RX Ready trigger causes a beat transfer in
|
||||
* this example.
|
||||
* \snippet qs_usart_dma_use.c setup_tx_3
|
||||
*
|
||||
* -# Allocate a DMA resource with the configurations.
|
||||
* \snippet qs_usart_dma_use.c setup_tx_4
|
||||
*
|
||||
* -# Create a DMA transfer descriptor configuration structure, which can be
|
||||
* filled out to adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_usart_dma_use.c setup_tx_5
|
||||
*
|
||||
* -# Initialize the DMA transfer descriptor configuration struct with the module's
|
||||
* default values.
|
||||
* \snippet qs_usart_dma_use.c setup_tx_6
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Set the specific parameters for a DMA transfer with transfer size, source
|
||||
* address, and destination address.
|
||||
* \snippet qs_usart_dma_use.c setup_tx_7
|
||||
*
|
||||
* -# Create the DMA transfer descriptor.
|
||||
* \snippet qs_usart_dma_use.c setup_tx_8
|
||||
*
|
||||
* \section asfdoc_sam0_usart_dma_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_dma_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_usart_dma_use.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_dma_use_case_main_flow Workflow
|
||||
* -# Wait for receiving data.
|
||||
* \snippet qs_usart_dma_use.c main_1
|
||||
*
|
||||
* -# Enter endless loop.
|
||||
* \snippet qs_usart_dma_use.c endless_loop
|
||||
*/
|
||||
@ -0,0 +1,94 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM USART LIN Quick Start
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_sercom_usart_lin_use_case Quick Start Guide for SERCOM USART LIN
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAMC21 Xplained Pro
|
||||
*
|
||||
* This quick start will set up LIN frame format transmission according to your
|
||||
* configuration \c CONF_LIN_NODE_TYPE.
|
||||
* For LIN master, it will send LIN command after startup.
|
||||
* For LIN salve, once received a format from LIN master with ID \c LIN_ID_FIELD_VALUE,
|
||||
* it will reply four data bytes plus a checksum.
|
||||
*
|
||||
* \section asfdoc_sam0_sercom_usart_lin_use_case_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_sercom_usart_lin_use_case_prereq Prerequisites
|
||||
* When verify data transmission between LIN master and slave, two boards are needed:
|
||||
* one is for LIN master and the other is for LIN slave.
|
||||
* connect LIN master LIN PIN with LIN slave LIN PIN.
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_lin_use_case_setup_code Code
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_lin.c module_var
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_lin.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_lin.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_lin_use_case_setup_flow Workflow
|
||||
* -# Create USART CDC and LIN module software instance structure for the USART module to store
|
||||
* the USART driver state while it is in use.
|
||||
* \snippet qs_lin.c module_inst
|
||||
* -# Define LIN ID field for header format.
|
||||
* \snippet qs_lin.c lin_id
|
||||
* \note The ID \c LIN_ID_FIELD_VALUE is eight bits as [P1,P0,ID5...ID0], when it's 0x64, the
|
||||
* data field length is four bytes plus a checksum byte.
|
||||
*
|
||||
* -# Define LIN RX/TX buffer.
|
||||
* \snippet qs_lin.c lin_buffer
|
||||
* \note For \c tx_buffer and \c rx_buffer, the last byte is for checksum.
|
||||
*
|
||||
* -# Configure the USART CDC for output message.
|
||||
* \snippet qs_lin.c CDC_setup
|
||||
*
|
||||
* -# Configure the USART LIN module.
|
||||
* \snippet qs_lin.c lin_setup
|
||||
* \note The LIN frame format can be configured as master or slave, refer to \c CONF_LIN_NODE_TYPE .
|
||||
*
|
||||
* \section asfdoc_sam0_usart_lin_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_lin_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_lin.c main_setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_usart_lin_use_case_main_flow Workflow
|
||||
* -# Set up USART LIN module.
|
||||
* \snippet qs_lin.c configure_lin
|
||||
* -# For LIN master, sending LIN command. For LIN slaver, start reading data .
|
||||
* \snippet qs_lin.c lin_master_cmd
|
||||
*/
|
||||
@ -0,0 +1,806 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM SERCOM USART Driver
|
||||
*
|
||||
* Copyright (c) 2012-2019 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#include "usart.h"
|
||||
#include <pinmux.h>
|
||||
#if USART_CALLBACK_MODE == true
|
||||
# include "usart_interrupt.h"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Set Configuration of the USART module
|
||||
*/
|
||||
static enum status_code _usart_set_config(
|
||||
struct usart_module *const module,
|
||||
const struct usart_config *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(module->hw);
|
||||
|
||||
/* Get a pointer to the hardware module instance */
|
||||
SercomUsart *const usart_hw = &(module->hw->USART);
|
||||
|
||||
/* Index for generic clock */
|
||||
uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
|
||||
uint32_t gclk_index;
|
||||
|
||||
#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35) || (SAMC21)
|
||||
if (sercom_index == 5) {
|
||||
gclk_index = SERCOM5_GCLK_ID_CORE;
|
||||
} else {
|
||||
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
|
||||
}
|
||||
#else
|
||||
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
|
||||
#endif
|
||||
|
||||
/* Cache new register values to minimize the number of register writes */
|
||||
uint32_t ctrla = 0;
|
||||
uint32_t ctrlb = 0;
|
||||
#ifdef FEATURE_USART_ISO7816
|
||||
uint32_t ctrlc = 0;
|
||||
#endif
|
||||
uint16_t baud = 0;
|
||||
uint32_t transfer_mode;
|
||||
|
||||
enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
|
||||
enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
|
||||
|
||||
#ifdef FEATURE_USART_OVER_SAMPLE
|
||||
switch (config->sample_rate) {
|
||||
case USART_SAMPLE_RATE_16X_ARITHMETIC:
|
||||
mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
|
||||
sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
|
||||
break;
|
||||
case USART_SAMPLE_RATE_8X_ARITHMETIC:
|
||||
mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
|
||||
sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
|
||||
break;
|
||||
case USART_SAMPLE_RATE_3X_ARITHMETIC:
|
||||
mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
|
||||
sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
|
||||
break;
|
||||
case USART_SAMPLE_RATE_16X_FRACTIONAL:
|
||||
mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
|
||||
sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
|
||||
break;
|
||||
case USART_SAMPLE_RATE_8X_FRACTIONAL:
|
||||
mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
|
||||
sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set data order, internal muxing, and clock polarity */
|
||||
ctrla = (uint32_t)config->data_order |
|
||||
(uint32_t)config->mux_setting |
|
||||
#ifdef FEATURE_USART_OVER_SAMPLE
|
||||
config->sample_adjustment |
|
||||
config->sample_rate |
|
||||
#endif
|
||||
#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
|
||||
(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
|
||||
#endif
|
||||
(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
|
||||
|
||||
enum status_code status_code = STATUS_OK;
|
||||
|
||||
transfer_mode = (uint32_t)config->transfer_mode;
|
||||
#ifdef FEATURE_USART_ISO7816
|
||||
if(config->iso7816_config.enabled) {
|
||||
transfer_mode = config->iso7816_config.protocol_t;
|
||||
}
|
||||
#endif
|
||||
/* Get baud value from mode and clock */
|
||||
#ifdef FEATURE_USART_ISO7816
|
||||
if(config->iso7816_config.enabled) {
|
||||
baud = config->baudrate;
|
||||
} else {
|
||||
#endif
|
||||
switch (transfer_mode)
|
||||
{
|
||||
case USART_TRANSFER_SYNCHRONOUSLY:
|
||||
if (!config->use_external_clock) {
|
||||
status_code = _sercom_get_sync_baud_val(config->baudrate,
|
||||
system_gclk_chan_get_hz(gclk_index), &baud);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case USART_TRANSFER_ASYNCHRONOUSLY:
|
||||
if (config->use_external_clock) {
|
||||
status_code =
|
||||
_sercom_get_async_baud_val(config->baudrate,
|
||||
config->ext_clock_freq, &baud, mode, sample_num);
|
||||
} else {
|
||||
status_code =
|
||||
_sercom_get_async_baud_val(config->baudrate,
|
||||
system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
/* Check if calculating the baudrate failed */
|
||||
if (status_code != STATUS_OK) {
|
||||
/* Abort */
|
||||
return status_code;
|
||||
}
|
||||
#ifdef FEATURE_USART_ISO7816
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef FEATURE_USART_IRDA
|
||||
if(config->encoding_format_enable) {
|
||||
usart_hw->RXPL.reg = config->receive_pulse_length;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*Set baud val */
|
||||
usart_hw->BAUD.reg = baud;
|
||||
|
||||
/* Set sample mode */
|
||||
ctrla |= transfer_mode;
|
||||
|
||||
if (config->use_external_clock == false) {
|
||||
ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
|
||||
}
|
||||
else {
|
||||
ctrla |= SERCOM_USART_CTRLA_MODE(0x0);
|
||||
}
|
||||
|
||||
/* Set stopbits and enable transceivers */
|
||||
ctrlb =
|
||||
#ifdef FEATURE_USART_IRDA
|
||||
(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
|
||||
#endif
|
||||
#ifdef FEATURE_USART_START_FRAME_DECTION
|
||||
(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
|
||||
#endif
|
||||
#ifdef FEATURE_USART_COLLISION_DECTION
|
||||
(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
|
||||
#endif
|
||||
(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
|
||||
(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
|
||||
|
||||
#ifdef FEATURE_USART_ISO7816
|
||||
if(config->iso7816_config.enabled) {
|
||||
ctrla |= SERCOM_USART_CTRLA_FORM(0x07);
|
||||
if (config->iso7816_config.enable_inverse) {
|
||||
ctrla |= SERCOM_USART_CTRLA_TXINV | SERCOM_USART_CTRLA_RXINV;
|
||||
}
|
||||
ctrlb |= USART_CHARACTER_SIZE_8BIT;
|
||||
|
||||
switch(config->iso7816_config.protocol_t) {
|
||||
case ISO7816_PROTOCOL_T_0:
|
||||
ctrlb |= (uint32_t)config->stopbits;
|
||||
ctrlc |= SERCOM_USART_CTRLC_GTIME(config->iso7816_config.guard_time) | \
|
||||
(config->iso7816_config.inhibit_nack) | \
|
||||
(config->iso7816_config.successive_recv_nack) | \
|
||||
SERCOM_USART_CTRLC_MAXITER(config->iso7816_config.max_iterations);
|
||||
break;
|
||||
case ISO7816_PROTOCOL_T_1:
|
||||
ctrlb |= USART_STOPBITS_1;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
#endif
|
||||
ctrlb |= (uint32_t)config->stopbits;
|
||||
ctrlb |= (uint32_t)config->character_size;
|
||||
/* Check parity mode bits */
|
||||
if (config->parity != USART_PARITY_NONE) {
|
||||
ctrla |= SERCOM_USART_CTRLA_FORM(1);
|
||||
ctrlb |= config->parity;
|
||||
} else {
|
||||
#ifdef FEATURE_USART_LIN_SLAVE
|
||||
if(config->lin_slave_enable) {
|
||||
ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
|
||||
} else {
|
||||
ctrla |= SERCOM_USART_CTRLA_FORM(0);
|
||||
}
|
||||
#else
|
||||
ctrla |= SERCOM_USART_CTRLA_FORM(0);
|
||||
#endif
|
||||
}
|
||||
#ifdef FEATURE_USART_ISO7816
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef FEATURE_USART_LIN_MASTER
|
||||
usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk)
|
||||
| config->lin_header_delay
|
||||
| config->lin_break_length;
|
||||
|
||||
if (config->lin_node != LIN_INVALID_MODE) {
|
||||
ctrla &= ~(SERCOM_USART_CTRLA_FORM(0xf));
|
||||
ctrla |= config->lin_node;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set whether module should run in standby. */
|
||||
if (config->run_in_standby || system_is_debugger_present()) {
|
||||
ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
|
||||
}
|
||||
|
||||
/* Wait until synchronization is complete */
|
||||
_usart_wait_for_sync(module);
|
||||
|
||||
/* Write configuration to CTRLB */
|
||||
usart_hw->CTRLB.reg = ctrlb;
|
||||
|
||||
/* Wait until synchronization is complete */
|
||||
_usart_wait_for_sync(module);
|
||||
|
||||
/* Write configuration to CTRLA */
|
||||
usart_hw->CTRLA.reg = ctrla;
|
||||
|
||||
#ifdef FEATURE_USART_RS485
|
||||
if ((usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_FORM_Msk) != \
|
||||
SERCOM_USART_CTRLA_FORM(0x07)) {
|
||||
usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7));
|
||||
usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef FEATURE_USART_ISO7816
|
||||
if(config->iso7816_config.enabled) {
|
||||
_usart_wait_for_sync(module);
|
||||
usart_hw->CTRLC.reg = ctrlc;
|
||||
}
|
||||
#endif
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initializes the device
|
||||
*
|
||||
* Initializes the USART device based on the setting specified in the
|
||||
* configuration struct.
|
||||
*
|
||||
* \param[out] module Pointer to USART device
|
||||
* \param[in] hw Pointer to USART hardware instance
|
||||
* \param[in] config Pointer to configuration struct
|
||||
*
|
||||
* \return Status of the initialization.
|
||||
*
|
||||
* \retval STATUS_OK The initialization was successful
|
||||
* \retval STATUS_BUSY The USART module is busy
|
||||
* resetting
|
||||
* \retval STATUS_ERR_DENIED The USART has not been disabled in
|
||||
* advance of initialization
|
||||
* \retval STATUS_ERR_INVALID_ARG The configuration struct contains
|
||||
* invalid configuration
|
||||
* \retval STATUS_ERR_ALREADY_INITIALIZED The SERCOM instance has already been
|
||||
* initialized with different clock
|
||||
* configuration
|
||||
* \retval STATUS_ERR_BAUD_UNAVAILABLE The BAUD rate given by the
|
||||
* configuration
|
||||
* struct cannot be reached with
|
||||
* the current clock configuration
|
||||
*/
|
||||
enum status_code usart_init(
|
||||
struct usart_module *const module,
|
||||
Sercom *const hw,
|
||||
const struct usart_config *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(hw);
|
||||
Assert(config);
|
||||
|
||||
enum status_code status_code = STATUS_OK;
|
||||
|
||||
/* Assign module pointer to software instance struct */
|
||||
module->hw = hw;
|
||||
|
||||
/* Get a pointer to the hardware module instance */
|
||||
SercomUsart *const usart_hw = &(module->hw->USART);
|
||||
|
||||
uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
|
||||
uint32_t pm_index, gclk_index;
|
||||
#if (SAML22) || (SAMC20)
|
||||
pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
|
||||
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
|
||||
#elif (SAML21) || (SAMR30) || (SAMR34) || (SAMR35)
|
||||
if (sercom_index == 5) {
|
||||
pm_index = MCLK_APBDMASK_SERCOM5_Pos;
|
||||
gclk_index = SERCOM5_GCLK_ID_CORE;
|
||||
} else {
|
||||
pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
|
||||
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
|
||||
}
|
||||
#elif (SAMC21)
|
||||
pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
|
||||
|
||||
if (sercom_index == 5){
|
||||
gclk_index = SERCOM5_GCLK_ID_CORE;
|
||||
} else {
|
||||
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
|
||||
}
|
||||
#else
|
||||
pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
|
||||
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
|
||||
#endif
|
||||
|
||||
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
|
||||
/* The module is busy resetting itself */
|
||||
return STATUS_BUSY;
|
||||
}
|
||||
|
||||
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
|
||||
/* Check the module is enabled */
|
||||
return STATUS_ERR_DENIED;
|
||||
}
|
||||
|
||||
/* Turn on module in PM */
|
||||
#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35)
|
||||
if (sercom_index == 5) {
|
||||
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
|
||||
} else {
|
||||
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
|
||||
}
|
||||
#else
|
||||
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
|
||||
#endif
|
||||
|
||||
/* Set up the GCLK for the module */
|
||||
struct system_gclk_chan_config gclk_chan_conf;
|
||||
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
|
||||
gclk_chan_conf.source_generator = config->generator_source;
|
||||
system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
|
||||
system_gclk_chan_enable(gclk_index);
|
||||
sercom_set_gclk_generator(config->generator_source, false);
|
||||
|
||||
/* Set character size */
|
||||
module->character_size = config->character_size;
|
||||
|
||||
/* Set transmitter and receiver status */
|
||||
module->receiver_enabled = config->receiver_enable;
|
||||
module->transmitter_enabled = config->transmitter_enable;
|
||||
|
||||
#ifdef FEATURE_USART_LIN_SLAVE
|
||||
module->lin_slave_enabled = config->lin_slave_enable;
|
||||
#endif
|
||||
#ifdef FEATURE_USART_START_FRAME_DECTION
|
||||
module->start_frame_detection_enabled = config->start_frame_detection_enable;
|
||||
#endif
|
||||
#ifdef FEATURE_USART_ISO7816
|
||||
module->iso7816_mode_enabled = config->iso7816_config.enabled;
|
||||
#endif
|
||||
/* Set configuration according to the config struct */
|
||||
status_code = _usart_set_config(module, config);
|
||||
if(status_code != STATUS_OK) {
|
||||
return status_code;
|
||||
}
|
||||
|
||||
struct system_pinmux_config pin_conf;
|
||||
system_pinmux_get_config_defaults(&pin_conf);
|
||||
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
|
||||
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
|
||||
|
||||
uint32_t pad_pinmuxes[] = {
|
||||
config->pinmux_pad0, config->pinmux_pad1,
|
||||
config->pinmux_pad2, config->pinmux_pad3
|
||||
};
|
||||
|
||||
/* Configure the SERCOM pins according to the user configuration */
|
||||
for (uint8_t pad = 0; pad < 4; pad++) {
|
||||
uint32_t current_pinmux = pad_pinmuxes[pad];
|
||||
|
||||
if (current_pinmux == PINMUX_DEFAULT) {
|
||||
current_pinmux = _sercom_get_default_pad(hw, pad);
|
||||
}
|
||||
|
||||
if (current_pinmux != PINMUX_UNUSED) {
|
||||
pin_conf.mux_position = current_pinmux & 0xFFFF;
|
||||
system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
|
||||
}
|
||||
}
|
||||
|
||||
#if USART_CALLBACK_MODE == true
|
||||
/* Initialize parameters */
|
||||
for (uint32_t i = 0; i < USART_CALLBACK_N; i++) {
|
||||
module->callback[i] = NULL;
|
||||
}
|
||||
|
||||
module->tx_buffer_ptr = NULL;
|
||||
module->rx_buffer_ptr = NULL;
|
||||
module->remaining_tx_buffer_length = 0x0000;
|
||||
module->remaining_rx_buffer_length = 0x0000;
|
||||
module->callback_reg_mask = 0x00;
|
||||
module->callback_enable_mask = 0x00;
|
||||
module->rx_status = STATUS_OK;
|
||||
module->tx_status = STATUS_OK;
|
||||
|
||||
/* Set interrupt handler and register USART software module struct in
|
||||
* look-up table */
|
||||
uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
|
||||
_sercom_set_handler(instance_index, _usart_interrupt_handler);
|
||||
_sercom_instances[instance_index] = module;
|
||||
#endif
|
||||
|
||||
return status_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Transmit a character via the USART
|
||||
*
|
||||
* This blocking function will transmit a single character via the
|
||||
* USART.
|
||||
*
|
||||
* \param[in] module Pointer to the software instance struct
|
||||
* \param[in] tx_data Data to transfer
|
||||
*
|
||||
* \return Status of the operation.
|
||||
* \retval STATUS_OK If the operation was completed
|
||||
* \retval STATUS_BUSY If the operation was not completed, due to the USART
|
||||
* module being busy
|
||||
* \retval STATUS_ERR_DENIED If the transmitter is not enabled
|
||||
*/
|
||||
enum status_code usart_write_wait(
|
||||
struct usart_module *const module,
|
||||
const uint16_t tx_data)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(module->hw);
|
||||
|
||||
/* Get a pointer to the hardware module instance */
|
||||
SercomUsart *const usart_hw = &(module->hw->USART);
|
||||
|
||||
/* Check that the transmitter is enabled */
|
||||
if (!(module->transmitter_enabled)) {
|
||||
return STATUS_ERR_DENIED;
|
||||
}
|
||||
|
||||
#if USART_CALLBACK_MODE == true
|
||||
/* Check if the USART is busy doing asynchronous operation. */
|
||||
if (module->remaining_tx_buffer_length > 0) {
|
||||
return STATUS_BUSY;
|
||||
}
|
||||
|
||||
#else
|
||||
/* Check if USART is ready for new data */
|
||||
if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
|
||||
/* Return error code */
|
||||
return STATUS_BUSY;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Write data to USART module */
|
||||
usart_hw->DATA.reg = tx_data;
|
||||
|
||||
while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
|
||||
/* Wait until data is sent */
|
||||
}
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Receive a character via the USART
|
||||
*
|
||||
* This blocking function will receive a character via the USART.
|
||||
*
|
||||
* \param[in] module Pointer to the software instance struct
|
||||
* \param[out] rx_data Pointer to received data
|
||||
*
|
||||
* \return Status of the operation.
|
||||
* \retval STATUS_OK If the operation was completed
|
||||
* \retval STATUS_BUSY If the operation was not completed,
|
||||
* due to the USART module being busy
|
||||
* \retval STATUS_ERR_BAD_FORMAT If the operation was not completed,
|
||||
* due to configuration mismatch between USART
|
||||
* and the sender
|
||||
* \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed,
|
||||
* due to the baudrate being too low or the
|
||||
* system frequency being too high
|
||||
* \retval STATUS_ERR_BAD_DATA If the operation was not completed, due to
|
||||
* data being corrupted
|
||||
* \retval STATUS_ERR_DENIED If the receiver is not enabled
|
||||
*/
|
||||
enum status_code usart_read_wait(
|
||||
struct usart_module *const module,
|
||||
uint16_t *const rx_data)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(module->hw);
|
||||
|
||||
/* Error variable */
|
||||
uint8_t error_code;
|
||||
|
||||
/* Get a pointer to the hardware module instance */
|
||||
SercomUsart *const usart_hw = &(module->hw->USART);
|
||||
|
||||
/* Check that the receiver is enabled */
|
||||
if (!(module->receiver_enabled)) {
|
||||
return STATUS_ERR_DENIED;
|
||||
}
|
||||
|
||||
#if USART_CALLBACK_MODE == true
|
||||
/* Check if the USART is busy doing asynchronous operation. */
|
||||
if (module->remaining_rx_buffer_length > 0) {
|
||||
return STATUS_BUSY;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Check if USART has new data */
|
||||
if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
|
||||
/* Return error code */
|
||||
return STATUS_BUSY;
|
||||
}
|
||||
|
||||
/* Read out the status code and mask away all but the 3 LSBs*/
|
||||
error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
|
||||
|
||||
/* Check if an error has occurred during the receiving */
|
||||
if (error_code) {
|
||||
/* Check which error occurred */
|
||||
if (error_code & SERCOM_USART_STATUS_FERR) {
|
||||
/* Clear flag by writing a 1 to it and
|
||||
* return with an error code */
|
||||
usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
|
||||
|
||||
return STATUS_ERR_BAD_FORMAT;
|
||||
} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
|
||||
/* Clear flag by writing a 1 to it and
|
||||
* return with an error code */
|
||||
usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
|
||||
|
||||
return STATUS_ERR_OVERFLOW;
|
||||
} else if (error_code & SERCOM_USART_STATUS_PERR) {
|
||||
/* Clear flag by writing a 1 to it and
|
||||
* return with an error code */
|
||||
usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
|
||||
|
||||
return STATUS_ERR_BAD_DATA;
|
||||
}
|
||||
#ifdef FEATURE_USART_LIN_SLAVE
|
||||
else if (error_code & SERCOM_USART_STATUS_ISF) {
|
||||
/* Clear flag by writing 1 to it and
|
||||
* return with an error code */
|
||||
usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
|
||||
|
||||
return STATUS_ERR_PROTOCOL;
|
||||
}
|
||||
#endif
|
||||
#ifdef FEATURE_USART_COLLISION_DECTION
|
||||
else if (error_code & SERCOM_USART_STATUS_COLL) {
|
||||
/* Clear flag by writing 1 to it
|
||||
* return with an error code */
|
||||
usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
|
||||
|
||||
return STATUS_ERR_PACKET_COLLISION;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Read data from USART module */
|
||||
*rx_data = usart_hw->DATA.reg;
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Transmit a buffer of characters via the USART
|
||||
*
|
||||
* This blocking function will transmit a block of \c length characters
|
||||
* via the USART.
|
||||
*
|
||||
* \note Using this function in combination with the interrupt (\c _job) functions is
|
||||
* not recommended as it has no functionality to check if there is an
|
||||
* ongoing interrupt driven operation running or not.
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[in] tx_data Pointer to data to transmit
|
||||
* \param[in] length Number of characters to transmit
|
||||
*
|
||||
* \note If using 9-bit data, the array that *tx_data point to should be defined
|
||||
* as uint16_t array and should be casted to uint8_t* pointer. Because it
|
||||
* is an address pointer, the highest byte is not discarded. For example:
|
||||
* \code
|
||||
#define TX_LEN 3
|
||||
uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
|
||||
usart_write_buffer_wait(&module, (uint8_t*)tx_buf, TX_LEN);
|
||||
\endcode
|
||||
*
|
||||
* \return Status of the operation.
|
||||
* \retval STATUS_OK If operation was completed
|
||||
* \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
|
||||
* arguments
|
||||
* \retval STATUS_ERR_TIMEOUT If operation was not completed, due to USART
|
||||
* module timing out
|
||||
* \retval STATUS_ERR_DENIED If the transmitter is not enabled
|
||||
*/
|
||||
enum status_code usart_write_buffer_wait(
|
||||
struct usart_module *const module,
|
||||
const uint8_t *tx_data,
|
||||
uint16_t length)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(module->hw);
|
||||
|
||||
/* Check if the buffer length is valid */
|
||||
if (length == 0) {
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
/* Check that the transmitter is enabled */
|
||||
if (!(module->transmitter_enabled)) {
|
||||
return STATUS_ERR_DENIED;
|
||||
}
|
||||
|
||||
/* Get a pointer to the hardware module instance */
|
||||
SercomUsart *const usart_hw = &(module->hw->USART);
|
||||
|
||||
uint16_t tx_pos = 0;
|
||||
|
||||
/* Blocks while buffer is being transferred */
|
||||
while (length--) {
|
||||
/* Wait for the USART to be ready for new data and abort
|
||||
* operation if it doesn't get ready within the timeout*/
|
||||
for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
|
||||
if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) {
|
||||
break;
|
||||
} else if (i == USART_TIMEOUT) {
|
||||
return STATUS_ERR_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Data to send is at least 8 bits long */
|
||||
uint16_t data_to_send = tx_data[tx_pos++];
|
||||
|
||||
/* Check if the character size exceeds 8 bit */
|
||||
if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
|
||||
data_to_send |= (tx_data[tx_pos++] << 8);
|
||||
}
|
||||
|
||||
/* Send the data through the USART module */
|
||||
usart_write_wait(module, data_to_send);
|
||||
}
|
||||
|
||||
/* Wait until Transmit is complete or timeout */
|
||||
for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
|
||||
if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {
|
||||
break;
|
||||
} else if (i == USART_TIMEOUT) {
|
||||
return STATUS_ERR_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Receive a buffer of \c length characters via the USART
|
||||
*
|
||||
* This blocking function will receive a block of \c length characters
|
||||
* via the USART.
|
||||
*
|
||||
* \note Using this function in combination with the interrupt (\c *_job)
|
||||
* functions is not recommended as it has no functionality to check if
|
||||
* there is an ongoing interrupt driven operation running or not.
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[out] rx_data Pointer to receive buffer
|
||||
* \param[in] length Number of characters to receive
|
||||
*
|
||||
* \note If using 9-bit data, the array that *rx_data point to should be defined
|
||||
* as uint16_t array and should be casted to uint8_t* pointer. Because it
|
||||
* is an address pointer, the highest byte is not discarded. For example:
|
||||
* \code
|
||||
#define RX_LEN 3
|
||||
uint16_t rx_buf[RX_LEN] = {0x0,};
|
||||
usart_read_buffer_wait(&module, (uint8_t*)rx_buf, RX_LEN);
|
||||
\endcode
|
||||
*
|
||||
* \return Status of the operation.
|
||||
* \retval STATUS_OK If operation was completed
|
||||
* \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to an
|
||||
* invalid argument being supplied
|
||||
* \retval STATUS_ERR_TIMEOUT If operation was not completed, due
|
||||
* to USART module timing out
|
||||
* \retval STATUS_ERR_BAD_FORMAT If the operation was not completed,
|
||||
* due to a configuration mismatch
|
||||
* between USART and the sender
|
||||
* \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed,
|
||||
* due to the baudrate being too low or the
|
||||
* system frequency being too high
|
||||
* \retval STATUS_ERR_BAD_DATA If the operation was not completed, due
|
||||
* to data being corrupted
|
||||
* \retval STATUS_ERR_DENIED If the receiver is not enabled
|
||||
*/
|
||||
enum status_code usart_read_buffer_wait(
|
||||
struct usart_module *const module,
|
||||
uint8_t *rx_data,
|
||||
uint16_t length)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(module->hw);
|
||||
|
||||
/* Check if the buffer length is valid */
|
||||
if (length == 0) {
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
/* Check that the receiver is enabled */
|
||||
if (!(module->receiver_enabled)) {
|
||||
return STATUS_ERR_DENIED;
|
||||
}
|
||||
|
||||
/* Get a pointer to the hardware module instance */
|
||||
SercomUsart *const usart_hw = &(module->hw->USART);
|
||||
|
||||
uint16_t rx_pos = 0;
|
||||
|
||||
/* Blocks while buffer is being received */
|
||||
while (length--) {
|
||||
/* Wait for the USART to have new data and abort operation if it
|
||||
* doesn't get ready within the timeout*/
|
||||
for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
|
||||
if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
|
||||
break;
|
||||
} else if (i == USART_TIMEOUT) {
|
||||
return STATUS_ERR_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
enum status_code retval;
|
||||
uint16_t received_data = 0;
|
||||
|
||||
retval = usart_read_wait(module, &received_data);
|
||||
|
||||
if (retval != STATUS_OK) {
|
||||
/* Overflow, abort */
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* Read value will be at least 8-bits long */
|
||||
rx_data[rx_pos++] = received_data;
|
||||
|
||||
/* If 9-bit data, write next received byte to the buffer */
|
||||
if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
|
||||
rx_data[rx_pos++] = (received_data >> 8);
|
||||
}
|
||||
}
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,656 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM SERCOM USART Asynchronous Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#include "usart_interrupt.h"
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Asynchronous write of a buffer with a given length
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[in] tx_data Pointer to data to be transmitted
|
||||
* \param[in] length Length of data buffer
|
||||
*
|
||||
*/
|
||||
enum status_code _usart_write_buffer(
|
||||
struct usart_module *const module,
|
||||
uint8_t *tx_data,
|
||||
uint16_t length)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(module->hw);
|
||||
Assert(tx_data);
|
||||
|
||||
/* Get a pointer to the hardware module instance */
|
||||
SercomUsart *const usart_hw = &(module->hw->USART);
|
||||
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Check if the USART transmitter is busy */
|
||||
if (module->remaining_tx_buffer_length > 0) {
|
||||
system_interrupt_leave_critical_section();
|
||||
return STATUS_BUSY;
|
||||
}
|
||||
|
||||
/* Write parameters to the device instance */
|
||||
module->remaining_tx_buffer_length = length;
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
|
||||
module->tx_buffer_ptr = tx_data;
|
||||
module->tx_status = STATUS_BUSY;
|
||||
|
||||
/* Enable the Data Register Empty Interrupt */
|
||||
usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE;
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Asynchronous read of a buffer with a given length
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[in] rx_data Pointer to data to be received
|
||||
* \param[in] length Length of data buffer
|
||||
*
|
||||
*/
|
||||
enum status_code _usart_read_buffer(
|
||||
struct usart_module *const module,
|
||||
uint8_t *rx_data,
|
||||
uint16_t length)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(module->hw);
|
||||
Assert(rx_data);
|
||||
|
||||
/* Get a pointer to the hardware module instance */
|
||||
SercomUsart *const usart_hw = &(module->hw->USART);
|
||||
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Check if the USART receiver is busy */
|
||||
if (module->remaining_rx_buffer_length > 0) {
|
||||
system_interrupt_leave_critical_section();
|
||||
return STATUS_BUSY;
|
||||
}
|
||||
|
||||
/* Set length for the buffer and the pointer, and let
|
||||
* the interrupt handler do the rest */
|
||||
module->remaining_rx_buffer_length = length;
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
|
||||
module->rx_buffer_ptr = rx_data;
|
||||
module->rx_status = STATUS_BUSY;
|
||||
|
||||
/* Enable the RX Complete Interrupt */
|
||||
usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
|
||||
|
||||
#ifdef FEATURE_USART_LIN_SLAVE
|
||||
/* Enable the break character is received Interrupt */
|
||||
if(module->lin_slave_enabled) {
|
||||
usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef FEATURE_USART_START_FRAME_DECTION
|
||||
/* Enable a start condition is detected Interrupt */
|
||||
if(module->start_frame_detection_enabled) {
|
||||
usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS;
|
||||
}
|
||||
#endif
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Registers a callback
|
||||
*
|
||||
* Registers a callback function, which is implemented by the user.
|
||||
*
|
||||
* \note The callback must be enabled by \ref usart_enable_callback
|
||||
* in order for the interrupt handler to call it when the conditions for
|
||||
* the callback type are met.
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[in] callback_func Pointer to callback function
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*
|
||||
*/
|
||||
void usart_register_callback(
|
||||
struct usart_module *const module,
|
||||
usart_callback_t callback_func,
|
||||
enum usart_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(callback_func);
|
||||
|
||||
/* Register callback function */
|
||||
module->callback[callback_type] = callback_func;
|
||||
|
||||
/* Set the bit corresponding to the callback_type */
|
||||
module->callback_reg_mask |= (1 << callback_type);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Unregisters a callback
|
||||
*
|
||||
* Unregisters a callback function, which is implemented by the user.
|
||||
*
|
||||
* \param[in,out] module Pointer to USART software instance struct
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*
|
||||
*/
|
||||
void usart_unregister_callback(
|
||||
struct usart_module *const module,
|
||||
enum usart_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
|
||||
/* Unregister callback function */
|
||||
module->callback[callback_type] = NULL;
|
||||
|
||||
/* Clear the bit corresponding to the callback_type */
|
||||
module->callback_reg_mask &= ~(1 << callback_type);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Asynchronous write a single char
|
||||
*
|
||||
* Sets up the driver to write the data given. If registered and enabled,
|
||||
* a callback function will be called when the transmit is completed.
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[in] tx_data Data to transfer
|
||||
*
|
||||
* \returns Status of the operation.
|
||||
* \retval STATUS_OK If operation was completed
|
||||
* \retval STATUS_BUSY If operation was not completed, due to the
|
||||
* USART module being busy
|
||||
* \retval STATUS_ERR_DENIED If the transmitter is not enabled
|
||||
*/
|
||||
enum status_code usart_write_job(
|
||||
struct usart_module *const module,
|
||||
const uint16_t *tx_data)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(tx_data);
|
||||
|
||||
|
||||
/* Check that the transmitter is enabled */
|
||||
if (!(module->transmitter_enabled)) {
|
||||
return STATUS_ERR_DENIED;
|
||||
}
|
||||
|
||||
/* Call internal write buffer function with length 1 */
|
||||
return _usart_write_buffer(module, (uint8_t *)tx_data, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Asynchronous read a single char
|
||||
*
|
||||
* Sets up the driver to read data from the USART module to the data
|
||||
* pointer given. If registered and enabled, a callback will be called
|
||||
* when the receiving is completed.
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[out] rx_data Pointer to where received data should be put
|
||||
*
|
||||
* \returns Status of the operation.
|
||||
* \retval STATUS_OK If operation was completed
|
||||
* \retval STATUS_BUSY If operation was not completed
|
||||
*/
|
||||
enum status_code usart_read_job(
|
||||
struct usart_module *const module,
|
||||
uint16_t *const rx_data)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(rx_data);
|
||||
|
||||
/* Call internal read buffer function with length 1 */
|
||||
return _usart_read_buffer(module, (uint8_t *)rx_data, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Asynchronous buffer write
|
||||
*
|
||||
* Sets up the driver to write a given buffer over the USART. If registered and
|
||||
* enabled, a callback function will be called.
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[in] tx_data Pointer do data buffer to transmit
|
||||
* \param[in] length Length of the data to transmit
|
||||
*
|
||||
* \note If using 9-bit data, the array that *tx_data point to should be defined
|
||||
* as uint16_t array and should be casted to uint8_t* pointer. Because it
|
||||
* is an address pointer, the highest byte is not discarded. For example:
|
||||
* \code
|
||||
#define TX_LEN 3
|
||||
uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
|
||||
usart_write_buffer_job(&module, (uint8_t*)tx_buf, TX_LEN);
|
||||
\endcode
|
||||
*
|
||||
* \returns Status of the operation.
|
||||
* \retval STATUS_OK If operation was completed successfully.
|
||||
* \retval STATUS_BUSY If operation was not completed, due to the
|
||||
* USART module being busy
|
||||
* \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
|
||||
* arguments
|
||||
* \retval STATUS_ERR_DENIED If the transmitter is not enabled
|
||||
*/
|
||||
enum status_code usart_write_buffer_job(
|
||||
struct usart_module *const module,
|
||||
uint8_t *tx_data,
|
||||
uint16_t length)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(tx_data);
|
||||
|
||||
if (length == 0) {
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
/* Check that the transmitter is enabled */
|
||||
if (!(module->transmitter_enabled)) {
|
||||
return STATUS_ERR_DENIED;
|
||||
}
|
||||
|
||||
/* Issue internal asynchronous write */
|
||||
return _usart_write_buffer(module, tx_data, length);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Asynchronous buffer read
|
||||
*
|
||||
* Sets up the driver to read from the USART to a given buffer. If registered
|
||||
* and enabled, a callback function will be called.
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[out] rx_data Pointer to data buffer to receive
|
||||
* \param[in] length Data buffer length
|
||||
*
|
||||
* \note If using 9-bit data, the array that *rx_data point to should be defined
|
||||
* as uint16_t array and should be casted to uint8_t* pointer. Because it
|
||||
* is an address pointer, the highest byte is not discarded. For example:
|
||||
* \code
|
||||
#define RX_LEN 3
|
||||
uint16_t rx_buf[RX_LEN] = {0x0,};
|
||||
usart_read_buffer_job(&module, (uint8_t*)rx_buf, RX_LEN);
|
||||
\endcode
|
||||
*
|
||||
* \returns Status of the operation.
|
||||
* \retval STATUS_OK If operation was completed
|
||||
* \retval STATUS_BUSY If operation was not completed, due to the
|
||||
* USART module being busy
|
||||
* \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
|
||||
* arguments
|
||||
* \retval STATUS_ERR_DENIED If the transmitter is not enabled
|
||||
*/
|
||||
enum status_code usart_read_buffer_job(
|
||||
struct usart_module *const module,
|
||||
uint8_t *rx_data,
|
||||
uint16_t length)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(rx_data);
|
||||
|
||||
if (length == 0) {
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
/* Check that the receiver is enabled */
|
||||
if (!(module->receiver_enabled)) {
|
||||
return STATUS_ERR_DENIED;
|
||||
}
|
||||
|
||||
/* Issue internal asynchronous read */
|
||||
return _usart_read_buffer(module, rx_data, length);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Cancels ongoing read/write operation
|
||||
*
|
||||
* Cancels the ongoing read/write operation modifying parameters in the
|
||||
* USART software struct.
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[in] transceiver_type Transfer type to cancel
|
||||
*/
|
||||
void usart_abort_job(
|
||||
struct usart_module *const module,
|
||||
enum usart_transceiver_type transceiver_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(module->hw);
|
||||
|
||||
/* Get a pointer to the hardware module instance */
|
||||
SercomUsart *const usart_hw = &(module->hw->USART);
|
||||
|
||||
switch(transceiver_type) {
|
||||
case USART_TRANSCEIVER_RX:
|
||||
/* Clear the interrupt flag in order to prevent the receive
|
||||
* complete callback to fire */
|
||||
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
|
||||
|
||||
/* Clear the software reception buffer */
|
||||
module->remaining_rx_buffer_length = 0;
|
||||
|
||||
break;
|
||||
|
||||
case USART_TRANSCEIVER_TX:
|
||||
/* Clear the interrupt flag in order to prevent the receive
|
||||
* complete callback to fire */
|
||||
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
|
||||
|
||||
/* Clear the software reception buffer */
|
||||
module->remaining_tx_buffer_length = 0;
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get status from the ongoing or last asynchronous transfer operation
|
||||
*
|
||||
* Returns the error from a given ongoing or last asynchronous transfer operation.
|
||||
* Either from a read or write transfer.
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[in] transceiver_type Transfer type to check
|
||||
*
|
||||
* \return Status of the given job.
|
||||
* \retval STATUS_OK No error occurred during the last transfer
|
||||
* \retval STATUS_BUSY A transfer is ongoing
|
||||
* \retval STATUS_ERR_BAD_DATA The last operation was aborted due to a
|
||||
* parity error. The transfer could be affected
|
||||
* by external noise
|
||||
* \retval STATUS_ERR_BAD_FORMAT The last operation was aborted due to a
|
||||
* frame error
|
||||
* \retval STATUS_ERR_OVERFLOW The last operation was aborted due to a
|
||||
* buffer overflow
|
||||
* \retval STATUS_ERR_INVALID_ARG An invalid transceiver enum given
|
||||
*/
|
||||
enum status_code usart_get_job_status(
|
||||
struct usart_module *const module,
|
||||
enum usart_transceiver_type transceiver_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
|
||||
/* Variable for status code */
|
||||
enum status_code status_code;
|
||||
|
||||
switch(transceiver_type) {
|
||||
case USART_TRANSCEIVER_RX:
|
||||
status_code = module->rx_status;
|
||||
break;
|
||||
|
||||
case USART_TRANSCEIVER_TX:
|
||||
status_code = module->tx_status;
|
||||
break;
|
||||
|
||||
default:
|
||||
status_code = STATUS_ERR_INVALID_ARG;
|
||||
break;
|
||||
}
|
||||
|
||||
return status_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Handles interrupts as they occur, and it will run callback functions
|
||||
* which are registered and enabled.
|
||||
*
|
||||
* \param[in] instance ID of the SERCOM instance calling the interrupt
|
||||
* handler.
|
||||
*/
|
||||
void _usart_interrupt_handler(
|
||||
uint8_t instance)
|
||||
{
|
||||
/* Temporary variables */
|
||||
uint16_t interrupt_status;
|
||||
uint16_t callback_status;
|
||||
uint8_t error_code;
|
||||
|
||||
|
||||
/* Get device instance from the look-up table */
|
||||
struct usart_module *module
|
||||
= (struct usart_module *)_sercom_instances[instance];
|
||||
|
||||
/* Pointer to the hardware module instance */
|
||||
SercomUsart *const usart_hw
|
||||
= &(module->hw->USART);
|
||||
|
||||
/* Wait for the synchronization to complete */
|
||||
_usart_wait_for_sync(module);
|
||||
|
||||
/* Read and mask interrupt flag register */
|
||||
interrupt_status = usart_hw->INTFLAG.reg;
|
||||
interrupt_status &= usart_hw->INTENSET.reg;
|
||||
callback_status = module->callback_reg_mask &
|
||||
module->callback_enable_mask;
|
||||
|
||||
/* Check if a DATA READY interrupt has occurred,
|
||||
* and if there is more to transfer */
|
||||
if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
|
||||
if (module->remaining_tx_buffer_length) {
|
||||
/* Write value will be at least 8-bits long */
|
||||
uint16_t data_to_send = *(module->tx_buffer_ptr);
|
||||
/* Increment 8-bit pointer */
|
||||
(module->tx_buffer_ptr)++;
|
||||
|
||||
if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
|
||||
data_to_send |= (*(module->tx_buffer_ptr) << 8);
|
||||
/* Increment 8-bit pointer */
|
||||
(module->tx_buffer_ptr)++;
|
||||
}
|
||||
/* Write the data to send */
|
||||
usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
|
||||
|
||||
if (--(module->remaining_tx_buffer_length) == 0) {
|
||||
/* Disable the Data Register Empty Interrupt */
|
||||
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
|
||||
/* Enable Transmission Complete interrupt */
|
||||
usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
|
||||
|
||||
}
|
||||
} else {
|
||||
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if the Transmission Complete interrupt has occurred and
|
||||
* that the transmit buffer is empty */
|
||||
if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
|
||||
|
||||
/* Disable TX Complete Interrupt, and set STATUS_OK */
|
||||
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
|
||||
module->tx_status = STATUS_OK;
|
||||
|
||||
/* Run callback if registered and enabled */
|
||||
if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
|
||||
(*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if the Receive Complete interrupt has occurred, and that
|
||||
* there's more data to receive */
|
||||
if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
|
||||
|
||||
if (module->remaining_rx_buffer_length) {
|
||||
/* Read out the status code and mask away all but the 4 LSBs*/
|
||||
error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
|
||||
#if !SAMD20
|
||||
/* CTS status should not be considered as an error */
|
||||
if(error_code & SERCOM_USART_STATUS_CTS) {
|
||||
error_code &= ~SERCOM_USART_STATUS_CTS;
|
||||
}
|
||||
#endif
|
||||
#ifdef FEATURE_USART_LIN_MASTER
|
||||
/* TXE status should not be considered as an error */
|
||||
if(error_code & SERCOM_USART_STATUS_TXE) {
|
||||
error_code &= ~SERCOM_USART_STATUS_TXE;
|
||||
}
|
||||
#endif
|
||||
/* Check if an error has occurred during the receiving */
|
||||
if (error_code) {
|
||||
/* Check which error occurred */
|
||||
if (error_code & SERCOM_USART_STATUS_FERR) {
|
||||
/* Store the error code and clear flag by writing 1 to it */
|
||||
module->rx_status = STATUS_ERR_BAD_FORMAT;
|
||||
usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
|
||||
} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
|
||||
/* Store the error code and clear flag by writing 1 to it */
|
||||
module->rx_status = STATUS_ERR_OVERFLOW;
|
||||
usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
|
||||
} else if (error_code & SERCOM_USART_STATUS_PERR) {
|
||||
/* Store the error code and clear flag by writing 1 to it */
|
||||
module->rx_status = STATUS_ERR_BAD_DATA;
|
||||
usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
|
||||
}
|
||||
#ifdef FEATURE_USART_LIN_SLAVE
|
||||
else if (error_code & SERCOM_USART_STATUS_ISF) {
|
||||
/* Store the error code and clear flag by writing 1 to it */
|
||||
module->rx_status = STATUS_ERR_PROTOCOL;
|
||||
usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
|
||||
}
|
||||
#endif
|
||||
#ifdef FEATURE_USART_COLLISION_DECTION
|
||||
else if (error_code & SERCOM_USART_STATUS_COLL) {
|
||||
/* Store the error code and clear flag by writing 1 to it */
|
||||
module->rx_status = STATUS_ERR_PACKET_COLLISION;
|
||||
usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Run callback if registered and enabled */
|
||||
if (callback_status
|
||||
& (1 << USART_CALLBACK_ERROR)) {
|
||||
(*(module->callback[USART_CALLBACK_ERROR]))(module);
|
||||
}
|
||||
|
||||
} else {
|
||||
|
||||
/* Read current packet from DATA register,
|
||||
* increment buffer pointer and decrement buffer length */
|
||||
uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
|
||||
|
||||
/* Read value will be at least 8-bits long */
|
||||
*(module->rx_buffer_ptr) = received_data;
|
||||
/* Increment 8-bit pointer */
|
||||
module->rx_buffer_ptr += 1;
|
||||
|
||||
if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
|
||||
/* 9-bit data, write next received byte to the buffer */
|
||||
*(module->rx_buffer_ptr) = (received_data >> 8);
|
||||
/* Increment 8-bit pointer */
|
||||
module->rx_buffer_ptr += 1;
|
||||
}
|
||||
|
||||
/* Check if the last character have been received */
|
||||
if(--(module->remaining_rx_buffer_length) == 0) {
|
||||
/* Disable RX Complete Interrupt,
|
||||
* and set STATUS_OK */
|
||||
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
|
||||
module->rx_status = STATUS_OK;
|
||||
|
||||
/* Run callback if registered and enabled */
|
||||
if (callback_status
|
||||
& (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
|
||||
(*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* This should not happen. Disable Receive Complete interrupt. */
|
||||
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
|
||||
if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
|
||||
/* Disable interrupts */
|
||||
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
|
||||
/* Clear interrupt flag */
|
||||
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
|
||||
|
||||
/* Run callback if registered and enabled */
|
||||
if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
|
||||
(*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef FEATURE_USART_LIN_SLAVE
|
||||
if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
|
||||
/* Disable interrupts */
|
||||
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
|
||||
/* Clear interrupt flag */
|
||||
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
|
||||
|
||||
/* Run callback if registered and enabled */
|
||||
if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
|
||||
(*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef FEATURE_USART_START_FRAME_DECTION
|
||||
if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
|
||||
/* Disable interrupts */
|
||||
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
|
||||
/* Clear interrupt flag */
|
||||
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
|
||||
|
||||
/* Run callback if registered and enabled */
|
||||
if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
|
||||
(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -0,0 +1,167 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM SERCOM USART Asynchronous Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef USART_INTERRUPT_H_INCLUDED
|
||||
#define USART_INTERRUPT_H_INCLUDED
|
||||
|
||||
#include "usart.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
enum status_code _usart_write_buffer(
|
||||
struct usart_module *const module,
|
||||
uint8_t *tx_data,
|
||||
uint16_t length);
|
||||
|
||||
enum status_code _usart_read_buffer(
|
||||
struct usart_module *const module,
|
||||
uint8_t *rx_data,
|
||||
uint16_t length);
|
||||
|
||||
void _usart_interrupt_handler(
|
||||
uint8_t instance);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup asfdoc_sam0_sercom_usart_group
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \name Callback Management
|
||||
* @{
|
||||
*/
|
||||
void usart_register_callback(
|
||||
struct usart_module *const module,
|
||||
usart_callback_t callback_func,
|
||||
enum usart_callback callback_type);
|
||||
|
||||
void usart_unregister_callback(
|
||||
struct usart_module *module,
|
||||
enum usart_callback callback_type);
|
||||
|
||||
/**
|
||||
* \brief Enables callback
|
||||
*
|
||||
* Enables the callback function registered by the \ref usart_register_callback.
|
||||
* The callback function will be called from the interrupt handler when the
|
||||
* conditions for the callback type are met.
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*/
|
||||
static inline void usart_enable_callback(
|
||||
struct usart_module *const module,
|
||||
enum usart_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
|
||||
/* Enable callback */
|
||||
module->callback_enable_mask |= (1 << callback_type);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable callback
|
||||
*
|
||||
* Disables the callback function registered by the \ref usart_register_callback,
|
||||
* and the callback will not be called from the interrupt routine.
|
||||
*
|
||||
* \param[in] module Pointer to USART software instance struct
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*/
|
||||
static inline void usart_disable_callback(
|
||||
struct usart_module *const module,
|
||||
enum usart_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
|
||||
/* Disable callback */
|
||||
module->callback_enable_mask &= ~(1 << callback_type);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* \name Writing and Reading
|
||||
* @{
|
||||
*/
|
||||
enum status_code usart_write_job(
|
||||
struct usart_module *const module,
|
||||
const uint16_t *tx_data);
|
||||
|
||||
enum status_code usart_read_job(
|
||||
struct usart_module *const module,
|
||||
uint16_t *const rx_data);
|
||||
|
||||
enum status_code usart_write_buffer_job(
|
||||
struct usart_module *const module,
|
||||
uint8_t *tx_data,
|
||||
uint16_t length);
|
||||
|
||||
enum status_code usart_read_buffer_job(
|
||||
struct usart_module *const module,
|
||||
uint8_t *rx_data,
|
||||
uint16_t length);
|
||||
|
||||
void usart_abort_job(
|
||||
struct usart_module *const module,
|
||||
enum usart_transceiver_type transceiver_type);
|
||||
|
||||
enum status_code usart_get_job_status(
|
||||
struct usart_module *const module,
|
||||
enum usart_transceiver_type transceiver_type);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* USART_INTERRUPT_H_INCLUDED */
|
||||
|
||||
@ -0,0 +1,43 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Clock Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef SYSTEM_CLOCK_H_INCLUDED
|
||||
#define SYSTEM_CLOCK_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
#include <gclk.h>
|
||||
#include <clock_feature.h>
|
||||
|
||||
#endif /* SYSTEM_CLOCK_H_INCLUDED */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,444 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM D21/R21/DA/HA Clock Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef CLOCK_CONFIG_CHECK_H
|
||||
# define CLOCK_CONFIG_CHECK_H
|
||||
|
||||
#if !defined(CONF_CLOCK_FLASH_WAIT_STATES)
|
||||
# error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_CPU_DIVIDER)
|
||||
# error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_APBA_DIVIDER)
|
||||
# error CONF_CLOCK_APBA_DIVIDER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_APBB_DIVIDER)
|
||||
# error CONF_CLOCK_APBB_DIVIDER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_APBC_DIVIDER)
|
||||
# error CONF_CLOCK_APBC_DIVIDER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_OSC8M_PRESCALER)
|
||||
# error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND)
|
||||
# error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC_ENABLE)
|
||||
# error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL)
|
||||
# error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY)
|
||||
# error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME)
|
||||
# error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL)
|
||||
# error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC_ON_DEMAND)
|
||||
# error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC32K_ENABLE)
|
||||
# error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL)
|
||||
# error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME)
|
||||
# error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL)
|
||||
# error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT)
|
||||
# error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT)
|
||||
# error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND)
|
||||
# error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_OSC32K_ENABLE)
|
||||
# error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME)
|
||||
# error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT)
|
||||
# error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT)
|
||||
# error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND)
|
||||
# error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_ENABLE)
|
||||
# error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_LOOP_MODE)
|
||||
# error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_ON_DEMAND)
|
||||
# error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_FINE_VALUE)
|
||||
# error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR)
|
||||
# error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR)
|
||||
# error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK)
|
||||
# error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK)
|
||||
# error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP)
|
||||
# error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE)
|
||||
# error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE)
|
||||
# error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE)
|
||||
# error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_ENABLE)
|
||||
# error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_ON_DEMAND)
|
||||
# error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS)
|
||||
# error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST)
|
||||
# error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE)
|
||||
# error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_LOCK_TIME)
|
||||
# error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK)
|
||||
# error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_FILTER)
|
||||
# error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY)
|
||||
# error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER)
|
||||
# error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY)
|
||||
# error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR)
|
||||
# error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR)
|
||||
# error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_CONFIGURE_GCLK)
|
||||
# error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_0_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE)
|
||||
# error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_0_PRESCALER)
|
||||
# error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_1_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE)
|
||||
# error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_1_PRESCALER)
|
||||
# error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_2_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE)
|
||||
# error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_2_PRESCALER)
|
||||
# error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_3_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE)
|
||||
# error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_3_PRESCALER)
|
||||
# error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_4_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE)
|
||||
# error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_4_PRESCALER)
|
||||
# error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_5_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE)
|
||||
# error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_5_PRESCALER)
|
||||
# error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_6_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE)
|
||||
# error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_6_PRESCALER)
|
||||
# error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_7_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE)
|
||||
# error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_7_PRESCALER)
|
||||
# error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_8_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY)
|
||||
# error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE)
|
||||
# error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_8_PRESCALER)
|
||||
# error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE)
|
||||
# error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h
|
||||
#endif
|
||||
|
||||
#endif /* CLOCK_CONFIG_CHECK_H */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,512 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM D21/R21/DA/HA Generic Clock Driver
|
||||
*
|
||||
* Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#include <gclk.h>
|
||||
#include <clock.h>
|
||||
#include <system_interrupt.h>
|
||||
|
||||
/**
|
||||
* \brief Determines if the hardware module(s) are currently synchronizing to the bus.
|
||||
*
|
||||
* Checks to see if the underlying hardware peripheral module(s) are currently
|
||||
* synchronizing across multiple clock domains to the hardware bus, This
|
||||
* function can be used to delay further operations on a module until such time
|
||||
* that it is ready, to prevent blocking delays for synchronization in the
|
||||
* user application.
|
||||
*
|
||||
* \return Synchronization status of the underlying hardware module(s).
|
||||
*
|
||||
* \retval false if the module has completed synchronization
|
||||
* \retval true if the module synchronization is ongoing
|
||||
*/
|
||||
static inline bool system_gclk_is_syncing(void)
|
||||
{
|
||||
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initializes the GCLK driver.
|
||||
*
|
||||
* Initializes the Generic Clock module, disabling and resetting all active
|
||||
* Generic Clock Generators and Channels to their power-on default values.
|
||||
*/
|
||||
void system_gclk_init(void)
|
||||
{
|
||||
/* Turn on the digital interface clock */
|
||||
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
|
||||
|
||||
/* Software reset the module to ensure it is re-initialized correctly */
|
||||
GCLK->CTRL.reg = GCLK_CTRL_SWRST;
|
||||
while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
|
||||
/* Wait for reset to complete */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Writes a Generic Clock Generator configuration to the hardware module.
|
||||
*
|
||||
* Writes out a given configuration of a Generic Clock Generator configuration
|
||||
* to the hardware module.
|
||||
*
|
||||
* \note Changing the clock source on the fly (on a running
|
||||
* generator) can take additional time if the clock source is configured
|
||||
* to only run on-demand (ONDEMAND bit is set) and it is not currently
|
||||
* running (no peripheral is requesting the clock source). In this case
|
||||
* the GCLK will request the new clock while still keeping a request to
|
||||
* the old clock source until the new clock source is ready.
|
||||
*
|
||||
* \note This function will not start a generator that is not already running;
|
||||
* to start the generator, call \ref system_gclk_gen_enable()
|
||||
* after configuring a generator.
|
||||
*
|
||||
* \param[in] generator Generic Clock Generator index to configure
|
||||
* \param[in] config Configuration settings for the generator
|
||||
*/
|
||||
void system_gclk_gen_set_config(
|
||||
const uint8_t generator,
|
||||
struct system_gclk_gen_config *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(config);
|
||||
|
||||
/* Cache new register configurations to minimize sync requirements. */
|
||||
uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
|
||||
uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos);
|
||||
|
||||
/* Select the requested source clock for the generator */
|
||||
new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
|
||||
|
||||
/* Configure the clock to be either high or low when disabled */
|
||||
if (config->high_when_disabled) {
|
||||
new_genctrl_config |= GCLK_GENCTRL_OOV;
|
||||
}
|
||||
|
||||
/* Configure if the clock output to I/O pin should be enabled. */
|
||||
if (config->output_enable) {
|
||||
new_genctrl_config |= GCLK_GENCTRL_OE;
|
||||
}
|
||||
|
||||
/* Set division factor */
|
||||
if (config->division_factor > 1) {
|
||||
/* Check if division is a power of two */
|
||||
if (((config->division_factor & (config->division_factor - 1)) == 0)) {
|
||||
/* Determine the index of the highest bit set to get the
|
||||
* division factor that must be loaded into the division
|
||||
* register */
|
||||
|
||||
uint32_t div2_count = 0;
|
||||
|
||||
uint32_t mask;
|
||||
for (mask = (1UL << 1); mask < config->division_factor;
|
||||
mask <<= 1) {
|
||||
div2_count++;
|
||||
}
|
||||
|
||||
/* Set binary divider power of 2 division factor */
|
||||
new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos;
|
||||
new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
|
||||
} else {
|
||||
/* Set integer division factor */
|
||||
|
||||
new_gendiv_config |=
|
||||
(config->division_factor) << GCLK_GENDIV_DIV_Pos;
|
||||
|
||||
/* Enable non-binary division with increased duty cycle accuracy */
|
||||
new_genctrl_config |= GCLK_GENCTRL_IDC;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Enable or disable the clock in standby mode */
|
||||
if (config->run_in_standby) {
|
||||
new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
|
||||
}
|
||||
|
||||
while (system_gclk_is_syncing()) {
|
||||
/* Wait for synchronization */
|
||||
};
|
||||
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Select the correct generator */
|
||||
*((uint8_t*)&GCLK->GENDIV.reg) = generator;
|
||||
|
||||
/* Write the new generator configuration */
|
||||
while (system_gclk_is_syncing()) {
|
||||
/* Wait for synchronization */
|
||||
};
|
||||
GCLK->GENDIV.reg = new_gendiv_config;
|
||||
|
||||
while (system_gclk_is_syncing()) {
|
||||
/* Wait for synchronization */
|
||||
};
|
||||
GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enables a Generic Clock Generator that was previously configured.
|
||||
*
|
||||
* Starts the clock generation of a Generic Clock Generator that was previously
|
||||
* configured via a call to \ref system_gclk_gen_set_config().
|
||||
*
|
||||
* \param[in] generator Generic Clock Generator index to enable
|
||||
*/
|
||||
void system_gclk_gen_enable(
|
||||
const uint8_t generator)
|
||||
{
|
||||
while (system_gclk_is_syncing()) {
|
||||
/* Wait for synchronization */
|
||||
};
|
||||
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Select the requested generator */
|
||||
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
|
||||
while (system_gclk_is_syncing()) {
|
||||
/* Wait for synchronization */
|
||||
};
|
||||
|
||||
/* Enable generator */
|
||||
GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disables a Generic Clock Generator that was previously enabled.
|
||||
*
|
||||
* Stops the clock generation of a Generic Clock Generator that was previously
|
||||
* started via a call to \ref system_gclk_gen_enable().
|
||||
*
|
||||
* \param[in] generator Generic Clock Generator index to disable
|
||||
*/
|
||||
void system_gclk_gen_disable(
|
||||
const uint8_t generator)
|
||||
{
|
||||
while (system_gclk_is_syncing()) {
|
||||
/* Wait for synchronization */
|
||||
};
|
||||
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Select the requested generator */
|
||||
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
|
||||
while (system_gclk_is_syncing()) {
|
||||
/* Wait for synchronization */
|
||||
};
|
||||
|
||||
/* Disable generator */
|
||||
GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
|
||||
while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {
|
||||
/* Wait for clock to become disabled */
|
||||
}
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Determins if the specified Generic Clock Generator is enabled.
|
||||
*
|
||||
* \param[in] generator Generic Clock Generator index to check
|
||||
*
|
||||
* \return The enabled status.
|
||||
* \retval true The Generic Clock Generator is enabled
|
||||
* \retval false The Generic Clock Generator is disabled
|
||||
*/
|
||||
bool system_gclk_gen_is_enabled(
|
||||
const uint8_t generator)
|
||||
{
|
||||
bool enabled;
|
||||
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Select the requested generator */
|
||||
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
|
||||
/* Obtain the enabled status */
|
||||
enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieves the clock frequency of a Generic Clock generator.
|
||||
*
|
||||
* Determines the clock frequency (in Hz) of a specified Generic Clock
|
||||
* generator, used as a source to a Generic Clock Channel module.
|
||||
*
|
||||
* \param[in] generator Generic Clock Generator index
|
||||
*
|
||||
* \return The frequency of the generic clock generator, in Hz.
|
||||
*/
|
||||
uint32_t system_gclk_gen_get_hz(
|
||||
const uint8_t generator)
|
||||
{
|
||||
while (system_gclk_is_syncing()) {
|
||||
/* Wait for synchronization */
|
||||
};
|
||||
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Select the appropriate generator */
|
||||
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
|
||||
while (system_gclk_is_syncing()) {
|
||||
/* Wait for synchronization */
|
||||
};
|
||||
|
||||
/* Get the frequency of the source connected to the GCLK generator */
|
||||
uint32_t gen_input_hz = system_clock_source_get_hz(
|
||||
(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
|
||||
|
||||
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
|
||||
|
||||
uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
|
||||
|
||||
/* Select the appropriate generator division register */
|
||||
*((uint8_t*)&GCLK->GENDIV.reg) = generator;
|
||||
while (system_gclk_is_syncing()) {
|
||||
/* Wait for synchronization */
|
||||
};
|
||||
|
||||
uint32_t divider = GCLK->GENDIV.bit.DIV;
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
|
||||
/* Check if the generator is using fractional or binary division */
|
||||
if (!divsel && divider > 1) {
|
||||
gen_input_hz /= divider;
|
||||
} else if (divsel) {
|
||||
gen_input_hz >>= (divider+1);
|
||||
}
|
||||
|
||||
return gen_input_hz;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Writes a Generic Clock configuration to the hardware module.
|
||||
*
|
||||
* Writes out a given configuration of a Generic Clock configuration to the
|
||||
* hardware module. If the clock is currently running, it will be stopped.
|
||||
*
|
||||
* \note Once called the clock will not be running; to start the clock,
|
||||
* call \ref system_gclk_chan_enable() after configuring a clock channel.
|
||||
*
|
||||
* \param[in] channel Generic Clock channel to configure
|
||||
* \param[in] config Configuration settings for the clock
|
||||
*
|
||||
*/
|
||||
void system_gclk_chan_set_config(
|
||||
const uint8_t channel,
|
||||
struct system_gclk_chan_config *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(config);
|
||||
|
||||
/* Cache the new config to reduce sync requirements */
|
||||
uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
|
||||
|
||||
/* Select the desired generic clock generator */
|
||||
new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
|
||||
|
||||
/* Disable generic clock channel */
|
||||
system_gclk_chan_disable(channel);
|
||||
|
||||
/* Write the new configuration */
|
||||
GCLK->CLKCTRL.reg = new_clkctrl_config;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enables a Generic Clock that was previously configured.
|
||||
*
|
||||
* Starts the clock generation of a Generic Clock that was previously
|
||||
* configured via a call to \ref system_gclk_chan_set_config().
|
||||
*
|
||||
* \param[in] channel Generic Clock channel to enable
|
||||
*/
|
||||
void system_gclk_chan_enable(
|
||||
const uint8_t channel)
|
||||
{
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Select the requested generator channel */
|
||||
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
|
||||
|
||||
/* Enable the generic clock */
|
||||
GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disables a Generic Clock that was previously enabled.
|
||||
*
|
||||
* Stops the clock generation of a Generic Clock that was previously started
|
||||
* via a call to \ref system_gclk_chan_enable().
|
||||
*
|
||||
* \param[in] channel Generic Clock channel to disable
|
||||
*/
|
||||
void system_gclk_chan_disable(
|
||||
const uint8_t channel)
|
||||
{
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Select the requested generator channel */
|
||||
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
|
||||
|
||||
/* Sanity check WRTLOCK */
|
||||
Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
|
||||
|
||||
/* Switch to known-working source so that the channel can be disabled */
|
||||
uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
|
||||
GCLK->CLKCTRL.bit.GEN = 0;
|
||||
|
||||
/* Disable the generic clock */
|
||||
GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
|
||||
while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
|
||||
/* Wait for clock to become disabled */
|
||||
}
|
||||
|
||||
/* Restore previous configured clock generator */
|
||||
GCLK->CLKCTRL.bit.GEN = prev_gen_id;
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Determins if the specified Generic Clock channel is enabled.
|
||||
*
|
||||
* \param[in] channel Generic Clock Channel index
|
||||
*
|
||||
* \return The enabled status.
|
||||
* \retval true The Generic Clock channel is enabled
|
||||
* \retval false The Generic Clock channel is disabled
|
||||
*/
|
||||
bool system_gclk_chan_is_enabled(
|
||||
const uint8_t channel)
|
||||
{
|
||||
bool enabled;
|
||||
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Select the requested generic clock channel */
|
||||
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
|
||||
enabled = GCLK->CLKCTRL.bit.CLKEN;
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Locks a Generic Clock channel from further configuration writes.
|
||||
*
|
||||
* Locks a generic clock channel from further configuration writes. It is only
|
||||
* possible to unlock the channel configuration through a power on reset.
|
||||
*
|
||||
* \param[in] channel Generic Clock channel to enable
|
||||
*/
|
||||
void system_gclk_chan_lock(
|
||||
const uint8_t channel)
|
||||
{
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Select the requested generator channel */
|
||||
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
|
||||
|
||||
/* Lock the generic clock */
|
||||
GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK | GCLK_CLKCTRL_CLKEN;
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Determins if the specified Generic Clock channel is locked.
|
||||
*
|
||||
* \param[in] channel Generic Clock Channel index
|
||||
*
|
||||
* \return The lock status.
|
||||
* \retval true The Generic Clock channel is locked
|
||||
* \retval false The Generic Clock channel is not locked
|
||||
*/
|
||||
bool system_gclk_chan_is_locked(
|
||||
const uint8_t channel)
|
||||
{
|
||||
bool locked;
|
||||
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Select the requested generic clock channel */
|
||||
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
|
||||
locked = GCLK->CLKCTRL.bit.WRTLOCK;
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
|
||||
return locked;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieves the clock frequency of a Generic Clock channel.
|
||||
*
|
||||
* Determines the clock frequency (in Hz) of a specified Generic Clock
|
||||
* channel, used as a source to a device peripheral module.
|
||||
*
|
||||
* \param[in] channel Generic Clock Channel index
|
||||
*
|
||||
* \return The frequency of the generic clock channel, in Hz.
|
||||
*/
|
||||
uint32_t system_gclk_chan_get_hz(
|
||||
const uint8_t channel)
|
||||
{
|
||||
uint8_t gen_id;
|
||||
|
||||
system_interrupt_enter_critical_section();
|
||||
|
||||
/* Select the requested generic clock channel */
|
||||
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
|
||||
gen_id = GCLK->CLKCTRL.bit.GEN;
|
||||
|
||||
system_interrupt_leave_critical_section();
|
||||
|
||||
/* Return the clock speed of the associated GCLK generator */
|
||||
return system_gclk_gen_get_hz(gen_id);
|
||||
}
|
||||
@ -0,0 +1,297 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Generic Clock Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED
|
||||
#define SYSTEM_CLOCK_GCLK_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup asfdoc_sam0_system_clock_group
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief List of available GCLK generators.
|
||||
*
|
||||
* List of Available GCLK generators. This enum is used in the peripheral
|
||||
* device drivers to select the GCLK generator to be used for its operation.
|
||||
*
|
||||
* The number of GCLK generators available is device dependent.
|
||||
*/
|
||||
enum gclk_generator {
|
||||
/** GCLK generator channel 0 */
|
||||
GCLK_GENERATOR_0,
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)
|
||||
/** GCLK generator channel 1 */
|
||||
GCLK_GENERATOR_1,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)
|
||||
/** GCLK generator channel 2 */
|
||||
GCLK_GENERATOR_2,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)
|
||||
/** GCLK generator channel 3 */
|
||||
GCLK_GENERATOR_3,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)
|
||||
/** GCLK generator channel 4 */
|
||||
GCLK_GENERATOR_4,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)
|
||||
/** GCLK generator channel 5 */
|
||||
GCLK_GENERATOR_5,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)
|
||||
/** GCLK generator channel 6 */
|
||||
GCLK_GENERATOR_6,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)
|
||||
/** GCLK generator channel 7 */
|
||||
GCLK_GENERATOR_7,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)
|
||||
/** GCLK generator channel 8 */
|
||||
GCLK_GENERATOR_8,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)
|
||||
/** GCLK generator channel 9 */
|
||||
GCLK_GENERATOR_9,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)
|
||||
/** GCLK generator channel 10 */
|
||||
GCLK_GENERATOR_10,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)
|
||||
/** GCLK generator channel 11 */
|
||||
GCLK_GENERATOR_11,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)
|
||||
/** GCLK generator channel 12 */
|
||||
GCLK_GENERATOR_12,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)
|
||||
/** GCLK generator channel 13 */
|
||||
GCLK_GENERATOR_13,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)
|
||||
/** GCLK generator channel 14 */
|
||||
GCLK_GENERATOR_14,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)
|
||||
/** GCLK generator channel 15 */
|
||||
GCLK_GENERATOR_15,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)
|
||||
/** GCLK generator channel 16 */
|
||||
GCLK_GENERATOR_16,
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Generic Clock Generator configuration structure.
|
||||
*
|
||||
* Configuration structure for a Generic Clock Generator channel. This
|
||||
* structure should be initialized by the
|
||||
* \ref system_gclk_gen_get_config_defaults() function before being modified by
|
||||
* the user application.
|
||||
*/
|
||||
struct system_gclk_gen_config {
|
||||
/** Source clock input channel index, see the \ref system_clock_source */
|
||||
uint8_t source_clock;
|
||||
/** If \c true, the generator output level is high when disabled */
|
||||
bool high_when_disabled;
|
||||
/** Integer division factor of the clock output compared to the input */
|
||||
uint32_t division_factor;
|
||||
/** If \c true, the clock is kept enabled during device standby mode */
|
||||
bool run_in_standby;
|
||||
/** If \c true, enables GCLK generator clock output to a GPIO pin */
|
||||
bool output_enable;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Generic Clock configuration structure.
|
||||
*
|
||||
* Configuration structure for a Generic Clock channel. This structure
|
||||
* should be initialized by the \ref system_gclk_chan_get_config_defaults()
|
||||
* function before being modified by the user application.
|
||||
*/
|
||||
struct system_gclk_chan_config {
|
||||
/** Generic Clock Generator source channel */
|
||||
enum gclk_generator source_generator;
|
||||
};
|
||||
|
||||
/** \name Generic Clock Management
|
||||
* @{
|
||||
*/
|
||||
void system_gclk_init(void);
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* \name Generic Clock Management (Generators)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initializes a Generic Clock Generator configuration structure to defaults.
|
||||
*
|
||||
* Initializes a given Generic Clock Generator configuration structure to
|
||||
* a set of known default values. This function should be called on all
|
||||
* new instances of these configuration structures before being modified
|
||||
* by the user application.
|
||||
*
|
||||
* The default configuration is:
|
||||
* \li The clock is generated undivided from the source frequency
|
||||
* \li The clock generator output is low when the generator is disabled
|
||||
* \li The input clock is sourced from input clock channel 0
|
||||
* \li The clock will be disabled during sleep
|
||||
* \li The clock output will not be routed to a physical GPIO pin
|
||||
*
|
||||
* \param[out] config Configuration structure to initialize to default values
|
||||
*/
|
||||
static inline void system_gclk_gen_get_config_defaults(
|
||||
struct system_gclk_gen_config *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(config);
|
||||
|
||||
/* Default configuration values */
|
||||
config->division_factor = 1;
|
||||
config->high_when_disabled = false;
|
||||
#if SAML21 || SAML22 || SAMR30 || SAMR34 || SAMR35
|
||||
config->source_clock = GCLK_SOURCE_OSC16M;
|
||||
#elif (SAMC20) || (SAMC21)
|
||||
config->source_clock = GCLK_SOURCE_OSC48M;
|
||||
#else
|
||||
config->source_clock = GCLK_SOURCE_OSC8M;
|
||||
#endif
|
||||
config->run_in_standby = false;
|
||||
config->output_enable = false;
|
||||
}
|
||||
|
||||
void system_gclk_gen_set_config(
|
||||
const uint8_t generator,
|
||||
struct system_gclk_gen_config *const config);
|
||||
|
||||
void system_gclk_gen_enable(
|
||||
const uint8_t generator);
|
||||
|
||||
void system_gclk_gen_disable(
|
||||
const uint8_t generator);
|
||||
|
||||
bool system_gclk_gen_is_enabled(
|
||||
const uint8_t generator);
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* \name Generic Clock Management (Channels)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initializes a Generic Clock configuration structure to defaults.
|
||||
*
|
||||
* Initializes a given Generic Clock configuration structure to a set of
|
||||
* known default values. This function should be called on all new
|
||||
* instances of these configuration structures before being modified by the
|
||||
* user application.
|
||||
*
|
||||
* The default configuration is as follows:
|
||||
* \li The clock is sourced from the Generic Clock Generator channel 0
|
||||
* \li The clock configuration will not be write-locked when set
|
||||
*
|
||||
* \param[out] config Configuration structure to initialize to default values
|
||||
*/
|
||||
static inline void system_gclk_chan_get_config_defaults(
|
||||
struct system_gclk_chan_config *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(config);
|
||||
|
||||
/* Default configuration values */
|
||||
config->source_generator = GCLK_GENERATOR_0;
|
||||
}
|
||||
|
||||
void system_gclk_chan_set_config(
|
||||
const uint8_t channel,
|
||||
struct system_gclk_chan_config *const config);
|
||||
|
||||
void system_gclk_chan_enable(
|
||||
const uint8_t channel);
|
||||
|
||||
void system_gclk_chan_disable(
|
||||
const uint8_t channel);
|
||||
|
||||
bool system_gclk_chan_is_enabled(
|
||||
const uint8_t channel);
|
||||
|
||||
void system_gclk_chan_lock(
|
||||
const uint8_t channel);
|
||||
|
||||
bool system_gclk_chan_is_locked(
|
||||
const uint8_t channel);
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* \name Generic Clock Frequency Retrieval
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t system_gclk_gen_get_hz(
|
||||
const uint8_t generator);
|
||||
|
||||
uint32_t system_gclk_chan_get_hz(
|
||||
const uint8_t channel);
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,207 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM System Interrupt Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#include "system_interrupt.h"
|
||||
|
||||
/**
|
||||
* \brief Check if a interrupt line is pending.
|
||||
*
|
||||
* Checks if the requested interrupt vector is pending.
|
||||
*
|
||||
* \param[in] vector Interrupt vector number to check
|
||||
*
|
||||
* \returns A boolean identifying if the requested interrupt vector is pending.
|
||||
*
|
||||
* \retval true Specified interrupt vector is pending
|
||||
* \retval false Specified interrupt vector is not pending
|
||||
*
|
||||
*/
|
||||
bool system_interrupt_is_pending(
|
||||
const enum system_interrupt_vector vector)
|
||||
{
|
||||
bool result;
|
||||
|
||||
if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
|
||||
result = ((NVIC->ISPR[0] & (1 << vector)) != 0);
|
||||
} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
|
||||
result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);
|
||||
} else {
|
||||
Assert(false);
|
||||
result = false;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set a interrupt vector as pending.
|
||||
*
|
||||
* Set the requested interrupt vector as pending (i.e. issues a software
|
||||
* interrupt request for the specified vector). The software handler will be
|
||||
* handled (if enabled) in a priority order based on vector number and
|
||||
* configured priority settings.
|
||||
*
|
||||
* \param[in] vector Interrupt vector number which is set as pending
|
||||
*
|
||||
* \returns Status code identifying if the vector was successfully set as
|
||||
* pending.
|
||||
*
|
||||
* \retval STATUS_OK If no error was detected
|
||||
* \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
|
||||
*/
|
||||
enum status_code system_interrupt_set_pending(
|
||||
const enum system_interrupt_vector vector)
|
||||
{
|
||||
enum status_code status = STATUS_OK;
|
||||
|
||||
if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
|
||||
NVIC->ISPR[0] = (1 << vector);
|
||||
} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
|
||||
/* Note: Because NMI has highest priority it will be executed
|
||||
* immediately after it has been set pending */
|
||||
SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;
|
||||
} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
|
||||
SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
|
||||
} else {
|
||||
/* The user want to set something unsupported as pending */
|
||||
Assert(false);
|
||||
status = STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Clear pending interrupt vector.
|
||||
*
|
||||
* Clear a pending interrupt vector, so the software handler is not executed.
|
||||
*
|
||||
* \param[in] vector Interrupt vector number to clear
|
||||
*
|
||||
* \returns A status code identifying if the interrupt pending state was
|
||||
* successfully cleared.
|
||||
*
|
||||
* \retval STATUS_OK If no error was detected
|
||||
* \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
|
||||
*/
|
||||
enum status_code system_interrupt_clear_pending(
|
||||
const enum system_interrupt_vector vector)
|
||||
{
|
||||
enum status_code status = STATUS_OK;
|
||||
|
||||
if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
|
||||
NVIC->ICPR[0] = (1 << vector);
|
||||
} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
|
||||
/* Note: Clearing of NMI pending interrupts does not make sense and is
|
||||
* not supported by the device, as it has the highest priority and will
|
||||
* always be executed at the moment it is set */
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
|
||||
SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
|
||||
} else {
|
||||
Assert(false);
|
||||
status = STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set interrupt vector priority level.
|
||||
*
|
||||
* Set the priority level of an external interrupt or exception.
|
||||
*
|
||||
* \param[in] vector Interrupt vector to change
|
||||
* \param[in] priority_level New vector priority level to set
|
||||
*
|
||||
* \returns Status code indicating if the priority level of the interrupt was
|
||||
* successfully set.
|
||||
*
|
||||
* \retval STATUS_OK If no error was detected
|
||||
* \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
|
||||
*/
|
||||
enum status_code system_interrupt_set_priority(
|
||||
const enum system_interrupt_vector vector,
|
||||
const enum system_interrupt_priority_level priority_level)
|
||||
{
|
||||
enum status_code status = STATUS_OK;
|
||||
|
||||
if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
|
||||
uint8_t register_num = vector / 4;
|
||||
uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
|
||||
|
||||
NVIC->IP[register_num] =
|
||||
(NVIC->IP[register_num] & ~(_SYSTEM_INTERRUPT_PRIORITY_MASK << priority_pos)) |
|
||||
(priority_level << priority_pos);
|
||||
|
||||
} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
|
||||
SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);
|
||||
} else {
|
||||
Assert(false);
|
||||
status = STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get interrupt vector priority level.
|
||||
*
|
||||
* Retrieves the priority level of the requested external interrupt or exception.
|
||||
*
|
||||
* \param[in] vector Interrupt vector of which the priority level will be read
|
||||
*
|
||||
* \return Currently configured interrupt priority level of the given interrupt
|
||||
* vector.
|
||||
*/
|
||||
enum system_interrupt_priority_level system_interrupt_get_priority(
|
||||
const enum system_interrupt_vector vector)
|
||||
{
|
||||
uint8_t register_num = vector / 4;
|
||||
uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
|
||||
|
||||
enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;
|
||||
|
||||
if (vector >= 0) {
|
||||
priority = (enum system_interrupt_priority_level)
|
||||
((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
|
||||
} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
|
||||
priority = (enum system_interrupt_priority_level)
|
||||
((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
|
||||
}
|
||||
|
||||
return priority;
|
||||
}
|
||||
|
||||
@ -0,0 +1,423 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM System Interrupt Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef SYSTEM_INTERRUPT_H_INCLUDED
|
||||
#define SYSTEM_INTERRUPT_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \defgroup asfdoc_sam0_system_interrupt_group SAM System Interrupt (SYSTEM INTERRUPT) Driver
|
||||
*
|
||||
* This driver for Atmel® | SMART ARM®-based microcontrollers provides
|
||||
* an interface for the configuration and management of internal software and
|
||||
* hardware interrupts/exceptions.
|
||||
*
|
||||
* The following peripheral is used by this module:
|
||||
* - NVIC (Nested Vector Interrupt Controller)
|
||||
*
|
||||
* The following devices can use this module:
|
||||
* - Atmel | SMART SAM D20/D21
|
||||
* - Atmel | SMART SAM R21
|
||||
* - Atmel | SMART SAM D09/D10/D11
|
||||
* - Atmel | SMART SAM L21/L22
|
||||
* - Atmel | SMART SAM DA1
|
||||
* - Atmel | SMART SAM C20/C21
|
||||
* - Atmel | SMART SAM HA1
|
||||
* - Atmel | SMART SAM R30
|
||||
* - Atmel | SMART SAM R34
|
||||
* - Atmel | SMART SAM R35
|
||||
*
|
||||
* The outline of this documentation is as follows:
|
||||
* - \ref asfdoc_sam0_system_interrupt_prerequisites
|
||||
* - \ref asfdoc_sam0_system_interrupt_module_overview
|
||||
* - \ref asfdoc_sam0_system_interrupt_special_considerations
|
||||
* - \ref asfdoc_sam0_system_interrupt_extra_info
|
||||
* - \ref asfdoc_sam0_system_interrupt_examples
|
||||
* - \ref asfdoc_sam0_system_interrupt_api_overview
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_interrupt_prerequisites Prerequisites
|
||||
*
|
||||
* There are no prerequisites for this module.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_interrupt_module_overview Module Overview
|
||||
*
|
||||
* The ARM® Cortex® M0+ core contains an interrupt and exception vector table, which
|
||||
* can be used to configure the device's interrupt handlers; individual
|
||||
* interrupts and exceptions can be enabled and disabled, as well as configured
|
||||
* with a variable priority.
|
||||
*
|
||||
* This driver provides a set of wrappers around the core interrupt functions,
|
||||
* to expose a simple API for the management of global and individual interrupts
|
||||
* within the device.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_interrupt_module_overview_criticalsec Critical Sections
|
||||
* In some applications it is important to ensure that no interrupts may be
|
||||
* executed by the system whilst a critical portion of code is being run; for
|
||||
* example, a buffer may be copied from one context to another - during which
|
||||
* interrupts must be disabled to avoid corruption of the source buffer contents
|
||||
* until the copy has completed. This driver provides a basic API to enter and
|
||||
* exit nested critical sections, so that global interrupts can be kept disabled
|
||||
* for as long as necessary to complete a critical application code section.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_interrupt_module_overview_softints Software Interrupts
|
||||
* For some applications, it may be desirable to raise a module or core
|
||||
* interrupt via software. For this reason, a set of APIs to set an interrupt or
|
||||
* exception as pending are provided to the user application.
|
||||
*
|
||||
* \section asfdoc_sam0_system_interrupt_special_considerations Special Considerations
|
||||
*
|
||||
* Interrupts from peripherals in the SAM devices are on a per-module basis;
|
||||
* an interrupt raised from any source within a module will cause a single,
|
||||
* module-common handler to execute. It is the user application or driver's
|
||||
* responsibility to de-multiplex the module-common interrupt to determine the
|
||||
* exact interrupt cause.
|
||||
*
|
||||
* \section asfdoc_sam0_system_interrupt_extra_info Extra Information
|
||||
*
|
||||
* For extra information, see \ref asfdoc_sam0_system_interrupt_extra. This includes:
|
||||
* - \ref asfdoc_sam0_system_interrupt_extra_acronyms
|
||||
* - \ref asfdoc_sam0_system_interrupt_extra_dependencies
|
||||
* - \ref asfdoc_sam0_system_interrupt_extra_errata
|
||||
* - \ref asfdoc_sam0_system_interrupt_extra_history
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_interrupt_examples Examples
|
||||
*
|
||||
* For a list of examples related to this driver, see
|
||||
* \ref asfdoc_sam0_system_interrupt_exqsg.
|
||||
*
|
||||
* \section asfdoc_sam0_system_interrupt_api_overview API Overview
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <core_cm0plus.h>
|
||||
#include "system_interrupt_features.h"
|
||||
|
||||
/**
|
||||
* \brief Table of possible system interrupt/exception vector priorities.
|
||||
*
|
||||
* Table of all possible interrupt and exception vector priorities within the
|
||||
* device.
|
||||
*/
|
||||
enum system_interrupt_priority_level {
|
||||
/** Priority level 0, the highest possible interrupt priority */
|
||||
SYSTEM_INTERRUPT_PRIORITY_LEVEL_0 = 0,
|
||||
/** Priority level 1 */
|
||||
SYSTEM_INTERRUPT_PRIORITY_LEVEL_1 = 1,
|
||||
/** Priority level 2 */
|
||||
SYSTEM_INTERRUPT_PRIORITY_LEVEL_2 = 2,
|
||||
/** Priority level 3, the lowest possible interrupt priority */
|
||||
SYSTEM_INTERRUPT_PRIORITY_LEVEL_3 = 3,
|
||||
};
|
||||
|
||||
/**
|
||||
* \name Critical Section Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Enters a critical section.
|
||||
*
|
||||
* Disables global interrupts. To support nested critical sections, an internal
|
||||
* count of the critical section nesting will be kept, so that global interrupts
|
||||
* are only re-enabled upon leaving the outermost nested critical section.
|
||||
*
|
||||
*/
|
||||
static inline void system_interrupt_enter_critical_section(void)
|
||||
{
|
||||
cpu_irq_enter_critical();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Leaves a critical section.
|
||||
*
|
||||
* Enables global interrupts. To support nested critical sections, an internal
|
||||
* count of the critical section nesting will be kept, so that global interrupts
|
||||
* are only re-enabled upon leaving the outermost nested critical section.
|
||||
*
|
||||
*/
|
||||
static inline void system_interrupt_leave_critical_section(void)
|
||||
{
|
||||
cpu_irq_leave_critical();
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \name Interrupt Enabling/Disabling
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Check if global interrupts are enabled.
|
||||
*
|
||||
* Checks if global interrupts are currently enabled.
|
||||
*
|
||||
* \returns A boolean that identifies if the global interrupts are enabled or not.
|
||||
*
|
||||
* \retval true Global interrupts are currently enabled
|
||||
* \retval false Global interrupts are currently disabled
|
||||
*
|
||||
*/
|
||||
static inline bool system_interrupt_is_global_enabled(void)
|
||||
{
|
||||
return cpu_irq_is_enabled();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enables global interrupts.
|
||||
*
|
||||
* Enables global interrupts in the device to fire any enabled interrupt handlers.
|
||||
*/
|
||||
static inline void system_interrupt_enable_global(void)
|
||||
{
|
||||
cpu_irq_enable();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disables global interrupts.
|
||||
*
|
||||
* Disabled global interrupts in the device, preventing any enabled interrupt
|
||||
* handlers from executing.
|
||||
*/
|
||||
static inline void system_interrupt_disable_global(void)
|
||||
{
|
||||
cpu_irq_disable();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Checks if an interrupt vector is enabled or not.
|
||||
*
|
||||
* Checks if a specific interrupt vector is currently enabled.
|
||||
*
|
||||
* \param[in] vector Interrupt vector number to check
|
||||
*
|
||||
* \returns A variable identifying if the requested interrupt vector is enabled.
|
||||
*
|
||||
* \retval true Specified interrupt vector is currently enabled
|
||||
* \retval false Specified interrupt vector is currently disabled
|
||||
*
|
||||
*/
|
||||
static inline bool system_interrupt_is_enabled(
|
||||
const enum system_interrupt_vector vector)
|
||||
{
|
||||
return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable interrupt vector.
|
||||
*
|
||||
* Enables execution of the software handler for the requested interrupt vector.
|
||||
*
|
||||
* \param[in] vector Interrupt vector to enable
|
||||
*/
|
||||
static inline void system_interrupt_enable(
|
||||
const enum system_interrupt_vector vector)
|
||||
{
|
||||
NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable interrupt vector.
|
||||
*
|
||||
* Disables execution of the software handler for the requested interrupt vector.
|
||||
*
|
||||
* \param[in] vector Interrupt vector to disable
|
||||
*/
|
||||
static inline void system_interrupt_disable(
|
||||
const enum system_interrupt_vector vector)
|
||||
{
|
||||
NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \name Interrupt State Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Get active interrupt (if any).
|
||||
*
|
||||
* Return the vector number for the current executing software handler, if any.
|
||||
*
|
||||
* \return Interrupt number that is currently executing.
|
||||
*/
|
||||
static inline enum system_interrupt_vector system_interrupt_get_active(void)
|
||||
{
|
||||
uint32_t IPSR = __get_IPSR();
|
||||
/* The IPSR returns the Exception number, which with an offset 16 to IRQ number. */
|
||||
return (enum system_interrupt_vector)((IPSR & _SYSTEM_INTERRUPT_IPSR_MASK) - 16);
|
||||
}
|
||||
|
||||
bool system_interrupt_is_pending(
|
||||
const enum system_interrupt_vector vector);
|
||||
|
||||
enum status_code system_interrupt_set_pending(
|
||||
const enum system_interrupt_vector vector);
|
||||
|
||||
enum status_code system_interrupt_clear_pending(
|
||||
const enum system_interrupt_vector vector);
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \name Interrupt Priority Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
enum status_code system_interrupt_set_priority(
|
||||
const enum system_interrupt_vector vector,
|
||||
const enum system_interrupt_priority_level priority_level);
|
||||
|
||||
enum system_interrupt_priority_level system_interrupt_get_priority(
|
||||
const enum system_interrupt_vector vector);
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver
|
||||
*
|
||||
* \section asfdoc_sam0_system_interrupt_extra_acronyms Acronyms
|
||||
* The table below presents the acronyms used in this module:
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Acronym</th>
|
||||
* <th>Description</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>ISR</td>
|
||||
* <td>Interrupt Service Routine</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>NMI</td>
|
||||
* <td>Non-maskable Interrupt</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>SERCOM</td>
|
||||
* <td>Serial Communication Interface</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_interrupt_extra_dependencies Dependencies
|
||||
* This driver has the following dependencies:
|
||||
*
|
||||
* - None
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_interrupt_extra_errata Errata
|
||||
* There are no errata related to this driver.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_interrupt_extra_history Module History
|
||||
* An overview of the module history is presented in the table below, with
|
||||
* details on the enhancements and fixes made to the module since its first
|
||||
* release. The current version of this corresponds to the newest version in
|
||||
* the table.
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Changelog</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Initial Release</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver
|
||||
*
|
||||
* This is a list of the available Quick Start guides (QSGs) and example
|
||||
* applications for \ref asfdoc_sam0_system_interrupt_group. QSGs are simple examples with
|
||||
* step-by-step instructions to configure and use this driver in a selection of
|
||||
* use cases. Note that a QSG can be compiled as a standalone application or be
|
||||
* added to the user application.
|
||||
*
|
||||
* - \subpage asfdoc_sam0_system_interrupt_critsec_use_case
|
||||
* - \subpage asfdoc_sam0_system_interrupt_enablemodint_use_case
|
||||
*
|
||||
* \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Doc. Rev.</th>
|
||||
* <th>Date</th>
|
||||
* <th>Comments</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42122E</td>
|
||||
* <td>12/2015</td>
|
||||
* <td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42122D</td>
|
||||
* <td>12/2014</td>
|
||||
* <td>Added support for SAM R21 and SAM D10/D11</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42122C</td>
|
||||
* <td>01/2014</td>
|
||||
* <td>Added support for SAM D21</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42122B</td>
|
||||
* <td>06/2013</td>
|
||||
* <td>Corrected documentation typos</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42122A</td>
|
||||
* <td>06/2013</td>
|
||||
* <td>Initial release</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED
|
||||
@ -0,0 +1,185 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM D21 System Interrupt Driver
|
||||
*
|
||||
* Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
|
||||
#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/* Generates a interrupt vector table enum list entry for a given module type
|
||||
and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
|
||||
# define _MODULE_IRQn(n, module) \
|
||||
SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
|
||||
|
||||
/* Generates interrupt vector table enum list entries for all instances of a
|
||||
given module type on the selected device. */
|
||||
# define _SYSTEM_INTERRUPT_MODULES(name) \
|
||||
MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
|
||||
|
||||
# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f
|
||||
# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000003
|
||||
|
||||
# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0
|
||||
|
||||
# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 30
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup asfdoc_sam0_system_interrupt_group
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Table of possible system interrupt/exception vector numbers.
|
||||
*
|
||||
* Table of all possible interrupt and exception vector indexes within the
|
||||
* SAM D21 device. Check peripherals configuration in SAM D21 datasheet for
|
||||
* available vector index for specific device.
|
||||
*
|
||||
*/
|
||||
#if defined(__DOXYGEN__)
|
||||
/** \note The actual enumeration name is "system_interrupt_vector". */
|
||||
enum system_interrupt_vector_samd21 {
|
||||
#else
|
||||
enum system_interrupt_vector {
|
||||
#endif
|
||||
/** Interrupt vector index for a NMI interrupt */
|
||||
SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn,
|
||||
/** Interrupt vector index for a Hard Fault memory access exception */
|
||||
SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn,
|
||||
/** Interrupt vector index for a Supervisor Call exception */
|
||||
SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn,
|
||||
/** Interrupt vector index for a Pending Supervisor interrupt */
|
||||
SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn,
|
||||
/** Interrupt vector index for a System Tick interrupt */
|
||||
SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn,
|
||||
|
||||
/** Interrupt vector index for a Power Manager peripheral interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn,
|
||||
/** Interrupt vector index for a System Control peripheral interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn,
|
||||
/** Interrupt vector index for a Watch Dog peripheral interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn,
|
||||
/** Interrupt vector index for a Real Time Clock peripheral interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn,
|
||||
/** Interrupt vector index for an External Interrupt peripheral interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn,
|
||||
/** Interrupt vector index for a Non Volatile Memory Controller interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn,
|
||||
/** Interrupt vector index for a Direct Memory Access interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn,
|
||||
#if defined(__DOXYGEN__) || defined(ID_USB)
|
||||
/** Interrupt vector index for a Universal Serial Bus interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn,
|
||||
#endif
|
||||
/** Interrupt vector index for an Event System interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn,
|
||||
#if defined(__DOXYGEN__)
|
||||
/** Interrupt vector index for a SERCOM peripheral interrupt.
|
||||
*
|
||||
* Each specific device may contain several SERCOM peripherals; each module
|
||||
* instance will have its own entry in the table, with the instance number
|
||||
* substituted for "n" in the entry name (e.g.
|
||||
* \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
|
||||
*/
|
||||
SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn,
|
||||
|
||||
/** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
|
||||
*
|
||||
* Each specific device may contain several TCC peripherals; each module
|
||||
* instance will have its own entry in the table, with the instance number
|
||||
* substituted for "n" in the entry name (e.g.
|
||||
* \c SYSTEM_INTERRUPT_MODULE_TCC0).
|
||||
*/
|
||||
SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn,
|
||||
|
||||
/** Interrupt vector index for a Timer/Counter peripheral interrupt.
|
||||
*
|
||||
* Each specific device may contain several TC peripherals; each module
|
||||
* instance will have its own entry in the table, with the instance number
|
||||
* substituted for "n" in the entry name (e.g.
|
||||
* \c SYSTEM_INTERRUPT_MODULE_TC3).
|
||||
*/
|
||||
SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn,
|
||||
#else
|
||||
_SYSTEM_INTERRUPT_MODULES(SERCOM)
|
||||
|
||||
_SYSTEM_INTERRUPT_MODULES(TCC)
|
||||
|
||||
SYSTEM_INTERRUPT_MODULE_TC3 = TC3_IRQn,
|
||||
SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn,
|
||||
SYSTEM_INTERRUPT_MODULE_TC5 = TC5_IRQn,
|
||||
# if defined(ID_TC6)
|
||||
SYSTEM_INTERRUPT_MODULE_TC6 = TC6_IRQn,
|
||||
# endif
|
||||
# if defined(ID_TC7)
|
||||
SYSTEM_INTERRUPT_MODULE_TC7 = TC7_IRQn,
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(__DOXYGEN__) || defined(ID_ADC)
|
||||
/** Interrupt vector index for an Analog-to-Digital peripheral interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn,
|
||||
#endif
|
||||
|
||||
#if defined(__DOXYGEN__) || defined(ID_AC)
|
||||
/** Interrupt vector index for an Analog Comparator peripheral interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn,
|
||||
#endif
|
||||
|
||||
#if defined(__DOXYGEN__) || defined(ID_DAC)
|
||||
/** Interrupt vector index for a Digital-to-Analog peripheral interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || defined(ID_PTC)
|
||||
/** Interrupt vector index for a Peripheral Touch Controller peripheral
|
||||
* interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || defined(ID_I2S)
|
||||
/** Interrupt vector index for a Inter-IC Sound Interface peripheral
|
||||
* interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_I2S = I2S_IRQn,
|
||||
#endif
|
||||
#if defined(__DOXYGEN__) || defined(ID_AC1)
|
||||
/** Interrupt vector index for an Analog Comparator 1 peripheral interrupt */
|
||||
SYSTEM_INTERRUPT_MODULE_AC1 = AC1_IRQn,
|
||||
#endif
|
||||
};
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,301 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Pin Multiplexer Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#include <pinmux.h>
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Writes out a given configuration of a Port pin configuration to the
|
||||
* hardware module.
|
||||
*
|
||||
* \note If the pin direction is set as an output, the pull-up/pull-down input
|
||||
* configuration setting is ignored.
|
||||
*
|
||||
* \param[in] port Base of the PORT module to configure
|
||||
* \param[in] pin_mask Mask of the port pin to configure
|
||||
* \param[in] config Configuration settings for the pin
|
||||
*/
|
||||
static void _system_pinmux_config(
|
||||
PortGroup *const port,
|
||||
const uint32_t pin_mask,
|
||||
const struct system_pinmux_config *const config)
|
||||
{
|
||||
Assert(port);
|
||||
Assert(config);
|
||||
|
||||
/* Track the configuration bits into a temporary variable before writing */
|
||||
uint32_t pin_cfg = 0;
|
||||
|
||||
/* Enabled powersave mode, don't create configuration */
|
||||
if (!config->powersave) {
|
||||
/* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
|
||||
* be written later) and store the new MUX mask */
|
||||
if (config->mux_position != SYSTEM_PINMUX_GPIO) {
|
||||
pin_cfg |= PORT_WRCONFIG_PMUXEN;
|
||||
pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
|
||||
}
|
||||
|
||||
/* Check if the user has requested that the input buffer be enabled */
|
||||
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
|
||||
(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
|
||||
/* Enable input buffer flag */
|
||||
pin_cfg |= PORT_WRCONFIG_INEN;
|
||||
|
||||
/* Enable pull-up/pull-down control flag if requested */
|
||||
if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
|
||||
pin_cfg |= PORT_WRCONFIG_PULLEN;
|
||||
}
|
||||
|
||||
/* Clear the port DIR bits to disable the output buffer */
|
||||
port->DIRCLR.reg = pin_mask;
|
||||
}
|
||||
|
||||
/* Check if the user has requested that the output buffer be enabled */
|
||||
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
|
||||
(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
|
||||
/* Cannot use a pull-up if the output driver is enabled,
|
||||
* if requested the input buffer can only sample the current
|
||||
* output state */
|
||||
pin_cfg &= ~PORT_WRCONFIG_PULLEN;
|
||||
}
|
||||
} else {
|
||||
port->DIRCLR.reg = pin_mask;
|
||||
}
|
||||
|
||||
/* The Write Configuration register (WRCONFIG) requires the
|
||||
* pins to to grouped into two 16-bit half-words - split them out here */
|
||||
uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
|
||||
uint32_t upper_pin_mask = (pin_mask >> 16);
|
||||
|
||||
/* Configure the lower 16-bits of the port to the desired configuration,
|
||||
* including the pin peripheral multiplexer just in case it is enabled */
|
||||
port->WRCONFIG.reg
|
||||
= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
|
||||
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
|
||||
|
||||
/* Configure the upper 16-bits of the port to the desired configuration,
|
||||
* including the pin peripheral multiplexer just in case it is enabled */
|
||||
port->WRCONFIG.reg
|
||||
= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
|
||||
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
|
||||
PORT_WRCONFIG_HWSEL;
|
||||
|
||||
if(!config->powersave) {
|
||||
/* Set the pull-up state once the port pins are configured if one was
|
||||
* requested and it does not violate the valid set of port
|
||||
* configurations */
|
||||
if (pin_cfg & PORT_WRCONFIG_PULLEN) {
|
||||
/* Set the OUT register bits to enable the pull-up if requested,
|
||||
* clear to enable pull-down */
|
||||
if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
|
||||
port->OUTSET.reg = pin_mask;
|
||||
} else {
|
||||
port->OUTCLR.reg = pin_mask;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if the user has requested that the output buffer be enabled */
|
||||
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
|
||||
(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
|
||||
/* Set the port DIR bits to enable the output buffer */
|
||||
port->DIRSET.reg = pin_mask;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Writes a Port pin configuration to the hardware module.
|
||||
*
|
||||
* Writes out a given configuration of a Port pin configuration to the hardware
|
||||
* module.
|
||||
*
|
||||
* \note If the pin direction is set as an output, the pull-up/pull-down input
|
||||
* configuration setting is ignored.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to configure
|
||||
* \param[in] config Configuration settings for the pin
|
||||
*/
|
||||
void system_pinmux_pin_set_config(
|
||||
const uint8_t gpio_pin,
|
||||
const struct system_pinmux_config *const config)
|
||||
{
|
||||
PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
|
||||
uint32_t pin_mask = (1UL << (gpio_pin % 32));
|
||||
|
||||
_system_pinmux_config(port, pin_mask, config);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Writes a Port pin group configuration to the hardware module.
|
||||
*
|
||||
* Writes out a given configuration of a Port pin group configuration to the
|
||||
* hardware module.
|
||||
*
|
||||
* \note If the pin direction is set as an output, the pull-up/pull-down input
|
||||
* configuration setting is ignored.
|
||||
*
|
||||
* \param[in] port Base of the PORT module to configure
|
||||
* \param[in] mask Mask of the port pin(s) to configure
|
||||
* \param[in] config Configuration settings for the pin
|
||||
*/
|
||||
void system_pinmux_group_set_config(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const struct system_pinmux_config *const config)
|
||||
{
|
||||
Assert(port);
|
||||
|
||||
for (int i = 0; i < 32; i++) {
|
||||
if (mask & (1UL << i)) {
|
||||
_system_pinmux_config(port, (1UL << i), config);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Configures the input sampling mode for a group of pins.
|
||||
*
|
||||
* Configures the input sampling mode for a group of pins, to
|
||||
* control when the physical I/O pin value is sampled and
|
||||
* stored inside the microcontroller.
|
||||
*
|
||||
* \param[in] port Base of the PORT module to configure
|
||||
* \param[in] mask Mask of the port pin(s) to configure
|
||||
* \param[in] mode New pin sampling mode to configure
|
||||
*/
|
||||
void system_pinmux_group_set_input_sample_mode(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const enum system_pinmux_pin_sample mode)
|
||||
{
|
||||
Assert(port);
|
||||
|
||||
if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
|
||||
port->CTRL.reg |= mask;
|
||||
} else {
|
||||
port->CTRL.reg &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
|
||||
/**
|
||||
* \brief Configures the output slew rate mode for a group of pins.
|
||||
*
|
||||
* Configures the output slew rate mode for a group of pins, to
|
||||
* control the speed at which the physical output pin can react to
|
||||
* logical changes of the I/O pin value.
|
||||
*
|
||||
* \param[in] port Base of the PORT module to configure
|
||||
* \param[in] mask Mask of the port pin(s) to configure
|
||||
* \param[in] mode New pin slew rate mode to configure
|
||||
*/
|
||||
void system_pinmux_group_set_output_slew_rate(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const enum system_pinmux_pin_slew_rate mode)
|
||||
{
|
||||
Assert(port);
|
||||
|
||||
for (int i = 0; i < 32; i++) {
|
||||
if (mask & (1UL << i)) {
|
||||
if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
|
||||
port->PINCFG[i].reg |= PORT_PINCFG_SLEWLIM;
|
||||
} else {
|
||||
port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
|
||||
/**
|
||||
* \brief Configures the output driver strength mode for a group of pins.
|
||||
*
|
||||
* Configures the output drive strength for a group of pins, to
|
||||
* control the amount of current the pad is able to sink/source.
|
||||
*
|
||||
* \param[in] port Base of the PORT module to configure
|
||||
* \param[in] mask Mask of the port pin(s) to configure
|
||||
* \param[in] mode New output driver strength mode to configure
|
||||
*/
|
||||
void system_pinmux_group_set_output_strength(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const enum system_pinmux_pin_strength mode)
|
||||
{
|
||||
Assert(port);
|
||||
|
||||
for (int i = 0; i < 32; i++) {
|
||||
if (mask & (1UL << i)) {
|
||||
if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
|
||||
port->PINCFG[i].reg |= PORT_PINCFG_DRVSTR;
|
||||
} else {
|
||||
port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
|
||||
/**
|
||||
* \brief Configures the output driver mode for a group of pins.
|
||||
*
|
||||
* Configures the output driver mode for a group of pins, to
|
||||
* control the pad behavior.
|
||||
*
|
||||
* \param[in] port Base of the PORT module to configure
|
||||
* \param[in] mask Mask of the port pin(s) to configure
|
||||
* \param[in] mode New pad output driver mode to configure
|
||||
*/
|
||||
void system_pinmux_group_set_output_drive(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const enum system_pinmux_pin_drive mode)
|
||||
{
|
||||
Assert(port);
|
||||
|
||||
for (int i = 0; i < 32; i++) {
|
||||
if (mask & (1UL << i)) {
|
||||
if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
|
||||
port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN;
|
||||
} else {
|
||||
port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@ -0,0 +1,669 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Pin Multiplexer Driver
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef PINMUX_H_INCLUDED
|
||||
#define PINMUX_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \defgroup asfdoc_sam0_system_pinmux_group SAM System Pin Multiplexer (SYSTEM PINMUX) Driver
|
||||
*
|
||||
* This driver for Atmel® | SMART ARM®-based microcontrollers provides
|
||||
* an interface for the configuration and management of the device's physical
|
||||
* I/O Pins, to alter the direction and input/drive characteristics as well as
|
||||
* to configure the pin peripheral multiplexer selection.
|
||||
*
|
||||
* The following peripheral is used by this module:
|
||||
* - PORT (Port I/O Management)
|
||||
*
|
||||
* The following devices can use this module:
|
||||
* - Atmel | SMART SAM D20/D21
|
||||
* - Atmel | SMART SAM R21
|
||||
* - Atmel | SMART SAM D09/D10/D11
|
||||
* - Atmel | SMART SAM L21/L22
|
||||
* - Atmel | SMART SAM DA1
|
||||
* - Atmel | SMART SAM C20/C21
|
||||
* - Atmel | SMART SAM HA1
|
||||
* - Atmel | SMART SAM R30
|
||||
* - Atmel | SMART SAM R34
|
||||
* - Atmel | SMART SAM R35
|
||||
*
|
||||
* The outline of this documentation is as follows:
|
||||
* - \ref asfdoc_sam0_system_pinmux_prerequisites
|
||||
* - \ref asfdoc_sam0_system_pinmux_module_overview
|
||||
* - \ref asfdoc_sam0_system_pinmux_special_considerations
|
||||
* - \ref asfdoc_sam0_system_pinmux_extra_info
|
||||
* - \ref asfdoc_sam0_system_pinmux_examples
|
||||
* - \ref asfdoc_sam0_system_pinmux_api_overview
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_prerequisites Prerequisites
|
||||
*
|
||||
* There are no prerequisites for this module.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_module_overview Module Overview
|
||||
*
|
||||
* The SAM devices contain a number of General Purpose I/O pins, used to
|
||||
* interface the user application logic and internal hardware peripherals to
|
||||
* an external system. The Pin Multiplexer (PINMUX) driver provides a method
|
||||
* of configuring the individual pin peripheral multiplexers to select
|
||||
* alternate pin functions.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_features Driver Feature Macro Definition
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Driver Feature Macro</th>
|
||||
* <th>Supported devices</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH</td>
|
||||
* <td>SAM L21, SAM C20/C21, SAM R34/R35</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
* \note The specific features are only available in the driver when the
|
||||
* selected device supports those features.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins
|
||||
* SAM devices use two naming conventions for the I/O pins in the device; one
|
||||
* physical and one logical. Each physical pin on a device package is assigned
|
||||
* both a physical port and pin identifier (e.g. "PORTA.0") as well as a
|
||||
* monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
|
||||
* former is used to map physical pins to their physical internal device module
|
||||
* counterparts, for simplicity the design of this driver uses the logical GPIO
|
||||
* numbers instead.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_peripheral_muxing Peripheral Multiplexing
|
||||
* SAM devices contain a peripheral MUX, which is individually controllable
|
||||
* for each I/O pin of the device. The peripheral MUX allows you to select the
|
||||
* function of a physical package pin - whether it will be controlled as a user
|
||||
* controllable GPIO pin, or whether it will be connected internally to one of
|
||||
* several peripheral modules (such as an I<SUP>2</SUP>C module). When a pin is
|
||||
* configured in GPIO mode, other peripherals connected to the same pin will be
|
||||
* disabled.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_pad_characteristics Special Pad Characteristics
|
||||
* There are several special modes that can be selected on one or more I/O pins
|
||||
* of the device, which alter the input and output characteristics of the pad.
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_system_pinmux_drive_strength Drive Strength
|
||||
* The Drive Strength configures the strength of the output driver on the
|
||||
* pad. Normally, there is a fixed current limit that each I/O pin can safely
|
||||
* drive, however some I/O pads offer a higher drive mode which increases this
|
||||
* limit for that I/O pin at the expense of an increased power consumption.
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_system_pinmux_slew_rate Slew Rate
|
||||
* The Slew Rate configures the slew rate of the output driver, limiting the
|
||||
* rate at which the pad output voltage can change with time.
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_system_pinmux_input_sample_mode Input Sample Mode
|
||||
* The Input Sample Mode configures the input sampler buffer of the pad. By
|
||||
* default, the input buffer is only sampled "on-demand", i.e. when the user
|
||||
* application attempts to read from the input buffer. This mode is the most
|
||||
* power efficient, but increases the latency of the input sample by two clock
|
||||
* cycles of the port clock. To reduce latency, the input sampler can instead
|
||||
* be configured to always sample the input buffer on each port clock cycle, at
|
||||
* the expense of an increased power consumption.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_module_overview_physical Physical Connection
|
||||
*
|
||||
* \ref asfdoc_sam0_system_pinmux_intconnections "The diagram below" shows
|
||||
* how this module is interconnected within the device:
|
||||
*
|
||||
* \anchor asfdoc_sam0_system_pinmux_intconnections
|
||||
* \dot
|
||||
* digraph overview {
|
||||
* node [label="Port Pad" shape=square] pad;
|
||||
*
|
||||
* subgraph driver {
|
||||
* node [label="Peripheral MUX" shape=trapezium] pinmux;
|
||||
* node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio;
|
||||
* node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
|
||||
* }
|
||||
*
|
||||
* pinmux -> gpio;
|
||||
* pad -> pinmux;
|
||||
* pinmux -> peripherals;
|
||||
* }
|
||||
* \enddot
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_special_considerations Special Considerations
|
||||
*
|
||||
* The SAM port pin input sampling mode is set in groups of four physical
|
||||
* pins; setting the sampling mode of any pin in a sub-group of eight I/O pins
|
||||
* will configure the sampling mode of the entire sub-group.
|
||||
*
|
||||
* High Drive Strength output driver mode is not available on all device pins -
|
||||
* refer to your device specific datasheet.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_extra_info Extra Information
|
||||
*
|
||||
* For extra information, see \ref asfdoc_sam0_system_pinmux_extra. This includes:
|
||||
* - \ref asfdoc_sam0_system_pinmux_extra_acronyms
|
||||
* - \ref asfdoc_sam0_system_pinmux_extra_dependencies
|
||||
* - \ref asfdoc_sam0_system_pinmux_extra_errata
|
||||
* - \ref asfdoc_sam0_system_pinmux_extra_history
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_examples Examples
|
||||
*
|
||||
* For a list of examples related to this driver, see
|
||||
* \ref asfdoc_sam0_system_pinmux_exqsg.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_api_overview API Overview
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*@{*/
|
||||
#if (SAML21) || (SAMC20) || (SAMC21) || (SAMD21) || (SAMD10) || (SAMD11) || (SAMR30) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
|
||||
/** Output Driver Strength Selection feature support */
|
||||
# define FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
|
||||
#endif
|
||||
/*@}*/
|
||||
|
||||
/** Peripheral multiplexer index to select GPIO mode for a pin */
|
||||
#define SYSTEM_PINMUX_GPIO (1 << 7)
|
||||
|
||||
/**
|
||||
* \brief Port pin direction configuration enum.
|
||||
*
|
||||
* Enum for the possible pin direction settings of the port pin configuration
|
||||
* structure, to indicate the direction the pin should use.
|
||||
*/
|
||||
enum system_pinmux_pin_dir {
|
||||
/** The pin's input buffer should be enabled, so that the pin state can
|
||||
* be read */
|
||||
SYSTEM_PINMUX_PIN_DIR_INPUT,
|
||||
/** The pin's output buffer should be enabled, so that the pin state can
|
||||
* be set (but not read back) */
|
||||
SYSTEM_PINMUX_PIN_DIR_OUTPUT,
|
||||
/** The pin's output and input buffers should both be enabled, so that the
|
||||
* pin state can be set and read back */
|
||||
SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Port pin input pull configuration enum.
|
||||
*
|
||||
* Enum for the possible pin pull settings of the port pin configuration
|
||||
* structure, to indicate the type of logic level pull the pin should use.
|
||||
*/
|
||||
enum system_pinmux_pin_pull {
|
||||
/** No logical pull should be applied to the pin */
|
||||
SYSTEM_PINMUX_PIN_PULL_NONE,
|
||||
/** Pin should be pulled up when idle */
|
||||
SYSTEM_PINMUX_PIN_PULL_UP,
|
||||
/** Pin should be pulled down when idle */
|
||||
SYSTEM_PINMUX_PIN_PULL_DOWN,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Port pin digital input sampling mode enum.
|
||||
*
|
||||
* Enum for the possible input sampling modes for the port pin configuration
|
||||
* structure, to indicate the type of sampling a port pin should use.
|
||||
*/
|
||||
enum system_pinmux_pin_sample {
|
||||
/** Pin input buffer should continuously sample the pin state */
|
||||
SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,
|
||||
/** Pin input buffer should be enabled when the IN register is read */
|
||||
SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Port pin configuration structure.
|
||||
*
|
||||
* Configuration structure for a port pin instance. This structure should
|
||||
* be initialized by the \ref system_pinmux_get_config_defaults() function
|
||||
* before being modified by the user application.
|
||||
*/
|
||||
struct system_pinmux_config {
|
||||
/** MUX index of the peripheral that should control the pin, if peripheral
|
||||
* control is desired. For GPIO use, this should be set to
|
||||
* \ref SYSTEM_PINMUX_GPIO. */
|
||||
uint8_t mux_position;
|
||||
|
||||
/** Port buffer input/output direction */
|
||||
enum system_pinmux_pin_dir direction;
|
||||
|
||||
/** Logic level pull of the input buffer */
|
||||
enum system_pinmux_pin_pull input_pull;
|
||||
|
||||
/** Enable lowest possible powerstate on the pin
|
||||
*
|
||||
* \note All other configurations will be ignored, the pin will be disabled.
|
||||
*/
|
||||
bool powersave;
|
||||
};
|
||||
|
||||
/** \name Configuration and Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initializes a Port pin configuration structure to defaults.
|
||||
*
|
||||
* Initializes a given Port pin configuration structure to a set of
|
||||
* known default values. This function should be called on all new
|
||||
* instances of these configuration structures before being modified by the
|
||||
* user application.
|
||||
*
|
||||
* The default configuration is as follows:
|
||||
* \li Non peripheral (i.e. GPIO) controlled
|
||||
* \li Input mode with internal pull-up enabled
|
||||
*
|
||||
* \param[out] config Configuration structure to initialize to default values
|
||||
*/
|
||||
static inline void system_pinmux_get_config_defaults(
|
||||
struct system_pinmux_config *const config)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(config);
|
||||
|
||||
/* Default configuration values */
|
||||
config->mux_position = SYSTEM_PINMUX_GPIO;
|
||||
config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
|
||||
config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
|
||||
config->powersave = false;
|
||||
}
|
||||
|
||||
void system_pinmux_pin_set_config(
|
||||
const uint8_t gpio_pin,
|
||||
const struct system_pinmux_config *const config);
|
||||
|
||||
void system_pinmux_group_set_config(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const struct system_pinmux_config *const config);
|
||||
|
||||
/** @} */
|
||||
|
||||
/** \name Special Mode Configuration (Physical Group Orientated)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Retrieves the PORT module group instance from a given GPIO pin number.
|
||||
*
|
||||
* Retrieves the PORT module group instance associated with a given logical
|
||||
* GPIO pin number.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to convert
|
||||
*
|
||||
* \return Base address of the associated PORT module.
|
||||
*/
|
||||
static inline PortGroup* system_pinmux_get_group_from_gpio_pin(
|
||||
const uint8_t gpio_pin)
|
||||
{
|
||||
uint8_t port_index = (gpio_pin / 128);
|
||||
uint8_t group_index = (gpio_pin / 32);
|
||||
|
||||
/* Array of available ports */
|
||||
Port *const ports[PORT_INST_NUM] = PORT_INSTS;
|
||||
|
||||
if (port_index < PORT_INST_NUM) {
|
||||
return &(ports[port_index]->Group[group_index]);
|
||||
} else {
|
||||
Assert(false);
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
void system_pinmux_group_set_input_sample_mode(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const enum system_pinmux_pin_sample mode);
|
||||
|
||||
/** @} */
|
||||
|
||||
/** \name Special Mode Configuration (Logical Pin Orientated)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Retrieves the currently selected MUX position of a logical pin.
|
||||
*
|
||||
* Retrieves the selected MUX peripheral on a given logical GPIO pin.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to configure
|
||||
*
|
||||
* \return Currently selected peripheral index on the specified pin.
|
||||
*/
|
||||
static inline uint8_t system_pinmux_pin_get_mux_position(
|
||||
const uint8_t gpio_pin)
|
||||
{
|
||||
PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
|
||||
uint32_t pin_index = (gpio_pin % 32);
|
||||
|
||||
if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) {
|
||||
return SYSTEM_PINMUX_GPIO;
|
||||
}
|
||||
|
||||
uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;
|
||||
|
||||
if (pin_index & 1) {
|
||||
return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
|
||||
}
|
||||
else {
|
||||
return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Configures the input sampling mode for a GPIO pin.
|
||||
*
|
||||
* Configures the input sampling mode for a GPIO input, to
|
||||
* control when the physical I/O pin value is sampled and
|
||||
* stored inside the microcontroller.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to configure
|
||||
* \param[in] mode New pin sampling mode to configure
|
||||
*/
|
||||
static inline void system_pinmux_pin_set_input_sample_mode(
|
||||
const uint8_t gpio_pin,
|
||||
const enum system_pinmux_pin_sample mode)
|
||||
{
|
||||
PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
|
||||
uint32_t pin_index = (gpio_pin % 32);
|
||||
|
||||
if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
|
||||
port->CTRL.reg |= (1 << pin_index);
|
||||
} else {
|
||||
port->CTRL.reg &= ~(1 << pin_index);
|
||||
}
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
|
||||
/**
|
||||
* \brief Port pin drive output strength enum.
|
||||
*
|
||||
* Enum for the possible output drive strengths for the port pin
|
||||
* configuration structure, to indicate the driver strength the pin should
|
||||
* use.
|
||||
*/
|
||||
enum system_pinmux_pin_strength {
|
||||
/** Normal output driver strength */
|
||||
SYSTEM_PINMUX_PIN_STRENGTH_NORMAL,
|
||||
/** High current output driver strength */
|
||||
SYSTEM_PINMUX_PIN_STRENGTH_HIGH,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Configures the output driver strength mode for a GPIO pin.
|
||||
*
|
||||
* Configures the output drive strength for a GPIO output, to
|
||||
* control the amount of current the pad is able to sink/source.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to configure
|
||||
* \param[in] mode New output driver strength mode to configure
|
||||
*/
|
||||
static inline void system_pinmux_pin_set_output_strength(
|
||||
const uint8_t gpio_pin,
|
||||
const enum system_pinmux_pin_strength mode)
|
||||
{
|
||||
PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
|
||||
uint32_t pin_index = (gpio_pin % 32);
|
||||
|
||||
if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
|
||||
port->PINCFG[pin_index].reg |= PORT_PINCFG_DRVSTR;
|
||||
}
|
||||
else {
|
||||
port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR;
|
||||
}
|
||||
}
|
||||
|
||||
void system_pinmux_group_set_output_strength(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const enum system_pinmux_pin_strength mode);
|
||||
#endif
|
||||
|
||||
#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
|
||||
/**
|
||||
* \brief Port pin output slew rate enum.
|
||||
*
|
||||
* Enum for the possible output drive slew rates for the port pin
|
||||
* configuration structure, to indicate the driver slew rate the pin should
|
||||
* use.
|
||||
*/
|
||||
enum system_pinmux_pin_slew_rate {
|
||||
/** Normal pin output slew rate */
|
||||
SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL,
|
||||
/** Enable slew rate limiter on the pin */
|
||||
SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Configures the output slew rate mode for a GPIO pin.
|
||||
*
|
||||
* Configures the output slew rate mode for a GPIO output, to
|
||||
* control the speed at which the physical output pin can react to
|
||||
* logical changes of the I/O pin value.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to configure
|
||||
* \param[in] mode New pin slew rate mode to configure
|
||||
*/
|
||||
static inline void system_pinmux_pin_set_output_slew_rate(
|
||||
const uint8_t gpio_pin,
|
||||
const enum system_pinmux_pin_slew_rate mode)
|
||||
{
|
||||
PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
|
||||
uint32_t pin_index = (gpio_pin % 32);
|
||||
|
||||
if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
|
||||
port->PINCFG[pin_index].reg |= PORT_PINCFG_SLEWLIM;
|
||||
}
|
||||
else {
|
||||
port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM;
|
||||
}
|
||||
}
|
||||
|
||||
void system_pinmux_group_set_output_slew_rate(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const enum system_pinmux_pin_slew_rate mode);
|
||||
#endif
|
||||
|
||||
#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
|
||||
/**
|
||||
* \brief Port pin output drive mode enum.
|
||||
*
|
||||
* Enum for the possible output drive modes for the port pin configuration
|
||||
* structure, to indicate the output mode the pin should use.
|
||||
*/
|
||||
enum system_pinmux_pin_drive {
|
||||
/** Use totem pole output drive mode */
|
||||
SYSTEM_PINMUX_PIN_DRIVE_TOTEM,
|
||||
/** Use open drain output drive mode */
|
||||
SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Configures the output driver mode for a GPIO pin.
|
||||
*
|
||||
* Configures the output driver mode for a GPIO output, to
|
||||
* control the pad behavior.
|
||||
*
|
||||
* \param[in] gpio_pin Index of the GPIO pin to configure
|
||||
* \param[in] mode New pad output driver mode to configure
|
||||
*/
|
||||
static inline void system_pinmux_pin_set_output_drive(
|
||||
const uint8_t gpio_pin,
|
||||
const enum system_pinmux_pin_drive mode)
|
||||
{
|
||||
PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
|
||||
uint32_t pin_index = (gpio_pin % 32);
|
||||
|
||||
if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
|
||||
port->PINCFG[pin_index].reg |= PORT_PINCFG_ODRAIN;
|
||||
}
|
||||
else {
|
||||
port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN;
|
||||
}
|
||||
}
|
||||
|
||||
void system_pinmux_group_set_output_drive(
|
||||
PortGroup *const port,
|
||||
const uint32_t mask,
|
||||
const enum system_pinmux_pin_drive mode);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_extra_acronyms Acronyms
|
||||
* The table below presents the acronyms used in this module:
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Acronym</th>
|
||||
* <th>Description</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>GPIO</td>
|
||||
* <td>General Purpose Input/Output</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>MUX</td>
|
||||
* <td>Multiplexer</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_extra_dependencies Dependencies
|
||||
* This driver has the following dependencies:
|
||||
*
|
||||
* - None
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_extra_errata Errata
|
||||
* There are no errata related to this driver.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_extra_history Module History
|
||||
* An overview of the module history is presented in the table below, with
|
||||
* details on the enhancements and fixes made to the module since its first
|
||||
* release. The current version of this corresponds to the newest version in
|
||||
* the table.
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Changelog</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Removed code of open drain, slew limit and drive strength
|
||||
* features</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Fixed broken sampling mode function implementations, which wrote
|
||||
* corrupt configuration values to the device registers</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Added missing NULL pointer asserts to the PORT driver functions</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Initial Release</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver
|
||||
*
|
||||
* This is a list of the available Quick Start guides (QSGs) and example
|
||||
* applications for \ref asfdoc_sam0_system_pinmux_group. QSGs are simple
|
||||
* examples with step-by-step instructions to configure and use this driver in a
|
||||
* selection of use cases. Note that a QSG can be compiled as a standalone
|
||||
* application or be added to the user application.
|
||||
*
|
||||
* - \subpage asfdoc_sam0_system_pinmux_basic_use_case
|
||||
*
|
||||
* \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Doc. Rev.</td>
|
||||
* <th>Date</td>
|
||||
* <th>Comments</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42121F</td>
|
||||
* <td>12/2015</td>
|
||||
* <td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42121E</td>
|
||||
* <td>12/2014</td>
|
||||
* <td>Added support for SAM R21 and SAM D10/D11</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42121D</td>
|
||||
* <td>01/2014</td>
|
||||
* <td>Added support for SAM D21</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42121C</td>
|
||||
* <td>09/2013</td>
|
||||
* <td>Fixed incorrect documentation for the device pin sampling mode</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42121B</td>
|
||||
* <td>06/2013</td>
|
||||
* <td>Corrected documentation typos</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42121A</td>
|
||||
* <td>06/2013</td>
|
||||
* <td>Initial release</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*/
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,86 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM PINMUX Driver Quick Start
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_system_pinmux_basic_use_case Quick Start Guide for SYSTEM PINMUX - Basic
|
||||
*
|
||||
* In this use case, the PINMUX module is configured for:
|
||||
* \li One pin in input mode, with pull-up enabled, connected to the GPIO
|
||||
* module
|
||||
* \li Sampling mode of the pin changed to sample on demand
|
||||
*
|
||||
* This use case sets up the PINMUX to configure a physical I/O pin set as
|
||||
* an input with pull-up and changes the sampling mode of the pin to reduce
|
||||
* power by only sampling the physical pin state when the user application
|
||||
* attempts to read it.
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_basic_use_case_setup Setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_prereq Prerequisites
|
||||
* There are no special setup requirements for this use-case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_code Code
|
||||
* Copy-paste the following setup code to your application:
|
||||
* \snippet qs_pinmux_basic.c setup
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_flow Workflow
|
||||
* -# Create a PINMUX module pin configuration struct, which can be filled out
|
||||
* to adjust the configuration of a single port pin.
|
||||
* \snippet qs_pinmux_basic.c pinmux_config
|
||||
* -# Initialize the pin configuration struct with the module's default values.
|
||||
* \snippet qs_pinmux_basic.c pinmux_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Adjust the configuration struct to request an input pin with pull-up
|
||||
* connected to the GPIO peripheral.
|
||||
* \snippet qs_pinmux_basic.c pinmux_update_config_values
|
||||
* -# Configure GPIO10 with the initialized pin configuration struct, to enable
|
||||
* the input sampler on the pin.
|
||||
* \snippet qs_pinmux_basic.c pinmux_set_config
|
||||
*
|
||||
* \section asfdoc_sam0_system_pinmux_basic_use_case_use_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_pinmux_basic.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_flow Workflow
|
||||
|
||||
* -# Adjust the configuration of the pin to enable on-demand sampling mode.
|
||||
* \snippet qs_pinmux_basic.c pinmux_change_input_sampling
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
@ -0,0 +1,239 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Power related functionality
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef POWER_H_INCLUDED
|
||||
#define POWER_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* MCU revision number */
|
||||
#define _SYSTEM_MCU_REVISION_D 3
|
||||
#define _SYSTEM_MCU_REVISION_E 4
|
||||
|
||||
/**
|
||||
* \addtogroup asfdoc_sam0_system_group
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Voltage references within the device.
|
||||
*
|
||||
* List of available voltage references (VREF) that may be used within the
|
||||
* device.
|
||||
*/
|
||||
enum system_voltage_reference {
|
||||
/** Temperature sensor voltage reference */
|
||||
SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
|
||||
/** Bandgap voltage reference */
|
||||
SYSTEM_VOLTAGE_REFERENCE_BANDGAP,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Device sleep modes.
|
||||
*
|
||||
* List of available sleep modes in the device. A table of clocks available in
|
||||
* different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
|
||||
*/
|
||||
enum system_sleepmode {
|
||||
/** IDLE 0 sleep mode */
|
||||
SYSTEM_SLEEPMODE_IDLE_0,
|
||||
/** IDLE 1 sleep mode */
|
||||
SYSTEM_SLEEPMODE_IDLE_1,
|
||||
/** IDLE 2 sleep mode */
|
||||
SYSTEM_SLEEPMODE_IDLE_2,
|
||||
/** Standby sleep mode */
|
||||
SYSTEM_SLEEPMODE_STANDBY,
|
||||
};
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \name Voltage References
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Enable the selected voltage reference
|
||||
*
|
||||
* Enables the selected voltage reference source, making the voltage reference
|
||||
* available on a pin as well as an input source to the analog peripherals.
|
||||
*
|
||||
* \param[in] vref Voltage reference to enable
|
||||
*/
|
||||
static inline void system_voltage_reference_enable(
|
||||
const enum system_voltage_reference vref)
|
||||
{
|
||||
switch (vref) {
|
||||
case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
|
||||
SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
|
||||
break;
|
||||
|
||||
case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
|
||||
SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
|
||||
break;
|
||||
|
||||
default:
|
||||
Assert(false);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable the selected voltage reference
|
||||
*
|
||||
* Disables the selected voltage reference source.
|
||||
*
|
||||
* \param[in] vref Voltage reference to disable
|
||||
*/
|
||||
static inline void system_voltage_reference_disable(
|
||||
const enum system_voltage_reference vref)
|
||||
{
|
||||
switch (vref) {
|
||||
case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
|
||||
SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN;
|
||||
break;
|
||||
|
||||
case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
|
||||
SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
|
||||
break;
|
||||
|
||||
default:
|
||||
Assert(false);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* \name Device Sleep Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Set the sleep mode of the device
|
||||
*
|
||||
* Sets the sleep mode of the device; the configured sleep mode will be entered
|
||||
* upon the next call of the \ref system_sleep() function.
|
||||
*
|
||||
* For an overview of which systems are disabled in sleep for the different
|
||||
* sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode.
|
||||
*
|
||||
* \param[in] sleep_mode Sleep mode to configure for the next sleep operation
|
||||
*
|
||||
* \retval STATUS_OK Operation completed successfully
|
||||
* \retval STATUS_ERR_INVALID_ARG The requested sleep mode was invalid or not
|
||||
* available
|
||||
*/
|
||||
static inline enum status_code system_set_sleepmode(
|
||||
const enum system_sleepmode sleep_mode)
|
||||
{
|
||||
|
||||
#if (SAMD20 || SAMD21 || SAMR21)
|
||||
|
||||
/* Get MCU revision */
|
||||
uint32_t rev = DSU->DID.reg;
|
||||
|
||||
rev &= DSU_DID_REVISION_Msk;
|
||||
rev = rev >> DSU_DID_REVISION_Pos;
|
||||
|
||||
#if (SAMD20)
|
||||
if (rev < _SYSTEM_MCU_REVISION_E) {
|
||||
/* Errata 13140: Make sure that the Flash does not power all the way down
|
||||
* when in sleep mode. */
|
||||
NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (SAMD21 || SAMR21)
|
||||
if (rev < _SYSTEM_MCU_REVISION_D) {
|
||||
/* Errata 13140: Make sure that the Flash does not power all the way down
|
||||
* when in sleep mode. */
|
||||
NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
switch (sleep_mode) {
|
||||
case SYSTEM_SLEEPMODE_IDLE_0:
|
||||
case SYSTEM_SLEEPMODE_IDLE_1:
|
||||
case SYSTEM_SLEEPMODE_IDLE_2:
|
||||
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
|
||||
PM->SLEEP.reg = sleep_mode;
|
||||
break;
|
||||
|
||||
case SYSTEM_SLEEPMODE_STANDBY:
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
break;
|
||||
|
||||
default:
|
||||
return STATUS_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Put the system to sleep waiting for interrupt
|
||||
*
|
||||
* Executes a device DSB (Data Synchronization Barrier) instruction to ensure
|
||||
* all ongoing memory accesses have completed, then a WFI (Wait For Interrupt)
|
||||
* instruction to place the device into the sleep mode specified by
|
||||
* \ref system_set_sleepmode until woken by an interrupt.
|
||||
*/
|
||||
static inline void system_sleep(void)
|
||||
{
|
||||
__DSB();
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* POWER_H_INCLUDED */
|
||||
@ -0,0 +1,109 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM Reset related functionality
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef RESET_H_INCLUDED
|
||||
#define RESET_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup asfdoc_sam0_system_group
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Reset causes of the system.
|
||||
*
|
||||
* List of possible reset causes of the system.
|
||||
*/
|
||||
enum system_reset_cause {
|
||||
/** The system was last reset by a software reset */
|
||||
SYSTEM_RESET_CAUSE_SOFTWARE = PM_RCAUSE_SYST,
|
||||
/** The system was last reset by the watchdog timer */
|
||||
SYSTEM_RESET_CAUSE_WDT = PM_RCAUSE_WDT,
|
||||
/** The system was last reset because the external reset line was pulled low */
|
||||
SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT,
|
||||
/** The system was last reset by the BOD33 */
|
||||
SYSTEM_RESET_CAUSE_BOD33 = PM_RCAUSE_BOD33,
|
||||
/** The system was last reset by the BOD12 */
|
||||
SYSTEM_RESET_CAUSE_BOD12 = PM_RCAUSE_BOD12,
|
||||
/** The system was last reset by the POR (Power on reset) */
|
||||
SYSTEM_RESET_CAUSE_POR = PM_RCAUSE_POR,
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* \name Reset Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Reset the MCU.
|
||||
*
|
||||
* Resets the MCU and all associated peripherals and registers, except RTC, all 32KHz sources,
|
||||
* WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set).
|
||||
*
|
||||
*/
|
||||
static inline void system_reset(void)
|
||||
{
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Return the reset cause.
|
||||
*
|
||||
* Retrieves the cause of the last system reset.
|
||||
*
|
||||
* \return An enum value indicating the cause of the last system reset.
|
||||
*/
|
||||
static inline enum system_reset_cause system_get_reset_cause(void)
|
||||
{
|
||||
return (enum system_reset_cause)PM->RCAUSE.reg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* RESET_H_INCLUDED */
|
||||
@ -0,0 +1,101 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM System related functionality
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#include <system.h>
|
||||
|
||||
/**
|
||||
* \internal
|
||||
* Dummy initialization function, used as a weak alias target for the various
|
||||
* init functions called by \ref system_init().
|
||||
*/
|
||||
void _system_dummy_init(void);
|
||||
void _system_dummy_init(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
# if defined(__GNUC__)
|
||||
void system_clock_init(void) WEAK __attribute__((alias("_system_dummy_init")));
|
||||
void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init")));
|
||||
void _system_events_init(void) WEAK __attribute__((alias("_system_dummy_init")));
|
||||
void _system_extint_init(void) WEAK __attribute__((alias("_system_dummy_init")));
|
||||
void _system_divas_init(void) WEAK __attribute__((alias("_system_dummy_init")));
|
||||
# elif defined(__ICCARM__)
|
||||
void system_clock_init(void);
|
||||
void system_board_init(void);
|
||||
void _system_events_init(void);
|
||||
void _system_extint_init(void);
|
||||
void _system_divas_init(void);
|
||||
# pragma weak system_clock_init=_system_dummy_init
|
||||
# pragma weak system_board_init=_system_dummy_init
|
||||
# pragma weak _system_events_init=_system_dummy_init
|
||||
# pragma weak _system_extint_init=_system_dummy_init
|
||||
# pragma weak _system_divas_init=_system_dummy_init
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Initialize system
|
||||
*
|
||||
* This function will call the various initialization functions within the
|
||||
* system namespace. If a given optional system module is not available, the
|
||||
* associated call will effectively be a NOP (No Operation).
|
||||
*
|
||||
* Currently the following initialization functions are supported:
|
||||
* - System clock initialization (via the SYSTEM CLOCK sub-module)
|
||||
* - Board hardware initialization (via the Board module)
|
||||
* - Event system driver initialization (via the EVSYS module)
|
||||
* - External Interrupt driver initialization (via the EXTINT module)
|
||||
*/
|
||||
void system_init(void)
|
||||
{
|
||||
/* Configure GCLK and clock sources according to conf_clocks.h */
|
||||
system_clock_init();
|
||||
|
||||
/* Initialize board hardware */
|
||||
system_board_init();
|
||||
|
||||
/* Initialize EVSYS hardware */
|
||||
_system_events_init();
|
||||
|
||||
/* Initialize External hardware */
|
||||
_system_extint_init();
|
||||
|
||||
/* Initialize DIVAS hardware */
|
||||
_system_divas_init();
|
||||
}
|
||||
|
||||
@ -0,0 +1,721 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM System related functionality
|
||||
*
|
||||
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
#ifndef SYSTEM_H_INCLUDED
|
||||
#define SYSTEM_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
#include <clock.h>
|
||||
#include <gclk.h>
|
||||
#include <pinmux.h>
|
||||
#include <power.h>
|
||||
#include <reset.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \defgroup asfdoc_sam0_system_group SAM System (SYSTEM) Driver
|
||||
*
|
||||
* This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration
|
||||
* and management of the device's system relation functionality, necessary for
|
||||
* the basic device operation. This is not limited to a single peripheral, but
|
||||
* extends across multiple hardware peripherals.
|
||||
*
|
||||
* The following peripherals are used by this module:
|
||||
* \if DEVICE_SAML21_SYSTEM_SUPPORT
|
||||
* - PM (Power Manager)
|
||||
* - RSTC (Reset Controller)
|
||||
* - SUPC (Supply Controller)
|
||||
* \endif
|
||||
* \if DEVICE_SAMC21_SYSTEM_SUPPORT
|
||||
* - PM (Power Manager)
|
||||
* - RSTC (Reset Controller)
|
||||
* - SUPC (Supply Controller)
|
||||
* \endif
|
||||
* \if DEVICE_SAMD21_SYSTEM_SUPPORT
|
||||
* - SYSCTRL (System Control)
|
||||
* - PM (Power Manager)
|
||||
* \endif
|
||||
*
|
||||
* The following devices can use this module:
|
||||
* \if DEVICE_SAML21_SYSTEM_SUPPORT
|
||||
* - Atmel | SMART SAM L21
|
||||
* - Atmel | SMART SAM R30
|
||||
* - Atmel | SMART SAM R34
|
||||
* - Atmel | SMART SAM R35
|
||||
* \endif
|
||||
* \if DEVICE_SAMC21_SYSTEM_SUPPORT
|
||||
* - Atmel | SMART SAM C20/C21
|
||||
* \endif
|
||||
* \if DEVICE_SAMD21_SYSTEM_SUPPORT
|
||||
* - Atmel | SMART SAM D20/D21
|
||||
* - Atmel | SMART SAM R21
|
||||
* - Atmel | SMART SAM D09/D10/D11
|
||||
* - Atmel | SMART SAM DA1
|
||||
* \endif
|
||||
*
|
||||
* The outline of this documentation is as follows:
|
||||
* - \ref asfdoc_sam0_system_prerequisites
|
||||
* - \ref asfdoc_sam0_system_module_overview
|
||||
* - \ref asfdoc_sam0_system_special_considerations
|
||||
* - \ref asfdoc_sam0_system_extra_info
|
||||
* - \ref asfdoc_sam0_system_examples
|
||||
* - \ref asfdoc_sam0_system_api_overview
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_prerequisites Prerequisites
|
||||
*
|
||||
* There are no prerequisites for this module.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_module_overview Module Overview
|
||||
*
|
||||
* The System driver provides a collection of interfaces between the user
|
||||
* application logic, and the core device functionality (such as clocks, reset
|
||||
* cause determination, etc.) that is required for all applications. It contains
|
||||
* a number of sub-modules that control one specific aspect of the device:
|
||||
*
|
||||
* - System Core (this module)
|
||||
* - \ref asfdoc_sam0_system_clock_group "System Clock Control" (sub-module)
|
||||
* - \ref asfdoc_sam0_system_interrupt_group "System Interrupt Control" (sub-module)
|
||||
* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Control" (sub-module)
|
||||
*
|
||||
*
|
||||
* \if DEVICE_SAML21_SYSTEM_SUPPORT
|
||||
* \subsection asfdoc_sam0_system_module_overview_vreg_l21 Voltage Regulator
|
||||
* The SAM device controls the voltage regulators for the core (VDDCORE) and
|
||||
* backup (VDDBU) domains. It sets the voltage regulators according to the sleep
|
||||
* modes, the performance level, or the user configuration.
|
||||
*
|
||||
* In active mode, the voltage regulator can be chosen on the fly between a LDO
|
||||
* or a Buck converter. In standby mode, the low power voltage regulator is used
|
||||
* to supply VDDCORE.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_module_overview_bbps Battery Backup Power Switch
|
||||
* The SAM device supports connection of a battery backup to the VBAT power pin.
|
||||
* It includes functionality that enables automatic power switching between main
|
||||
* power and battery backup power. This will ensure power to the backup domain,
|
||||
* when the main battery or power source is unavailable.
|
||||
* \endif
|
||||
*
|
||||
* \if DEVICE_SAMC21_SYSTEM_SUPPORT
|
||||
* \subsection asfdoc_sam0_system_module_overview_vreg_c21 Voltage Regulator
|
||||
* The SAM device controls the voltage regulators for the core (VDDCORE). It sets
|
||||
* the voltage regulators according to the sleep modes.
|
||||
*
|
||||
* There are a selectable reference voltage and voltage dependent on the temperature
|
||||
* which can be used by analog modules like the ADC.
|
||||
* \endif
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_module_overview_vref Voltage References
|
||||
* The various analog modules within the SAM devices (such as AC, ADC, and
|
||||
* DAC) require a voltage reference to be configured to act as a reference point
|
||||
* for comparisons and conversions.
|
||||
*
|
||||
* The SAM devices contain multiple references, including an internal
|
||||
* temperature sensor and a fixed band-gap voltage source. When enabled, the
|
||||
* associated voltage reference can be selected within the desired peripheral
|
||||
* where applicable.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_module_overview_reset_cause System Reset Cause
|
||||
* In some applications there may be a need to execute a different program
|
||||
* flow based on how the device was reset. For example, if the cause of reset
|
||||
* was the Watchdog timer (WDT), this might indicate an error in the application,
|
||||
* and a form of error handling or error logging might be needed.
|
||||
*
|
||||
* For this reason, an API is provided to retrieve the cause of the last system
|
||||
* reset, so that appropriate action can be taken.
|
||||
*
|
||||
* \if DEVICE_SAML21_SYSTEM_SUPPORT
|
||||
* There are three groups of reset sources:
|
||||
* - Power supply reset: Resets caused by an electrical issue. It covers POR and BOD reset.
|
||||
* - User reset: Resets caused by the application. It covers external reset,
|
||||
* system reset, and watchdog reset.
|
||||
* - Backup reset: Resets caused by a backup mode exit condition.
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_module_overview_performance_level Performance Level
|
||||
* Performance level allows the user to adjust the regulator output voltage to reduce
|
||||
* power consumption. The user can on the fly select the most suitable performance
|
||||
* level, depending on the application demands.
|
||||
*
|
||||
* The SAM device can operate at two different performance levels (PL0 and PL2).
|
||||
* When operating at PL0, the voltage applied on the full logic area is reduced
|
||||
* by voltage scaling. This voltage scaling technique allows to reduce the active
|
||||
* power consumption while decreasing the maximum frequency of the device. When
|
||||
* operating at PL2, the voltage regulator supplies the highest voltage, allowing
|
||||
* the device to run at higher clock speeds.
|
||||
*
|
||||
* Performance level transition is possible only when the device is in active
|
||||
* mode. After a reset, the device starts at the lowest performance level
|
||||
* (lowest power consumption and lowest max. frequency). The application can then
|
||||
* switch to another performance level at any time without any stop in the code
|
||||
* execution. As shown in \ref asfdoc_sam0_system_performance_level_transition_figure.
|
||||
*
|
||||
* \note When scaling down the performance level, the bus frequency should first be
|
||||
* scaled down in order to not exceed the maximum frequency allowed for the
|
||||
* low performance level.
|
||||
* When scaling up the performance level (e.g. from PL0 to PL2), check the performance
|
||||
* level status before increasing the bus frequency. It can be increased only
|
||||
* when the performance level transition is completed.
|
||||
*
|
||||
* \anchor asfdoc_sam0_system_performance_level_transition_figure
|
||||
* \image html performance_level_transition.svg "Performance Level Transition"
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_module_overview_power_domain Power Domain Gating
|
||||
* Power domain gating allows power saving by reducing the voltage in logic
|
||||
* areas in the device to a low-power supply. The feature is available in
|
||||
* Standby sleep mode and will reduce the voltage in domains where all peripherals
|
||||
* are idle. Internal logic will maintain its content, meaning the corresponding
|
||||
* peripherals will not need to be reconfigured when normal operating voltage
|
||||
* is returned. Most power domains can be in the following three states:
|
||||
*
|
||||
* - Active state: The power domain is powered on.
|
||||
* - Retention state: The main voltage supply for the power domain is switched off,
|
||||
* while maintaining a secondary low-power supply for the sequential cells. The
|
||||
* logic context is restored when waking up.
|
||||
* - Off state: The power domain is entirely powered off. The logic context is lost.
|
||||
*
|
||||
* The SAM L21 device contains three power domains which can be controlled using
|
||||
* power domain gating, namely PD0, PD1, and PD2. These power domains can be
|
||||
* configured to the following cases:
|
||||
* - Default with no sleepwalking peripherals: A power domain is automatically set
|
||||
* to retention state in standby sleep mode if no activity require it. The application
|
||||
* can force all power domains to remain in active state during standby sleep mode
|
||||
* in order to accelerate wakeup time.
|
||||
* - Default with sleepwalking peripherals: If one or more peripherals are enabled
|
||||
* to perform sleepwalking tasks in standby sleep mode, the corresponding power
|
||||
* domain (PDn) remains in active state as well as all inferior power domains (<PDn).
|
||||
* - Sleepwalking with dynamic power domain gating: During standby sleep mode, a
|
||||
* power domain (PDn) in active can wake up a superior power domain (>PDn) in order
|
||||
* to perform a sleepwalking task. The superior power domain is then automatically
|
||||
* set to active state. At the end of the sleepwalking task, the device can either
|
||||
* be woken up or the superior power domain can return to retention state.
|
||||
*
|
||||
* Power domains can be linked to each other, it allows a power domain (PDn) to be kept
|
||||
* in active state if the inferior power domain (PDn-1) is in active state too.
|
||||
*
|
||||
* \ref asfdoc_sam0_system_power_domain_overview_table illustrates the
|
||||
* four cases to consider in standby mode.
|
||||
*
|
||||
* \anchor asfdoc_sam0_system_power_domain_overview_table
|
||||
* <table>
|
||||
* <caption>Sleep Mode versus Power Domain State Overview</caption>
|
||||
* <tr>
|
||||
* <th>Sleep mode</th>
|
||||
* <th>PD0</th>
|
||||
* <th>PD1</th>
|
||||
* <th>PD2</th>
|
||||
* <th>PDTOP</th>
|
||||
* <th>PDBACKUP</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Idle</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Standby - Case 1</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Standby - Case 2</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* <td>retention</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Standby - Case 3</td>
|
||||
* <td>active</td>
|
||||
* <td>retention</td>
|
||||
* <td>retention</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Standby - Case 4</td>
|
||||
* <td>retention</td>
|
||||
* <td>retention</td>
|
||||
* <td>retention</td>
|
||||
* <td>active</td>
|
||||
* <td>active</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Backup</td>
|
||||
* <td>off</td>
|
||||
* <td>off</td>
|
||||
* <td>off</td>
|
||||
* <td>off</td>
|
||||
* <td>active</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Off</td>
|
||||
* <td>off</td>
|
||||
* <td>off</td>
|
||||
* <td>off</td>
|
||||
* <td>off</td>
|
||||
* <td>off</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_module_overview_ram_state RAMs Low Power Mode
|
||||
* By default, in standby sleep mode, RAM is in low power mode (back biased)
|
||||
* if its power domain is in retention state.
|
||||
* \ref asfdoc_sam0_system_power_ram_state_table lists RAMs low power mode.
|
||||
*
|
||||
* \anchor asfdoc_sam0_system_power_ram_state_table
|
||||
* <table>
|
||||
* <caption>RAM Back-biasing Mode</caption>
|
||||
* <tr>
|
||||
* <th>RAM mode</th>
|
||||
* <th>Description</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Retention Back-biasing mode</td>
|
||||
* <td>RAM is back-biased if its power domain is in retention mode</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Standby Back-biasing mode</td>
|
||||
* <td>RAM is back-biased if the device is in standby mode</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Standby OFF mode</td>
|
||||
* <td>RAM is OFF if the device is in standby mode</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Always OFF mode</td>
|
||||
* <td>RAM is OFF if the device is in RET mode</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*
|
||||
* \endif
|
||||
*
|
||||
* \subsection asfdoc_sam0_system_module_overview_sleep_mode Sleep Modes
|
||||
* The SAM devices have several sleep modes. The sleep mode controls
|
||||
* which clock systems on the device will remain enabled or disabled when the
|
||||
* device enters a low power sleep mode.
|
||||
* \ref asfdoc_sam0_system_module_sleep_mode_table "The table below" lists the
|
||||
* clock settings of the different sleep modes.
|
||||
*
|
||||
* \anchor asfdoc_sam0_system_module_sleep_mode_table
|
||||
* <table>
|
||||
* <caption>SAM Device Sleep Modes</caption>
|
||||
* \if DEVICE_SAML21_SYSTEM_SUPPORT
|
||||
* <tr>
|
||||
* <th>Sleep mode</th>
|
||||
* <th>System clock</th>
|
||||
* <th>CPU clock</th>
|
||||
* <th>AHB/AHB clock</th>
|
||||
* <th>GCLK clocks</th>
|
||||
* <th>Oscillators (ONDEMAND = 0)</th>
|
||||
* <th>Oscillators (ONDEMAND = 1)</th>
|
||||
* <th>Regulator mode</th>
|
||||
* <th>RAM mode</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Idle</td>
|
||||
* <td>Run</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Run if requested</td>
|
||||
* <td>Run</td>
|
||||
* <td>Run</td>
|
||||
* <td>Run if requested</td>
|
||||
* <td>Normal</td>
|
||||
* <td>Normal</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Standby</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Run if requested</td>
|
||||
* <td>Run if requested</td>
|
||||
* <td>Run if requested or RUNSTDBY = 1</td>
|
||||
* <td>Run if requested</td>
|
||||
* <td>Low pwer</td>
|
||||
* <td>Low pwer</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Backup</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Backup</td>
|
||||
* <td>Off</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Off</td>
|
||||
* <td>Off</td>
|
||||
* <td>Off</td>
|
||||
* <td>Off</td>
|
||||
* <td>Off</td>
|
||||
* <td>Off</td>
|
||||
* <td>Off</td>
|
||||
* <td>Off</td>
|
||||
* <td>Off</td>
|
||||
* </tr>
|
||||
* \else
|
||||
* <tr>
|
||||
* <th>Sleep mode</th>
|
||||
* <th>CPU clock</th>
|
||||
* <th>AHB clock</th>
|
||||
* <th>APB clocks</th>
|
||||
* <th>Clock sources</th>
|
||||
* <th>System clock</th>
|
||||
* <th>32KHz</th>
|
||||
* <th>Reg mode</th>
|
||||
* <th>RAM mode</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Idle 0</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Run</td>
|
||||
* <td>Run</td>
|
||||
* <td>Run</td>
|
||||
* <td>Run</td>
|
||||
* <td>Run</td>
|
||||
* <td>Normal</td>
|
||||
* <td>Normal</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Idle 1</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Run</td>
|
||||
* <td>Run</td>
|
||||
* <td>Run</td>
|
||||
* <td>Run</td>
|
||||
* <td>Normal</td>
|
||||
* <td>Normal</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Idle 2</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Run</td>
|
||||
* <td>Run</td>
|
||||
* <td>Run</td>
|
||||
* <td>Normal</td>
|
||||
* <td>Normal</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Standby</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Stop</td>
|
||||
* <td>Low Power</td>
|
||||
* <td>Source/Drain biasing</td>
|
||||
* </tr>
|
||||
* \endif
|
||||
* </table>
|
||||
*
|
||||
* Before entering device sleep, one of the available sleep modes must be set.
|
||||
* The device will automatically wake up in response to an interrupt being
|
||||
* generated or upon any other sleep mode exit condition.
|
||||
*
|
||||
* Some peripheral clocks will remain enabled during sleep, depending on their
|
||||
* configuration. If desired, the modules can remain clocked during sleep to allow
|
||||
* them continue to operate while other parts of the system are powered down
|
||||
* to save power.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_special_considerations Special Considerations
|
||||
*
|
||||
* Most of the functions in this driver have device specific restrictions and
|
||||
* caveats; refer to your device datasheet.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_extra_info Extra Information
|
||||
*
|
||||
* For extra information, see \ref asfdoc_sam0_system_extra. This includes:
|
||||
* - \ref asfdoc_sam0_system_extra_acronyms
|
||||
* - \ref asfdoc_sam0_system_extra_dependencies
|
||||
* - \ref asfdoc_sam0_system_extra_errata
|
||||
* - \ref asfdoc_sam0_system_extra_history
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_examples Examples
|
||||
*
|
||||
* For SYSTEM module related examples, refer to the sub-modules listed in
|
||||
* the \ref asfdoc_sam0_system_module_overview "Module Overview".
|
||||
*
|
||||
* \if DEVICE_SAML21_SYSTEM_SUPPORT
|
||||
* For a list of examples related to this driver, see
|
||||
* \ref asfdoc_sam0_drivers_power_exqsg.
|
||||
* \endif
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_api_overview API Overview
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \name System Debugger
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Check if debugger is present.
|
||||
*
|
||||
* Check if debugger is connected to the onboard debug system (DAP).
|
||||
*
|
||||
* \return A bool identifying if a debugger is present.
|
||||
*
|
||||
* \retval true Debugger is connected to the system
|
||||
* \retval false Debugger is not connected to the system
|
||||
*
|
||||
*/
|
||||
static inline bool system_is_debugger_present(void)
|
||||
{
|
||||
return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* \name System Identification
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Retrieve the device identification signature.
|
||||
*
|
||||
* Retrieves the signature of the current device.
|
||||
*
|
||||
* \return Device ID signature as a 32-bit integer.
|
||||
*/
|
||||
static inline uint32_t system_get_device_id(void)
|
||||
{
|
||||
return DSU->DID.reg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* \name System Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
void system_init(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
*
|
||||
* \if DEVICE_SAML21_SYSTEM_SUPPORT
|
||||
* \page asfdoc_sam0_drivers_power_exqsg Examples for SYSTEM Driver
|
||||
*
|
||||
* This is a list of the available Quick Start Guides (QSGs) and example
|
||||
* applications for \ref asfdoc_sam0_system_group. QSGs are simple examples with step-by-step instructions to
|
||||
* configure and use this driver in a selection of
|
||||
* use cases. Note that a QSG can be compiled as a standalone application or be
|
||||
* added to the user application.
|
||||
*
|
||||
* - \subpage asfdoc_sam0_power_basic_use_case
|
||||
* \endif
|
||||
*
|
||||
* \page asfdoc_sam0_system_extra Extra Information for SYSTEM Driver
|
||||
*
|
||||
* \section asfdoc_sam0_system_extra_acronyms Acronyms
|
||||
* Below is a table listing the acronyms used in this module, along with their
|
||||
* intended meanings.
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Acronym</th>
|
||||
* <th>Definition</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>PM</td>
|
||||
* <td>Power Manager</td>
|
||||
* </tr>
|
||||
* \if DEVICE_SAML21_SYSTEM_SUPPORT
|
||||
* <tr>
|
||||
* <td>SUPC</td>
|
||||
* <td>Supply Controller</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>RSTC</td>
|
||||
* <td>Reset Controller</td>
|
||||
* </tr>
|
||||
* \endif
|
||||
* \if DEVICE_SAMC21_SYSTEM_SUPPORT
|
||||
* <tr>
|
||||
* <td>SUPC</td>
|
||||
* <td>Supply Controller</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>RSTC</td>
|
||||
* <td>Reset Controller</td>
|
||||
* </tr>
|
||||
* \endif
|
||||
* \if DEVICE_SAMD21_SYSTEM_SUPPORT
|
||||
* <tr>
|
||||
* <td>SYSCTRL</td>
|
||||
* <td>System control interface</td>
|
||||
* </tr>
|
||||
* \endif
|
||||
* </table>
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_extra_dependencies Dependencies
|
||||
* This driver has the following dependencies:
|
||||
*
|
||||
* - None
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_extra_errata Errata
|
||||
* There are no errata related to this driver.
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_system_extra_history Module History
|
||||
* An overview of the module history is presented in the table below, with
|
||||
* details on the enhancements and fixes made to the module since its first
|
||||
* release. The current version of this corresponds to the newest version in
|
||||
* the table.
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Changelog</th>
|
||||
* </tr>
|
||||
* \if DEVICE_SAML21_SYSTEM_SUPPORT
|
||||
* <tr>
|
||||
* <td>Initial Release</td>
|
||||
* </tr>
|
||||
* \endif
|
||||
* \if DEVICE_SAMC21_SYSTEM_SUPPORT
|
||||
* <tr>
|
||||
* <td>Initial Release</td>
|
||||
* </tr>
|
||||
* \endif
|
||||
* \if DEVICE_SAMD21_SYSTEM_SUPPORT
|
||||
* <tr>
|
||||
* <td>Added new \c system_reset() to reset the complete MCU with some exceptions</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Added new \c system_get_device_id() function to retrieved the device
|
||||
* ID</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Initial Release</td>
|
||||
* </tr>
|
||||
* \endif
|
||||
* </table>
|
||||
*
|
||||
* \page asfdoc_sam0_system_document_revision_history Document Revision History
|
||||
*
|
||||
* <table>
|
||||
* <tr>
|
||||
* <th>Doc. Rev.</th>
|
||||
* <th>Date</th>
|
||||
* <th>Comments</th>
|
||||
* </tr>
|
||||
* \if DEVICE_SAML21_SYSTEM_SUPPORT
|
||||
* <tr>
|
||||
* <td>42449A</td>
|
||||
* <td>07/2015</td>
|
||||
* <td>Initial document release</td>
|
||||
* </tr>
|
||||
* \endif
|
||||
* \if DEVICE_SAMC21_SYSTEM_SUPPORT
|
||||
* <tr>
|
||||
* <td>42484A</td>
|
||||
* <td>12/2015</td>
|
||||
* <td>Initial document release.</td>
|
||||
* </tr>
|
||||
* \endif
|
||||
* \if DEVICE_SAMD21_SYSTEM_SUPPORT
|
||||
* <tr>
|
||||
* <td>42120E</td>
|
||||
* <td>12/2015</td>
|
||||
* <td>Added support for SAM DA1 and SAM D09</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42120D</td>
|
||||
* <td>12/2014</td>
|
||||
* <td>Added support for SAM R21 and SAM D10/D11</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42120C</td>
|
||||
* <td>01/2014</td>
|
||||
* <td>Added support for SAM D21</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42120B</td>
|
||||
* <td>06/2013</td>
|
||||
* <td>Corrected documentation typos</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>42120A</td>
|
||||
* <td>06/2013</td>
|
||||
* <td>Initial document release</td>
|
||||
* </tr>
|
||||
* \endif
|
||||
* </table>
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_H_INCLUDED */
|
||||
|
||||
@ -0,0 +1,139 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM TCC Driver Quick Start
|
||||
*
|
||||
* Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_tcc_basic_use_case Quick Start Guide for TCC - Basic
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAM D21/R21/L21/L22/DA1/C21/HA1G16A Xplained Pro
|
||||
*
|
||||
* In this use case, the TCC will be used to generate a PWM signal. Here
|
||||
* the pulse width is set to one quarter of the period.
|
||||
* When the PWM signal connects to LED, LED will light. To see the waveform,
|
||||
* you may need an oscilloscope.
|
||||
* SAMHA1G16A Xpro LED is PA00 which isn't connected out, use PA04 instead,
|
||||
* so we can't see LED blink but only see the waveform from oscilloscope.
|
||||
*
|
||||
* The PWM output is set up as follows:
|
||||
* <table>
|
||||
* <tr><th> Board </td><th> Pin </td><th> Connect to </td></tr>
|
||||
* <tr><td> SAM D21 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM R21 Xpro </td><td> PA19 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM L21 Xpro </td><td> PB10 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM L22 Xpro </td><td> PC27 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM DA1 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM C21 Xpro </td><td> PA15 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM HA1G16A Xpro </td><td> PA04 </td><td> NULL </td></tr>
|
||||
* </table>
|
||||
*
|
||||
* The TCC module will be set up as follows:
|
||||
* - GCLK generator 0 (GCLK main) clock source
|
||||
* - Use double buffering write when set top, compare, or pattern through API
|
||||
* - No dithering on the counter or compare
|
||||
* - Prescaler is set to 256
|
||||
* - Single Slope PWM wave generation
|
||||
* - GCLK reload action
|
||||
* - Don't run in standby
|
||||
* - No fault or waveform extensions
|
||||
* - No inversion of waveform output
|
||||
* - No capture enabled
|
||||
* - Count upward
|
||||
* - Don't perform one-shot operations
|
||||
* - No event input enabled
|
||||
* - No event action
|
||||
* - No event generation enabled
|
||||
* - Counter starts on 0
|
||||
* - Counter top set to 0xFFFF
|
||||
* - Capture compare channel 0 set to 0xFFFF/4
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_basic_use_case_setup Quick Start
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_basic_use_case_prereq Prerequisites
|
||||
* There are no prerequisites for this use case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_basic_use_case_setup_code Code
|
||||
*
|
||||
* Add to the main application source file, before any functions:
|
||||
* \snippet conf_quick_start.h definition_pwm
|
||||
*
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_tcc_basic.c module_inst
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_tcc_basic.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_tcc_basic.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_basic_use_case_setup_flow Workflow
|
||||
* -# Create a module software instance structure for the TCC module to store
|
||||
* the TCC driver state while it is in use.
|
||||
* \snippet qs_tcc_basic.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Configure the TCC module.
|
||||
* -# Create a TCC module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical TCC peripheral.
|
||||
* \snippet qs_tcc_basic.c setup_config
|
||||
* -# Initialize the TCC configuration struct with the module's default values.
|
||||
* \snippet qs_tcc_basic.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Alter the TCC settings to configure the counter width, wave generation
|
||||
* mode, and the compare channel 0 value.
|
||||
* \snippet qs_tcc_basic.c setup_change_config
|
||||
* -# Alter the TCC settings to configure the PWM output on a physical device
|
||||
* pin.
|
||||
* \snippet qs_tcc_basic.c setup_change_config_pwm
|
||||
* -# Configure the TCC module with the desired settings.
|
||||
* \snippet qs_tcc_basic.c setup_set_config
|
||||
* -# Enable the TCC module to start the timer and begin PWM signal generation.
|
||||
* \snippet qs_tcc_basic.c setup_enable
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_basic_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_basic_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_tcc_basic.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_basic_use_case_main_flow Workflow
|
||||
* -# Enter an infinite loop while the PWM wave is generated via the TCC module.
|
||||
* \snippet qs_tcc_basic.c main_loop
|
||||
*/
|
||||
@ -0,0 +1,145 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM TCC Driver Double Buffering Quick Start
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_tcc_buffering_use_case Quick Start Guide for TCC - Double Buffering and Circular
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAM D21/R21/L21/L22/DA1/C21/HA1G16A Xplained Pro
|
||||
*
|
||||
* In this use case, the TCC will be used to generate a PWM signal. Here
|
||||
* the pulse width alters in one quarter and three quarter of the period.
|
||||
* When the PWM signal connects to LED, LED will light. To see the waveform,
|
||||
* you may need an oscilloscope.
|
||||
* SAMHA1G16A Xpro LED is PA00 which isn't connected out, use PA04 instead,
|
||||
* so we can't see LED blink but only see the waveform from oscilloscope.
|
||||
*
|
||||
* The PWM output is set up as follows:
|
||||
* <table>
|
||||
* <tr><th> Board </td><th> Pin </td><th> Connect to </td></tr>
|
||||
* <tr><td> SAM D21 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM R21 Xpro </td><td> PA19 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM L21 Xpro </td><td> PB10 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM L22 Xpro </td><td> PC27 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM DA1 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM C21 Xpro </td><td> PA15 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM HA1G16A Xpro </td><td> PA04 </td><td> NULL </td></tr>
|
||||
* </table>
|
||||
*
|
||||
* The TCC module will be set up as follows:
|
||||
* - GCLK generator 0 (GCLK main) clock source
|
||||
* - Use double buffering write when set top, compare, or pattern through API
|
||||
* - No dithering on the counter or compare
|
||||
* - Prescaler is set to 1024
|
||||
* - Single Slope PWM wave generation
|
||||
* - GCLK reload action
|
||||
* - Don't run in standby
|
||||
* - No fault or waveform extensions
|
||||
* - No inversion of waveform output
|
||||
* - No capture enabled
|
||||
* - Count upward
|
||||
* - Don't perform one-shot operations
|
||||
* - No event input enabled
|
||||
* - No event action
|
||||
* - No event generation enabled
|
||||
* - Counter starts on 0
|
||||
* - Counter top set to 8000
|
||||
* - Capture compare channel set to 8000/4
|
||||
* - Capture compare channel buffer set to 8000*3/4
|
||||
* - Circular option for compare channel is enabled so that the compare
|
||||
* values keep switching on update condition
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_buffering_use_case_setup Quick Start
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_buffering_use_case_prereq Prerequisites
|
||||
* There are no prerequisites for this use case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_buffering_use_case_setup_code Code
|
||||
*
|
||||
* Add to the main application source file, before any functions:
|
||||
* \snippet conf_quick_start_buffering.h definition_pwm
|
||||
*
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_tcc_buffering.c module_inst
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_tcc_buffering.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_tcc_buffering.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_buffering_use_case_setup_flow Workflow
|
||||
* -# Create a module software instance structure for the TCC module to store
|
||||
* the TCC driver state while it is in use.
|
||||
* \snippet qs_tcc_buffering.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Configure the TCC module.
|
||||
* -# Create a TCC module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical TCC peripheral.
|
||||
* \snippet qs_tcc_buffering.c setup_config
|
||||
* -# Initialize the TCC configuration struct with the module's default values.
|
||||
* \snippet qs_tcc_buffering.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Alter the TCC settings to configure the counter width, wave generation
|
||||
* mode, and the compare channel 0 value.
|
||||
* \snippet qs_tcc_buffering.c setup_change_config
|
||||
* -# Alter the TCC settings to configure the PWM output on a physical device
|
||||
* pin.
|
||||
* \snippet qs_tcc_buffering.c setup_change_config_pwm
|
||||
* -# Configure the TCC module with the desired settings.
|
||||
* \snippet qs_tcc_buffering.c setup_set_config
|
||||
* -# Set to compare buffer value and enable circular of double buffered
|
||||
* compare values.
|
||||
* \snippet qs_tcc_buffering.c setup_set_buffering
|
||||
* -# Enable the TCC module to start the timer and begin PWM signal generation.
|
||||
* \snippet qs_tcc_buffering.c setup_enable
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_buffering_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_buffering_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_tcc_buffering.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_buffering_use_case_main_flow Workflow
|
||||
* -# Enter an infinite loop while the PWM wave is generated via the TCC module.
|
||||
* \snippet qs_tcc_buffering.c main_loop
|
||||
*/
|
||||
@ -0,0 +1,151 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM TCC - Timer Counter for Control Applications Callback Driver Quick Start
|
||||
*
|
||||
* Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_tcc_callback_use_case Quick Start Guide for TCC - Callback
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAM D21/R21/L21/L22/DA1/C21/HA1G16A Xplained Pro
|
||||
*
|
||||
* In this use case, the TCC will be used to generate a PWM signal, with a
|
||||
* varying duty cycle. Here the pulse width is increased each time the timer
|
||||
* count matches the set compare value.
|
||||
* When the PWM signal connects to LED, LED will light. To see the waveform,
|
||||
* you may need an oscilloscope.
|
||||
* SAMHA1G16A Xpro LED is PA00 which isn't connected out, use PA04 instead,
|
||||
* so we can't see LED blink but only see the waveform from oscilloscope.
|
||||
*
|
||||
* The PWM output is set up as follows:
|
||||
* <table>
|
||||
* <tr><th> Board </td><th> Pin </td><th> Connect to </td></tr>
|
||||
* <tr><td> SAM D21 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM R21 Xpro </td><td> PA19 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM L21 Xpro </td><td> PB10 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM L22 Xpro </td><td> PC27 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM DA1 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM C21 Xpro </td><td> PA15 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM HA1G16A Xpro </td><td> PA04 </td><td> NULL </td></tr>
|
||||
* </table>
|
||||
*
|
||||
* The TCC module will be set up as follows:
|
||||
* - GCLK generator 0 (GCLK main) clock source
|
||||
* - Use double buffering write when set top, compare, or pattern through API
|
||||
* - No dithering on the counter or compare
|
||||
* - No prescaler
|
||||
* - Single Slope PWM wave generation
|
||||
* - GCLK reload action
|
||||
* - Don't run in standby
|
||||
* - No faults or waveform extensions
|
||||
* - No inversion of waveform output
|
||||
* - No capture enabled
|
||||
* - Count upward
|
||||
* - Don't perform one-shot operations
|
||||
* - No event input enabled
|
||||
* - No event action
|
||||
* - No event generation enabled
|
||||
* - Counter starts on 0
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_callback_use_case_setup Quick Start
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_callback_use_case_prereq Prerequisites
|
||||
* There are no prerequisites for this use case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_callback_use_case_setup_code Code
|
||||
*
|
||||
* Add to the main application source file, before any functions:
|
||||
* \snippet conf_quick_start.h definition_pwm
|
||||
*
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_tcc_callback.c module_inst
|
||||
*
|
||||
* Copy-paste the following callback function code to your user application:
|
||||
* \snippet qs_tcc_callback.c callback_funcs
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_tcc_callback.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_tcc_callback.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_callback_use_case_setup_flow Workflow
|
||||
* -# Create a module software instance structure for the TCC module to store
|
||||
* the TCC driver state while it is in use.
|
||||
* \snippet qs_tcc_callback.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Configure the TCC module.
|
||||
* -# Create a TCC module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical TCC peripheral.
|
||||
* \snippet qs_tcc_callback.c setup_config
|
||||
* -# Initialize the TCC configuration struct with the module's default values.
|
||||
* \snippet qs_tcc_callback.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Alter the TCC settings to configure the counter width, wave generation
|
||||
* mode, and the compare channel 0 value.
|
||||
* \snippet qs_tcc_callback.c setup_change_config
|
||||
* -# Alter the TCC settings to configure the PWM output on a physical device
|
||||
* pin.
|
||||
* \snippet qs_tcc_callback.c setup_change_config_pwm
|
||||
* -# Configure the TCC module with the desired settings.
|
||||
* \snippet qs_tcc_callback.c setup_set_config
|
||||
* -# Enable the TCC module to start the timer and begin PWM signal generation.
|
||||
* \snippet qs_tcc_callback.c setup_enable
|
||||
* -# Configure the TCC callbacks.
|
||||
* -# Register the Compare Channel 0 Match callback functions with the driver.
|
||||
* \snippet qs_tcc_callback.c setup_register_callback
|
||||
* -# Enable the Compare Channel 0 Match callback so that it will be called by
|
||||
* the driver when appropriate.
|
||||
* \snippet qs_tcc_callback.c setup_enable_callback
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_callback_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_callback_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_tcc_callback.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_callback_use_case_main_flow Workflow
|
||||
* -# Enter an infinite loop while the PWM wave is generated via the TCC module.
|
||||
* \snippet qs_tcc_callback.c main_loop
|
||||
*/
|
||||
|
||||
|
||||
#include <asf.h>
|
||||
#include <conf_clocks.h>
|
||||
@ -0,0 +1,275 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM TCC Driver Quick Start with DMA
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_tcc_dma_use_case Quick Start Guide for Using DMA with TCC
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAM D21/R21/L21/L22/DA1/C21/HA1G16A Xplained Pro
|
||||
*
|
||||
* In this use case, the TCC will be used to generate a PWM signal. Here
|
||||
* the pulse width varies through the following values with the help of DMA
|
||||
* transfer: one quarter of the period, half of the period, and three quarters
|
||||
* of the period.
|
||||
* The PWM output can be used to drive a LED. The waveform can also be
|
||||
* viewed using an oscilloscope.
|
||||
* The output signal is also fed back to another TCC channel by event system,
|
||||
* the event stamps are captured and transferred to a buffer by DMA.
|
||||
* SAMHA1G16A Xpro LED is PA00 which isn't connected out, use PA04 instead,
|
||||
* so we can't see LED blink but only see the waveform from oscilloscope.
|
||||
*
|
||||
* The PWM output is set up as follows:
|
||||
* <table>
|
||||
* <tr><th> Board </td><th> Pin </td><th> Connect to </td></tr>
|
||||
* <tr><td> SAM D21 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM R21 Xpro </td><td> PA19 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM L21 Xpro </td><td> PB10 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM L22 Xpro </td><td> PC27 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM DA1 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM C21 Xpro </td><td> PA15 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM HA1G16A Xpro </td><td> PA04 </td><td> NULL </td></tr>
|
||||
* </table>
|
||||
*
|
||||
* The TCC module will be setup as follows:
|
||||
* - GCLK generator 0 (GCLK main) clock source
|
||||
* - Use double buffering write when set top, compare, or pattern through API
|
||||
* - No dithering on the counter or compare
|
||||
* - Prescaler is set to 1024
|
||||
* - Single Slope PWM wave generation
|
||||
* - GCLK reload action
|
||||
* - Don't run in standby
|
||||
* - No fault or waveform extensions
|
||||
* - No inversion of waveform output
|
||||
* - No capture enabled
|
||||
* - Count upward
|
||||
* - Don't perform one-shot operations
|
||||
* - Counter starts on 0
|
||||
* - Counter top set to 0x1000
|
||||
* - Channel 0 (on SAM D21 Xpro) or 3 (on SAM R21 Xpro) is set to
|
||||
* compare and match value 0x1000*3/4 and generate event
|
||||
* - Channel 1 is set to capture on input event
|
||||
*
|
||||
* The event resource of EVSYS module will be setup as follows:
|
||||
* - TCC match capture channel 0 (on SAM D21 Xpro) or 3 (on SAM R21 Xpro) is
|
||||
* selected as event generator
|
||||
* - Event generation is synchronous, with rising edge detected
|
||||
* - TCC match capture channel 1 is the event user
|
||||
*
|
||||
* The DMA resource of DMAC module will be setup as follows:
|
||||
* - Two DMA resources are used
|
||||
* - Both DMA resources use peripheral trigger
|
||||
* - Both DMA resources perform beat transfer on trigger
|
||||
* - Both DMA resources use beat size of 16 bits
|
||||
* - Both DMA resources are configured to transfer three beats and
|
||||
* then repeat again in same buffer
|
||||
* - On DMA resource which controls the compare value
|
||||
* - TCC0 overflow triggers DMA transfer
|
||||
* - The source address increment is enabled
|
||||
* - The destination address is fixed to TCC channel 0 Compare/Capture
|
||||
*register
|
||||
* - On DMA resource which reads the captured value
|
||||
* - TCC0 capture on channel 1 triggers DMA transfer
|
||||
* - The source address is fixed to TCC channel 1 Compare/Capture register
|
||||
* - The destination address increment is enabled
|
||||
* - The captured value is transferred to an array in SRAM
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_dma_use_case_setup Quick Start
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_dma_use_case_prereq Prerequisites
|
||||
* There are no prerequisites for this use case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_dma_use_case_setup_code Code
|
||||
*
|
||||
* Add to the main application source file, before any functions, according to
|
||||
* the kit used:
|
||||
* - SAM D21 Xplained Pro
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_pwm
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_feedback
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_dma.h definition_dma_capture_trigger
|
||||
* - SAM R21 Xplained Pro
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_pwm
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_feedback
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_dma.h definition_dma_capture_trigger
|
||||
* - SAM L21 Xplained Pro
|
||||
* \snippet saml21_xplained_pro/conf_quick_start_dma.h definition_pwm
|
||||
* \snippet saml21_xplained_pro/conf_quick_start_dma.h definition_feedback
|
||||
* \snippet saml21_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger
|
||||
* - SAM L22 Xplained Pro
|
||||
* \snippet saml22_xplained_pro/conf_quick_start_dma.h definition_pwm
|
||||
* \snippet saml22_xplained_pro/conf_quick_start_dma.h definition_feedback
|
||||
* \snippet saml22_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger
|
||||
* - SAM DA1 Xplained Pro
|
||||
* \snippet samda1_xplained_pro/conf_quick_start_dma.h definition_pwm
|
||||
* \snippet samda1_xplained_pro/conf_quick_start_dma.h definition_feedback
|
||||
* \snippet samda1_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger
|
||||
* \snippet samda1_xplained_pro/conf_quick_start_dma.h definition_dma_capture_trigger
|
||||
* - SAM C21 Xplained Pro
|
||||
* \snippet samc21_xplained_pro/conf_quick_start_dma.h definition_pwm
|
||||
* \snippet samc21_xplained_pro/conf_quick_start_dma.h definition_feedback
|
||||
* \snippet samc21_xplained_pro/conf_quick_start_dma.h definition_dma_compare_trigger
|
||||
*
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_tcc_dma.c module_inst
|
||||
* \snippet qs_tcc_dma.c capture_variables
|
||||
* \snippet qs_tcc_dma.c compare_variables
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_tcc_dma.c config_event_for_capture
|
||||
* \snippet qs_tcc_dma.c config_dma_for_capture
|
||||
* \snippet qs_tcc_dma.c config_dma_for_wave
|
||||
* \snippet qs_tcc_dma.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_tcc_dma.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_dma_use_case_setup_flow Workflow
|
||||
* \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_tcc Configure the TCC
|
||||
* -# Create a module software instance structure for the TCC module to store
|
||||
* the TCC driver state while it is in use.
|
||||
* \snippet qs_tcc_dma.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
* -# Create a TCC module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical TCC peripheral.
|
||||
* \snippet qs_tcc_dma.c setup_config
|
||||
* -# Initialize the TCC configuration struct with the module's default values.
|
||||
* \snippet qs_tcc_dma.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
* -# Alter the TCC settings to configure the counter width, wave generation
|
||||
* mode, and the compare channel 0 value.
|
||||
* \snippet qs_tcc_dma.c setup_change_config
|
||||
* -# Alter the TCC settings to configure the PWM output on a physical device
|
||||
* pin.
|
||||
* \snippet qs_tcc_dma.c setup_change_config_pwm
|
||||
* -# Configure the TCC module with the desired settings.
|
||||
* \snippet qs_tcc_dma.c setup_set_config
|
||||
* -# Configure and enable the desired events for the TCC module.
|
||||
* \snippet qs_tcc_dma.c setup_events
|
||||
* \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_event Configure the Event System
|
||||
* Configure the EVSYS module to wire channel 0 event to channel 1.
|
||||
* -# Create an event resource instance.
|
||||
* \snippet qs_tcc_dma.c capture_event_resource
|
||||
* \note This should never go out of scope as long as the resource is in
|
||||
* use. In most cases, this should be global.
|
||||
*
|
||||
* -# Create an event resource configuration struct.
|
||||
* \snippet qs_tcc_dma.c event_setup_1
|
||||
* -# Initialize the event resource configuration struct with default values.
|
||||
* \snippet qs_tcc_dma.c event_setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
* -# Adjust the event resource configuration to desired values.
|
||||
* \snippet qs_tcc_dma.c event_setup_3
|
||||
* -# Allocate and configure the resource using the configuration structure.
|
||||
* \snippet qs_tcc_dma.c event_setup_4
|
||||
* -# Attach a user to the resource.
|
||||
* \snippet qs_tcc_dma.c event_setup_5
|
||||
* \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_dma_capture Configure the DMA for Capture TCC Channel 1
|
||||
* Configure the DMAC module to obtain captured value from TCC channel 1.
|
||||
* -# Create a DMA resource instance.
|
||||
* \snippet qs_tcc_dma.c capture_dma_resource
|
||||
* \note This should never go out of scope as long as the resource is in
|
||||
* use. In most cases, this should be global.
|
||||
* -# Create a DMA resource configuration struct.
|
||||
* \snippet qs_tcc_dma.c dma_setup_1
|
||||
* -# Initialize the DMA resource configuration struct with default values.
|
||||
* \snippet qs_tcc_dma.c dma_setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
* -# Adjust the DMA resource configurations.
|
||||
* \snippet qs_tcc_dma.c dma_setup_3
|
||||
* -# Allocate a DMA resource with the configurations.
|
||||
* \snippet qs_tcc_dma.c dma_setup_4
|
||||
* -# Prepare DMA transfer descriptor.
|
||||
* -# Create a DMA transfer descriptor.
|
||||
* \snippet qs_tcc_dma.c capture_dma_descriptor
|
||||
* \note When multiple descriptors are linked, the linked item should
|
||||
* never go out of scope before it is loaded (to DMA Write-Back
|
||||
* memory section). In most cases, if more than one descriptors are
|
||||
* used, they should be global except the very first one.
|
||||
* -# Create a DMA transfer descriptor struct.
|
||||
* -# Create a DMA transfer descriptor configuration structure, which can be
|
||||
* filled out to adjust the configuration of a single DMA transfer.
|
||||
* \snippet qs_tcc_dma.c dma_setup_5
|
||||
* -# Initialize the DMA transfer descriptor configuration struct with
|
||||
* default values.
|
||||
* \snippet qs_tcc_dma.c dma_setup_6
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
* -# Adjust the DMA transfer descriptor configurations.
|
||||
* \snippet qs_tcc_dma.c dma_setup_7
|
||||
* -# Create the DMA transfer descriptor with the given configuration.
|
||||
* \snippet qs_tcc_dma.c dma_setup_8
|
||||
* -# Start DMA transfer job with prepared descriptor.
|
||||
* -# Add the DMA transfer descriptor to the allocated DMA resource.
|
||||
* \snippet qs_tcc_dma.c dma_setup_10
|
||||
* \note When adding multiple descriptors, the last one added is linked
|
||||
* at the end of the descriptor queue. If ringed list is needed,
|
||||
* just add the first descriptor again to build the circle.
|
||||
* -# Start the DMA transfer job with the allocated DMA resource and
|
||||
* transfer descriptor.
|
||||
* \snippet qs_tcc_dma.c dma_setup_11
|
||||
* \subsubsection asfdoc_sam0_tcc_dma_use_case_setup_flow_dma_compare Configure the DMA for Compare TCC Channel 0
|
||||
* Configure the DMAC module to update TCC channel 0 compare value.
|
||||
* The flow is similar to last DMA configure step for capture.
|
||||
* -# Allocate and configure the DMA resource.
|
||||
* \snippet qs_tcc_dma.c compare_dma_resource
|
||||
* \snippet qs_tcc_dma.c config_dma_resource_for_wave
|
||||
* -# Prepare DMA transfer descriptor.
|
||||
* \snippet qs_tcc_dma.c compare_dma_descriptor
|
||||
* \snippet qs_tcc_dma.c config_dma_descriptor_for_wave
|
||||
* -# Start DMA transfer job with prepared descriptor.
|
||||
* \snippet qs_tcc_dma.c config_dma_job_for_wave
|
||||
* -# Enable the TCC module to start the timer and begin PWM signal generation.
|
||||
* \snippet qs_tcc_dma.c setup_enable
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_dma_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_dma_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_tcc_dma.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_dma_use_case_main_flow Workflow
|
||||
* -# Enter an infinite loop while the PWM wave is generated via the TCC module.
|
||||
* \snippet qs_tcc_dma.c main_loop
|
||||
*/
|
||||
@ -0,0 +1,277 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM TCC - Timer Counter for Control Applications Callback Driver Quick Start (with Recoverable Fault)
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_tcc_faultn_use_case Quick Start Guide for TCC - Recoverable Fault
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAM D21/R21/L21/L22/DA1/C21/HA1G16A Xplained Pro
|
||||
*
|
||||
* In this use case, the TCC will be used to generate a PWM signal, with a
|
||||
* varying duty cycle. Here the pulse width is increased each time the timer
|
||||
* count matches the set compare value. There is a recoverable fault input
|
||||
* which controls PWM output. When this fault is active (low) the PWM output
|
||||
* will be frozen (could be off or on, no light changing).
|
||||
* When fault is released (input high) the PWM output will go on.
|
||||
*
|
||||
* When the PWM signal connects to LED, LED will light. If fault input is from
|
||||
* a button, the LED will be frozen and not changing it's light
|
||||
* when the button is down and will go on when the button is up.
|
||||
* To see the PWM waveform, you may need an oscilloscope.
|
||||
* SAMHA1G16A Xpro LED is PA00 which isn't connected out, use PA04 instead,
|
||||
* so we can't see LED blink but only see the waveform from oscilloscope.
|
||||
*
|
||||
* The PWM output and fault input is set up as follows:
|
||||
* <table>
|
||||
* <tr><th> Board </td><th> Pin </td><th> Connect to </td></tr>
|
||||
* <tr><td> SAM D21 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM D21 Xpro </td><td> PA15 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM R21 Xpro </td><td> PA06 </td><td> EXT1 Pin 3 </td></tr>
|
||||
* <tr><td> SAM R21 Xpro </td><td> PA28 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM L21 Xpro </td><td> PB10 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM L21 Xpro </td><td> PA16 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM L22 Xpro </td><td> PB18 </td><td> EXT3 Pin 9 </td></tr>
|
||||
* <tr><td> SAM L22 Xpro </td><td> PC01 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM DA1 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM DA1 Xpro </td><td> PA15 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM C21 Xpro </td><td> PA15 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM C21 Xpro </td><td> PA28 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM HA1G16A Xpro </td><td> PA04 </td><td> NULL </td></tr>
|
||||
* <tr><td> SAM HA1G16A Xpro </td><td> PB03 </td><td> SW0 </td></tr>
|
||||
* </table>
|
||||
*
|
||||
* The TCC module will be set up as follows:
|
||||
* - GCLK generator 0 (GCLK main) clock source
|
||||
* - Use double buffering write when set top, compare, or pattern through API
|
||||
* - No dithering on the counter or compare
|
||||
* - No prescaler
|
||||
* - Single Slope PWM wave generation
|
||||
* - GCLK reload action
|
||||
* - Don't run in standby
|
||||
* - No waveform extentions
|
||||
* - No inversion of waveform output
|
||||
* - No capture enabled
|
||||
* - Count upward
|
||||
* - Don't perform one-shot operations
|
||||
* - No event input except channel 0 event enabled
|
||||
* - No event action
|
||||
* - No event generation enabled
|
||||
* - Counter starts on 0
|
||||
* - Recoverable Fault A is generated from channel 0 event input, fault halt
|
||||
* acts as software halt, other actions or options are all disabled
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_faultn_use_case_setup Quick Start
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_faultn_use_case_prereq Prerequisites
|
||||
* There are no prerequisites for this use case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_faultn_use_case_setup_code Code
|
||||
*
|
||||
* Add to the main application source file, before any functions, according to
|
||||
* the kit used:
|
||||
* - SAM D21 Xplained Pro
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_faultn.h definition_pwm
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_faultn.h definition_fault
|
||||
* - SAM R21 Xplained Pro
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_faultn.h definition_pwm
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_faultn.h definition_fault
|
||||
* - SAM L21 Xplained Pro
|
||||
* \snippet saml21_xplained_pro/conf_quick_start_faultn.h definition_pwm
|
||||
* \snippet saml21_xplained_pro/conf_quick_start_faultn.h definition_fault
|
||||
* - SAM L22 Xplained Pro
|
||||
* \snippet saml22_xplained_pro/conf_quick_start_faultn.h definition_pwm
|
||||
* \snippet saml22_xplained_pro/conf_quick_start_faultn.h definition_fault
|
||||
* - SAM DA1 Xplained Pro
|
||||
* \snippet samda1_xplained_pro/conf_quick_start_faultn.h definition_pwm
|
||||
* \snippet samda1_xplained_pro/conf_quick_start_faultn.h definition_fault
|
||||
* - SAM C21 Xplained Pro
|
||||
* \snippet samc21_xplained_pro/conf_quick_start_faultx.h definition_pwm
|
||||
* \snippet samc21_xplained_pro/conf_quick_start_faultx.h definition_fault
|
||||
* - SAM HA1G16A Xplained Pro:
|
||||
* \snippet samha1g16a_xplained_pro/conf_quick_start_faultx.h definition_pwm
|
||||
* \snippet samha1g16a_xplained_pro/conf_quick_start_faultx.h definition_fault
|
||||
*
|
||||
* Add to the main application source file, before any functions:
|
||||
* \snippet qs_tcc_faultn.c additional_include
|
||||
*
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_tcc_faultn.c module_inst
|
||||
* \snippet qs_tcc_faultn.c events_resource
|
||||
*
|
||||
* Copy-paste the following callback function code to your user application:
|
||||
* \snippet qs_tcc_faultn.c callback_funcs
|
||||
* \snippet qs_tcc_faultn.c callback_eic
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_tcc_faultn.c setup
|
||||
* \snippet qs_tcc_faultn.c config_eic
|
||||
* \snippet qs_tcc_faultn.c config_event
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_tcc_faultn.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_faultn_use_case_setup_flow Workflow
|
||||
* \subsubsection asfdoc_sam0_tcc_faultn_use_case_setup_flow_tcc Configure TCC
|
||||
* -# Create a module software instance struct for the TCC module to store
|
||||
* the TCC driver state while it is in use.
|
||||
* \snippet qs_tcc_faultn.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Create a TCC module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical TCC peripheral.
|
||||
* \snippet qs_tcc_faultn.c setup_config
|
||||
* -# Initialize the TCC configuration struct with the module's default values.
|
||||
* \snippet qs_tcc_faultn.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Alter the TCC settings to configure the counter width, wave generation
|
||||
* mode, and the compare channel 0 value and fault options. Here the
|
||||
* Recoverable Fault input is enabled and halt action is set to
|
||||
* software mode (must use software to clear halt state).
|
||||
* \snippet qs_tcc_faultn.c setup_change_config
|
||||
* \snippet qs_tcc_faultn.c setup_change_config_faults
|
||||
* -# Alter the TCC settings to configure the PWM output on a physical device
|
||||
* pin.
|
||||
* \snippet qs_tcc_faultn.c setup_change_config_pwm
|
||||
* -# Configure the TCC module with the desired settings.
|
||||
* \snippet qs_tcc_faultn.c setup_set_config
|
||||
*
|
||||
* -# Create a TCC events configuration struct, which can be filled out to
|
||||
* enable/disable events and configure event settings. Reset all fields
|
||||
* to zero.
|
||||
* \snippet qs_tcc_faultn.c setup_events
|
||||
* -# Alter the TCC events settings to enable/disable desired events, to
|
||||
* change event generating options and modify event actions. Here channel
|
||||
* event 0 input is enabled as source of recoverable fault.
|
||||
* \snippet qs_tcc_faultn.c setup_change_events_faults
|
||||
* -# Enable and apply events settings.
|
||||
* \snippet qs_tcc_faultn.c setup_events_enable
|
||||
*
|
||||
* -# Enable the TCC module to start the timer and begin PWM signal generation.
|
||||
* \snippet qs_tcc_faultn.c setup_enable
|
||||
*
|
||||
* -# Register the Compare Channel 0 Match callback functions with the driver.
|
||||
* \snippet qs_tcc_faultn.c setup_register_callback
|
||||
* -# Enable the Compare Channel 0 Match callback so that it will be called by
|
||||
* the driver when appropriate.
|
||||
* \snippet qs_tcc_faultn.c setup_enable_callback
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_tcc_faultn_use_case_setup_flow_eic Configure EXTINT for fault input
|
||||
* -# Create an EXTINT module channel configuration struct, which can be filled
|
||||
* out to adjust the configuration of a single external interrupt channel.
|
||||
* \snippet qs_tcc_faultn.c eic_setup_1
|
||||
* -# Initialize the channel configuration struct with the module's default
|
||||
* values.
|
||||
* \snippet qs_tcc_faultn.c eic_setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Adjust the configuration struct to configure the pin MUX (to route the
|
||||
* desired physical pin to the logical channel) to the board button, and to
|
||||
* configure the channel to detect both rising and falling edges.
|
||||
* \snippet qs_tcc_faultn.c eic_setup_3
|
||||
* -# Configure external interrupt channel with the desired channel settings.
|
||||
* \snippet qs_tcc_faultn.c eic_setup_4
|
||||
*
|
||||
* -# Create a TXTINT events configuration struct, which can be filled out to
|
||||
* enable/disable events. Reset all fields to zero.
|
||||
* \snippet qs_tcc_faultn.c eic_event_setup_1
|
||||
* -# Adjust the configuration struct, set the channels to be enabled to
|
||||
* \c true. Here the channel to the board button is used.
|
||||
* \snippet qs_tcc_faultn.c eic_event_setup_2
|
||||
* -# Enable the events.
|
||||
* \snippet qs_tcc_faultn.c eic_event_setup_3
|
||||
*
|
||||
* -# Define the EXTINT callback that will be fired when a detection event
|
||||
* occurs. For this example, when fault line is released, the TCC fault
|
||||
* state is cleared to go on PWM generating.
|
||||
* \snippet qs_tcc_faultn.c callback_eic
|
||||
* -# Register a callback function \c eic_callback_to_clear_halt() to handle
|
||||
* detections from the External Interrupt Controller (EIC).
|
||||
* \snippet qs_tcc_faultn.c eic_callback_setup_1
|
||||
* -# Enable the registered callback function for the configured External
|
||||
* Interrupt channel, so that it will be called by the module when the
|
||||
* channel detects an edge.
|
||||
* \snippet qs_tcc_faultn.c eic_callback_setup_2
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_tcc_faultn_use_case_setup_flow_evt Configure EVENTS for fault input
|
||||
* -# Create an event resource instance struct for the EVENTS module to store.
|
||||
* \snippet qs_tcc_faultn.c events_resource
|
||||
* \note This should never go out of scope as long as the resource is in use.
|
||||
* In most cases, this should be global.
|
||||
* -# Create an event channel configuration struct, which can be filled out to
|
||||
* adjust the configuration of a single event channel.
|
||||
* \snippet qs_tcc_faultn.c event_setup_1
|
||||
* -# Initialize the event channel configuration struct with the module's
|
||||
* default values.
|
||||
* \snippet qs_tcc_faultn.c event_setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Adjust the configuration struct to request that the channel will be attached
|
||||
* to the specified event generator, and that the asynchronous event path will
|
||||
* be used. Here the EIC channel connected to board button is the event
|
||||
* generator.
|
||||
* \snippet qs_tcc_faultn.c event_setup_3
|
||||
* -# Allocate and configure the channel using the configuration structure.
|
||||
* \snippet qs_tcc_faultn.c event_setup_4
|
||||
* \note The existing configuration struct may be re-used, as long as any
|
||||
* values that have been altered from the default settings are taken
|
||||
* into account by the user application.
|
||||
*
|
||||
* -# Attach a user to the channel. Here the user is TCC channel 0 event,
|
||||
* which has been configured as input of Recoverable Fault.
|
||||
* \snippet qs_tcc_faultn.c event_setup_5
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_faultn_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_faultn_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_tcc_callback.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_faultn_use_case_main_flow Workflow
|
||||
* -# Enter an infinite loop while the PWM wave is generated via the TCC module.
|
||||
* \snippet qs_tcc_callback.c main_loop
|
||||
*/
|
||||
|
||||
|
||||
#include <asf.h>
|
||||
#include <conf_clocks.h>
|
||||
@ -0,0 +1,273 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM TCC - Timer Counter for Control Applications Callback Driver Quick Start (with Non-Recoverable Fault)
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_tcc_faultx_use_case Quick Start Guide for TCC - Non-Recoverable Fault
|
||||
*
|
||||
* The supported kit list:
|
||||
* - SAM D21/R21/L21/L22/DA1/C21/HA1G16A Xplained Pro
|
||||
*
|
||||
* In this use case, the TCC will be used to generate a PWM signal, with a
|
||||
* varying duty cycle. Here the pulse width is increased each time the timer
|
||||
* count matches the set compare value. There is a non-recoverable fault input
|
||||
* which controls PWM output. When this fault is active (low) the PWM output
|
||||
* will be forced to be high. When fault is released (input high) the PWM
|
||||
* output will go on.
|
||||
*
|
||||
* When the PWM signal connects to LED, LED will light. If fault input is from
|
||||
* a button, the LED will be off when the button is down and on when the button
|
||||
* is up. To see the PWM waveform, you may need an oscilloscope.
|
||||
*
|
||||
* SAMHA1G16A Xpro LED is PA00 which isn't connected out, use PA04 instead,
|
||||
* so we can't see LED blink but only see the waveform from oscilloscope.
|
||||
|
||||
* The PWM output and fault input is set up as follows:
|
||||
* <table>
|
||||
* <tr><th> Board </td><th> Pin </td><th> Connect to </td></tr>
|
||||
* <tr><td> SAM D21 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM D21 Xpro </td><td> PA15 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM R21 Xpro </td><td> PA19 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM R21 Xpro </td><td> PA28 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM L21 Xpro </td><td> PB10 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM L21 Xpro </td><td> PA16 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM L22 Xpro </td><td> PC27 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM L22 Xpro </td><td> PC01 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM DA1 Xpro </td><td> PB30 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM DA1 Xpro </td><td> PA15 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM C21 Xpro </td><td> PA15 </td><td> LED0 </td></tr>
|
||||
* <tr><td> SAM C21 Xpro </td><td> PA28 </td><td> SW0 </td></tr>
|
||||
* <tr><td> SAM HA1G16A Xpro </td><td> PA04 </td><td> NULL </td></tr>
|
||||
* <tr><td> SAM HA1G16A Xpro </td><td> PB03 </td><td> SW0 </td></tr>
|
||||
* </table>
|
||||
*
|
||||
* The TCC module will be set up as follows:
|
||||
* - GCLK generator 0 (GCLK main) clock source
|
||||
* - Use double buffering write when set top, compare, or pattern through API
|
||||
* - No dithering on the counter or compare
|
||||
* - No prescaler
|
||||
* - Single Slope PWM wave generation
|
||||
* - GCLK reload action
|
||||
* - Don't run in standby
|
||||
* - No waveform extentions
|
||||
* - No inversion of waveform output
|
||||
* - No capture enabled
|
||||
* - Count upward
|
||||
* - Don't perform one-shot operations
|
||||
* - No event input except TCC event0 enabled
|
||||
* - No event action except TCC event0 acts as Non-Recoverable Fault
|
||||
* - No event generation enabled
|
||||
* - Counter starts on 0
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_faultx_use_case_setup Quick Start
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_faultx_use_case_prereq Prerequisites
|
||||
* There are no prerequisites for this use case.
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_faultx_use_case_setup_code Code
|
||||
*
|
||||
* Add to the main application source file, before any functions:
|
||||
* - SAM D21 Xplained Pro
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_faultx.h definition_pwm
|
||||
* \snippet samd21_xplained_pro/conf_quick_start_faultx.h definition_fault
|
||||
* - SAM R21 Xplained Pro
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_faultx.h definition_pwm
|
||||
* \snippet samr21_xplained_pro/conf_quick_start_faultx.h definition_fault
|
||||
* - SAM L21 Xplained Pro
|
||||
* \snippet saml21_xplained_pro/conf_quick_start_faultx.h definition_pwm
|
||||
* \snippet saml21_xplained_pro/conf_quick_start_faultx.h definition_fault
|
||||
* - SAM L22 Xplained Pro
|
||||
* \snippet saml22_xplained_pro/conf_quick_start_faultx.h definition_pwm
|
||||
* \snippet saml22_xplained_pro/conf_quick_start_faultx.h definition_fault
|
||||
* - SAM DA1 Xplained Pro
|
||||
* \snippet samda1_xplained_pro/conf_quick_start_faultx.h definition_pwm
|
||||
* \snippet samda1_xplained_pro/conf_quick_start_faultx.h definition_fault
|
||||
* - SAM C21 Xplained Pro
|
||||
* \snippet samc21_xplained_pro/conf_quick_start_faultx.h definition_pwm
|
||||
* \snippet samc21_xplained_pro/conf_quick_start_faultx.h definition_fault
|
||||
* - SAM HA1G16A Xplained Pro:
|
||||
* \snippet samha1g16a_xplained_pro/conf_quick_start_faultx.h definition_pwm
|
||||
* \snippet samha1g16a_xplained_pro/conf_quick_start_faultx.h definition_fault
|
||||
*
|
||||
* Add to the main application source file, before any functions:
|
||||
* \snippet qs_tcc_faultx.c additional_include
|
||||
*
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_tcc_faultx.c module_inst
|
||||
* \snippet qs_tcc_faultx.c events_resource
|
||||
*
|
||||
* Copy-paste the following callback function code to your user application:
|
||||
* \snippet qs_tcc_faultx.c callback_funcs
|
||||
* \snippet qs_tcc_faultx.c callback_eic
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_tcc_faultx.c setup
|
||||
* \snippet qs_tcc_faultx.c config_eic
|
||||
* \snippet qs_tcc_faultx.c config_event
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_tcc_faultx.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_faultx_use_case_setup_flow Workflow
|
||||
* \subsubsection asfdoc_sam0_tcc_faultx_use_case_setup_flow_tcc Configure TCC
|
||||
* -# Create a module software instance struct for the TCC module to store
|
||||
* the TCC driver state while it is in use.
|
||||
* \snippet qs_tcc_faultx.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Create a TCC module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical TCC peripheral.
|
||||
* \snippet qs_tcc_faultx.c setup_config
|
||||
* -# Initialize the TCC configuration struct with the module's default values.
|
||||
* \snippet qs_tcc_faultx.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Alter the TCC settings to configure the counter width, wave generation
|
||||
* mode, and the compare channel 0 value and fault options. Here the
|
||||
* Non-Recoverable Fault output is enabled and set to high level (1).
|
||||
* \snippet qs_tcc_faultx.c setup_change_config
|
||||
* \snippet qs_tcc_faultx.c setup_change_config_faults
|
||||
* -# Alter the TCC settings to configure the PWM output on a physical device
|
||||
* pin.
|
||||
* \snippet qs_tcc_faultx.c setup_change_config_pwm
|
||||
* -# Configure the TCC module with the desired settings.
|
||||
* \snippet qs_tcc_faultx.c setup_set_config
|
||||
*
|
||||
* -# Create a TCC events configuration struct, which can be filled out to
|
||||
* enable/disable events and configure event settings. Reset all fields
|
||||
* to zero.
|
||||
* \snippet qs_tcc_faultx.c setup_events
|
||||
* -# Alter the TCC events settings to enable/disable desired events, to
|
||||
* change event generating options and modify event actions. Here TCC
|
||||
* event0 will act as Non-Recoverable Fault input.
|
||||
* \snippet qs_tcc_faultx.c setup_change_events_faults
|
||||
* -# Enable and apply events settings.
|
||||
* \snippet qs_tcc_faultx.c setup_events_enable
|
||||
*
|
||||
* -# Enable the TCC module to start the timer and begin PWM signal generation.
|
||||
* \snippet qs_tcc_faultx.c setup_enable
|
||||
*
|
||||
* -# Register the Compare Channel 0 Match callback functions with the driver.
|
||||
* \snippet qs_tcc_faultx.c setup_register_callback
|
||||
* -# Enable the Compare Channel 0 Match callback so that it will be called by
|
||||
* the driver when appropriate.
|
||||
* \snippet qs_tcc_faultx.c setup_enable_callback
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_tcc_faultx_use_case_setup_flow_eic Configure EXTINT for fault input
|
||||
* -# Create an EXTINT module channel configuration struct, which can be filled
|
||||
* out to adjust the configuration of a single external interrupt channel.
|
||||
* \snippet qs_tcc_faultx.c eic_setup_1
|
||||
* -# Initialize the channel configuration struct with the module's default
|
||||
* values.
|
||||
* \snippet qs_tcc_faultx.c eic_setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Adjust the configuration struct to configure the pin MUX (to route the
|
||||
* desired physical pin to the logical channel) to the board button, and to
|
||||
* configure the channel to detect both rising and falling edges.
|
||||
* \snippet qs_tcc_faultx.c eic_setup_3
|
||||
* -# Configure external interrupt channel with the desired channel settings.
|
||||
* \snippet qs_tcc_faultx.c eic_setup_4
|
||||
*
|
||||
* -# Create a TXTINT events configuration struct, which can be filled out to
|
||||
* enable/disable events. Reset all fields to zero.
|
||||
* \snippet qs_tcc_faultx.c eic_event_setup_1
|
||||
* -# Adjust the configuration struct, set the channels to be enabled to
|
||||
* \c true. Here the channel to the board button is used.
|
||||
* \snippet qs_tcc_faultx.c eic_event_setup_2
|
||||
* -# Enable the events.
|
||||
* \snippet qs_tcc_faultx.c eic_event_setup_3
|
||||
*
|
||||
* -# Define the EXTINT callback that will be fired when a detection event
|
||||
* occurs. For this example, when fault line is released, the TCC fault
|
||||
* state is cleared to go on PWM generating.
|
||||
* \snippet qs_tcc_faultx.c callback_eic
|
||||
* -# Register a callback function \c eic_callback_to_clear_halt() to handle
|
||||
* detections from the External Interrupt Controller (EIC).
|
||||
* \snippet qs_tcc_faultx.c eic_callback_setup_1
|
||||
* -# Enable the registered callback function for the configured External
|
||||
* Interrupt channel, so that it will be called by the module when the
|
||||
* channel detects an edge.
|
||||
* \snippet qs_tcc_faultx.c eic_callback_setup_2
|
||||
*
|
||||
* \subsubsection asfdoc_sam0_tcc_faultx_use_case_setup_flow_evt Configure EVENTS for fault input
|
||||
* -# Create an event resource instance struct for the EVENTS module to store.
|
||||
* \snippet qs_tcc_faultx.c events_resource
|
||||
* \note This should never go out of scope as long as the resource is in use.
|
||||
* In most cases, this should be global.
|
||||
* -# Create an event channel configuration struct, which can be filled out to
|
||||
* adjust the configuration of a single event channel.
|
||||
* \snippet qs_tcc_faultx.c event_setup_1
|
||||
* -# Initialize the event channel configuration struct with the module's
|
||||
* default values.
|
||||
* \snippet qs_tcc_faultx.c event_setup_2
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Adjust the configuration struct to request that the channel will be attached
|
||||
* to the specified event generator, and that the asynchronous event path will
|
||||
* be used. Here the EIC channel connected to board button is the event
|
||||
* generator.
|
||||
* \snippet qs_tcc_faultx.c event_setup_3
|
||||
* -# Allocate and configure the channel using the configuration structure.
|
||||
* \snippet qs_tcc_faultx.c event_setup_4
|
||||
* \note The existing configuration struct may be re-used, as long as any
|
||||
* values that have been altered from the default settings are taken
|
||||
* into account by the user application.
|
||||
*
|
||||
* -# Attach a user to the channel. Here the user is TCC event0, which has been
|
||||
* configured as input of Non-Recoverable Fault.
|
||||
* \snippet qs_tcc_faultx.c event_setup_5
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_faultx_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_faultx_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_tcc_callback.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_faultx_use_case_main_flow Workflow
|
||||
* -# Enter an infinite loop while the PWM wave is generated via the TCC module.
|
||||
* \snippet qs_tcc_callback.c main_loop
|
||||
*/
|
||||
|
||||
|
||||
#include <asf.h>
|
||||
#include <conf_clocks.h>
|
||||
@ -0,0 +1,137 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM TCC - Timer Counter for Control Applications Driver Quick Start
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \page asfdoc_sam0_tcc_timer_use_case Quick Start Guide for TCC - Timer
|
||||
*
|
||||
* The supported board list:
|
||||
* - SAM D21/R21/L21/L22/DA1/C21/HA1G16A Xplained Pro
|
||||
* - SAM D11 Xplained Pro
|
||||
*
|
||||
* In this use case, the TCC will be used as a timer, to generate overflow and
|
||||
* compare match callbacks. In the callbacks the on-board LED is toggled.
|
||||
*
|
||||
* The TCC module will be set up as follows:
|
||||
* - GCLK generator 1 (GCLK 32K) clock source
|
||||
* - Use double buffering write when set top, compare, or pattern through API
|
||||
* - No dithering on the counter or compare
|
||||
* - Prescaler is divided by 64
|
||||
* - GCLK reload action
|
||||
* - Count upward
|
||||
* - Don't run in standby
|
||||
* - No waveform outputs
|
||||
* - No capture enabled
|
||||
* - Don't perform one-shot operations
|
||||
* - No event input enabled
|
||||
* - No event action
|
||||
* - No event generation enabled
|
||||
* - Counter starts on 0
|
||||
* - Counter top set to 2000 (about 4s) and generate overflow callback
|
||||
* - Channel 0 is set to compare and match value 900 and generate callback
|
||||
* - Channel 1 is set to compare and match value 930 and generate callback
|
||||
* - Channel 2 is set to compare and match value 1100 and generate callback
|
||||
* - Channel 3 is set to compare and match value 1250 and generate callback
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_timer_use_case_setup Quick Start
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_timer_use_case_prereq Prerequisites
|
||||
* For this use case, XOSC32K/OSC32K should be enabled and available through GCLK
|
||||
* generator 1 clock source selection. Within Atmel Software Framework (ASF)
|
||||
* it can be done through modifying <i>conf_clocks.h</i>.
|
||||
* See \ref asfdoc_sam0_system_clock_group "System Clock Management Driver" for
|
||||
* more details about clock configuration.
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_timer_use_case_setup_code Code
|
||||
*
|
||||
* Add to the main application source file, outside of any functions:
|
||||
* \snippet qs_tcc_timer.c module_inst
|
||||
*
|
||||
* Copy-paste the following callback function code to your user application:
|
||||
* \snippet qs_tcc_timer.c callback_funcs
|
||||
*
|
||||
* Copy-paste the following setup code to your user application:
|
||||
* \snippet qs_tcc_timer.c setup
|
||||
*
|
||||
* Add to user application initialization (typically the start of \c main()):
|
||||
* \snippet qs_tcc_timer.c setup_init
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_timer_use_case_setup_flow Workflow
|
||||
* -# Create a module software instance structure for the TCC module to store
|
||||
* the TCC driver state while it is in use.
|
||||
* \snippet qs_tcc_timer.c module_inst
|
||||
* \note This should never go out of scope as long as the module is in use.
|
||||
* In most cases, this should be global.
|
||||
*
|
||||
* -# Configure the TCC module.
|
||||
* -# Create a TCC module configuration struct, which can be filled out to
|
||||
* adjust the configuration of a physical TCC peripheral.
|
||||
* \snippet qs_tcc_timer.c setup_config
|
||||
* -# Initialize the TCC configuration struct with the module's default values.
|
||||
* \snippet qs_tcc_timer.c setup_config_defaults
|
||||
* \note This should always be performed before using the configuration
|
||||
* struct to ensure that all values are initialized to known default
|
||||
* settings.
|
||||
*
|
||||
* -# Alter the TCC settings to configure the GCLK source, prescaler, period,
|
||||
* and compare channel values.
|
||||
* \snippet qs_tcc_timer.c setup_change_config
|
||||
* -# Configure the TCC module with the desired settings.
|
||||
* \snippet qs_tcc_timer.c setup_set_config
|
||||
* -# Enable the TCC module to start the timer.
|
||||
* \snippet qs_tcc_timer.c setup_enable
|
||||
* -# Configure the TCC callbacks.
|
||||
* -# Register the Overflow and Compare Channel Match callback functions with
|
||||
* the driver.
|
||||
* \snippet qs_tcc_timer.c setup_register_callback
|
||||
* -# Enable the Overflow and Compare Channel Match callbacks so that it will
|
||||
* be called by the driver when appropriate.
|
||||
* \snippet qs_tcc_timer.c setup_enable_callback
|
||||
*
|
||||
*
|
||||
* \section asfdoc_sam0_tcc_timer_use_case_main Use Case
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_timer_use_case_main_code Code
|
||||
* Copy-paste the following code to your user application:
|
||||
* \snippet qs_tcc_timer.c main
|
||||
*
|
||||
* \subsection asfdoc_sam0_tcc_timer_use_case_main_flow Workflow
|
||||
* -# Enter an infinite loop while the timer is running.
|
||||
* \snippet qs_tcc_timer.c main_loop
|
||||
*/
|
||||
|
||||
|
||||
#include <asf.h>
|
||||
#include <conf_clocks.h>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,235 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM TCC - Timer Counter for Control Applications Callback Driver
|
||||
*
|
||||
* Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#include "tcc_callback.h"
|
||||
|
||||
void *_tcc_instances[TCC_INST_NUM];
|
||||
|
||||
void _tcc_interrupt_handler(uint8_t module_index);
|
||||
|
||||
const uint32_t _tcc_intflag[TCC_CALLBACK_N] = {
|
||||
TCC_INTFLAG_OVF,
|
||||
TCC_INTFLAG_TRG,
|
||||
TCC_INTFLAG_CNT,
|
||||
TCC_INTFLAG_ERR,
|
||||
TCC_INTFLAG_FAULTA,
|
||||
TCC_INTFLAG_FAULTB,
|
||||
TCC_INTFLAG_FAULT0,
|
||||
TCC_INTFLAG_FAULT1,
|
||||
#define _TCC_INTFLAG_MC(n,dummy) TCC_INTFLAG_MC##n,
|
||||
/* TCC_INTFLAG_MC0 ~ ... */
|
||||
MREPEAT(TCC_NUM_CHANNELS, _TCC_INTFLAG_MC, 0)
|
||||
#undef _TCC_INTFLAG_MC
|
||||
};
|
||||
|
||||
# define _TCC_INTERRUPT_VECT_NUM(n, unused) \
|
||||
SYSTEM_INTERRUPT_MODULE_TCC##n,
|
||||
/**
|
||||
* \internal Get the interrupt vector for the given device instance
|
||||
*
|
||||
* \param[in] The TCC module instance number
|
||||
*
|
||||
* \return Interrupt vector for of the given TCC module instance.
|
||||
*/
|
||||
static enum system_interrupt_vector _tcc_interrupt_get_interrupt_vector(
|
||||
uint32_t inst_num)
|
||||
{
|
||||
static uint8_t tcc_interrupt_vectors[TCC_INST_NUM] = {
|
||||
MREPEAT(TCC_INST_NUM, _TCC_INTERRUPT_VECT_NUM, 0)
|
||||
};
|
||||
|
||||
return (enum system_interrupt_vector)tcc_interrupt_vectors[inst_num];
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Registers a callback
|
||||
*
|
||||
* Registers a callback function which is implemented by the user.
|
||||
*
|
||||
* \note The callback must be enabled by \ref tcc_enable_callback,
|
||||
* in order for the interrupt handler to call it when the conditions for the
|
||||
* callback type is met.
|
||||
*
|
||||
* \param[in] module Pointer to TCC software instance struct
|
||||
* \param[in] callback_func Pointer to callback function
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*/
|
||||
enum status_code tcc_register_callback(
|
||||
struct tcc_module *const module,
|
||||
tcc_callback_t callback_func,
|
||||
const enum tcc_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(callback_func);
|
||||
|
||||
/* Register callback function */
|
||||
module->callback[callback_type] = callback_func;
|
||||
|
||||
/* Set the bit corresponding to the callback_type */
|
||||
module->register_callback_mask |= _tcc_intflag[callback_type];
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Unregisters a callback
|
||||
*
|
||||
* Unregisters a callback function implemented by the user. The callback should
|
||||
* be disabled before it is unregistered.
|
||||
*
|
||||
* \param[in] module Pointer to TCC software instance struct
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*/
|
||||
enum status_code tcc_unregister_callback(
|
||||
struct tcc_module *const module,
|
||||
const enum tcc_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
|
||||
/* Unregister callback function */
|
||||
module->callback[callback_type] = NULL;
|
||||
|
||||
/* Clear the bit corresponding to the callback_type */
|
||||
module->register_callback_mask &= ~_tcc_intflag[callback_type];
|
||||
|
||||
return STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enables callback
|
||||
*
|
||||
* Enables the callback function registered by the \ref
|
||||
* tcc_register_callback. The callback function will be called from the
|
||||
* interrupt handler when the conditions for the callback type are
|
||||
* met. This function will also enable the appropriate interrupts.
|
||||
*
|
||||
* \param[in] module Pointer to TCC software instance struct
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*/
|
||||
void tcc_enable_callback(
|
||||
struct tcc_module *const module,
|
||||
const enum tcc_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(module->hw);
|
||||
|
||||
/* Enable interrupts for this TCC module */
|
||||
system_interrupt_enable(_tcc_interrupt_get_interrupt_vector(
|
||||
_tcc_get_inst_index(module->hw)));
|
||||
|
||||
/* Enable channel or other callbacks */
|
||||
module->enable_callback_mask |= _tcc_intflag[callback_type];
|
||||
module->hw->INTENSET.reg = _tcc_intflag[callback_type];
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disables callback
|
||||
*
|
||||
* Disables the callback function registered by the \ref
|
||||
* tcc_register_callback, and the callback will not be called from the
|
||||
* interrupt routine. The function will also disable the appropriate
|
||||
* interrupts.
|
||||
*
|
||||
* \param[in] module Pointer to TCC software instance struct
|
||||
* \param[in] callback_type Callback type given by an enum
|
||||
*/
|
||||
void tcc_disable_callback(
|
||||
struct tcc_module *const module,
|
||||
const enum tcc_callback callback_type)
|
||||
{
|
||||
/* Sanity check arguments */
|
||||
Assert(module);
|
||||
Assert(module->hw);
|
||||
|
||||
/* Disable interrupts for this TCC module */
|
||||
system_interrupt_disable(_tcc_interrupt_get_interrupt_vector(
|
||||
_tcc_get_inst_index(module->hw)));
|
||||
|
||||
/* Disable channel or other callbacks */
|
||||
module->enable_callback_mask &= ~_tcc_intflag[callback_type];
|
||||
module->hw->INTENCLR.reg = _tcc_intflag[callback_type];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \internal ISR handler for TCC
|
||||
*
|
||||
* Auto-generate a set of interrupt handlers for each TCC in the device.
|
||||
*/
|
||||
#define _TCC_INTERRUPT_HANDLER(n, m) \
|
||||
void TCC##n##_Handler(void) \
|
||||
{ \
|
||||
_tcc_interrupt_handler(n); \
|
||||
}
|
||||
|
||||
MREPEAT(TCC_INST_NUM, _TCC_INTERRUPT_HANDLER, 0)
|
||||
|
||||
/**
|
||||
* \internal Interrupt handler for the TCC module
|
||||
*
|
||||
* Handles interrupts as they occur, it will run the callback functions
|
||||
* that are registered and enabled.
|
||||
*
|
||||
* \param[in] module_index ID of the TCC instance calling the interrupt
|
||||
* handler
|
||||
*/
|
||||
void _tcc_interrupt_handler(
|
||||
uint8_t module_index)
|
||||
{
|
||||
int i;
|
||||
|
||||
uint32_t interrupt_and_callback_status_mask;
|
||||
|
||||
struct tcc_module *module =
|
||||
(struct tcc_module *)_tcc_instances[module_index];
|
||||
|
||||
interrupt_and_callback_status_mask = (module->hw->INTFLAG.reg &
|
||||
module->register_callback_mask &
|
||||
module->enable_callback_mask);
|
||||
|
||||
/* Check if callback interrupt has occured */
|
||||
for (i = 0; i < TCC_CALLBACK_N; i ++) {
|
||||
if (interrupt_and_callback_status_mask & _tcc_intflag[i]) {
|
||||
/* Invoke the registered and enabled callback function */
|
||||
(module->callback[i])(module);
|
||||
/* Clear interrupt flag */
|
||||
module->hw->INTFLAG.reg = _tcc_intflag[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,83 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief SAM TCC - Timer Counter for Control Applications Callback Driver
|
||||
*
|
||||
* Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
|
||||
#ifndef TCC_CALLBACK_H_INCLUDED
|
||||
#define TCC_CALLBACK_H_INCLUDED
|
||||
|
||||
#include "tcc.h"
|
||||
#include <system_interrupt.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern void *_tcc_instances[TCC_INST_NUM];
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* \name Callback Management
|
||||
* {@
|
||||
*/
|
||||
|
||||
enum status_code tcc_register_callback(
|
||||
struct tcc_module *const module,
|
||||
tcc_callback_t callback_func,
|
||||
const enum tcc_callback callback_type);
|
||||
|
||||
enum status_code tcc_unregister_callback(
|
||||
struct tcc_module *const module,
|
||||
const enum tcc_callback callback_type);
|
||||
|
||||
void tcc_enable_callback(
|
||||
struct tcc_module *const module,
|
||||
const enum tcc_callback callback_type);
|
||||
|
||||
void tcc_disable_callback(
|
||||
struct tcc_module *const module,
|
||||
const enum tcc_callback callback_type);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* TCC_CALLBACK_H_INCLUDED */
|
||||
@ -0,0 +1,549 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for AC
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_AC_COMPONENT_
|
||||
#define _SAMD21_AC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR AC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_AC Analog Comparators */
|
||||
/*@{*/
|
||||
|
||||
#define AC_U2205
|
||||
#define REV_AC 0x112
|
||||
|
||||
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
|
||||
uint8_t :4; /*!< bit: 3.. 6 Reserved */
|
||||
uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_CTRLA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
|
||||
#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */
|
||||
|
||||
#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
|
||||
#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos)
|
||||
#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
|
||||
#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos)
|
||||
#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */
|
||||
#define AC_CTRLA_RUNSTDBY_Msk (0x1ul << AC_CTRLA_RUNSTDBY_Pos)
|
||||
#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos))
|
||||
#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */
|
||||
#define AC_CTRLA_LPMUX (0x1ul << AC_CTRLA_LPMUX_Pos)
|
||||
#define AC_CTRLA_MASK 0x87ul /**< \brief (AC_CTRLA) MASK Register */
|
||||
|
||||
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
|
||||
uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_CTRLB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
|
||||
#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */
|
||||
|
||||
#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
|
||||
#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos)
|
||||
#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
|
||||
#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos)
|
||||
#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
|
||||
#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos)
|
||||
#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
|
||||
#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */
|
||||
|
||||
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
|
||||
uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
|
||||
uint16_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
|
||||
uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
|
||||
uint16_t :6; /*!< bit: 10..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
|
||||
uint16_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
|
||||
uint16_t :6; /*!< bit: 10..15 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} AC_EVCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
|
||||
#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */
|
||||
|
||||
#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
|
||||
#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos)
|
||||
#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
|
||||
#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos)
|
||||
#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
|
||||
#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos)
|
||||
#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
|
||||
#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
|
||||
#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos)
|
||||
#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
|
||||
#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos)
|
||||
#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
|
||||
#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
|
||||
#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos)
|
||||
#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
|
||||
#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos)
|
||||
#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */
|
||||
#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos)
|
||||
#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
|
||||
#define AC_EVCTRL_MASK 0x0313ul /**< \brief (AC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
|
||||
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
|
||||
#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos)
|
||||
#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
|
||||
#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos)
|
||||
#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
|
||||
#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos)
|
||||
#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
|
||||
#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
|
||||
#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos)
|
||||
#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
|
||||
#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos)
|
||||
#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
|
||||
#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
|
||||
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
|
||||
#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
|
||||
#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos)
|
||||
#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
|
||||
#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos)
|
||||
#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
|
||||
#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos)
|
||||
#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
|
||||
#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
|
||||
#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos)
|
||||
#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
|
||||
#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos)
|
||||
#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
|
||||
#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
|
||||
__I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
|
||||
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
__I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
|
||||
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
__I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
|
||||
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
__I uint8_t WIN:1; /*!< bit: 4 Window x */
|
||||
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
|
||||
#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos)
|
||||
#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
|
||||
#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos)
|
||||
#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
|
||||
#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos)
|
||||
#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
|
||||
#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
|
||||
#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos)
|
||||
#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
|
||||
#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos)
|
||||
#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
|
||||
#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
|
||||
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_STATUSA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */
|
||||
#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */
|
||||
|
||||
#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
|
||||
#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos)
|
||||
#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
|
||||
#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos)
|
||||
#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
|
||||
#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos)
|
||||
#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
|
||||
#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
|
||||
#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos)
|
||||
#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
|
||||
#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */
|
||||
#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */
|
||||
#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */
|
||||
#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
|
||||
#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
|
||||
#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
|
||||
#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */
|
||||
|
||||
/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
|
||||
uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
|
||||
uint8_t :5; /*!< bit: 2.. 6 Reserved */
|
||||
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_STATUSB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */
|
||||
#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */
|
||||
|
||||
#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
|
||||
#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos)
|
||||
#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
|
||||
#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos)
|
||||
#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
|
||||
#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos)
|
||||
#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
|
||||
#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */
|
||||
#define AC_STATUSB_SYNCBUSY (0x1ul << AC_STATUSB_SYNCBUSY_Pos)
|
||||
#define AC_STATUSB_MASK 0x83ul /**< \brief (AC_STATUSB) MASK Register */
|
||||
|
||||
/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
|
||||
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_STATUSC_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */
|
||||
#define AC_STATUSC_RESETVALUE 0x00ul /**< \brief (AC_STATUSC reset_value) Status C */
|
||||
|
||||
#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */
|
||||
#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos)
|
||||
#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */
|
||||
#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos)
|
||||
#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */
|
||||
#define AC_STATUSC_STATE_Msk (0x3ul << AC_STATUSC_STATE_Pos)
|
||||
#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos))
|
||||
#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */
|
||||
#define AC_STATUSC_WSTATE0_Msk (0x3ul << AC_STATUSC_WSTATE0_Pos)
|
||||
#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos))
|
||||
#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSC) Signal is above window */
|
||||
#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSC) Signal is inside window */
|
||||
#define AC_STATUSC_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSC) Signal is below window */
|
||||
#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos)
|
||||
#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
|
||||
#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos)
|
||||
#define AC_STATUSC_MASK 0x33ul /**< \brief (AC_STATUSC) MASK Register */
|
||||
|
||||
/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
|
||||
uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_WINCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */
|
||||
#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */
|
||||
|
||||
#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
|
||||
#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
|
||||
#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
|
||||
#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */
|
||||
#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
|
||||
#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */
|
||||
#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
|
||||
#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
|
||||
#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */
|
||||
|
||||
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t ENABLE:1; /*!< bit: 0 Enable */
|
||||
uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
|
||||
uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
|
||||
uint32_t :1; /*!< bit: 4 Reserved */
|
||||
uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
|
||||
uint32_t :1; /*!< bit: 7 Reserved */
|
||||
uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
|
||||
uint32_t :1; /*!< bit: 11 Reserved */
|
||||
uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
|
||||
uint32_t :1; /*!< bit: 14 Reserved */
|
||||
uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
|
||||
uint32_t OUT:2; /*!< bit: 16..17 Output */
|
||||
uint32_t :1; /*!< bit: 18 Reserved */
|
||||
uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
|
||||
uint32_t :5; /*!< bit: 27..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AC_COMPCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
|
||||
#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
|
||||
|
||||
#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */
|
||||
#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos)
|
||||
#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
|
||||
#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos)
|
||||
#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */
|
||||
#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos)
|
||||
#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
|
||||
#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */
|
||||
#define AC_COMPCTRL_SPEED_HIGH_Val 0x1ul /**< \brief (AC_COMPCTRL) High speed */
|
||||
#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos)
|
||||
#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
|
||||
#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */
|
||||
#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
|
||||
#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
|
||||
#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
|
||||
#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
|
||||
#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
|
||||
#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
|
||||
#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
|
||||
#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */
|
||||
#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */
|
||||
#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */
|
||||
#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
|
||||
#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
|
||||
#define AC_COMPCTRL_MUXPOS_Msk (0x3ul << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
|
||||
#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
|
||||
#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos)
|
||||
#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */
|
||||
#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos)
|
||||
#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
|
||||
#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
|
||||
#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
|
||||
#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
|
||||
#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
|
||||
#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
|
||||
#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
|
||||
#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
|
||||
#define AC_COMPCTRL_HYST (0x1ul << AC_COMPCTRL_HYST_Pos)
|
||||
#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
|
||||
#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos)
|
||||
#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
|
||||
#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */
|
||||
#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
|
||||
#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
|
||||
#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
|
||||
#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
|
||||
#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
|
||||
#define AC_COMPCTRL_MASK 0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */
|
||||
|
||||
/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_SCALER_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */
|
||||
#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */
|
||||
|
||||
#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
|
||||
#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos)
|
||||
#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
|
||||
#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */
|
||||
|
||||
/** \brief AC hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
|
||||
__O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
|
||||
__IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
|
||||
__IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
|
||||
__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
|
||||
__IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
|
||||
RoReg8 Reserved1[0x1];
|
||||
__I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
|
||||
__I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
|
||||
__I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
|
||||
RoReg8 Reserved2[0x1];
|
||||
__IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
|
||||
RoReg8 Reserved3[0x3];
|
||||
__IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
|
||||
RoReg8 Reserved4[0x8];
|
||||
__IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
|
||||
} Ac;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_AC_COMPONENT_ */
|
||||
@ -0,0 +1,689 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for ADC
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_ADC_COMPONENT_
|
||||
#define _SAMD21_ADC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR ADC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_ADC Analog Digital Converter */
|
||||
/*@{*/
|
||||
|
||||
#define ADC_U2204
|
||||
#define REV_ADC 0x120
|
||||
|
||||
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_CTRLA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
|
||||
#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */
|
||||
|
||||
#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
|
||||
#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos)
|
||||
#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
|
||||
#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos)
|
||||
#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */
|
||||
#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos)
|
||||
#define ADC_CTRLA_MASK 0x07ul /**< \brief (ADC_CTRLA) MASK Register */
|
||||
|
||||
/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
|
||||
uint8_t :3; /*!< bit: 4.. 6 Reserved */
|
||||
uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_REFCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */
|
||||
#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */
|
||||
|
||||
#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
|
||||
#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
|
||||
#define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
|
||||
#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External reference */
|
||||
#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External reference */
|
||||
#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
|
||||
#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos)
|
||||
#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
|
||||
uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
|
||||
uint8_t :1; /*!< bit: 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_AVGCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */
|
||||
#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */
|
||||
|
||||
#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
|
||||
#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
|
||||
#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
|
||||
#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
|
||||
#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_SAMPCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
|
||||
#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
|
||||
|
||||
#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
|
||||
#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
|
||||
#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
|
||||
#define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
|
||||
uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
|
||||
uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
|
||||
uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
|
||||
uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
|
||||
uint16_t :5; /*!< bit: 11..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_CTRLB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */
|
||||
#define ADC_CTRLB_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLB reset_value) Control B */
|
||||
|
||||
#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */
|
||||
#define ADC_CTRLB_DIFFMODE (0x1ul << ADC_CTRLB_DIFFMODE_Pos)
|
||||
#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
|
||||
#define ADC_CTRLB_LEFTADJ (0x1ul << ADC_CTRLB_LEFTADJ_Pos)
|
||||
#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */
|
||||
#define ADC_CTRLB_FREERUN (0x1ul << ADC_CTRLB_FREERUN_Pos)
|
||||
#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
|
||||
#define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos)
|
||||
#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
|
||||
#define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
|
||||
#define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */
|
||||
#define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */
|
||||
#define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */
|
||||
#define ADC_CTRLB_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLB) 8-bit result */
|
||||
#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */
|
||||
#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos)
|
||||
#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
|
||||
#define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV32_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV64_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV128_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV256_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV512_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos)
|
||||
#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos)
|
||||
#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
|
||||
#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
|
||||
#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
|
||||
#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
|
||||
#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
|
||||
#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
|
||||
#define ADC_CTRLB_MASK 0x073Ful /**< \brief (ADC_CTRLB) MASK Register */
|
||||
|
||||
/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_WINCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
|
||||
#define ADC_WINCTRL_RESETVALUE 0x00ul /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
|
||||
|
||||
#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */
|
||||
#define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos)
|
||||
#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
|
||||
#define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */
|
||||
#define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
|
||||
#define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
|
||||
#define ADC_WINCTRL_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
|
||||
#define ADC_WINCTRL_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
|
||||
#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
|
||||
#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
|
||||
#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
|
||||
#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
|
||||
#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
|
||||
#define ADC_WINCTRL_MASK 0x07ul /**< \brief (ADC_WINCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
|
||||
uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_SWTRIG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */
|
||||
#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
|
||||
|
||||
#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
|
||||
#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos)
|
||||
#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */
|
||||
#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos)
|
||||
#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */
|
||||
|
||||
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
|
||||
uint32_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
|
||||
uint32_t :3; /*!< bit: 13..15 Reserved */
|
||||
uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
|
||||
uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
|
||||
uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} ADC_INPUTCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */
|
||||
#define ADC_INPUTCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
|
||||
|
||||
#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
|
||||
#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Reference */
|
||||
#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
|
||||
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
|
||||
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
|
||||
#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
|
||||
#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Internal Ground */
|
||||
#define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19ul /**< \brief (ADC_INPUTCTRL) I/O Ground */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
|
||||
#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
|
||||
#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
|
||||
#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
|
||||
#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
|
||||
#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
|
||||
#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
|
||||
#define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos)
|
||||
#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
|
||||
#define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */
|
||||
#define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */
|
||||
#define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */
|
||||
#define ADC_INPUTCTRL_GAIN_8X_Val 0x3ul /**< \brief (ADC_INPUTCTRL) 8x */
|
||||
#define ADC_INPUTCTRL_GAIN_16X_Val 0x4ul /**< \brief (ADC_INPUTCTRL) 16x */
|
||||
#define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFul /**< \brief (ADC_INPUTCTRL) 1/2x */
|
||||
#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos)
|
||||
#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos)
|
||||
#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos)
|
||||
#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos)
|
||||
#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos)
|
||||
#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos)
|
||||
#define ADC_INPUTCTRL_MASK 0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
|
||||
uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
|
||||
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_EVCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */
|
||||
#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */
|
||||
|
||||
#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */
|
||||
#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos)
|
||||
#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */
|
||||
#define ADC_EVCTRL_SYNCEI (0x1ul << ADC_EVCTRL_SYNCEI_Pos)
|
||||
#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
|
||||
#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos)
|
||||
#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
|
||||
#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos)
|
||||
#define ADC_EVCTRL_MASK 0x33ul /**< \brief (ADC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
|
||||
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
|
||||
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
|
||||
#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos)
|
||||
#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
|
||||
#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos)
|
||||
#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
|
||||
#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos)
|
||||
#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
|
||||
#define ADC_INTENCLR_SYNCRDY (0x1ul << ADC_INTENCLR_SYNCRDY_Pos)
|
||||
#define ADC_INTENCLR_MASK 0x0Ful /**< \brief (ADC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
|
||||
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
|
||||
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
|
||||
#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
|
||||
#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos)
|
||||
#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
|
||||
#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos)
|
||||
#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
|
||||
#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos)
|
||||
#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
|
||||
#define ADC_INTENSET_SYNCRDY (0x1ul << ADC_INTENSET_SYNCRDY_Pos)
|
||||
#define ADC_INTENSET_MASK 0x0Ful /**< \brief (ADC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
|
||||
__I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
|
||||
__I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
|
||||
__I uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */
|
||||
#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos)
|
||||
#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */
|
||||
#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos)
|
||||
#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */
|
||||
#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos)
|
||||
#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */
|
||||
#define ADC_INTFLAG_SYNCRDY (0x1ul << ADC_INTFLAG_SYNCRDY_Pos)
|
||||
#define ADC_INTFLAG_MASK 0x0Ful /**< \brief (ADC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
||||
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_STATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */
|
||||
#define ADC_STATUS_RESETVALUE 0x00ul /**< \brief (ADC_STATUS reset_value) Status */
|
||||
|
||||
#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */
|
||||
#define ADC_STATUS_SYNCBUSY (0x1ul << ADC_STATUS_SYNCBUSY_Pos)
|
||||
#define ADC_STATUS_MASK 0x80ul /**< \brief (ADC_STATUS) MASK Register */
|
||||
|
||||
/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_RESULT_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */
|
||||
#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */
|
||||
|
||||
#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
|
||||
#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos)
|
||||
#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
|
||||
#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */
|
||||
|
||||
/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_WINLT_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
|
||||
#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
|
||||
|
||||
#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
|
||||
#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos)
|
||||
#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
|
||||
#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */
|
||||
|
||||
/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_WINUT_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
|
||||
#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
|
||||
|
||||
#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
|
||||
#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos)
|
||||
#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
|
||||
#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */
|
||||
|
||||
/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
|
||||
uint16_t :4; /*!< bit: 12..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_GAINCORR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */
|
||||
#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
|
||||
|
||||
#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
|
||||
#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
|
||||
#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
|
||||
#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */
|
||||
|
||||
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
|
||||
uint16_t :4; /*!< bit: 12..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_OFFSETCORR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
|
||||
#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
|
||||
|
||||
#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
|
||||
#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
|
||||
#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
|
||||
#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */
|
||||
|
||||
/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
|
||||
uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
|
||||
uint16_t :5; /*!< bit: 11..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_CALIB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */
|
||||
#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */
|
||||
|
||||
#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */
|
||||
#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
|
||||
#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
|
||||
#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */
|
||||
#define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
|
||||
#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
|
||||
#define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */
|
||||
|
||||
/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_DBGCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */
|
||||
#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
|
||||
|
||||
#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
|
||||
#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos)
|
||||
#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */
|
||||
|
||||
/** \brief ADC hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
|
||||
__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
|
||||
__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
|
||||
__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
|
||||
__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
|
||||
RoReg8 Reserved1[0x2];
|
||||
__IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
|
||||
RoReg8 Reserved2[0x3];
|
||||
__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
|
||||
RoReg8 Reserved3[0x3];
|
||||
__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
|
||||
__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
|
||||
RoReg8 Reserved4[0x1];
|
||||
__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
|
||||
__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
|
||||
__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
|
||||
__I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
|
||||
__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
|
||||
__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
|
||||
RoReg8 Reserved5[0x2];
|
||||
__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
|
||||
RoReg8 Reserved6[0x2];
|
||||
__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
|
||||
__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
|
||||
__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
|
||||
__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
|
||||
} Adc;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_ADC_COMPONENT_ */
|
||||
@ -0,0 +1,276 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for DAC
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DAC_COMPONENT_
|
||||
#define _SAMD21_DAC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR DAC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_DAC Digital Analog Converter */
|
||||
/*@{*/
|
||||
|
||||
#define DAC_U2214
|
||||
#define REV_DAC 0x110
|
||||
|
||||
/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_CTRLA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */
|
||||
#define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */
|
||||
|
||||
#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
|
||||
#define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos)
|
||||
#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
|
||||
#define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos)
|
||||
#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */
|
||||
#define DAC_CTRLA_RUNSTDBY (0x1ul << DAC_CTRLA_RUNSTDBY_Pos)
|
||||
#define DAC_CTRLA_MASK 0x07ul /**< \brief (DAC_CTRLA) MASK Register */
|
||||
|
||||
/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
|
||||
uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
|
||||
uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
|
||||
uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
|
||||
uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
|
||||
uint8_t :1; /*!< bit: 5 Reserved */
|
||||
uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_CTRLB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */
|
||||
#define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */
|
||||
|
||||
#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
|
||||
#define DAC_CTRLB_EOEN (0x1ul << DAC_CTRLB_EOEN_Pos)
|
||||
#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
|
||||
#define DAC_CTRLB_IOEN (0x1ul << DAC_CTRLB_IOEN_Pos)
|
||||
#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
|
||||
#define DAC_CTRLB_LEFTADJ (0x1ul << DAC_CTRLB_LEFTADJ_Pos)
|
||||
#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
|
||||
#define DAC_CTRLB_VPD (0x1ul << DAC_CTRLB_VPD_Pos)
|
||||
#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
|
||||
#define DAC_CTRLB_BDWP (0x1ul << DAC_CTRLB_BDWP_Pos)
|
||||
#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
|
||||
#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
|
||||
#define DAC_CTRLB_REFSEL_INT1V_Val 0x0ul /**< \brief (DAC_CTRLB) Internal 1.0V reference */
|
||||
#define DAC_CTRLB_REFSEL_AVCC_Val 0x1ul /**< \brief (DAC_CTRLB) AVCC */
|
||||
#define DAC_CTRLB_REFSEL_VREFP_Val 0x2ul /**< \brief (DAC_CTRLB) External reference */
|
||||
#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_MASK 0xDFul /**< \brief (DAC_CTRLB) MASK Register */
|
||||
|
||||
/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
|
||||
uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_EVCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */
|
||||
#define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */
|
||||
|
||||
#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
|
||||
#define DAC_EVCTRL_STARTEI (0x1ul << DAC_EVCTRL_STARTEI_Pos)
|
||||
#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
|
||||
#define DAC_EVCTRL_EMPTYEO (0x1ul << DAC_EVCTRL_EMPTYEO_Pos)
|
||||
#define DAC_EVCTRL_MASK 0x03ul /**< \brief (DAC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
|
||||
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
|
||||
#define DAC_INTENCLR_UNDERRUN (0x1ul << DAC_INTENCLR_UNDERRUN_Pos)
|
||||
#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
|
||||
#define DAC_INTENCLR_EMPTY (0x1ul << DAC_INTENCLR_EMPTY_Pos)
|
||||
#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
|
||||
#define DAC_INTENCLR_SYNCRDY (0x1ul << DAC_INTENCLR_SYNCRDY_Pos)
|
||||
#define DAC_INTENCLR_MASK 0x07ul /**< \brief (DAC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
|
||||
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
|
||||
#define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
|
||||
#define DAC_INTENSET_UNDERRUN (0x1ul << DAC_INTENSET_UNDERRUN_Pos)
|
||||
#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
|
||||
#define DAC_INTENSET_EMPTY (0x1ul << DAC_INTENSET_EMPTY_Pos)
|
||||
#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
|
||||
#define DAC_INTENSET_SYNCRDY (0x1ul << DAC_INTENSET_SYNCRDY_Pos)
|
||||
#define DAC_INTENSET_MASK 0x07ul /**< \brief (DAC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
|
||||
__I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
|
||||
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
|
||||
#define DAC_INTFLAG_UNDERRUN (0x1ul << DAC_INTFLAG_UNDERRUN_Pos)
|
||||
#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
|
||||
#define DAC_INTFLAG_EMPTY (0x1ul << DAC_INTFLAG_EMPTY_Pos)
|
||||
#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */
|
||||
#define DAC_INTFLAG_SYNCRDY (0x1ul << DAC_INTFLAG_SYNCRDY_Pos)
|
||||
#define DAC_INTFLAG_MASK 0x07ul /**< \brief (DAC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
||||
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_STATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */
|
||||
#define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */
|
||||
|
||||
#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */
|
||||
#define DAC_STATUS_SYNCBUSY (0x1ul << DAC_STATUS_SYNCBUSY_Pos)
|
||||
#define DAC_STATUS_MASK 0x80ul /**< \brief (DAC_STATUS) MASK Register */
|
||||
|
||||
/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} DAC_DATA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */
|
||||
#define DAC_DATA_RESETVALUE 0x0000ul /**< \brief (DAC_DATA reset_value) Data */
|
||||
|
||||
#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
|
||||
#define DAC_DATA_DATA_Msk (0xFFFFul << DAC_DATA_DATA_Pos)
|
||||
#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
|
||||
#define DAC_DATA_MASK 0xFFFFul /**< \brief (DAC_DATA) MASK Register */
|
||||
|
||||
/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} DAC_DATABUF_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */
|
||||
#define DAC_DATABUF_RESETVALUE 0x0000ul /**< \brief (DAC_DATABUF reset_value) Data Buffer */
|
||||
|
||||
#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
|
||||
#define DAC_DATABUF_DATABUF_Msk (0xFFFFul << DAC_DATABUF_DATABUF_Pos)
|
||||
#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
|
||||
#define DAC_DATABUF_MASK 0xFFFFul /**< \brief (DAC_DATABUF) MASK Register */
|
||||
|
||||
/** \brief DAC hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
|
||||
__IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
|
||||
__IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
|
||||
RoReg8 Reserved1[0x1];
|
||||
__IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
|
||||
__IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
|
||||
__IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
|
||||
__I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
|
||||
__IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
|
||||
RoReg8 Reserved2[0x2];
|
||||
__IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
|
||||
} Dac;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_DAC_COMPONENT_ */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,541 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for DSU
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DSU_COMPONENT_
|
||||
#define _SAMD21_DSU_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR DSU */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_DSU Device Service Unit */
|
||||
/*@{*/
|
||||
|
||||
#define DSU_U2209
|
||||
#define REV_DSU 0x203
|
||||
|
||||
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t :1; /*!< bit: 1 Reserved */
|
||||
uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
|
||||
uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
|
||||
uint8_t CE:1; /*!< bit: 4 Chip Erase */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DSU_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */
|
||||
#define DSU_CTRL_RESETVALUE 0x00ul /**< \brief (DSU_CTRL reset_value) Control */
|
||||
|
||||
#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
|
||||
#define DSU_CTRL_SWRST (0x1ul << DSU_CTRL_SWRST_Pos)
|
||||
#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
|
||||
#define DSU_CTRL_CRC (0x1ul << DSU_CTRL_CRC_Pos)
|
||||
#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
|
||||
#define DSU_CTRL_MBIST (0x1ul << DSU_CTRL_MBIST_Pos)
|
||||
#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */
|
||||
#define DSU_CTRL_CE (0x1ul << DSU_CTRL_CE_Pos)
|
||||
#define DSU_CTRL_MASK 0x1Dul /**< \brief (DSU_CTRL) MASK Register */
|
||||
|
||||
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t DONE:1; /*!< bit: 0 Done */
|
||||
uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
|
||||
uint8_t BERR:1; /*!< bit: 2 Bus Error */
|
||||
uint8_t FAIL:1; /*!< bit: 3 Failure */
|
||||
uint8_t PERR:1; /*!< bit: 4 Protection Error */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DSU_STATUSA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */
|
||||
#define DSU_STATUSA_RESETVALUE 0x00ul /**< \brief (DSU_STATUSA reset_value) Status A */
|
||||
|
||||
#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */
|
||||
#define DSU_STATUSA_DONE (0x1ul << DSU_STATUSA_DONE_Pos)
|
||||
#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
|
||||
#define DSU_STATUSA_CRSTEXT (0x1ul << DSU_STATUSA_CRSTEXT_Pos)
|
||||
#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */
|
||||
#define DSU_STATUSA_BERR (0x1ul << DSU_STATUSA_BERR_Pos)
|
||||
#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */
|
||||
#define DSU_STATUSA_FAIL (0x1ul << DSU_STATUSA_FAIL_Pos)
|
||||
#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */
|
||||
#define DSU_STATUSA_PERR (0x1ul << DSU_STATUSA_PERR_Pos)
|
||||
#define DSU_STATUSA_MASK 0x1Ful /**< \brief (DSU_STATUSA) MASK Register */
|
||||
|
||||
/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t PROT:1; /*!< bit: 0 Protected */
|
||||
uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
|
||||
uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
|
||||
uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
|
||||
uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DSU_STATUSB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
|
||||
#define DSU_STATUSB_RESETVALUE 0x10ul /**< \brief (DSU_STATUSB reset_value) Status B */
|
||||
|
||||
#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
|
||||
#define DSU_STATUSB_PROT (0x1ul << DSU_STATUSB_PROT_Pos)
|
||||
#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */
|
||||
#define DSU_STATUSB_DBGPRES (0x1ul << DSU_STATUSB_DBGPRES_Pos)
|
||||
#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
|
||||
#define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos)
|
||||
#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
|
||||
#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos)
|
||||
#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
|
||||
#define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos)
|
||||
#define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
|
||||
#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
|
||||
#define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos)
|
||||
#define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */
|
||||
|
||||
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint32_t ADDR:30; /*!< bit: 2..31 Address */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_ADDR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
|
||||
#define DSU_ADDR_RESETVALUE 0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
|
||||
|
||||
#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
|
||||
#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
|
||||
#define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
|
||||
#define DSU_ADDR_MASK 0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
|
||||
|
||||
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint32_t LENGTH:30; /*!< bit: 2..31 Length */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_LENGTH_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */
|
||||
#define DSU_LENGTH_RESETVALUE 0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */
|
||||
|
||||
#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
|
||||
#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
|
||||
#define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
|
||||
#define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
|
||||
|
||||
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DATA:32; /*!< bit: 0..31 Data */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_DATA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */
|
||||
#define DSU_DATA_RESETVALUE 0x00000000ul /**< \brief (DSU_DATA reset_value) Data */
|
||||
|
||||
#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
|
||||
#define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
|
||||
#define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
|
||||
#define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
|
||||
|
||||
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DATA:32; /*!< bit: 0..31 Data */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_DCC_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */
|
||||
#define DSU_DCC_RESETVALUE 0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
|
||||
|
||||
#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
|
||||
#define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
|
||||
#define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
|
||||
#define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
|
||||
|
||||
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
|
||||
uint32_t REVISION:4; /*!< bit: 8..11 Revision */
|
||||
uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
|
||||
uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
|
||||
uint32_t :1; /*!< bit: 22 Reserved */
|
||||
uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
|
||||
uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_DID_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */
|
||||
|
||||
#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
|
||||
#define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos)
|
||||
#define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
|
||||
#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */
|
||||
#define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos)
|
||||
#define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
|
||||
#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */
|
||||
#define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos)
|
||||
#define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
|
||||
#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */
|
||||
#define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos)
|
||||
#define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
|
||||
#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */
|
||||
#define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos)
|
||||
#define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
|
||||
#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
|
||||
#define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos)
|
||||
#define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
|
||||
#define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
|
||||
|
||||
/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t EPRES:1; /*!< bit: 0 Entry Present */
|
||||
uint32_t FMT:1; /*!< bit: 1 Format */
|
||||
uint32_t :10; /*!< bit: 2..11 Reserved */
|
||||
uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_ENTRY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
|
||||
#define DSU_ENTRY_RESETVALUE 0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
|
||||
|
||||
#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */
|
||||
#define DSU_ENTRY_EPRES (0x1ul << DSU_ENTRY_EPRES_Pos)
|
||||
#define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */
|
||||
#define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos)
|
||||
#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */
|
||||
#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
|
||||
#define DSU_ENTRY_ADDOFF(value) (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))
|
||||
#define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
|
||||
|
||||
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t END:32; /*!< bit: 0..31 End Marker */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_END_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */
|
||||
#define DSU_END_RESETVALUE 0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */
|
||||
|
||||
#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
|
||||
#define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos)
|
||||
#define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
|
||||
#define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
|
||||
|
||||
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
|
||||
uint32_t :31; /*!< bit: 1..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_MEMTYPE_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
|
||||
#define DSU_MEMTYPE_RESETVALUE 0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
|
||||
|
||||
#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */
|
||||
#define DSU_MEMTYPE_SMEMP (0x1ul << DSU_MEMTYPE_SMEMP_Pos)
|
||||
#define DSU_MEMTYPE_MASK 0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */
|
||||
|
||||
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
|
||||
uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_PID4_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
|
||||
#define DSU_PID4_RESETVALUE 0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
|
||||
|
||||
#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
|
||||
#define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos)
|
||||
#define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
|
||||
#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */
|
||||
#define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos)
|
||||
#define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
|
||||
#define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */
|
||||
|
||||
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_PID0_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
|
||||
#define DSU_PID0_RESETVALUE 0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
|
||||
|
||||
#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
|
||||
#define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos)
|
||||
#define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
|
||||
#define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */
|
||||
|
||||
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
|
||||
uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_PID1_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
|
||||
#define DSU_PID1_RESETVALUE 0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
|
||||
|
||||
#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
|
||||
#define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos)
|
||||
#define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
|
||||
#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
|
||||
#define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos)
|
||||
#define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
|
||||
#define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */
|
||||
|
||||
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
|
||||
uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
|
||||
uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_PID2_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
|
||||
#define DSU_PID2_RESETVALUE 0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
|
||||
|
||||
#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
|
||||
#define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos)
|
||||
#define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
|
||||
#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
|
||||
#define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos)
|
||||
#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
|
||||
#define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos)
|
||||
#define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
|
||||
#define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */
|
||||
|
||||
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
|
||||
uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_PID3_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
|
||||
#define DSU_PID3_RESETVALUE 0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
|
||||
|
||||
#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
|
||||
#define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos)
|
||||
#define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
|
||||
#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
|
||||
#define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos)
|
||||
#define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
|
||||
#define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */
|
||||
|
||||
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_CID0_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
|
||||
#define DSU_CID0_RESETVALUE 0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
|
||||
|
||||
#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
|
||||
#define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
|
||||
#define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
|
||||
#define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */
|
||||
|
||||
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
|
||||
uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_CID1_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
|
||||
#define DSU_CID1_RESETVALUE 0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
|
||||
|
||||
#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
|
||||
#define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos)
|
||||
#define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
|
||||
#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
|
||||
#define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos)
|
||||
#define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
|
||||
#define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */
|
||||
|
||||
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_CID2_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
|
||||
#define DSU_CID2_RESETVALUE 0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
|
||||
|
||||
#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
|
||||
#define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
|
||||
#define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
|
||||
#define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */
|
||||
|
||||
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_CID3_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
|
||||
#define DSU_CID3_RESETVALUE 0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
|
||||
|
||||
#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
|
||||
#define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
|
||||
#define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
|
||||
#define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */
|
||||
|
||||
/** \brief DSU hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
|
||||
__IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
|
||||
__I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
|
||||
RoReg8 Reserved1[0x1];
|
||||
__IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
|
||||
__IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
|
||||
__IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
|
||||
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
|
||||
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
|
||||
RoReg8 Reserved2[0xFE4];
|
||||
__I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
|
||||
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
|
||||
RoReg8 Reserved3[0xFC0];
|
||||
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
|
||||
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
|
||||
RoReg8 Reserved4[0xC];
|
||||
__I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
|
||||
__I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
|
||||
__I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
|
||||
__I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
|
||||
__I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
|
||||
__I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
|
||||
__I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
|
||||
__I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
|
||||
} Dsu;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_DSU_COMPONENT_ */
|
||||
@ -0,0 +1,671 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for EIC
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EIC_COMPONENT_
|
||||
#define _SAMD21_EIC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR EIC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_EIC External Interrupt Controller */
|
||||
/*@{*/
|
||||
|
||||
#define EIC_U2217
|
||||
#define REV_EIC 0x101
|
||||
|
||||
/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} EIC_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */
|
||||
#define EIC_CTRL_RESETVALUE 0x00ul /**< \brief (EIC_CTRL reset_value) Control */
|
||||
|
||||
#define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */
|
||||
#define EIC_CTRL_SWRST (0x1ul << EIC_CTRL_SWRST_Pos)
|
||||
#define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */
|
||||
#define EIC_CTRL_ENABLE (0x1ul << EIC_CTRL_ENABLE_Pos)
|
||||
#define EIC_CTRL_MASK 0x03ul /**< \brief (EIC_CTRL) MASK Register */
|
||||
|
||||
/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
||||
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} EIC_STATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */
|
||||
#define EIC_STATUS_RESETVALUE 0x00ul /**< \brief (EIC_STATUS reset_value) Status */
|
||||
|
||||
#define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */
|
||||
#define EIC_STATUS_SYNCBUSY (0x1ul << EIC_STATUS_SYNCBUSY_Pos)
|
||||
#define EIC_STATUS_MASK 0x80ul /**< \brief (EIC_STATUS) MASK Register */
|
||||
|
||||
/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
|
||||
uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} EIC_NMICTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
|
||||
#define EIC_NMICTRL_RESETVALUE 0x00ul /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
|
||||
|
||||
#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
|
||||
#define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
|
||||
#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
|
||||
#define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */
|
||||
#define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising-edge detection */
|
||||
#define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling-edge detection */
|
||||
#define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3ul /**< \brief (EIC_NMICTRL) Both-edges detection */
|
||||
#define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4ul /**< \brief (EIC_NMICTRL) High-level detection */
|
||||
#define EIC_NMICTRL_NMISENSE_LOW_Val 0x5ul /**< \brief (EIC_NMICTRL) Low-level detection */
|
||||
#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
|
||||
#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
|
||||
#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
|
||||
#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
|
||||
#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
|
||||
#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
|
||||
#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
|
||||
#define EIC_NMICTRL_NMIFILTEN (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos)
|
||||
#define EIC_NMICTRL_MASK 0x0Ful /**< \brief (EIC_NMICTRL) MASK Register */
|
||||
|
||||
/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} EIC_NMIFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
|
||||
#define EIC_NMIFLAG_RESETVALUE 0x00ul /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
|
||||
|
||||
#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
|
||||
#define EIC_NMIFLAG_NMI (0x1ul << EIC_NMIFLAG_NMI_Pos)
|
||||
#define EIC_NMIFLAG_MASK 0x01ul /**< \brief (EIC_NMIFLAG) MASK Register */
|
||||
|
||||
/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
|
||||
uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
|
||||
uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
|
||||
uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
|
||||
uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
|
||||
uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
|
||||
uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
|
||||
uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
|
||||
uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
|
||||
uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
|
||||
uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
|
||||
uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
|
||||
uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
|
||||
uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
|
||||
uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
|
||||
uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_EVCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */
|
||||
#define EIC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */
|
||||
|
||||
#define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
|
||||
#define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
|
||||
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
|
||||
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
|
||||
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
|
||||
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
|
||||
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
|
||||
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
|
||||
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
|
||||
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
|
||||
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
|
||||
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
|
||||
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
|
||||
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
|
||||
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
|
||||
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
|
||||
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define EIC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
|
||||
#define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos)
|
||||
#define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
|
||||
#define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos)
|
||||
#define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
|
||||
#define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos)
|
||||
#define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
|
||||
#define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos)
|
||||
#define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
|
||||
#define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos)
|
||||
#define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
|
||||
#define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos)
|
||||
#define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
|
||||
#define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos)
|
||||
#define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
|
||||
#define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos)
|
||||
#define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
|
||||
#define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos)
|
||||
#define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
|
||||
#define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos)
|
||||
#define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
|
||||
#define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos)
|
||||
#define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
|
||||
#define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos)
|
||||
#define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
|
||||
#define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos)
|
||||
#define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
|
||||
#define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos)
|
||||
#define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
|
||||
#define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos)
|
||||
#define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
|
||||
#define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos)
|
||||
#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
|
||||
#define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
|
||||
#define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
|
||||
#define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
|
||||
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
|
||||
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
|
||||
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
|
||||
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
|
||||
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
|
||||
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
|
||||
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
|
||||
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
|
||||
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
|
||||
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
|
||||
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
|
||||
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
|
||||
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
|
||||
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
|
||||
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
|
||||
#define EIC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
|
||||
#define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos)
|
||||
#define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
|
||||
#define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos)
|
||||
#define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
|
||||
#define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos)
|
||||
#define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
|
||||
#define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos)
|
||||
#define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
|
||||
#define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos)
|
||||
#define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
|
||||
#define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos)
|
||||
#define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
|
||||
#define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos)
|
||||
#define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
|
||||
#define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos)
|
||||
#define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
|
||||
#define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos)
|
||||
#define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
|
||||
#define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos)
|
||||
#define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
|
||||
#define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos)
|
||||
#define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
|
||||
#define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos)
|
||||
#define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
|
||||
#define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos)
|
||||
#define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
|
||||
#define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos)
|
||||
#define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
|
||||
#define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos)
|
||||
#define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
|
||||
#define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos)
|
||||
#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */
|
||||
#define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
|
||||
#define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
|
||||
#define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
|
||||
__I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
|
||||
__I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
|
||||
__I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
|
||||
__I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
|
||||
__I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
|
||||
__I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
|
||||
__I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
|
||||
__I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
|
||||
__I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
|
||||
__I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
|
||||
__I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
|
||||
__I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
|
||||
__I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
|
||||
__I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
|
||||
__I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
|
||||
__I uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
__I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
|
||||
__I uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define EIC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */
|
||||
#define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos)
|
||||
#define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */
|
||||
#define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos)
|
||||
#define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */
|
||||
#define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos)
|
||||
#define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */
|
||||
#define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos)
|
||||
#define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */
|
||||
#define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos)
|
||||
#define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */
|
||||
#define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos)
|
||||
#define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */
|
||||
#define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos)
|
||||
#define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */
|
||||
#define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos)
|
||||
#define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */
|
||||
#define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos)
|
||||
#define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */
|
||||
#define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos)
|
||||
#define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */
|
||||
#define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos)
|
||||
#define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */
|
||||
#define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos)
|
||||
#define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */
|
||||
#define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos)
|
||||
#define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */
|
||||
#define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos)
|
||||
#define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */
|
||||
#define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos)
|
||||
#define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */
|
||||
#define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos)
|
||||
#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */
|
||||
#define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
|
||||
#define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
|
||||
#define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
|
||||
uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
|
||||
uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
|
||||
uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
|
||||
uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
|
||||
uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
|
||||
uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
|
||||
uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
|
||||
uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
|
||||
uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
|
||||
uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
|
||||
uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
|
||||
uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
|
||||
uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
|
||||
uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
|
||||
uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_WAKEUP_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
|
||||
#define EIC_WAKEUP_RESETVALUE 0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
|
||||
|
||||
#define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN(value) (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))
|
||||
#define EIC_WAKEUP_MASK 0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
|
||||
|
||||
/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
|
||||
uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
|
||||
uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
|
||||
uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
|
||||
uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
|
||||
uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
|
||||
uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
|
||||
uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
|
||||
uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
|
||||
uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
|
||||
uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
|
||||
uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
|
||||
uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
|
||||
uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
|
||||
uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
|
||||
uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_CONFIG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */
|
||||
#define EIC_CONFIG_RESETVALUE 0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */
|
||||
|
||||
#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
|
||||
#define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos)
|
||||
#define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
|
||||
#define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising-edge detection */
|
||||
#define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling-edge detection */
|
||||
#define EIC_CONFIG_SENSE0_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both-edges detection */
|
||||
#define EIC_CONFIG_SENSE0_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High-level detection */
|
||||
#define EIC_CONFIG_SENSE0_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low-level detection */
|
||||
#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
|
||||
#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
|
||||
#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
|
||||
#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
|
||||
#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
|
||||
#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
|
||||
#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */
|
||||
#define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos)
|
||||
#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
|
||||
#define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos)
|
||||
#define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
|
||||
#define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
#define EIC_CONFIG_SENSE1_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
|
||||
#define EIC_CONFIG_SENSE1_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
|
||||
#define EIC_CONFIG_SENSE1_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
|
||||
#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
|
||||
#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
|
||||
#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
|
||||
#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
|
||||
#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
|
||||
#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
|
||||
#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */
|
||||
#define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos)
|
||||
#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
|
||||
#define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos)
|
||||
#define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
|
||||
#define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
#define EIC_CONFIG_SENSE2_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
|
||||
#define EIC_CONFIG_SENSE2_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
|
||||
#define EIC_CONFIG_SENSE2_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
|
||||
#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
|
||||
#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
|
||||
#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
|
||||
#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
|
||||
#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
|
||||
#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
|
||||
#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */
|
||||
#define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos)
|
||||
#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
|
||||
#define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos)
|
||||
#define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
|
||||
#define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
#define EIC_CONFIG_SENSE3_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
|
||||
#define EIC_CONFIG_SENSE3_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
|
||||
#define EIC_CONFIG_SENSE3_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
|
||||
#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
|
||||
#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
|
||||
#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
|
||||
#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
|
||||
#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
|
||||
#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
|
||||
#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */
|
||||
#define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos)
|
||||
#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
|
||||
#define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos)
|
||||
#define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
|
||||
#define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
#define EIC_CONFIG_SENSE4_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
|
||||
#define EIC_CONFIG_SENSE4_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
|
||||
#define EIC_CONFIG_SENSE4_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
|
||||
#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
|
||||
#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
|
||||
#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
|
||||
#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
|
||||
#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
|
||||
#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
|
||||
#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */
|
||||
#define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos)
|
||||
#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
|
||||
#define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos)
|
||||
#define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
|
||||
#define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
#define EIC_CONFIG_SENSE5_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
|
||||
#define EIC_CONFIG_SENSE5_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
|
||||
#define EIC_CONFIG_SENSE5_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
|
||||
#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
|
||||
#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
|
||||
#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
|
||||
#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
|
||||
#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
|
||||
#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
|
||||
#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */
|
||||
#define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos)
|
||||
#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
|
||||
#define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos)
|
||||
#define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
|
||||
#define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
#define EIC_CONFIG_SENSE6_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
|
||||
#define EIC_CONFIG_SENSE6_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
|
||||
#define EIC_CONFIG_SENSE6_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
|
||||
#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
|
||||
#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
|
||||
#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
|
||||
#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
|
||||
#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
|
||||
#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
|
||||
#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */
|
||||
#define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos)
|
||||
#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
|
||||
#define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos)
|
||||
#define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
|
||||
#define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
#define EIC_CONFIG_SENSE7_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
|
||||
#define EIC_CONFIG_SENSE7_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
|
||||
#define EIC_CONFIG_SENSE7_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
|
||||
#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
|
||||
#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
|
||||
#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
|
||||
#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
|
||||
#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
|
||||
#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
|
||||
#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */
|
||||
#define EIC_CONFIG_FILTEN7 (0x1ul << EIC_CONFIG_FILTEN7_Pos)
|
||||
#define EIC_CONFIG_MASK 0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */
|
||||
|
||||
/** \brief EIC hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
|
||||
__I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
|
||||
__IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
|
||||
__IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
|
||||
__IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
|
||||
__IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
|
||||
__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
|
||||
__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
|
||||
__IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
|
||||
__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
|
||||
} Eic;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_EIC_COMPONENT_ */
|
||||
@ -0,0 +1,594 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for EVSYS
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EVSYS_COMPONENT_
|
||||
#define _SAMD21_EVSYS_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR EVSYS */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_EVSYS Event System Interface */
|
||||
/*@{*/
|
||||
|
||||
#define EVSYS_U2208
|
||||
#define REV_EVSYS 0x101
|
||||
|
||||
/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t :3; /*!< bit: 1.. 3 Reserved */
|
||||
uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} EVSYS_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */
|
||||
#define EVSYS_CTRL_RESETVALUE 0x00ul /**< \brief (EVSYS_CTRL reset_value) Control */
|
||||
|
||||
#define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */
|
||||
#define EVSYS_CTRL_SWRST (0x1ul << EVSYS_CTRL_SWRST_Pos)
|
||||
#define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */
|
||||
#define EVSYS_CTRL_GCLKREQ (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
|
||||
#define EVSYS_CTRL_MASK 0x11ul /**< \brief (EVSYS_CTRL) MASK Register */
|
||||
|
||||
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
|
||||
uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
uint32_t SWEVT:1; /*!< bit: 8 Software Event */
|
||||
uint32_t :7; /*!< bit: 9..15 Reserved */
|
||||
uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
|
||||
uint32_t :1; /*!< bit: 23 Reserved */
|
||||
uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
|
||||
uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_CHANNEL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */
|
||||
#define EVSYS_CHANNEL_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
|
||||
|
||||
#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
|
||||
#define EVSYS_CHANNEL_CHANNEL_Msk (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
|
||||
#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
|
||||
#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
|
||||
#define EVSYS_CHANNEL_SWEVT (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
|
||||
#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
|
||||
#define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
|
||||
#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
|
||||
#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
|
||||
#define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
|
||||
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */
|
||||
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */
|
||||
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */
|
||||
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
|
||||
#define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
|
||||
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_MASK 0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
|
||||
|
||||
/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
|
||||
uint16_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
|
||||
uint16_t :3; /*!< bit: 13..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} EVSYS_USER_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */
|
||||
#define EVSYS_USER_RESETVALUE 0x0000ul /**< \brief (EVSYS_USER reset_value) User Multiplexer */
|
||||
|
||||
#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
|
||||
#define EVSYS_USER_USER_Msk (0x1Ful << EVSYS_USER_USER_Pos)
|
||||
#define EVSYS_USER_USER(value) (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
|
||||
#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
|
||||
#define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos)
|
||||
#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
|
||||
#define EVSYS_USER_CHANNEL_0_Val 0x0ul /**< \brief (EVSYS_USER) No Channel Output Selected */
|
||||
#define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
|
||||
#define EVSYS_USER_MASK 0x1F1Ful /**< \brief (EVSYS_USER) MASK Register */
|
||||
|
||||
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
|
||||
uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
|
||||
uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
|
||||
uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
|
||||
uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
|
||||
uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
|
||||
uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
|
||||
uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
|
||||
uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
|
||||
uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
|
||||
uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
|
||||
uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
|
||||
uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
|
||||
uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
|
||||
uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
|
||||
uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
|
||||
uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
|
||||
uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
|
||||
uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
|
||||
uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
|
||||
uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
|
||||
uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
|
||||
uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
|
||||
uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
|
||||
uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_CHSTATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
|
||||
#define EVSYS_CHSTATUS_RESETVALUE 0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
|
||||
|
||||
#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
|
||||
#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
|
||||
#define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
|
||||
#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
|
||||
#define EVSYS_CHSTATUS_MASK 0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
|
||||
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
|
||||
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
|
||||
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
|
||||
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
|
||||
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
|
||||
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
|
||||
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
|
||||
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
|
||||
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
|
||||
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
|
||||
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
|
||||
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
|
||||
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
|
||||
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
|
||||
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
|
||||
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
|
||||
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
|
||||
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
|
||||
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
|
||||
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
|
||||
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
|
||||
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
|
||||
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
|
||||
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define EVSYS_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos)
|
||||
#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos)
|
||||
#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos)
|
||||
#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos)
|
||||
#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos)
|
||||
#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos)
|
||||
#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos)
|
||||
#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
|
||||
#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR_Msk (0xFFul << EVSYS_INTENCLR_OVR_Pos)
|
||||
#define EVSYS_INTENCLR_OVR(value) (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
|
||||
#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
|
||||
#define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos)
|
||||
#define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos)
|
||||
#define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos)
|
||||
#define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos)
|
||||
#define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos)
|
||||
#define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos)
|
||||
#define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
|
||||
#define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD_Msk (0xFFul << EVSYS_INTENCLR_EVD_Pos)
|
||||
#define EVSYS_INTENCLR_EVD(value) (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
|
||||
#define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
|
||||
#define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos)
|
||||
#define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos)
|
||||
#define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
|
||||
#define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVRp8_Msk (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
|
||||
#define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
|
||||
#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
|
||||
#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos)
|
||||
#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos)
|
||||
#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
|
||||
#define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVDp8_Msk (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
|
||||
#define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
|
||||
#define EVSYS_INTENCLR_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
|
||||
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
|
||||
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
|
||||
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
|
||||
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
|
||||
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
|
||||
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
|
||||
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
|
||||
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
|
||||
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
|
||||
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
|
||||
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
|
||||
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
|
||||
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
|
||||
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
|
||||
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
|
||||
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
|
||||
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
|
||||
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
|
||||
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
|
||||
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
|
||||
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
|
||||
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
|
||||
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
|
||||
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
|
||||
#define EVSYS_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos)
|
||||
#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos)
|
||||
#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos)
|
||||
#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos)
|
||||
#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos)
|
||||
#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos)
|
||||
#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos)
|
||||
#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
|
||||
#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR_Msk (0xFFul << EVSYS_INTENSET_OVR_Pos)
|
||||
#define EVSYS_INTENSET_OVR(value) (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
|
||||
#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
|
||||
#define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos)
|
||||
#define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos)
|
||||
#define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos)
|
||||
#define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos)
|
||||
#define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos)
|
||||
#define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos)
|
||||
#define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
|
||||
#define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD_Msk (0xFFul << EVSYS_INTENSET_EVD_Pos)
|
||||
#define EVSYS_INTENSET_EVD(value) (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
|
||||
#define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
|
||||
#define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos)
|
||||
#define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos)
|
||||
#define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
|
||||
#define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVRp8_Msk (0xFul << EVSYS_INTENSET_OVRp8_Pos)
|
||||
#define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
|
||||
#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
|
||||
#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos)
|
||||
#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos)
|
||||
#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
|
||||
#define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVDp8_Msk (0xFul << EVSYS_INTENSET_EVDp8_Pos)
|
||||
#define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
|
||||
#define EVSYS_INTENSET_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
|
||||
__I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
|
||||
__I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
|
||||
__I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
|
||||
__I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
|
||||
__I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
|
||||
__I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
|
||||
__I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
|
||||
__I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
|
||||
__I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
|
||||
__I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
|
||||
__I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
|
||||
__I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
|
||||
__I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
|
||||
__I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
|
||||
__I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
|
||||
__I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
|
||||
__I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
|
||||
__I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
|
||||
__I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
|
||||
__I uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
__I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
|
||||
__I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
|
||||
__I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
|
||||
__I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
|
||||
__I uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
__I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
|
||||
__I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
|
||||
__I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
|
||||
__I uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
__I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
|
||||
__I uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define EVSYS_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos)
|
||||
#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos)
|
||||
#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos)
|
||||
#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos)
|
||||
#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos)
|
||||
#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos)
|
||||
#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos)
|
||||
#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
|
||||
#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
|
||||
#define EVSYS_INTFLAG_OVR_Msk (0xFFul << EVSYS_INTFLAG_OVR_Pos)
|
||||
#define EVSYS_INTFLAG_OVR(value) (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
|
||||
#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
|
||||
#define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos)
|
||||
#define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos)
|
||||
#define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos)
|
||||
#define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos)
|
||||
#define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos)
|
||||
#define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos)
|
||||
#define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
|
||||
#define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD_Msk (0xFFul << EVSYS_INTFLAG_EVD_Pos)
|
||||
#define EVSYS_INTFLAG_EVD(value) (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
|
||||
#define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
|
||||
#define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos)
|
||||
#define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos)
|
||||
#define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
|
||||
#define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
|
||||
#define EVSYS_INTFLAG_OVRp8_Msk (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
|
||||
#define EVSYS_INTFLAG_OVRp8(value) (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
|
||||
#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
|
||||
#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos)
|
||||
#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos)
|
||||
#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
|
||||
#define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVDp8_Msk (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
|
||||
#define EVSYS_INTFLAG_EVDp8(value) (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
|
||||
#define EVSYS_INTFLAG_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
|
||||
|
||||
/** \brief EVSYS hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
|
||||
RoReg8 Reserved1[0x3];
|
||||
__IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
|
||||
__IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
|
||||
RoReg8 Reserved2[0x2];
|
||||
__I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
|
||||
__IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
|
||||
__IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
|
||||
__IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
|
||||
} Evsys;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_EVSYS_COMPONENT_ */
|
||||
@ -0,0 +1,594 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for EVSYS
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EVSYS_COMPONENT_
|
||||
#define _SAMD21_EVSYS_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR EVSYS */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_EVSYS Event System Interface */
|
||||
/*@{*/
|
||||
|
||||
#define EVSYS_U2208
|
||||
#define REV_EVSYS 0x101
|
||||
|
||||
/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t :3; /*!< bit: 1.. 3 Reserved */
|
||||
uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} EVSYS_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */
|
||||
#define EVSYS_CTRL_RESETVALUE 0x00ul /**< \brief (EVSYS_CTRL reset_value) Control */
|
||||
|
||||
#define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */
|
||||
#define EVSYS_CTRL_SWRST (0x1ul << EVSYS_CTRL_SWRST_Pos)
|
||||
#define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */
|
||||
#define EVSYS_CTRL_GCLKREQ (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
|
||||
#define EVSYS_CTRL_MASK 0x11ul /**< \brief (EVSYS_CTRL) MASK Register */
|
||||
|
||||
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
|
||||
uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
uint32_t SWEVT:1; /*!< bit: 8 Software Event */
|
||||
uint32_t :7; /*!< bit: 9..15 Reserved */
|
||||
uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
|
||||
uint32_t :1; /*!< bit: 23 Reserved */
|
||||
uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
|
||||
uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_CHANNEL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */
|
||||
#define EVSYS_CHANNEL_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
|
||||
|
||||
#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
|
||||
#define EVSYS_CHANNEL_CHANNEL_Msk (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
|
||||
#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
|
||||
#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
|
||||
#define EVSYS_CHANNEL_SWEVT (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
|
||||
#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
|
||||
#define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
|
||||
#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
|
||||
#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
|
||||
#define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
|
||||
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */
|
||||
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */
|
||||
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */
|
||||
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
|
||||
#define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
|
||||
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_MASK 0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
|
||||
|
||||
/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t USER:6; /*!< bit: 0.. 5 User Multiplexer Selection */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
|
||||
uint16_t :3; /*!< bit: 13..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} EVSYS_USER_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */
|
||||
#define EVSYS_USER_RESETVALUE 0x0000ul /**< \brief (EVSYS_USER reset_value) User Multiplexer */
|
||||
|
||||
#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
|
||||
#define EVSYS_USER_USER_Msk (0x3Ful << EVSYS_USER_USER_Pos)
|
||||
#define EVSYS_USER_USER(value) (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
|
||||
#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
|
||||
#define EVSYS_USER_CHANNEL_Msk (0x3Ful << EVSYS_USER_CHANNEL_Pos)
|
||||
#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
|
||||
#define EVSYS_USER_CHANNEL_0_Val 0x0ul /**< \brief (EVSYS_USER) No Channel Output Selected */
|
||||
#define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
|
||||
#define EVSYS_USER_MASK 0x1F3Ful /**< \brief (EVSYS_USER) MASK Register */
|
||||
|
||||
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
|
||||
uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
|
||||
uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
|
||||
uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
|
||||
uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
|
||||
uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
|
||||
uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
|
||||
uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
|
||||
uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
|
||||
uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
|
||||
uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
|
||||
uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
|
||||
uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
|
||||
uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
|
||||
uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
|
||||
uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
|
||||
uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
|
||||
uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
|
||||
uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
|
||||
uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
|
||||
uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
|
||||
uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
|
||||
uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
|
||||
uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
|
||||
uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_CHSTATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
|
||||
#define EVSYS_CHSTATUS_RESETVALUE 0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
|
||||
|
||||
#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
|
||||
#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
|
||||
#define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
|
||||
#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
|
||||
#define EVSYS_CHSTATUS_MASK 0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
|
||||
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
|
||||
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
|
||||
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
|
||||
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
|
||||
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
|
||||
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
|
||||
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
|
||||
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
|
||||
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
|
||||
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
|
||||
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
|
||||
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
|
||||
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
|
||||
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
|
||||
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
|
||||
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
|
||||
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
|
||||
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
|
||||
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
|
||||
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
|
||||
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
|
||||
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
|
||||
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
|
||||
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define EVSYS_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos)
|
||||
#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos)
|
||||
#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos)
|
||||
#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos)
|
||||
#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos)
|
||||
#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos)
|
||||
#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos)
|
||||
#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
|
||||
#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR_Msk (0xFFul << EVSYS_INTENCLR_OVR_Pos)
|
||||
#define EVSYS_INTENCLR_OVR(value) (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
|
||||
#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
|
||||
#define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos)
|
||||
#define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos)
|
||||
#define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos)
|
||||
#define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos)
|
||||
#define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos)
|
||||
#define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos)
|
||||
#define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
|
||||
#define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD_Msk (0xFFul << EVSYS_INTENCLR_EVD_Pos)
|
||||
#define EVSYS_INTENCLR_EVD(value) (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
|
||||
#define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
|
||||
#define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos)
|
||||
#define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos)
|
||||
#define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
|
||||
#define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVRp8_Msk (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
|
||||
#define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
|
||||
#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
|
||||
#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos)
|
||||
#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos)
|
||||
#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
|
||||
#define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVDp8_Msk (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
|
||||
#define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
|
||||
#define EVSYS_INTENCLR_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
|
||||
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
|
||||
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
|
||||
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
|
||||
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
|
||||
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
|
||||
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
|
||||
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
|
||||
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
|
||||
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
|
||||
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
|
||||
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
|
||||
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
|
||||
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
|
||||
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
|
||||
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
|
||||
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
|
||||
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
|
||||
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
|
||||
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
|
||||
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
|
||||
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
|
||||
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
|
||||
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
|
||||
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
|
||||
#define EVSYS_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos)
|
||||
#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos)
|
||||
#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos)
|
||||
#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos)
|
||||
#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos)
|
||||
#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos)
|
||||
#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos)
|
||||
#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
|
||||
#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR_Msk (0xFFul << EVSYS_INTENSET_OVR_Pos)
|
||||
#define EVSYS_INTENSET_OVR(value) (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
|
||||
#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
|
||||
#define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos)
|
||||
#define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos)
|
||||
#define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos)
|
||||
#define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos)
|
||||
#define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos)
|
||||
#define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos)
|
||||
#define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
|
||||
#define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD_Msk (0xFFul << EVSYS_INTENSET_EVD_Pos)
|
||||
#define EVSYS_INTENSET_EVD(value) (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
|
||||
#define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
|
||||
#define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos)
|
||||
#define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos)
|
||||
#define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
|
||||
#define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVRp8_Msk (0xFul << EVSYS_INTENSET_OVRp8_Pos)
|
||||
#define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
|
||||
#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
|
||||
#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos)
|
||||
#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos)
|
||||
#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
|
||||
#define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVDp8_Msk (0xFul << EVSYS_INTENSET_EVDp8_Pos)
|
||||
#define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
|
||||
#define EVSYS_INTENSET_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
|
||||
__I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
|
||||
__I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
|
||||
__I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
|
||||
__I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
|
||||
__I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
|
||||
__I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
|
||||
__I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
|
||||
__I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
|
||||
__I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
|
||||
__I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
|
||||
__I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
|
||||
__I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
|
||||
__I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
|
||||
__I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
|
||||
__I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
|
||||
__I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
|
||||
__I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
|
||||
__I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
|
||||
__I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
|
||||
__I uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
__I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
|
||||
__I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
|
||||
__I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
|
||||
__I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
|
||||
__I uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
__I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
|
||||
__I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
|
||||
__I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
|
||||
__I uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
__I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
|
||||
__I uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define EVSYS_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos)
|
||||
#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos)
|
||||
#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos)
|
||||
#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos)
|
||||
#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos)
|
||||
#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos)
|
||||
#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos)
|
||||
#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
|
||||
#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
|
||||
#define EVSYS_INTFLAG_OVR_Msk (0xFFul << EVSYS_INTFLAG_OVR_Pos)
|
||||
#define EVSYS_INTFLAG_OVR(value) (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
|
||||
#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
|
||||
#define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos)
|
||||
#define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos)
|
||||
#define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos)
|
||||
#define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos)
|
||||
#define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos)
|
||||
#define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos)
|
||||
#define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
|
||||
#define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD_Msk (0xFFul << EVSYS_INTFLAG_EVD_Pos)
|
||||
#define EVSYS_INTFLAG_EVD(value) (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
|
||||
#define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
|
||||
#define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos)
|
||||
#define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos)
|
||||
#define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
|
||||
#define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
|
||||
#define EVSYS_INTFLAG_OVRp8_Msk (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
|
||||
#define EVSYS_INTFLAG_OVRp8(value) (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
|
||||
#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
|
||||
#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos)
|
||||
#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos)
|
||||
#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
|
||||
#define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVDp8_Msk (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
|
||||
#define EVSYS_INTFLAG_EVDp8(value) (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
|
||||
#define EVSYS_INTFLAG_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
|
||||
|
||||
/** \brief EVSYS hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
|
||||
RoReg8 Reserved1[0x3];
|
||||
__IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
|
||||
__IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
|
||||
RoReg8 Reserved2[0x2];
|
||||
__I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
|
||||
__IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
|
||||
__IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
|
||||
__IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
|
||||
} Evsys;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_EVSYS_COMPONENT_ */
|
||||
@ -0,0 +1,300 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for GCLK
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_GCLK_COMPONENT_
|
||||
#define _SAMD21_GCLK_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR GCLK */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_GCLK Generic Clock Generator */
|
||||
/*@{*/
|
||||
|
||||
#define GCLK_U2102
|
||||
#define REV_GCLK 0x210
|
||||
|
||||
/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} GCLK_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */
|
||||
#define GCLK_CTRL_RESETVALUE 0x00ul /**< \brief (GCLK_CTRL reset_value) Control */
|
||||
|
||||
#define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */
|
||||
#define GCLK_CTRL_SWRST (0x1ul << GCLK_CTRL_SWRST_Pos)
|
||||
#define GCLK_CTRL_MASK 0x01ul /**< \brief (GCLK_CTRL) MASK Register */
|
||||
|
||||
/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
||||
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} GCLK_STATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */
|
||||
#define GCLK_STATUS_RESETVALUE 0x00ul /**< \brief (GCLK_STATUS reset_value) Status */
|
||||
|
||||
#define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */
|
||||
#define GCLK_STATUS_SYNCBUSY (0x1ul << GCLK_STATUS_SYNCBUSY_Pos)
|
||||
#define GCLK_STATUS_MASK 0x80ul /**< \brief (GCLK_STATUS) MASK Register */
|
||||
|
||||
/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
|
||||
uint16_t :2; /*!< bit: 12..13 Reserved */
|
||||
uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
|
||||
uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} GCLK_CLKCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
|
||||
#define GCLK_CLKCTRL_RESETVALUE 0x0000ul /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
|
||||
|
||||
#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
|
||||
#define GCLK_CLKCTRL_ID_Msk (0x3Ful << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID(value) (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
|
||||
#define GCLK_CLKCTRL_ID_DFLL48_Val 0x0ul /**< \brief (GCLK_CLKCTRL) DFLL48 */
|
||||
#define GCLK_CLKCTRL_ID_FDPLL_Val 0x1ul /**< \brief (GCLK_CLKCTRL) FDPLL */
|
||||
#define GCLK_CLKCTRL_ID_FDPLL32K_Val 0x2ul /**< \brief (GCLK_CLKCTRL) FDPLL32K */
|
||||
#define GCLK_CLKCTRL_ID_WDT_Val 0x3ul /**< \brief (GCLK_CLKCTRL) WDT */
|
||||
#define GCLK_CLKCTRL_ID_RTC_Val 0x4ul /**< \brief (GCLK_CLKCTRL) RTC */
|
||||
#define GCLK_CLKCTRL_ID_EIC_Val 0x5ul /**< \brief (GCLK_CLKCTRL) EIC */
|
||||
#define GCLK_CLKCTRL_ID_USB_Val 0x6ul /**< \brief (GCLK_CLKCTRL) USB */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_0_Val 0x7ul /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_1_Val 0x8ul /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_2_Val 0x9ul /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_3_Val 0xAul /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_4_Val 0xBul /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_5_Val 0xCul /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_6_Val 0xDul /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_7_Val 0xEul /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_8_Val 0xFul /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_9_Val 0x10ul /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_10_Val 0x11ul /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_11_Val 0x12ul /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
|
||||
#define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
|
||||
#define GCLK_CLKCTRL_ID_TCC0_TCC1_Val 0x1Aul /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
|
||||
#define GCLK_CLKCTRL_ID_TCC2_TC3_Val 0x1Bul /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
|
||||
#define GCLK_CLKCTRL_ID_TC4_TC5_Val 0x1Cul /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
|
||||
#define GCLK_CLKCTRL_ID_TC6_TC7_Val 0x1Dul /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
|
||||
#define GCLK_CLKCTRL_ID_ADC_Val 0x1Eul /**< \brief (GCLK_CLKCTRL) ADC */
|
||||
#define GCLK_CLKCTRL_ID_AC_DIG_Val 0x1Ful /**< \brief (GCLK_CLKCTRL) AC_DIG */
|
||||
#define GCLK_CLKCTRL_ID_AC_ANA_Val 0x20ul /**< \brief (GCLK_CLKCTRL) AC_ANA */
|
||||
#define GCLK_CLKCTRL_ID_DAC_Val 0x21ul /**< \brief (GCLK_CLKCTRL) DAC */
|
||||
#define GCLK_CLKCTRL_ID_PTC_Val 0x22ul /**< \brief (GCLK_CLKCTRL) PTC */
|
||||
#define GCLK_CLKCTRL_ID_I2S_0_Val 0x23ul /**< \brief (GCLK_CLKCTRL) I2S_0 */
|
||||
#define GCLK_CLKCTRL_ID_I2S_1_Val 0x24ul /**< \brief (GCLK_CLKCTRL) I2S_1 */
|
||||
#define GCLK_CLKCTRL_ID_DFLL48 (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_FDPLL (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_FDPLL32K (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_WDT (GCLK_CLKCTRL_ID_WDT_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_RTC (GCLK_CLKCTRL_ID_RTC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EIC (GCLK_CLKCTRL_ID_EIC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_USB (GCLK_CLKCTRL_ID_USB_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_0 (GCLK_CLKCTRL_ID_EVSYS_0_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_1 (GCLK_CLKCTRL_ID_EVSYS_1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_2 (GCLK_CLKCTRL_ID_EVSYS_2_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_3 (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_4 (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_5 (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_6 (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_7 (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_8 (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_9 (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_10 (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_11 (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TCC0_TCC1 (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TCC2_TC3 (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TC4_TC5 (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TC6_TC7 (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_ADC (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_AC_DIG (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_AC_ANA (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_DAC (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_PTC (GCLK_CLKCTRL_ID_PTC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_I2S_0 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
|
||||
#define GCLK_CLKCTRL_GEN_Msk (0xFul << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN(value) (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
|
||||
#define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */
|
||||
#define GCLK_CLKCTRL_CLKEN (0x1ul << GCLK_CLKCTRL_CLKEN_Pos)
|
||||
#define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */
|
||||
#define GCLK_CLKCTRL_WRTLOCK (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos)
|
||||
#define GCLK_CLKCTRL_MASK 0xCF3Ful /**< \brief (GCLK_CLKCTRL) MASK Register */
|
||||
|
||||
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
|
||||
uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
uint32_t SRC:5; /*!< bit: 8..12 Source Select */
|
||||
uint32_t :3; /*!< bit: 13..15 Reserved */
|
||||
uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
|
||||
uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
|
||||
uint32_t OOV:1; /*!< bit: 18 Output Off Value */
|
||||
uint32_t OE:1; /*!< bit: 19 Output Enable */
|
||||
uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
|
||||
uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
|
||||
uint32_t :10; /*!< bit: 22..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} GCLK_GENCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
|
||||
#define GCLK_GENCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
|
||||
|
||||
#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
|
||||
#define GCLK_GENCTRL_ID_Msk (0xFul << GCLK_GENCTRL_ID_Pos)
|
||||
#define GCLK_GENCTRL_ID(value) (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
|
||||
#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
|
||||
#define GCLK_GENCTRL_SRC_Msk (0x1Ful << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
|
||||
#define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */
|
||||
#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
|
||||
#define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3ul /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_OSC32K_Val 0x4ul /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5ul /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_OSC8M_Val 0x6ul /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7ul /**< \brief (GCLK_GENCTRL) DFLL48M output */
|
||||
#define GCLK_GENCTRL_SRC_FDPLL_Val 0x8ul /**< \brief (GCLK_GENCTRL) FDPLL output */
|
||||
#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_FDPLL (GCLK_GENCTRL_SRC_FDPLL_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
|
||||
#define GCLK_GENCTRL_GENEN (0x1ul << GCLK_GENCTRL_GENEN_Pos)
|
||||
#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
|
||||
#define GCLK_GENCTRL_IDC (0x1ul << GCLK_GENCTRL_IDC_Pos)
|
||||
#define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */
|
||||
#define GCLK_GENCTRL_OOV (0x1ul << GCLK_GENCTRL_OOV_Pos)
|
||||
#define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */
|
||||
#define GCLK_GENCTRL_OE (0x1ul << GCLK_GENCTRL_OE_Pos)
|
||||
#define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */
|
||||
#define GCLK_GENCTRL_DIVSEL (0x1ul << GCLK_GENCTRL_DIVSEL_Pos)
|
||||
#define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */
|
||||
#define GCLK_GENCTRL_RUNSTDBY (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos)
|
||||
#define GCLK_GENCTRL_MASK 0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */
|
||||
|
||||
/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
|
||||
uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
|
||||
uint32_t :8; /*!< bit: 24..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} GCLK_GENDIV_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
|
||||
#define GCLK_GENDIV_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
|
||||
|
||||
#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
|
||||
#define GCLK_GENDIV_ID_Msk (0xFul << GCLK_GENDIV_ID_Pos)
|
||||
#define GCLK_GENDIV_ID(value) (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
|
||||
#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
|
||||
#define GCLK_GENDIV_DIV_Msk (0xFFFFul << GCLK_GENDIV_DIV_Pos)
|
||||
#define GCLK_GENDIV_DIV(value) (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
|
||||
#define GCLK_GENDIV_MASK 0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */
|
||||
|
||||
/** \brief GCLK hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
|
||||
__I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
|
||||
__IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
|
||||
__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
|
||||
__IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
|
||||
} Gclk;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_GCLK_COMPONENT_ */
|
||||
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Reference in New Issue