doc/html/component_2gmac_8h_source.html

#ifndef _SAME54_GMAC_COMPONENT_

#define _SAME54_GMAC_COMPONENT_


/* ========================================================================== */

/* ========================================================================== */


#define GMAC_U2005

#define REV_GMAC                    0x100


/* -------- GMAC_NCR : (GMAC Offset: 0x000) (R/W 32) Network Control Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t :1;

    uint32_t LBL:1;

    uint32_t RXEN:1;

    uint32_t TXEN:1;

    uint32_t MPE:1;

    uint32_t CLRSTAT:1;

    uint32_t INCSTAT:1;

    uint32_t WESTAT:1;

    uint32_t BP:1;

    uint32_t TSTART:1;

    uint32_t THALT:1;

    uint32_t TXPF:1;

    uint32_t TXZQPF:1;

    uint32_t :2;

    uint32_t SRTSM:1;

    uint32_t ENPBPR:1;

    uint32_t TXPBPF:1;

    uint32_t FNP:1;

    uint32_t LPI:1;

    uint32_t :12;

  } bit;

  uint32_t reg;

} GMAC_NCR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_NCR_OFFSET             0x000

#define GMAC_NCR_RESETVALUE         _U_(0x00000000)

#define GMAC_NCR_LBL_Pos            1

#define GMAC_NCR_LBL                (_U_(0x1) << GMAC_NCR_LBL_Pos)

#define GMAC_NCR_RXEN_Pos           2

#define GMAC_NCR_RXEN               (_U_(0x1) << GMAC_NCR_RXEN_Pos)

#define GMAC_NCR_TXEN_Pos           3

#define GMAC_NCR_TXEN               (_U_(0x1) << GMAC_NCR_TXEN_Pos)

#define GMAC_NCR_MPE_Pos            4

#define GMAC_NCR_MPE                (_U_(0x1) << GMAC_NCR_MPE_Pos)

#define GMAC_NCR_CLRSTAT_Pos        5

#define GMAC_NCR_CLRSTAT            (_U_(0x1) << GMAC_NCR_CLRSTAT_Pos)

#define GMAC_NCR_INCSTAT_Pos        6

#define GMAC_NCR_INCSTAT            (_U_(0x1) << GMAC_NCR_INCSTAT_Pos)

#define GMAC_NCR_WESTAT_Pos         7

#define GMAC_NCR_WESTAT             (_U_(0x1) << GMAC_NCR_WESTAT_Pos)

#define GMAC_NCR_BP_Pos             8

#define GMAC_NCR_BP                 (_U_(0x1) << GMAC_NCR_BP_Pos)

#define GMAC_NCR_TSTART_Pos         9

#define GMAC_NCR_TSTART             (_U_(0x1) << GMAC_NCR_TSTART_Pos)

#define GMAC_NCR_THALT_Pos          10

#define GMAC_NCR_THALT              (_U_(0x1) << GMAC_NCR_THALT_Pos)

#define GMAC_NCR_TXPF_Pos           11

#define GMAC_NCR_TXPF               (_U_(0x1) << GMAC_NCR_TXPF_Pos)

#define GMAC_NCR_TXZQPF_Pos         12

#define GMAC_NCR_TXZQPF             (_U_(0x1) << GMAC_NCR_TXZQPF_Pos)

#define GMAC_NCR_SRTSM_Pos          15

#define GMAC_NCR_SRTSM              (_U_(0x1) << GMAC_NCR_SRTSM_Pos)

#define GMAC_NCR_ENPBPR_Pos         16

#define GMAC_NCR_ENPBPR             (_U_(0x1) << GMAC_NCR_ENPBPR_Pos)

#define GMAC_NCR_TXPBPF_Pos         17

#define GMAC_NCR_TXPBPF             (_U_(0x1) << GMAC_NCR_TXPBPF_Pos)

#define GMAC_NCR_FNP_Pos            18

#define GMAC_NCR_FNP                (_U_(0x1) << GMAC_NCR_FNP_Pos)

#define GMAC_NCR_LPI_Pos            19

#define GMAC_NCR_LPI                (_U_(0x1) << GMAC_NCR_LPI_Pos)

#define GMAC_NCR_MASK               _U_(0x000F9FFE)

/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) (R/W 32) Network Configuration Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t SPD:1;

    uint32_t FD:1;

    uint32_t DNVLAN:1;

    uint32_t JFRAME:1;

    uint32_t CAF:1;

    uint32_t NBC:1;

    uint32_t MTIHEN:1;

    uint32_t UNIHEN:1;

    uint32_t MAXFS:1;

    uint32_t :3;

    uint32_t RTY:1;

    uint32_t PEN:1;

    uint32_t RXBUFO:2;

    uint32_t LFERD:1;

    uint32_t RFCS:1;

    uint32_t CLK:3;

    uint32_t DBW:2;

    uint32_t DCPF:1;

    uint32_t RXCOEN:1;

    uint32_t EFRHD:1;

    uint32_t IRXFCS:1;

    uint32_t :1;

    uint32_t IPGSEN:1;

    uint32_t RXBP:1;

    uint32_t IRXER:1;

    uint32_t :1;

  } bit;

  uint32_t reg;

} GMAC_NCFGR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_NCFGR_OFFSET           0x004

#define GMAC_NCFGR_RESETVALUE       _U_(0x00080000)

#define GMAC_NCFGR_SPD_Pos          0

#define GMAC_NCFGR_SPD              (_U_(0x1) << GMAC_NCFGR_SPD_Pos)

#define GMAC_NCFGR_FD_Pos           1

#define GMAC_NCFGR_FD               (_U_(0x1) << GMAC_NCFGR_FD_Pos)

#define GMAC_NCFGR_DNVLAN_Pos       2

#define GMAC_NCFGR_DNVLAN           (_U_(0x1) << GMAC_NCFGR_DNVLAN_Pos)

#define GMAC_NCFGR_JFRAME_Pos       3

#define GMAC_NCFGR_JFRAME           (_U_(0x1) << GMAC_NCFGR_JFRAME_Pos)

#define GMAC_NCFGR_CAF_Pos          4

#define GMAC_NCFGR_CAF              (_U_(0x1) << GMAC_NCFGR_CAF_Pos)

#define GMAC_NCFGR_NBC_Pos          5

#define GMAC_NCFGR_NBC              (_U_(0x1) << GMAC_NCFGR_NBC_Pos)

#define GMAC_NCFGR_MTIHEN_Pos       6

#define GMAC_NCFGR_MTIHEN           (_U_(0x1) << GMAC_NCFGR_MTIHEN_Pos)

#define GMAC_NCFGR_UNIHEN_Pos       7

#define GMAC_NCFGR_UNIHEN           (_U_(0x1) << GMAC_NCFGR_UNIHEN_Pos)

#define GMAC_NCFGR_MAXFS_Pos        8

#define GMAC_NCFGR_MAXFS            (_U_(0x1) << GMAC_NCFGR_MAXFS_Pos)

#define GMAC_NCFGR_RTY_Pos          12

#define GMAC_NCFGR_RTY              (_U_(0x1) << GMAC_NCFGR_RTY_Pos)

#define GMAC_NCFGR_PEN_Pos          13

#define GMAC_NCFGR_PEN              (_U_(0x1) << GMAC_NCFGR_PEN_Pos)

#define GMAC_NCFGR_RXBUFO_Pos       14

#define GMAC_NCFGR_RXBUFO_Msk       (_U_(0x3) << GMAC_NCFGR_RXBUFO_Pos)

#define GMAC_NCFGR_RXBUFO(value)    (GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))

#define GMAC_NCFGR_LFERD_Pos        16

#define GMAC_NCFGR_LFERD            (_U_(0x1) << GMAC_NCFGR_LFERD_Pos)

#define GMAC_NCFGR_RFCS_Pos         17

#define GMAC_NCFGR_RFCS             (_U_(0x1) << GMAC_NCFGR_RFCS_Pos)

#define GMAC_NCFGR_CLK_Pos          18

#define GMAC_NCFGR_CLK_Msk          (_U_(0x7) << GMAC_NCFGR_CLK_Pos)

#define GMAC_NCFGR_CLK(value)       (GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))

#define GMAC_NCFGR_DBW_Pos          21

#define GMAC_NCFGR_DBW_Msk          (_U_(0x3) << GMAC_NCFGR_DBW_Pos)

#define GMAC_NCFGR_DBW(value)       (GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))

#define GMAC_NCFGR_DCPF_Pos         23

#define GMAC_NCFGR_DCPF             (_U_(0x1) << GMAC_NCFGR_DCPF_Pos)

#define GMAC_NCFGR_RXCOEN_Pos       24

#define GMAC_NCFGR_RXCOEN           (_U_(0x1) << GMAC_NCFGR_RXCOEN_Pos)

#define GMAC_NCFGR_EFRHD_Pos        25

#define GMAC_NCFGR_EFRHD            (_U_(0x1) << GMAC_NCFGR_EFRHD_Pos)

#define GMAC_NCFGR_IRXFCS_Pos       26

#define GMAC_NCFGR_IRXFCS           (_U_(0x1) << GMAC_NCFGR_IRXFCS_Pos)

#define GMAC_NCFGR_IPGSEN_Pos       28

#define GMAC_NCFGR_IPGSEN           (_U_(0x1) << GMAC_NCFGR_IPGSEN_Pos)

#define GMAC_NCFGR_RXBP_Pos         29

#define GMAC_NCFGR_RXBP             (_U_(0x1) << GMAC_NCFGR_RXBP_Pos)

#define GMAC_NCFGR_IRXER_Pos        30

#define GMAC_NCFGR_IRXER            (_U_(0x1) << GMAC_NCFGR_IRXER_Pos)

#define GMAC_NCFGR_MASK             _U_(0x77FFF1FF)

/* -------- GMAC_NSR : (GMAC Offset: 0x008) (R/  32) Network Status Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t :1;

    uint32_t MDIO:1;

    uint32_t IDLE:1;

    uint32_t :29;

  } bit;

  uint32_t reg;

} GMAC_NSR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_NSR_OFFSET             0x008

#define GMAC_NSR_RESETVALUE         _U_(0x00000004)

#define GMAC_NSR_MDIO_Pos           1

#define GMAC_NSR_MDIO               (_U_(0x1) << GMAC_NSR_MDIO_Pos)

#define GMAC_NSR_IDLE_Pos           2

#define GMAC_NSR_IDLE               (_U_(0x1) << GMAC_NSR_IDLE_Pos)

#define GMAC_NSR_MASK               _U_(0x00000006)

/* -------- GMAC_UR : (GMAC Offset: 0x00C) (R/W 32) User Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t MII:1;

    uint32_t :31;

  } bit;

  uint32_t reg;

} GMAC_UR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_UR_OFFSET              0x00C

#define GMAC_UR_RESETVALUE          _U_(0x00000000)

#define GMAC_UR_MII_Pos             0

#define GMAC_UR_MII                 (_U_(0x1) << GMAC_UR_MII_Pos)

#define GMAC_UR_MASK                _U_(0x00000001)

/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) (R/W 32) DMA Configuration Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t FBLDO:5;

    uint32_t :1;

    uint32_t ESMA:1;

    uint32_t ESPA:1;

    uint32_t RXBMS:2;

    uint32_t TXPBMS:1;

    uint32_t TXCOEN:1;

    uint32_t :4;

    uint32_t DRBS:8;

    uint32_t DDRP:1;

    uint32_t :7;

  } bit;

  uint32_t reg;

} GMAC_DCFGR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_DCFGR_OFFSET           0x010

#define GMAC_DCFGR_RESETVALUE       _U_(0x00020704)

#define GMAC_DCFGR_FBLDO_Pos        0

#define GMAC_DCFGR_FBLDO_Msk        (_U_(0x1F) << GMAC_DCFGR_FBLDO_Pos)

#define GMAC_DCFGR_FBLDO(value)     (GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))

#define GMAC_DCFGR_ESMA_Pos         6

#define GMAC_DCFGR_ESMA             (_U_(0x1) << GMAC_DCFGR_ESMA_Pos)

#define GMAC_DCFGR_ESPA_Pos         7

#define GMAC_DCFGR_ESPA             (_U_(0x1) << GMAC_DCFGR_ESPA_Pos)

#define GMAC_DCFGR_RXBMS_Pos        8

#define GMAC_DCFGR_RXBMS_Msk        (_U_(0x3) << GMAC_DCFGR_RXBMS_Pos)

#define GMAC_DCFGR_RXBMS(value)     (GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))

#define GMAC_DCFGR_TXPBMS_Pos       10

#define GMAC_DCFGR_TXPBMS           (_U_(0x1) << GMAC_DCFGR_TXPBMS_Pos)

#define GMAC_DCFGR_TXCOEN_Pos       11

#define GMAC_DCFGR_TXCOEN           (_U_(0x1) << GMAC_DCFGR_TXCOEN_Pos)

#define GMAC_DCFGR_DRBS_Pos         16

#define GMAC_DCFGR_DRBS_Msk         (_U_(0xFF) << GMAC_DCFGR_DRBS_Pos)

#define GMAC_DCFGR_DRBS(value)      (GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))

#define GMAC_DCFGR_DDRP_Pos         24

#define GMAC_DCFGR_DDRP             (_U_(0x1) << GMAC_DCFGR_DDRP_Pos)

#define GMAC_DCFGR_MASK             _U_(0x01FF0FDF)

/* -------- GMAC_TSR : (GMAC Offset: 0x014) (R/W 32) Transmit Status Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t UBR:1;

    uint32_t COL:1;

    uint32_t RLE:1;

    uint32_t TXGO:1;

    uint32_t TFC:1;

    uint32_t TXCOMP:1;

    uint32_t UND:1;

    uint32_t :1;

    uint32_t HRESP:1;

    uint32_t :23;

  } bit;

  uint32_t reg;

} GMAC_TSR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TSR_OFFSET             0x014

#define GMAC_TSR_RESETVALUE         _U_(0x00000000)

#define GMAC_TSR_UBR_Pos            0

#define GMAC_TSR_UBR                (_U_(0x1) << GMAC_TSR_UBR_Pos)

#define GMAC_TSR_COL_Pos            1

#define GMAC_TSR_COL                (_U_(0x1) << GMAC_TSR_COL_Pos)

#define GMAC_TSR_RLE_Pos            2

#define GMAC_TSR_RLE                (_U_(0x1) << GMAC_TSR_RLE_Pos)

#define GMAC_TSR_TXGO_Pos           3

#define GMAC_TSR_TXGO               (_U_(0x1) << GMAC_TSR_TXGO_Pos)

#define GMAC_TSR_TFC_Pos            4

#define GMAC_TSR_TFC                (_U_(0x1) << GMAC_TSR_TFC_Pos)

#define GMAC_TSR_TXCOMP_Pos         5

#define GMAC_TSR_TXCOMP             (_U_(0x1) << GMAC_TSR_TXCOMP_Pos)

#define GMAC_TSR_UND_Pos            6

#define GMAC_TSR_UND                (_U_(0x1) << GMAC_TSR_UND_Pos)

#define GMAC_TSR_HRESP_Pos          8

#define GMAC_TSR_HRESP              (_U_(0x1) << GMAC_TSR_HRESP_Pos)

#define GMAC_TSR_MASK               _U_(0x0000017F)

/* -------- GMAC_RBQB : (GMAC Offset: 0x018) (R/W 32) Receive Buffer Queue Base Address -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t :2;

    uint32_t ADDR:30;

  } bit;

  uint32_t reg;

} GMAC_RBQB_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_RBQB_OFFSET            0x018

#define GMAC_RBQB_RESETVALUE        _U_(0x00000000)

#define GMAC_RBQB_ADDR_Pos          2

#define GMAC_RBQB_ADDR_Msk          (_U_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos)

#define GMAC_RBQB_ADDR(value)       (GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))

#define GMAC_RBQB_MASK              _U_(0xFFFFFFFC)

/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) (R/W 32) Transmit Buffer Queue Base Address -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t :2;

    uint32_t ADDR:30;

  } bit;

  uint32_t reg;

} GMAC_TBQB_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TBQB_OFFSET            0x01C

#define GMAC_TBQB_RESETVALUE        _U_(0x00000000)

#define GMAC_TBQB_ADDR_Pos          2

#define GMAC_TBQB_ADDR_Msk          (_U_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos)

#define GMAC_TBQB_ADDR(value)       (GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))

#define GMAC_TBQB_MASK              _U_(0xFFFFFFFC)

/* -------- GMAC_RSR : (GMAC Offset: 0x020) (R/W 32) Receive Status Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t BNA:1;

    uint32_t REC:1;

    uint32_t RXOVR:1;

    uint32_t HNO:1;

    uint32_t :28;

  } bit;

  uint32_t reg;

} GMAC_RSR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_RSR_OFFSET             0x020

#define GMAC_RSR_RESETVALUE         _U_(0x00000000)

#define GMAC_RSR_BNA_Pos            0

#define GMAC_RSR_BNA                (_U_(0x1) << GMAC_RSR_BNA_Pos)

#define GMAC_RSR_REC_Pos            1

#define GMAC_RSR_REC                (_U_(0x1) << GMAC_RSR_REC_Pos)

#define GMAC_RSR_RXOVR_Pos          2

#define GMAC_RSR_RXOVR              (_U_(0x1) << GMAC_RSR_RXOVR_Pos)

#define GMAC_RSR_HNO_Pos            3

#define GMAC_RSR_HNO                (_U_(0x1) << GMAC_RSR_HNO_Pos)

#define GMAC_RSR_MASK               _U_(0x0000000F)

/* -------- GMAC_ISR : (GMAC Offset: 0x024) (R/W 32) Interrupt Status Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t MFS:1;

    uint32_t RCOMP:1;

    uint32_t RXUBR:1;

    uint32_t TXUBR:1;

    uint32_t TUR:1;

    uint32_t RLEX:1;

    uint32_t TFC:1;

    uint32_t TCOMP:1;

    uint32_t :2;

    uint32_t ROVR:1;

    uint32_t HRESP:1;

    uint32_t PFNZ:1;

    uint32_t PTZ:1;

    uint32_t PFTR:1;

    uint32_t :3;

    uint32_t DRQFR:1;

    uint32_t SFR:1;

    uint32_t DRQFT:1;

    uint32_t SFT:1;

    uint32_t PDRQFR:1;

    uint32_t PDRSFR:1;

    uint32_t PDRQFT:1;

    uint32_t PDRSFT:1;

    uint32_t SRI:1;

    uint32_t :1;

    uint32_t WOL:1;

    uint32_t TSUCMP:1;

    uint32_t :2;

  } bit;

  uint32_t reg;

} GMAC_ISR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_ISR_OFFSET             0x024

#define GMAC_ISR_RESETVALUE         _U_(0x00000000)

#define GMAC_ISR_MFS_Pos            0

#define GMAC_ISR_MFS                (_U_(0x1) << GMAC_ISR_MFS_Pos)

#define GMAC_ISR_RCOMP_Pos          1

#define GMAC_ISR_RCOMP              (_U_(0x1) << GMAC_ISR_RCOMP_Pos)

#define GMAC_ISR_RXUBR_Pos          2

#define GMAC_ISR_RXUBR              (_U_(0x1) << GMAC_ISR_RXUBR_Pos)

#define GMAC_ISR_TXUBR_Pos          3

#define GMAC_ISR_TXUBR              (_U_(0x1) << GMAC_ISR_TXUBR_Pos)

#define GMAC_ISR_TUR_Pos            4

#define GMAC_ISR_TUR                (_U_(0x1) << GMAC_ISR_TUR_Pos)

#define GMAC_ISR_RLEX_Pos           5

#define GMAC_ISR_RLEX               (_U_(0x1) << GMAC_ISR_RLEX_Pos)

#define GMAC_ISR_TFC_Pos            6

#define GMAC_ISR_TFC                (_U_(0x1) << GMAC_ISR_TFC_Pos)

#define GMAC_ISR_TCOMP_Pos          7

#define GMAC_ISR_TCOMP              (_U_(0x1) << GMAC_ISR_TCOMP_Pos)

#define GMAC_ISR_ROVR_Pos           10

#define GMAC_ISR_ROVR               (_U_(0x1) << GMAC_ISR_ROVR_Pos)

#define GMAC_ISR_HRESP_Pos          11

#define GMAC_ISR_HRESP              (_U_(0x1) << GMAC_ISR_HRESP_Pos)

#define GMAC_ISR_PFNZ_Pos           12

#define GMAC_ISR_PFNZ               (_U_(0x1) << GMAC_ISR_PFNZ_Pos)

#define GMAC_ISR_PTZ_Pos            13

#define GMAC_ISR_PTZ                (_U_(0x1) << GMAC_ISR_PTZ_Pos)

#define GMAC_ISR_PFTR_Pos           14

#define GMAC_ISR_PFTR               (_U_(0x1) << GMAC_ISR_PFTR_Pos)

#define GMAC_ISR_DRQFR_Pos          18

#define GMAC_ISR_DRQFR              (_U_(0x1) << GMAC_ISR_DRQFR_Pos)

#define GMAC_ISR_SFR_Pos            19

#define GMAC_ISR_SFR                (_U_(0x1) << GMAC_ISR_SFR_Pos)

#define GMAC_ISR_DRQFT_Pos          20

#define GMAC_ISR_DRQFT              (_U_(0x1) << GMAC_ISR_DRQFT_Pos)

#define GMAC_ISR_SFT_Pos            21

#define GMAC_ISR_SFT                (_U_(0x1) << GMAC_ISR_SFT_Pos)

#define GMAC_ISR_PDRQFR_Pos         22

#define GMAC_ISR_PDRQFR             (_U_(0x1) << GMAC_ISR_PDRQFR_Pos)

#define GMAC_ISR_PDRSFR_Pos         23

#define GMAC_ISR_PDRSFR             (_U_(0x1) << GMAC_ISR_PDRSFR_Pos)

#define GMAC_ISR_PDRQFT_Pos         24

#define GMAC_ISR_PDRQFT             (_U_(0x1) << GMAC_ISR_PDRQFT_Pos)

#define GMAC_ISR_PDRSFT_Pos         25

#define GMAC_ISR_PDRSFT             (_U_(0x1) << GMAC_ISR_PDRSFT_Pos)

#define GMAC_ISR_SRI_Pos            26

#define GMAC_ISR_SRI                (_U_(0x1) << GMAC_ISR_SRI_Pos)

#define GMAC_ISR_WOL_Pos            28

#define GMAC_ISR_WOL                (_U_(0x1) << GMAC_ISR_WOL_Pos)

#define GMAC_ISR_TSUCMP_Pos         29

#define GMAC_ISR_TSUCMP             (_U_(0x1) << GMAC_ISR_TSUCMP_Pos)

#define GMAC_ISR_MASK               _U_(0x37FC7CFF)

/* -------- GMAC_IER : (GMAC Offset: 0x028) ( /W 32) Interrupt Enable Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t MFS:1;

    uint32_t RCOMP:1;

    uint32_t RXUBR:1;

    uint32_t TXUBR:1;

    uint32_t TUR:1;

    uint32_t RLEX:1;

    uint32_t TFC:1;

    uint32_t TCOMP:1;

    uint32_t :2;

    uint32_t ROVR:1;

    uint32_t HRESP:1;

    uint32_t PFNZ:1;

    uint32_t PTZ:1;

    uint32_t PFTR:1;

    uint32_t EXINT:1;

    uint32_t :2;

    uint32_t DRQFR:1;

    uint32_t SFR:1;

    uint32_t DRQFT:1;

    uint32_t SFT:1;

    uint32_t PDRQFR:1;

    uint32_t PDRSFR:1;

    uint32_t PDRQFT:1;

    uint32_t PDRSFT:1;

    uint32_t SRI:1;

    uint32_t :1;

    uint32_t WOL:1;

    uint32_t TSUCMP:1;

    uint32_t :2;

  } bit;

  uint32_t reg;

} GMAC_IER_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_IER_OFFSET             0x028

#define GMAC_IER_MFS_Pos            0

#define GMAC_IER_MFS                (_U_(0x1) << GMAC_IER_MFS_Pos)

#define GMAC_IER_RCOMP_Pos          1

#define GMAC_IER_RCOMP              (_U_(0x1) << GMAC_IER_RCOMP_Pos)

#define GMAC_IER_RXUBR_Pos          2

#define GMAC_IER_RXUBR              (_U_(0x1) << GMAC_IER_RXUBR_Pos)

#define GMAC_IER_TXUBR_Pos          3

#define GMAC_IER_TXUBR              (_U_(0x1) << GMAC_IER_TXUBR_Pos)

#define GMAC_IER_TUR_Pos            4

#define GMAC_IER_TUR                (_U_(0x1) << GMAC_IER_TUR_Pos)

#define GMAC_IER_RLEX_Pos           5

#define GMAC_IER_RLEX               (_U_(0x1) << GMAC_IER_RLEX_Pos)

#define GMAC_IER_TFC_Pos            6

#define GMAC_IER_TFC                (_U_(0x1) << GMAC_IER_TFC_Pos)

#define GMAC_IER_TCOMP_Pos          7

#define GMAC_IER_TCOMP              (_U_(0x1) << GMAC_IER_TCOMP_Pos)

#define GMAC_IER_ROVR_Pos           10

#define GMAC_IER_ROVR               (_U_(0x1) << GMAC_IER_ROVR_Pos)

#define GMAC_IER_HRESP_Pos          11

#define GMAC_IER_HRESP              (_U_(0x1) << GMAC_IER_HRESP_Pos)

#define GMAC_IER_PFNZ_Pos           12

#define GMAC_IER_PFNZ               (_U_(0x1) << GMAC_IER_PFNZ_Pos)

#define GMAC_IER_PTZ_Pos            13

#define GMAC_IER_PTZ                (_U_(0x1) << GMAC_IER_PTZ_Pos)

#define GMAC_IER_PFTR_Pos           14

#define GMAC_IER_PFTR               (_U_(0x1) << GMAC_IER_PFTR_Pos)

#define GMAC_IER_EXINT_Pos          15

#define GMAC_IER_EXINT              (_U_(0x1) << GMAC_IER_EXINT_Pos)

#define GMAC_IER_DRQFR_Pos          18

#define GMAC_IER_DRQFR              (_U_(0x1) << GMAC_IER_DRQFR_Pos)

#define GMAC_IER_SFR_Pos            19

#define GMAC_IER_SFR                (_U_(0x1) << GMAC_IER_SFR_Pos)

#define GMAC_IER_DRQFT_Pos          20

#define GMAC_IER_DRQFT              (_U_(0x1) << GMAC_IER_DRQFT_Pos)

#define GMAC_IER_SFT_Pos            21

#define GMAC_IER_SFT                (_U_(0x1) << GMAC_IER_SFT_Pos)

#define GMAC_IER_PDRQFR_Pos         22

#define GMAC_IER_PDRQFR             (_U_(0x1) << GMAC_IER_PDRQFR_Pos)

#define GMAC_IER_PDRSFR_Pos         23

#define GMAC_IER_PDRSFR             (_U_(0x1) << GMAC_IER_PDRSFR_Pos)

#define GMAC_IER_PDRQFT_Pos         24

#define GMAC_IER_PDRQFT             (_U_(0x1) << GMAC_IER_PDRQFT_Pos)

#define GMAC_IER_PDRSFT_Pos         25

#define GMAC_IER_PDRSFT             (_U_(0x1) << GMAC_IER_PDRSFT_Pos)

#define GMAC_IER_SRI_Pos            26

#define GMAC_IER_SRI                (_U_(0x1) << GMAC_IER_SRI_Pos)

#define GMAC_IER_WOL_Pos            28

#define GMAC_IER_WOL                (_U_(0x1) << GMAC_IER_WOL_Pos)

#define GMAC_IER_TSUCMP_Pos         29

#define GMAC_IER_TSUCMP             (_U_(0x1) << GMAC_IER_TSUCMP_Pos)

#define GMAC_IER_MASK               _U_(0x37FCFCFF)

/* -------- GMAC_IDR : (GMAC Offset: 0x02C) ( /W 32) Interrupt Disable Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t MFS:1;

    uint32_t RCOMP:1;

    uint32_t RXUBR:1;

    uint32_t TXUBR:1;

    uint32_t TUR:1;

    uint32_t RLEX:1;

    uint32_t TFC:1;

    uint32_t TCOMP:1;

    uint32_t :2;

    uint32_t ROVR:1;

    uint32_t HRESP:1;

    uint32_t PFNZ:1;

    uint32_t PTZ:1;

    uint32_t PFTR:1;

    uint32_t EXINT:1;

    uint32_t :2;

    uint32_t DRQFR:1;

    uint32_t SFR:1;

    uint32_t DRQFT:1;

    uint32_t SFT:1;

    uint32_t PDRQFR:1;

    uint32_t PDRSFR:1;

    uint32_t PDRQFT:1;

    uint32_t PDRSFT:1;

    uint32_t SRI:1;

    uint32_t :1;

    uint32_t WOL:1;

    uint32_t TSUCMP:1;

    uint32_t :2;

  } bit;

  uint32_t reg;

} GMAC_IDR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_IDR_OFFSET             0x02C

#define GMAC_IDR_MFS_Pos            0

#define GMAC_IDR_MFS                (_U_(0x1) << GMAC_IDR_MFS_Pos)

#define GMAC_IDR_RCOMP_Pos          1

#define GMAC_IDR_RCOMP              (_U_(0x1) << GMAC_IDR_RCOMP_Pos)

#define GMAC_IDR_RXUBR_Pos          2

#define GMAC_IDR_RXUBR              (_U_(0x1) << GMAC_IDR_RXUBR_Pos)

#define GMAC_IDR_TXUBR_Pos          3

#define GMAC_IDR_TXUBR              (_U_(0x1) << GMAC_IDR_TXUBR_Pos)

#define GMAC_IDR_TUR_Pos            4

#define GMAC_IDR_TUR                (_U_(0x1) << GMAC_IDR_TUR_Pos)

#define GMAC_IDR_RLEX_Pos           5

#define GMAC_IDR_RLEX               (_U_(0x1) << GMAC_IDR_RLEX_Pos)

#define GMAC_IDR_TFC_Pos            6

#define GMAC_IDR_TFC                (_U_(0x1) << GMAC_IDR_TFC_Pos)

#define GMAC_IDR_TCOMP_Pos          7

#define GMAC_IDR_TCOMP              (_U_(0x1) << GMAC_IDR_TCOMP_Pos)

#define GMAC_IDR_ROVR_Pos           10

#define GMAC_IDR_ROVR               (_U_(0x1) << GMAC_IDR_ROVR_Pos)

#define GMAC_IDR_HRESP_Pos          11

#define GMAC_IDR_HRESP              (_U_(0x1) << GMAC_IDR_HRESP_Pos)

#define GMAC_IDR_PFNZ_Pos           12

#define GMAC_IDR_PFNZ               (_U_(0x1) << GMAC_IDR_PFNZ_Pos)

#define GMAC_IDR_PTZ_Pos            13

#define GMAC_IDR_PTZ                (_U_(0x1) << GMAC_IDR_PTZ_Pos)

#define GMAC_IDR_PFTR_Pos           14

#define GMAC_IDR_PFTR               (_U_(0x1) << GMAC_IDR_PFTR_Pos)

#define GMAC_IDR_EXINT_Pos          15

#define GMAC_IDR_EXINT              (_U_(0x1) << GMAC_IDR_EXINT_Pos)

#define GMAC_IDR_DRQFR_Pos          18

#define GMAC_IDR_DRQFR              (_U_(0x1) << GMAC_IDR_DRQFR_Pos)

#define GMAC_IDR_SFR_Pos            19

#define GMAC_IDR_SFR                (_U_(0x1) << GMAC_IDR_SFR_Pos)

#define GMAC_IDR_DRQFT_Pos          20

#define GMAC_IDR_DRQFT              (_U_(0x1) << GMAC_IDR_DRQFT_Pos)

#define GMAC_IDR_SFT_Pos            21

#define GMAC_IDR_SFT                (_U_(0x1) << GMAC_IDR_SFT_Pos)

#define GMAC_IDR_PDRQFR_Pos         22

#define GMAC_IDR_PDRQFR             (_U_(0x1) << GMAC_IDR_PDRQFR_Pos)

#define GMAC_IDR_PDRSFR_Pos         23

#define GMAC_IDR_PDRSFR             (_U_(0x1) << GMAC_IDR_PDRSFR_Pos)

#define GMAC_IDR_PDRQFT_Pos         24

#define GMAC_IDR_PDRQFT             (_U_(0x1) << GMAC_IDR_PDRQFT_Pos)

#define GMAC_IDR_PDRSFT_Pos         25

#define GMAC_IDR_PDRSFT             (_U_(0x1) << GMAC_IDR_PDRSFT_Pos)

#define GMAC_IDR_SRI_Pos            26

#define GMAC_IDR_SRI                (_U_(0x1) << GMAC_IDR_SRI_Pos)

#define GMAC_IDR_WOL_Pos            28

#define GMAC_IDR_WOL                (_U_(0x1) << GMAC_IDR_WOL_Pos)

#define GMAC_IDR_TSUCMP_Pos         29

#define GMAC_IDR_TSUCMP             (_U_(0x1) << GMAC_IDR_TSUCMP_Pos)

#define GMAC_IDR_MASK               _U_(0x37FCFCFF)

/* -------- GMAC_IMR : (GMAC Offset: 0x030) (R/  32) Interrupt Mask Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t MFS:1;

    uint32_t RCOMP:1;

    uint32_t RXUBR:1;

    uint32_t TXUBR:1;

    uint32_t TUR:1;

    uint32_t RLEX:1;

    uint32_t TFC:1;

    uint32_t TCOMP:1;

    uint32_t :2;

    uint32_t ROVR:1;

    uint32_t HRESP:1;

    uint32_t PFNZ:1;

    uint32_t PTZ:1;

    uint32_t PFTR:1;

    uint32_t EXINT:1;

    uint32_t :2;

    uint32_t DRQFR:1;

    uint32_t SFR:1;

    uint32_t DRQFT:1;

    uint32_t SFT:1;

    uint32_t PDRQFR:1;

    uint32_t PDRSFR:1;

    uint32_t PDRQFT:1;

    uint32_t PDRSFT:1;

    uint32_t SRI:1;

    uint32_t :1;

    uint32_t WOL:1;

    uint32_t TSUCMP:1;

    uint32_t :2;

  } bit;

  uint32_t reg;

} GMAC_IMR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_IMR_OFFSET             0x030

#define GMAC_IMR_RESETVALUE         _U_(0x3FFFFFFF)

#define GMAC_IMR_MFS_Pos            0

#define GMAC_IMR_MFS                (_U_(0x1) << GMAC_IMR_MFS_Pos)

#define GMAC_IMR_RCOMP_Pos          1

#define GMAC_IMR_RCOMP              (_U_(0x1) << GMAC_IMR_RCOMP_Pos)

#define GMAC_IMR_RXUBR_Pos          2

#define GMAC_IMR_RXUBR              (_U_(0x1) << GMAC_IMR_RXUBR_Pos)

#define GMAC_IMR_TXUBR_Pos          3

#define GMAC_IMR_TXUBR              (_U_(0x1) << GMAC_IMR_TXUBR_Pos)

#define GMAC_IMR_TUR_Pos            4

#define GMAC_IMR_TUR                (_U_(0x1) << GMAC_IMR_TUR_Pos)

#define GMAC_IMR_RLEX_Pos           5

#define GMAC_IMR_RLEX               (_U_(0x1) << GMAC_IMR_RLEX_Pos)

#define GMAC_IMR_TFC_Pos            6

#define GMAC_IMR_TFC                (_U_(0x1) << GMAC_IMR_TFC_Pos)

#define GMAC_IMR_TCOMP_Pos          7

#define GMAC_IMR_TCOMP              (_U_(0x1) << GMAC_IMR_TCOMP_Pos)

#define GMAC_IMR_ROVR_Pos           10

#define GMAC_IMR_ROVR               (_U_(0x1) << GMAC_IMR_ROVR_Pos)

#define GMAC_IMR_HRESP_Pos          11

#define GMAC_IMR_HRESP              (_U_(0x1) << GMAC_IMR_HRESP_Pos)

#define GMAC_IMR_PFNZ_Pos           12

#define GMAC_IMR_PFNZ               (_U_(0x1) << GMAC_IMR_PFNZ_Pos)

#define GMAC_IMR_PTZ_Pos            13

#define GMAC_IMR_PTZ                (_U_(0x1) << GMAC_IMR_PTZ_Pos)

#define GMAC_IMR_PFTR_Pos           14

#define GMAC_IMR_PFTR               (_U_(0x1) << GMAC_IMR_PFTR_Pos)

#define GMAC_IMR_EXINT_Pos          15

#define GMAC_IMR_EXINT              (_U_(0x1) << GMAC_IMR_EXINT_Pos)

#define GMAC_IMR_DRQFR_Pos          18

#define GMAC_IMR_DRQFR              (_U_(0x1) << GMAC_IMR_DRQFR_Pos)

#define GMAC_IMR_SFR_Pos            19

#define GMAC_IMR_SFR                (_U_(0x1) << GMAC_IMR_SFR_Pos)

#define GMAC_IMR_DRQFT_Pos          20

#define GMAC_IMR_DRQFT              (_U_(0x1) << GMAC_IMR_DRQFT_Pos)

#define GMAC_IMR_SFT_Pos            21

#define GMAC_IMR_SFT                (_U_(0x1) << GMAC_IMR_SFT_Pos)

#define GMAC_IMR_PDRQFR_Pos         22

#define GMAC_IMR_PDRQFR             (_U_(0x1) << GMAC_IMR_PDRQFR_Pos)

#define GMAC_IMR_PDRSFR_Pos         23

#define GMAC_IMR_PDRSFR             (_U_(0x1) << GMAC_IMR_PDRSFR_Pos)

#define GMAC_IMR_PDRQFT_Pos         24

#define GMAC_IMR_PDRQFT             (_U_(0x1) << GMAC_IMR_PDRQFT_Pos)

#define GMAC_IMR_PDRSFT_Pos         25

#define GMAC_IMR_PDRSFT             (_U_(0x1) << GMAC_IMR_PDRSFT_Pos)

#define GMAC_IMR_SRI_Pos            26

#define GMAC_IMR_SRI                (_U_(0x1) << GMAC_IMR_SRI_Pos)

#define GMAC_IMR_WOL_Pos            28

#define GMAC_IMR_WOL                (_U_(0x1) << GMAC_IMR_WOL_Pos)

#define GMAC_IMR_TSUCMP_Pos         29

#define GMAC_IMR_TSUCMP             (_U_(0x1) << GMAC_IMR_TSUCMP_Pos)

#define GMAC_IMR_MASK               _U_(0x37FCFCFF)

/* -------- GMAC_MAN : (GMAC Offset: 0x034) (R/W 32) PHY Maintenance Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t DATA:16;

    uint32_t WTN:2;

    uint32_t REGA:5;

    uint32_t PHYA:5;

    uint32_t OP:2;

    uint32_t CLTTO:1;

    uint32_t WZO:1;

  } bit;

  uint32_t reg;

} GMAC_MAN_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_MAN_OFFSET             0x034

#define GMAC_MAN_RESETVALUE         _U_(0x00000000)

#define GMAC_MAN_DATA_Pos           0

#define GMAC_MAN_DATA_Msk           (_U_(0xFFFF) << GMAC_MAN_DATA_Pos)

#define GMAC_MAN_DATA(value)        (GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))

#define GMAC_MAN_WTN_Pos            16

#define GMAC_MAN_WTN_Msk            (_U_(0x3) << GMAC_MAN_WTN_Pos)

#define GMAC_MAN_WTN(value)         (GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))

#define GMAC_MAN_REGA_Pos           18

#define GMAC_MAN_REGA_Msk           (_U_(0x1F) << GMAC_MAN_REGA_Pos)

#define GMAC_MAN_REGA(value)        (GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))

#define GMAC_MAN_PHYA_Pos           23

#define GMAC_MAN_PHYA_Msk           (_U_(0x1F) << GMAC_MAN_PHYA_Pos)

#define GMAC_MAN_PHYA(value)        (GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))

#define GMAC_MAN_OP_Pos             28

#define GMAC_MAN_OP_Msk             (_U_(0x3) << GMAC_MAN_OP_Pos)

#define GMAC_MAN_OP(value)          (GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))

#define GMAC_MAN_CLTTO_Pos          30

#define GMAC_MAN_CLTTO              (_U_(0x1) << GMAC_MAN_CLTTO_Pos)

#define GMAC_MAN_WZO_Pos            31

#define GMAC_MAN_WZO                (_U_(0x1) << GMAC_MAN_WZO_Pos)

#define GMAC_MAN_MASK               _U_(0xFFFFFFFF)

/* -------- GMAC_RPQ : (GMAC Offset: 0x038) (R/  32) Received Pause Quantum Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RPQ:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_RPQ_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_RPQ_OFFSET             0x038

#define GMAC_RPQ_RESETVALUE         _U_(0x00000000)

#define GMAC_RPQ_RPQ_Pos            0

#define GMAC_RPQ_RPQ_Msk            (_U_(0xFFFF) << GMAC_RPQ_RPQ_Pos)

#define GMAC_RPQ_RPQ(value)         (GMAC_RPQ_RPQ_Msk & ((value) << GMAC_RPQ_RPQ_Pos))

#define GMAC_RPQ_MASK               _U_(0x0000FFFF)

/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) (R/W 32) Transmit Pause Quantum Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TPQ:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_TPQ_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TPQ_OFFSET             0x03C

#define GMAC_TPQ_RESETVALUE         _U_(0x0000FFFF)

#define GMAC_TPQ_TPQ_Pos            0

#define GMAC_TPQ_TPQ_Msk            (_U_(0xFFFF) << GMAC_TPQ_TPQ_Pos)

#define GMAC_TPQ_TPQ(value)         (GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))

#define GMAC_TPQ_MASK               _U_(0x0000FFFF)

/* -------- GMAC_TPSF : (GMAC Offset: 0x040) (R/W 32) TX partial store and forward Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TPB1ADR:10;

    uint32_t :21;

    uint32_t ENTXP:1;

  } bit;

  uint32_t reg;

} GMAC_TPSF_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TPSF_OFFSET            0x040

#define GMAC_TPSF_RESETVALUE        _U_(0x000003FF)

#define GMAC_TPSF_TPB1ADR_Pos       0

#define GMAC_TPSF_TPB1ADR_Msk       (_U_(0x3FF) << GMAC_TPSF_TPB1ADR_Pos)

#define GMAC_TPSF_TPB1ADR(value)    (GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))

#define GMAC_TPSF_ENTXP_Pos         31

#define GMAC_TPSF_ENTXP             (_U_(0x1) << GMAC_TPSF_ENTXP_Pos)

#define GMAC_TPSF_MASK              _U_(0x800003FF)

/* -------- GMAC_RPSF : (GMAC Offset: 0x044) (R/W 32) RX partial store and forward Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RPB1ADR:10;

    uint32_t :21;

    uint32_t ENRXP:1;

  } bit;

  uint32_t reg;

} GMAC_RPSF_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_RPSF_OFFSET            0x044

#define GMAC_RPSF_RESETVALUE        _U_(0x000003FF)

#define GMAC_RPSF_RPB1ADR_Pos       0

#define GMAC_RPSF_RPB1ADR_Msk       (_U_(0x3FF) << GMAC_RPSF_RPB1ADR_Pos)

#define GMAC_RPSF_RPB1ADR(value)    (GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))

#define GMAC_RPSF_ENRXP_Pos         31

#define GMAC_RPSF_ENRXP             (_U_(0x1) << GMAC_RPSF_ENRXP_Pos)

#define GMAC_RPSF_MASK              _U_(0x800003FF)

/* -------- GMAC_RJFML : (GMAC Offset: 0x048) (R/W 32) RX Jumbo Frame Max Length Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t FML:14;

    uint32_t :18;

  } bit;

  uint32_t reg;

} GMAC_RJFML_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_RJFML_OFFSET           0x048

#define GMAC_RJFML_RESETVALUE       _U_(0x00003FFF)

#define GMAC_RJFML_FML_Pos          0

#define GMAC_RJFML_FML_Msk          (_U_(0x3FFF) << GMAC_RJFML_FML_Pos)

#define GMAC_RJFML_FML(value)       (GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))

#define GMAC_RJFML_MASK             _U_(0x00003FFF)

/* -------- GMAC_HRB : (GMAC Offset: 0x080) (R/W 32) Hash Register Bottom [31:0] -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t ADDR:32;

  } bit;

  uint32_t reg;

} GMAC_HRB_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_HRB_OFFSET             0x080

#define GMAC_HRB_RESETVALUE         _U_(0x00000000)

#define GMAC_HRB_ADDR_Pos           0

#define GMAC_HRB_ADDR_Msk           (_U_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos)

#define GMAC_HRB_ADDR(value)        (GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))

#define GMAC_HRB_MASK               _U_(0xFFFFFFFF)

/* -------- GMAC_HRT : (GMAC Offset: 0x084) (R/W 32) Hash Register Top [63:32] -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t ADDR:32;

  } bit;

  uint32_t reg;

} GMAC_HRT_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_HRT_OFFSET             0x084

#define GMAC_HRT_RESETVALUE         _U_(0x00000000)

#define GMAC_HRT_ADDR_Pos           0

#define GMAC_HRT_ADDR_Msk           (_U_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos)

#define GMAC_HRT_ADDR(value)        (GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))

#define GMAC_HRT_MASK               _U_(0xFFFFFFFF)

/* -------- GMAC_SAB : (GMAC Offset: 0x088) (R/W 32) SA Specific Address Bottom [31:0] Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t ADDR:32;

  } bit;

  uint32_t reg;

} GMAC_SAB_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_SAB_OFFSET             0x088

#define GMAC_SAB_RESETVALUE         _U_(0x00000000)

#define GMAC_SAB_ADDR_Pos           0

#define GMAC_SAB_ADDR_Msk           (_U_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos)

#define GMAC_SAB_ADDR(value)        (GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))

#define GMAC_SAB_MASK               _U_(0xFFFFFFFF)

/* -------- GMAC_SAT : (GMAC Offset: 0x08C) (R/W 32) SA Specific Address Top [47:32] Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t ADDR:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_SAT_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_SAT_OFFSET             0x08C

#define GMAC_SAT_RESETVALUE         _U_(0x00000000)

#define GMAC_SAT_ADDR_Pos           0

#define GMAC_SAT_ADDR_Msk           (_U_(0xFFFF) << GMAC_SAT_ADDR_Pos)

#define GMAC_SAT_ADDR(value)        (GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))

#define GMAC_SAT_MASK               _U_(0x0000FFFF)

/* -------- GMAC_TIDM : (GMAC Offset: 0x0A8) (R/W 32) Type ID Match Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TID:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_TIDM_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TIDM_OFFSET            0x0A8

#define GMAC_TIDM_RESETVALUE        _U_(0x00000000)

#define GMAC_TIDM_TID_Pos           0

#define GMAC_TIDM_TID_Msk           (_U_(0xFFFF) << GMAC_TIDM_TID_Pos)

#define GMAC_TIDM_TID(value)        (GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos))

#define GMAC_TIDM_MASK              _U_(0x0000FFFF)

/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) (R/W 32) Wake on LAN -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t IP:16;

    uint32_t MAG:1;

    uint32_t ARP:1;

    uint32_t SA1:1;

    uint32_t MTI:1;

    uint32_t :12;

  } bit;

  uint32_t reg;

} GMAC_WOL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_WOL_OFFSET             0x0B8

#define GMAC_WOL_RESETVALUE         _U_(0x00000000)

#define GMAC_WOL_IP_Pos             0

#define GMAC_WOL_IP_Msk             (_U_(0xFFFF) << GMAC_WOL_IP_Pos)

#define GMAC_WOL_IP(value)          (GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))

#define GMAC_WOL_MAG_Pos            16

#define GMAC_WOL_MAG                (_U_(0x1) << GMAC_WOL_MAG_Pos)

#define GMAC_WOL_ARP_Pos            17

#define GMAC_WOL_ARP                (_U_(0x1) << GMAC_WOL_ARP_Pos)

#define GMAC_WOL_SA1_Pos            18

#define GMAC_WOL_SA1                (_U_(0x1) << GMAC_WOL_SA1_Pos)

#define GMAC_WOL_MTI_Pos            19

#define GMAC_WOL_MTI                (_U_(0x1) << GMAC_WOL_MTI_Pos)

#define GMAC_WOL_MASK               _U_(0x000FFFFF)

/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) (R/W 32) IPG Stretch Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t FL:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_IPGS_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_IPGS_OFFSET            0x0BC

#define GMAC_IPGS_RESETVALUE        _U_(0x00000000)

#define GMAC_IPGS_FL_Pos            0

#define GMAC_IPGS_FL_Msk            (_U_(0xFFFF) << GMAC_IPGS_FL_Pos)

#define GMAC_IPGS_FL(value)         (GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))

#define GMAC_IPGS_MASK              _U_(0x0000FFFF)

/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) (R/W 32) Stacked VLAN Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t VLAN_TYPE:16;

    uint32_t :15;

    uint32_t ESVLAN:1;

  } bit;

  uint32_t reg;

} GMAC_SVLAN_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_SVLAN_OFFSET           0x0C0

#define GMAC_SVLAN_RESETVALUE       _U_(0x00000000)

#define GMAC_SVLAN_VLAN_TYPE_Pos    0

#define GMAC_SVLAN_VLAN_TYPE_Msk    (_U_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos)

#define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))

#define GMAC_SVLAN_ESVLAN_Pos       31

#define GMAC_SVLAN_ESVLAN           (_U_(0x1) << GMAC_SVLAN_ESVLAN_Pos)

#define GMAC_SVLAN_MASK             _U_(0x8000FFFF)

/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) (R/W 32) Transmit PFC Pause Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t PEV:8;

    uint32_t PQ:8;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_TPFCP_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TPFCP_OFFSET           0x0C4

#define GMAC_TPFCP_RESETVALUE       _U_(0x00000000)

#define GMAC_TPFCP_PEV_Pos          0

#define GMAC_TPFCP_PEV_Msk          (_U_(0xFF) << GMAC_TPFCP_PEV_Pos)

#define GMAC_TPFCP_PEV(value)       (GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))

#define GMAC_TPFCP_PQ_Pos           8

#define GMAC_TPFCP_PQ_Msk           (_U_(0xFF) << GMAC_TPFCP_PQ_Pos)

#define GMAC_TPFCP_PQ(value)        (GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))

#define GMAC_TPFCP_MASK             _U_(0x0000FFFF)

/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) (R/W 32) Specific Address 1 Mask Bottom [31:0] Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t ADDR:32;

  } bit;

  uint32_t reg;

} GMAC_SAMB1_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_SAMB1_OFFSET           0x0C8

#define GMAC_SAMB1_RESETVALUE       _U_(0x00000000)

#define GMAC_SAMB1_ADDR_Pos         0

#define GMAC_SAMB1_ADDR_Msk         (_U_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos)

#define GMAC_SAMB1_ADDR(value)      (GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))

#define GMAC_SAMB1_MASK             _U_(0xFFFFFFFF)

/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) (R/W 32) Specific Address 1 Mask Top [47:32] Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t ADDR:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_SAMT1_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_SAMT1_OFFSET           0x0CC

#define GMAC_SAMT1_RESETVALUE       _U_(0x00000000)

#define GMAC_SAMT1_ADDR_Pos         0

#define GMAC_SAMT1_ADDR_Msk         (_U_(0xFFFF) << GMAC_SAMT1_ADDR_Pos)

#define GMAC_SAMT1_ADDR(value)      (GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))

#define GMAC_SAMT1_MASK             _U_(0x0000FFFF)

/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) (R/W 32) Tsu timer comparison nanoseconds Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NANOSEC:21;

    uint32_t :11;

  } bit;

  uint32_t reg;

} GMAC_NSC_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_NSC_OFFSET             0x0DC

#define GMAC_NSC_RESETVALUE         _U_(0x00000000)

#define GMAC_NSC_NANOSEC_Pos        0

#define GMAC_NSC_NANOSEC_Msk        (_U_(0x1FFFFF) << GMAC_NSC_NANOSEC_Pos)

#define GMAC_NSC_NANOSEC(value)     (GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))

#define GMAC_NSC_MASK               _U_(0x001FFFFF)

/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) (R/W 32) Tsu timer second comparison Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t SEC:32;

  } bit;

  uint32_t reg;

} GMAC_SCL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_SCL_OFFSET             0x0E0

#define GMAC_SCL_RESETVALUE         _U_(0x00000000)

#define GMAC_SCL_SEC_Pos            0

#define GMAC_SCL_SEC_Msk            (_U_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos)

#define GMAC_SCL_SEC(value)         (GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))

#define GMAC_SCL_MASK               _U_(0xFFFFFFFF)

/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) (R/W 32) Tsu timer second comparison Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t SEC:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_SCH_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_SCH_OFFSET             0x0E4

#define GMAC_SCH_RESETVALUE         _U_(0x00000000)

#define GMAC_SCH_SEC_Pos            0

#define GMAC_SCH_SEC_Msk            (_U_(0xFFFF) << GMAC_SCH_SEC_Pos)

#define GMAC_SCH_SEC(value)         (GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))

#define GMAC_SCH_MASK               _U_(0x0000FFFF)

/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) (R/  32) PTP Event Frame Transmitted Seconds High Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_EFTSH_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_EFTSH_OFFSET           0x0E8

#define GMAC_EFTSH_RESETVALUE       _U_(0x00000000)

#define GMAC_EFTSH_RUD_Pos          0

#define GMAC_EFTSH_RUD_Msk          (_U_(0xFFFF) << GMAC_EFTSH_RUD_Pos)

#define GMAC_EFTSH_RUD(value)       (GMAC_EFTSH_RUD_Msk & ((value) << GMAC_EFTSH_RUD_Pos))

#define GMAC_EFTSH_MASK             _U_(0x0000FFFF)

/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) (R/  32) PTP Event Frame Received Seconds High Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_EFRSH_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_EFRSH_OFFSET           0x0EC

#define GMAC_EFRSH_RESETVALUE       _U_(0x00000000)

#define GMAC_EFRSH_RUD_Pos          0

#define GMAC_EFRSH_RUD_Msk          (_U_(0xFFFF) << GMAC_EFRSH_RUD_Pos)

#define GMAC_EFRSH_RUD(value)       (GMAC_EFRSH_RUD_Msk & ((value) << GMAC_EFRSH_RUD_Pos))

#define GMAC_EFRSH_MASK             _U_(0x0000FFFF)

/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) (R/  32) PTP Peer Event Frame Transmitted Seconds High Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_PEFTSH_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_PEFTSH_OFFSET          0x0F0

#define GMAC_PEFTSH_RESETVALUE      _U_(0x00000000)

#define GMAC_PEFTSH_RUD_Pos         0

#define GMAC_PEFTSH_RUD_Msk         (_U_(0xFFFF) << GMAC_PEFTSH_RUD_Pos)

#define GMAC_PEFTSH_RUD(value)      (GMAC_PEFTSH_RUD_Msk & ((value) << GMAC_PEFTSH_RUD_Pos))

#define GMAC_PEFTSH_MASK            _U_(0x0000FFFF)

/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) (R/  32) PTP Peer Event Frame Received Seconds High Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_PEFRSH_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_PEFRSH_OFFSET          0x0F4

#define GMAC_PEFRSH_RESETVALUE      _U_(0x00000000)

#define GMAC_PEFRSH_RUD_Pos         0

#define GMAC_PEFRSH_RUD_Msk         (_U_(0xFFFF) << GMAC_PEFRSH_RUD_Pos)

#define GMAC_PEFRSH_RUD(value)      (GMAC_PEFRSH_RUD_Msk & ((value) << GMAC_PEFRSH_RUD_Pos))

#define GMAC_PEFRSH_MASK            _U_(0x0000FFFF)

/* -------- GMAC_OTLO : (GMAC Offset: 0x100) (R/  32) Octets Transmitted [31:0] Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TXO:32;

  } bit;

  uint32_t reg;

} GMAC_OTLO_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_OTLO_OFFSET            0x100

#define GMAC_OTLO_RESETVALUE        _U_(0x00000000)

#define GMAC_OTLO_TXO_Pos           0

#define GMAC_OTLO_TXO_Msk           (_U_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos)

#define GMAC_OTLO_TXO(value)        (GMAC_OTLO_TXO_Msk & ((value) << GMAC_OTLO_TXO_Pos))

#define GMAC_OTLO_MASK              _U_(0xFFFFFFFF)

/* -------- GMAC_OTHI : (GMAC Offset: 0x104) (R/  32) Octets Transmitted [47:32] Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TXO:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_OTHI_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_OTHI_OFFSET            0x104

#define GMAC_OTHI_RESETVALUE        _U_(0x00000000)

#define GMAC_OTHI_TXO_Pos           0

#define GMAC_OTHI_TXO_Msk           (_U_(0xFFFF) << GMAC_OTHI_TXO_Pos)

#define GMAC_OTHI_TXO(value)        (GMAC_OTHI_TXO_Msk & ((value) << GMAC_OTHI_TXO_Pos))

#define GMAC_OTHI_MASK              _U_(0x0000FFFF)

/* -------- GMAC_FT : (GMAC Offset: 0x108) (R/  32) Frames Transmitted Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t FTX:32;

  } bit;

  uint32_t reg;

} GMAC_FT_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_FT_OFFSET              0x108

#define GMAC_FT_RESETVALUE          _U_(0x00000000)

#define GMAC_FT_FTX_Pos             0

#define GMAC_FT_FTX_Msk             (_U_(0xFFFFFFFF) << GMAC_FT_FTX_Pos)

#define GMAC_FT_FTX(value)          (GMAC_FT_FTX_Msk & ((value) << GMAC_FT_FTX_Pos))

#define GMAC_FT_MASK                _U_(0xFFFFFFFF)

/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) (R/  32) Broadcast Frames Transmitted Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t BFTX:32;

  } bit;

  uint32_t reg;

} GMAC_BCFT_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_BCFT_OFFSET            0x10C

#define GMAC_BCFT_RESETVALUE        _U_(0x00000000)

#define GMAC_BCFT_BFTX_Pos          0

#define GMAC_BCFT_BFTX_Msk          (_U_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos)

#define GMAC_BCFT_BFTX(value)       (GMAC_BCFT_BFTX_Msk & ((value) << GMAC_BCFT_BFTX_Pos))

#define GMAC_BCFT_MASK              _U_(0xFFFFFFFF)

/* -------- GMAC_MFT : (GMAC Offset: 0x110) (R/  32) Multicast Frames Transmitted Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t MFTX:32;

  } bit;

  uint32_t reg;

} GMAC_MFT_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_MFT_OFFSET             0x110

#define GMAC_MFT_RESETVALUE         _U_(0x00000000)

#define GMAC_MFT_MFTX_Pos           0

#define GMAC_MFT_MFTX_Msk           (_U_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos)

#define GMAC_MFT_MFTX(value)        (GMAC_MFT_MFTX_Msk & ((value) << GMAC_MFT_MFTX_Pos))

#define GMAC_MFT_MASK               _U_(0xFFFFFFFF)

/* -------- GMAC_PFT : (GMAC Offset: 0x114) (R/  32) Pause Frames Transmitted Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t PFTX:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_PFT_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_PFT_OFFSET             0x114

#define GMAC_PFT_RESETVALUE         _U_(0x00000000)

#define GMAC_PFT_PFTX_Pos           0

#define GMAC_PFT_PFTX_Msk           (_U_(0xFFFF) << GMAC_PFT_PFTX_Pos)

#define GMAC_PFT_PFTX(value)        (GMAC_PFT_PFTX_Msk & ((value) << GMAC_PFT_PFTX_Pos))

#define GMAC_PFT_MASK               _U_(0x0000FFFF)

/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) (R/  32) 64 Byte Frames Transmitted Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFTX:32;

  } bit;

  uint32_t reg;

} GMAC_BFT64_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_BFT64_OFFSET           0x118

#define GMAC_BFT64_RESETVALUE       _U_(0x00000000)

#define GMAC_BFT64_NFTX_Pos         0

#define GMAC_BFT64_NFTX_Msk         (_U_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos)

#define GMAC_BFT64_NFTX(value)      (GMAC_BFT64_NFTX_Msk & ((value) << GMAC_BFT64_NFTX_Pos))

#define GMAC_BFT64_MASK             _U_(0xFFFFFFFF)

/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) (R/  32) 65 to 127 Byte Frames Transmitted Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFTX:32;

  } bit;

  uint32_t reg;

} GMAC_TBFT127_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TBFT127_OFFSET         0x11C

#define GMAC_TBFT127_RESETVALUE     _U_(0x00000000)

#define GMAC_TBFT127_NFTX_Pos       0

#define GMAC_TBFT127_NFTX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos)

#define GMAC_TBFT127_NFTX(value)    (GMAC_TBFT127_NFTX_Msk & ((value) << GMAC_TBFT127_NFTX_Pos))

#define GMAC_TBFT127_MASK           _U_(0xFFFFFFFF)

/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) (R/  32) 128 to 255 Byte Frames Transmitted Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFTX:32;

  } bit;

  uint32_t reg;

} GMAC_TBFT255_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TBFT255_OFFSET         0x120

#define GMAC_TBFT255_RESETVALUE     _U_(0x00000000)

#define GMAC_TBFT255_NFTX_Pos       0

#define GMAC_TBFT255_NFTX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos)

#define GMAC_TBFT255_NFTX(value)    (GMAC_TBFT255_NFTX_Msk & ((value) << GMAC_TBFT255_NFTX_Pos))

#define GMAC_TBFT255_MASK           _U_(0xFFFFFFFF)

/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) (R/  32) 256 to 511 Byte Frames Transmitted Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFTX:32;

  } bit;

  uint32_t reg;

} GMAC_TBFT511_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TBFT511_OFFSET         0x124

#define GMAC_TBFT511_RESETVALUE     _U_(0x00000000)

#define GMAC_TBFT511_NFTX_Pos       0

#define GMAC_TBFT511_NFTX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos)

#define GMAC_TBFT511_NFTX(value)    (GMAC_TBFT511_NFTX_Msk & ((value) << GMAC_TBFT511_NFTX_Pos))

#define GMAC_TBFT511_MASK           _U_(0xFFFFFFFF)

/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) (R/  32) 512 to 1023 Byte Frames Transmitted Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFTX:32;

  } bit;

  uint32_t reg;

} GMAC_TBFT1023_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TBFT1023_OFFSET        0x128

#define GMAC_TBFT1023_RESETVALUE    _U_(0x00000000)

#define GMAC_TBFT1023_NFTX_Pos      0

#define GMAC_TBFT1023_NFTX_Msk      (_U_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos)

#define GMAC_TBFT1023_NFTX(value)   (GMAC_TBFT1023_NFTX_Msk & ((value) << GMAC_TBFT1023_NFTX_Pos))

#define GMAC_TBFT1023_MASK          _U_(0xFFFFFFFF)

/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) (R/  32) 1024 to 1518 Byte Frames Transmitted Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFTX:32;

  } bit;

  uint32_t reg;

} GMAC_TBFT1518_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TBFT1518_OFFSET        0x12C

#define GMAC_TBFT1518_RESETVALUE    _U_(0x00000000)

#define GMAC_TBFT1518_NFTX_Pos      0

#define GMAC_TBFT1518_NFTX_Msk      (_U_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos)

#define GMAC_TBFT1518_NFTX(value)   (GMAC_TBFT1518_NFTX_Msk & ((value) << GMAC_TBFT1518_NFTX_Pos))

#define GMAC_TBFT1518_MASK          _U_(0xFFFFFFFF)

/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) (R/  32) Greater Than 1518 Byte Frames Transmitted Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFTX:32;

  } bit;

  uint32_t reg;

} GMAC_GTBFT1518_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_GTBFT1518_OFFSET       0x130

#define GMAC_GTBFT1518_RESETVALUE   _U_(0x00000000)

#define GMAC_GTBFT1518_NFTX_Pos     0

#define GMAC_GTBFT1518_NFTX_Msk     (_U_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos)

#define GMAC_GTBFT1518_NFTX(value)  (GMAC_GTBFT1518_NFTX_Msk & ((value) << GMAC_GTBFT1518_NFTX_Pos))

#define GMAC_GTBFT1518_MASK         _U_(0xFFFFFFFF)

/* -------- GMAC_TUR : (GMAC Offset: 0x134) (R/  32) Transmit Underruns Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TXUNR:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_TUR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TUR_OFFSET             0x134

#define GMAC_TUR_RESETVALUE         _U_(0x00000000)

#define GMAC_TUR_TXUNR_Pos          0

#define GMAC_TUR_TXUNR_Msk          (_U_(0x3FF) << GMAC_TUR_TXUNR_Pos)

#define GMAC_TUR_TXUNR(value)       (GMAC_TUR_TXUNR_Msk & ((value) << GMAC_TUR_TXUNR_Pos))

#define GMAC_TUR_MASK               _U_(0x000003FF)

/* -------- GMAC_SCF : (GMAC Offset: 0x138) (R/  32) Single Collision Frames Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t SCOL:18;

    uint32_t :14;

  } bit;

  uint32_t reg;

} GMAC_SCF_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_SCF_OFFSET             0x138

#define GMAC_SCF_RESETVALUE         _U_(0x00000000)

#define GMAC_SCF_SCOL_Pos           0

#define GMAC_SCF_SCOL_Msk           (_U_(0x3FFFF) << GMAC_SCF_SCOL_Pos)

#define GMAC_SCF_SCOL(value)        (GMAC_SCF_SCOL_Msk & ((value) << GMAC_SCF_SCOL_Pos))

#define GMAC_SCF_MASK               _U_(0x0003FFFF)

/* -------- GMAC_MCF : (GMAC Offset: 0x13C) (R/  32) Multiple Collision Frames Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t MCOL:18;

    uint32_t :14;

  } bit;

  uint32_t reg;

} GMAC_MCF_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_MCF_OFFSET             0x13C

#define GMAC_MCF_RESETVALUE         _U_(0x00000000)

#define GMAC_MCF_MCOL_Pos           0

#define GMAC_MCF_MCOL_Msk           (_U_(0x3FFFF) << GMAC_MCF_MCOL_Pos)

#define GMAC_MCF_MCOL(value)        (GMAC_MCF_MCOL_Msk & ((value) << GMAC_MCF_MCOL_Pos))

#define GMAC_MCF_MASK               _U_(0x0003FFFF)

/* -------- GMAC_EC : (GMAC Offset: 0x140) (R/  32) Excessive Collisions Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t XCOL:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_EC_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_EC_OFFSET              0x140

#define GMAC_EC_RESETVALUE          _U_(0x00000000)

#define GMAC_EC_XCOL_Pos            0

#define GMAC_EC_XCOL_Msk            (_U_(0x3FF) << GMAC_EC_XCOL_Pos)

#define GMAC_EC_XCOL(value)         (GMAC_EC_XCOL_Msk & ((value) << GMAC_EC_XCOL_Pos))

#define GMAC_EC_MASK                _U_(0x000003FF)

/* -------- GMAC_LC : (GMAC Offset: 0x144) (R/  32) Late Collisions Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t LCOL:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_LC_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_LC_OFFSET              0x144

#define GMAC_LC_RESETVALUE          _U_(0x00000000)

#define GMAC_LC_LCOL_Pos            0

#define GMAC_LC_LCOL_Msk            (_U_(0x3FF) << GMAC_LC_LCOL_Pos)

#define GMAC_LC_LCOL(value)         (GMAC_LC_LCOL_Msk & ((value) << GMAC_LC_LCOL_Pos))

#define GMAC_LC_MASK                _U_(0x000003FF)

/* -------- GMAC_DTF : (GMAC Offset: 0x148) (R/  32) Deferred Transmission Frames Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t DEFT:18;

    uint32_t :14;

  } bit;

  uint32_t reg;

} GMAC_DTF_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_DTF_OFFSET             0x148

#define GMAC_DTF_RESETVALUE         _U_(0x00000000)

#define GMAC_DTF_DEFT_Pos           0

#define GMAC_DTF_DEFT_Msk           (_U_(0x3FFFF) << GMAC_DTF_DEFT_Pos)

#define GMAC_DTF_DEFT(value)        (GMAC_DTF_DEFT_Msk & ((value) << GMAC_DTF_DEFT_Pos))

#define GMAC_DTF_MASK               _U_(0x0003FFFF)

/* -------- GMAC_CSE : (GMAC Offset: 0x14C) (R/  32) Carrier Sense Errors Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t CSR:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_CSE_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_CSE_OFFSET             0x14C

#define GMAC_CSE_RESETVALUE         _U_(0x00000000)

#define GMAC_CSE_CSR_Pos            0

#define GMAC_CSE_CSR_Msk            (_U_(0x3FF) << GMAC_CSE_CSR_Pos)

#define GMAC_CSE_CSR(value)         (GMAC_CSE_CSR_Msk & ((value) << GMAC_CSE_CSR_Pos))

#define GMAC_CSE_MASK               _U_(0x000003FF)

/* -------- GMAC_ORLO : (GMAC Offset: 0x150) (R/  32) Octets Received [31:0] Received -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RXO:32;

  } bit;

  uint32_t reg;

} GMAC_ORLO_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_ORLO_OFFSET            0x150

#define GMAC_ORLO_RESETVALUE        _U_(0x00000000)

#define GMAC_ORLO_RXO_Pos           0

#define GMAC_ORLO_RXO_Msk           (_U_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos)

#define GMAC_ORLO_RXO(value)        (GMAC_ORLO_RXO_Msk & ((value) << GMAC_ORLO_RXO_Pos))

#define GMAC_ORLO_MASK              _U_(0xFFFFFFFF)

/* -------- GMAC_ORHI : (GMAC Offset: 0x154) (R/  32) Octets Received [47:32] Received -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RXO:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_ORHI_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_ORHI_OFFSET            0x154

#define GMAC_ORHI_RESETVALUE        _U_(0x00000000)

#define GMAC_ORHI_RXO_Pos           0

#define GMAC_ORHI_RXO_Msk           (_U_(0xFFFF) << GMAC_ORHI_RXO_Pos)

#define GMAC_ORHI_RXO(value)        (GMAC_ORHI_RXO_Msk & ((value) << GMAC_ORHI_RXO_Pos))

#define GMAC_ORHI_MASK              _U_(0x0000FFFF)

/* -------- GMAC_FR : (GMAC Offset: 0x158) (R/  32) Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t FRX:32;

  } bit;

  uint32_t reg;

} GMAC_FR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_FR_OFFSET              0x158

#define GMAC_FR_RESETVALUE          _U_(0x00000000)

#define GMAC_FR_FRX_Pos             0

#define GMAC_FR_FRX_Msk             (_U_(0xFFFFFFFF) << GMAC_FR_FRX_Pos)

#define GMAC_FR_FRX(value)          (GMAC_FR_FRX_Msk & ((value) << GMAC_FR_FRX_Pos))

#define GMAC_FR_MASK                _U_(0xFFFFFFFF)

/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) (R/  32) Broadcast Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t BFRX:32;

  } bit;

  uint32_t reg;

} GMAC_BCFR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_BCFR_OFFSET            0x15C

#define GMAC_BCFR_RESETVALUE        _U_(0x00000000)

#define GMAC_BCFR_BFRX_Pos          0

#define GMAC_BCFR_BFRX_Msk          (_U_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos)

#define GMAC_BCFR_BFRX(value)       (GMAC_BCFR_BFRX_Msk & ((value) << GMAC_BCFR_BFRX_Pos))

#define GMAC_BCFR_MASK              _U_(0xFFFFFFFF)

/* -------- GMAC_MFR : (GMAC Offset: 0x160) (R/  32) Multicast Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t MFRX:32;

  } bit;

  uint32_t reg;

} GMAC_MFR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_MFR_OFFSET             0x160

#define GMAC_MFR_RESETVALUE         _U_(0x00000000)

#define GMAC_MFR_MFRX_Pos           0

#define GMAC_MFR_MFRX_Msk           (_U_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos)

#define GMAC_MFR_MFRX(value)        (GMAC_MFR_MFRX_Msk & ((value) << GMAC_MFR_MFRX_Pos))

#define GMAC_MFR_MASK               _U_(0xFFFFFFFF)

/* -------- GMAC_PFR : (GMAC Offset: 0x164) (R/  32) Pause Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t PFRX:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_PFR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_PFR_OFFSET             0x164

#define GMAC_PFR_RESETVALUE         _U_(0x00000000)

#define GMAC_PFR_PFRX_Pos           0

#define GMAC_PFR_PFRX_Msk           (_U_(0xFFFF) << GMAC_PFR_PFRX_Pos)

#define GMAC_PFR_PFRX(value)        (GMAC_PFR_PFRX_Msk & ((value) << GMAC_PFR_PFRX_Pos))

#define GMAC_PFR_MASK               _U_(0x0000FFFF)

/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) (R/  32) 64 Byte Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFRX:32;

  } bit;

  uint32_t reg;

} GMAC_BFR64_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_BFR64_OFFSET           0x168

#define GMAC_BFR64_RESETVALUE       _U_(0x00000000)

#define GMAC_BFR64_NFRX_Pos         0

#define GMAC_BFR64_NFRX_Msk         (_U_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos)

#define GMAC_BFR64_NFRX(value)      (GMAC_BFR64_NFRX_Msk & ((value) << GMAC_BFR64_NFRX_Pos))

#define GMAC_BFR64_MASK             _U_(0xFFFFFFFF)

/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) (R/  32) 65 to 127 Byte Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFRX:32;

  } bit;

  uint32_t reg;

} GMAC_TBFR127_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TBFR127_OFFSET         0x16C

#define GMAC_TBFR127_RESETVALUE     _U_(0x00000000)

#define GMAC_TBFR127_NFRX_Pos       0

#define GMAC_TBFR127_NFRX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos)

#define GMAC_TBFR127_NFRX(value)    (GMAC_TBFR127_NFRX_Msk & ((value) << GMAC_TBFR127_NFRX_Pos))

#define GMAC_TBFR127_MASK           _U_(0xFFFFFFFF)

/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) (R/  32) 128 to 255 Byte Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFRX:32;

  } bit;

  uint32_t reg;

} GMAC_TBFR255_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TBFR255_OFFSET         0x170

#define GMAC_TBFR255_RESETVALUE     _U_(0x00000000)

#define GMAC_TBFR255_NFRX_Pos       0

#define GMAC_TBFR255_NFRX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos)

#define GMAC_TBFR255_NFRX(value)    (GMAC_TBFR255_NFRX_Msk & ((value) << GMAC_TBFR255_NFRX_Pos))

#define GMAC_TBFR255_MASK           _U_(0xFFFFFFFF)

/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) (R/  32) 256 to 511Byte Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFRX:32;

  } bit;

  uint32_t reg;

} GMAC_TBFR511_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TBFR511_OFFSET         0x174

#define GMAC_TBFR511_RESETVALUE     _U_(0x00000000)

#define GMAC_TBFR511_NFRX_Pos       0

#define GMAC_TBFR511_NFRX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos)

#define GMAC_TBFR511_NFRX(value)    (GMAC_TBFR511_NFRX_Msk & ((value) << GMAC_TBFR511_NFRX_Pos))

#define GMAC_TBFR511_MASK           _U_(0xFFFFFFFF)

/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) (R/  32) 512 to 1023 Byte Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFRX:32;

  } bit;

  uint32_t reg;

} GMAC_TBFR1023_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TBFR1023_OFFSET        0x178

#define GMAC_TBFR1023_RESETVALUE    _U_(0x00000000)

#define GMAC_TBFR1023_NFRX_Pos      0

#define GMAC_TBFR1023_NFRX_Msk      (_U_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos)

#define GMAC_TBFR1023_NFRX(value)   (GMAC_TBFR1023_NFRX_Msk & ((value) << GMAC_TBFR1023_NFRX_Pos))

#define GMAC_TBFR1023_MASK          _U_(0xFFFFFFFF)

/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) (R/  32) 1024 to 1518 Byte Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFRX:32;

  } bit;

  uint32_t reg;

} GMAC_TBFR1518_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TBFR1518_OFFSET        0x17C

#define GMAC_TBFR1518_RESETVALUE    _U_(0x00000000)

#define GMAC_TBFR1518_NFRX_Pos      0

#define GMAC_TBFR1518_NFRX_Msk      (_U_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos)

#define GMAC_TBFR1518_NFRX(value)   (GMAC_TBFR1518_NFRX_Msk & ((value) << GMAC_TBFR1518_NFRX_Pos))

#define GMAC_TBFR1518_MASK          _U_(0xFFFFFFFF)

/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) (R/  32) 1519 to Maximum Byte Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t NFRX:32;

  } bit;

  uint32_t reg;

} GMAC_TMXBFR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TMXBFR_OFFSET          0x180

#define GMAC_TMXBFR_RESETVALUE      _U_(0x00000000)

#define GMAC_TMXBFR_NFRX_Pos        0

#define GMAC_TMXBFR_NFRX_Msk        (_U_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos)

#define GMAC_TMXBFR_NFRX(value)     (GMAC_TMXBFR_NFRX_Msk & ((value) << GMAC_TMXBFR_NFRX_Pos))

#define GMAC_TMXBFR_MASK            _U_(0xFFFFFFFF)

/* -------- GMAC_UFR : (GMAC Offset: 0x184) (R/  32) Undersize Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t UFRX:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_UFR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_UFR_OFFSET             0x184

#define GMAC_UFR_RESETVALUE         _U_(0x00000000)

#define GMAC_UFR_UFRX_Pos           0

#define GMAC_UFR_UFRX_Msk           (_U_(0x3FF) << GMAC_UFR_UFRX_Pos)

#define GMAC_UFR_UFRX(value)        (GMAC_UFR_UFRX_Msk & ((value) << GMAC_UFR_UFRX_Pos))

#define GMAC_UFR_MASK               _U_(0x000003FF)

/* -------- GMAC_OFR : (GMAC Offset: 0x188) (R/  32) Oversize Frames Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t OFRX:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_OFR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_OFR_OFFSET             0x188

#define GMAC_OFR_RESETVALUE         _U_(0x00000000)

#define GMAC_OFR_OFRX_Pos           0

#define GMAC_OFR_OFRX_Msk           (_U_(0x3FF) << GMAC_OFR_OFRX_Pos)

#define GMAC_OFR_OFRX(value)        (GMAC_OFR_OFRX_Msk & ((value) << GMAC_OFR_OFRX_Pos))

#define GMAC_OFR_MASK               _U_(0x000003FF)

/* -------- GMAC_JR : (GMAC Offset: 0x18C) (R/  32) Jabbers Received Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t JRX:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_JR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_JR_OFFSET              0x18C

#define GMAC_JR_RESETVALUE          _U_(0x00000000)

#define GMAC_JR_JRX_Pos             0

#define GMAC_JR_JRX_Msk             (_U_(0x3FF) << GMAC_JR_JRX_Pos)

#define GMAC_JR_JRX(value)          (GMAC_JR_JRX_Msk & ((value) << GMAC_JR_JRX_Pos))

#define GMAC_JR_MASK                _U_(0x000003FF)

/* -------- GMAC_FCSE : (GMAC Offset: 0x190) (R/  32) Frame Check Sequence Errors Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t FCKR:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_FCSE_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_FCSE_OFFSET            0x190

#define GMAC_FCSE_RESETVALUE        _U_(0x00000000)

#define GMAC_FCSE_FCKR_Pos          0

#define GMAC_FCSE_FCKR_Msk          (_U_(0x3FF) << GMAC_FCSE_FCKR_Pos)

#define GMAC_FCSE_FCKR(value)       (GMAC_FCSE_FCKR_Msk & ((value) << GMAC_FCSE_FCKR_Pos))

#define GMAC_FCSE_MASK              _U_(0x000003FF)

/* -------- GMAC_LFFE : (GMAC Offset: 0x194) (R/  32) Length Field Frame Errors Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t LFER:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_LFFE_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_LFFE_OFFSET            0x194

#define GMAC_LFFE_RESETVALUE        _U_(0x00000000)

#define GMAC_LFFE_LFER_Pos          0

#define GMAC_LFFE_LFER_Msk          (_U_(0x3FF) << GMAC_LFFE_LFER_Pos)

#define GMAC_LFFE_LFER(value)       (GMAC_LFFE_LFER_Msk & ((value) << GMAC_LFFE_LFER_Pos))

#define GMAC_LFFE_MASK              _U_(0x000003FF)

/* -------- GMAC_RSE : (GMAC Offset: 0x198) (R/  32) Receive Symbol Errors Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RXSE:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_RSE_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_RSE_OFFSET             0x198

#define GMAC_RSE_RESETVALUE         _U_(0x00000000)

#define GMAC_RSE_RXSE_Pos           0

#define GMAC_RSE_RXSE_Msk           (_U_(0x3FF) << GMAC_RSE_RXSE_Pos)

#define GMAC_RSE_RXSE(value)        (GMAC_RSE_RXSE_Msk & ((value) << GMAC_RSE_RXSE_Pos))

#define GMAC_RSE_MASK               _U_(0x000003FF)

/* -------- GMAC_AE : (GMAC Offset: 0x19C) (R/  32) Alignment Errors Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t AER:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_AE_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_AE_OFFSET              0x19C

#define GMAC_AE_RESETVALUE          _U_(0x00000000)

#define GMAC_AE_AER_Pos             0

#define GMAC_AE_AER_Msk             (_U_(0x3FF) << GMAC_AE_AER_Pos)

#define GMAC_AE_AER(value)          (GMAC_AE_AER_Msk & ((value) << GMAC_AE_AER_Pos))

#define GMAC_AE_MASK                _U_(0x000003FF)

/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) (R/  32) Receive Resource Errors Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RXRER:18;

    uint32_t :14;

  } bit;

  uint32_t reg;

} GMAC_RRE_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_RRE_OFFSET             0x1A0

#define GMAC_RRE_RESETVALUE         _U_(0x00000000)

#define GMAC_RRE_RXRER_Pos          0

#define GMAC_RRE_RXRER_Msk          (_U_(0x3FFFF) << GMAC_RRE_RXRER_Pos)

#define GMAC_RRE_RXRER(value)       (GMAC_RRE_RXRER_Msk & ((value) << GMAC_RRE_RXRER_Pos))

#define GMAC_RRE_MASK               _U_(0x0003FFFF)

/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) (R/  32) Receive Overrun Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RXOVR:10;

    uint32_t :22;

  } bit;

  uint32_t reg;

} GMAC_ROE_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_ROE_OFFSET             0x1A4

#define GMAC_ROE_RESETVALUE         _U_(0x00000000)

#define GMAC_ROE_RXOVR_Pos          0

#define GMAC_ROE_RXOVR_Msk          (_U_(0x3FF) << GMAC_ROE_RXOVR_Pos)

#define GMAC_ROE_RXOVR(value)       (GMAC_ROE_RXOVR_Msk & ((value) << GMAC_ROE_RXOVR_Pos))

#define GMAC_ROE_MASK               _U_(0x000003FF)

/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) (R/  32) IP Header Checksum Errors Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t HCKER:8;

    uint32_t :24;

  } bit;

  uint32_t reg;

} GMAC_IHCE_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_IHCE_OFFSET            0x1A8

#define GMAC_IHCE_RESETVALUE        _U_(0x00000000)

#define GMAC_IHCE_HCKER_Pos         0

#define GMAC_IHCE_HCKER_Msk         (_U_(0xFF) << GMAC_IHCE_HCKER_Pos)

#define GMAC_IHCE_HCKER(value)      (GMAC_IHCE_HCKER_Msk & ((value) << GMAC_IHCE_HCKER_Pos))

#define GMAC_IHCE_MASK              _U_(0x000000FF)

/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) (R/  32) TCP Checksum Errors Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TCKER:8;

    uint32_t :24;

  } bit;

  uint32_t reg;

} GMAC_TCE_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TCE_OFFSET             0x1AC

#define GMAC_TCE_RESETVALUE         _U_(0x00000000)

#define GMAC_TCE_TCKER_Pos          0

#define GMAC_TCE_TCKER_Msk          (_U_(0xFF) << GMAC_TCE_TCKER_Pos)

#define GMAC_TCE_TCKER(value)       (GMAC_TCE_TCKER_Msk & ((value) << GMAC_TCE_TCKER_Pos))

#define GMAC_TCE_MASK               _U_(0x000000FF)

/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) (R/  32) UDP Checksum Errors Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t UCKER:8;

    uint32_t :24;

  } bit;

  uint32_t reg;

} GMAC_UCE_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_UCE_OFFSET             0x1B0

#define GMAC_UCE_RESETVALUE         _U_(0x00000000)

#define GMAC_UCE_UCKER_Pos          0

#define GMAC_UCE_UCKER_Msk          (_U_(0xFF) << GMAC_UCE_UCKER_Pos)

#define GMAC_UCE_UCKER(value)       (GMAC_UCE_UCKER_Msk & ((value) << GMAC_UCE_UCKER_Pos))

#define GMAC_UCE_MASK               _U_(0x000000FF)

/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t LSBTIR:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_TISUBN_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TISUBN_OFFSET          0x1BC

#define GMAC_TISUBN_RESETVALUE      _U_(0x00000000)

#define GMAC_TISUBN_LSBTIR_Pos      0

#define GMAC_TISUBN_LSBTIR_Msk      (_U_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos)

#define GMAC_TISUBN_LSBTIR(value)   (GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))

#define GMAC_TISUBN_MASK            _U_(0x0000FFFF)

/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) (R/W 32) 1588 Timer Seconds High [15:0] Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TCS:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_TSH_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TSH_OFFSET             0x1C0

#define GMAC_TSH_RESETVALUE         _U_(0x00000000)

#define GMAC_TSH_TCS_Pos            0

#define GMAC_TSH_TCS_Msk            (_U_(0xFFFF) << GMAC_TSH_TCS_Pos)

#define GMAC_TSH_TCS(value)         (GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))

#define GMAC_TSH_MASK               _U_(0x0000FFFF)

/* -------- GMAC_TSSSL : (GMAC Offset: 0x1C8) (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t VTS:32;

  } bit;

  uint32_t reg;

} GMAC_TSSSL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TSSSL_OFFSET           0x1C8

#define GMAC_TSSSL_RESETVALUE       _U_(0x00000000)

#define GMAC_TSSSL_VTS_Pos          0

#define GMAC_TSSSL_VTS_Msk          (_U_(0xFFFFFFFF) << GMAC_TSSSL_VTS_Pos)

#define GMAC_TSSSL_VTS(value)       (GMAC_TSSSL_VTS_Msk & ((value) << GMAC_TSSSL_VTS_Pos))

#define GMAC_TSSSL_MASK             _U_(0xFFFFFFFF)

/* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t VTN:30;

    uint32_t :2;

  } bit;

  uint32_t reg;

} GMAC_TSSN_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TSSN_OFFSET            0x1CC

#define GMAC_TSSN_RESETVALUE        _U_(0x00000000)

#define GMAC_TSSN_VTN_Pos           0

#define GMAC_TSSN_VTN_Msk           (_U_(0x3FFFFFFF) << GMAC_TSSN_VTN_Pos)

#define GMAC_TSSN_VTN(value)        (GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos))

#define GMAC_TSSN_MASK              _U_(0x3FFFFFFF)

/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) (R/W 32) 1588 Timer Seconds [31:0] Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TCS:32;

  } bit;

  uint32_t reg;

} GMAC_TSL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TSL_OFFSET             0x1D0

#define GMAC_TSL_RESETVALUE         _U_(0x00000000)

#define GMAC_TSL_TCS_Pos            0

#define GMAC_TSL_TCS_Msk            (_U_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos)

#define GMAC_TSL_TCS(value)         (GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))

#define GMAC_TSL_MASK               _U_(0xFFFFFFFF)

/* -------- GMAC_TN : (GMAC Offset: 0x1D4) (R/W 32) 1588 Timer Nanoseconds Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TNS:30;

    uint32_t :2;

  } bit;

  uint32_t reg;

} GMAC_TN_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TN_OFFSET              0x1D4

#define GMAC_TN_RESETVALUE          _U_(0x00000000)

#define GMAC_TN_TNS_Pos             0

#define GMAC_TN_TNS_Msk             (_U_(0x3FFFFFFF) << GMAC_TN_TNS_Pos)

#define GMAC_TN_TNS(value)          (GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))

#define GMAC_TN_MASK                _U_(0x3FFFFFFF)

/* -------- GMAC_TA : (GMAC Offset: 0x1D8) ( /W 32) 1588 Timer Adjust Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t ITDT:30;

    uint32_t :1;

    uint32_t ADJ:1;

  } bit;

  uint32_t reg;

} GMAC_TA_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TA_OFFSET              0x1D8

#define GMAC_TA_RESETVALUE          _U_(0x00000000)

#define GMAC_TA_ITDT_Pos            0

#define GMAC_TA_ITDT_Msk            (_U_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos)

#define GMAC_TA_ITDT(value)         (GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))

#define GMAC_TA_ADJ_Pos             31

#define GMAC_TA_ADJ                 (_U_(0x1) << GMAC_TA_ADJ_Pos)

#define GMAC_TA_MASK                _U_(0xBFFFFFFF)

/* -------- GMAC_TI : (GMAC Offset: 0x1DC) (R/W 32) 1588 Timer Increment Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t CNS:8;

    uint32_t ACNS:8;

    uint32_t NIT:8;

    uint32_t :8;

  } bit;

  uint32_t reg;

} GMAC_TI_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TI_OFFSET              0x1DC

#define GMAC_TI_RESETVALUE          _U_(0x00000000)

#define GMAC_TI_CNS_Pos             0

#define GMAC_TI_CNS_Msk             (_U_(0xFF) << GMAC_TI_CNS_Pos)

#define GMAC_TI_CNS(value)          (GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))

#define GMAC_TI_ACNS_Pos            8

#define GMAC_TI_ACNS_Msk            (_U_(0xFF) << GMAC_TI_ACNS_Pos)

#define GMAC_TI_ACNS(value)         (GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))

#define GMAC_TI_NIT_Pos             16

#define GMAC_TI_NIT_Msk             (_U_(0xFF) << GMAC_TI_NIT_Pos)

#define GMAC_TI_NIT(value)          (GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))

#define GMAC_TI_MASK                _U_(0x00FFFFFF)

/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) (R/  32) PTP Event Frame Transmitted Seconds Low Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:32;

  } bit;

  uint32_t reg;

} GMAC_EFTSL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_EFTSL_OFFSET           0x1E0

#define GMAC_EFTSL_RESETVALUE       _U_(0x00000000)

#define GMAC_EFTSL_RUD_Pos          0

#define GMAC_EFTSL_RUD_Msk          (_U_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos)

#define GMAC_EFTSL_RUD(value)       (GMAC_EFTSL_RUD_Msk & ((value) << GMAC_EFTSL_RUD_Pos))

#define GMAC_EFTSL_MASK             _U_(0xFFFFFFFF)

/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) (R/  32) PTP Event Frame Transmitted Nanoseconds -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:30;

    uint32_t :2;

  } bit;

  uint32_t reg;

} GMAC_EFTN_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_EFTN_OFFSET            0x1E4

#define GMAC_EFTN_RESETVALUE        _U_(0x00000000)

#define GMAC_EFTN_RUD_Pos           0

#define GMAC_EFTN_RUD_Msk           (_U_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos)

#define GMAC_EFTN_RUD(value)        (GMAC_EFTN_RUD_Msk & ((value) << GMAC_EFTN_RUD_Pos))

#define GMAC_EFTN_MASK              _U_(0x3FFFFFFF)

/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) (R/  32) PTP Event Frame Received Seconds Low Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:32;

  } bit;

  uint32_t reg;

} GMAC_EFRSL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_EFRSL_OFFSET           0x1E8

#define GMAC_EFRSL_RESETVALUE       _U_(0x00000000)

#define GMAC_EFRSL_RUD_Pos          0

#define GMAC_EFRSL_RUD_Msk          (_U_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos)

#define GMAC_EFRSL_RUD(value)       (GMAC_EFRSL_RUD_Msk & ((value) << GMAC_EFRSL_RUD_Pos))

#define GMAC_EFRSL_MASK             _U_(0xFFFFFFFF)

/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) (R/  32) PTP Event Frame Received Nanoseconds -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:30;

    uint32_t :2;

  } bit;

  uint32_t reg;

} GMAC_EFRN_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_EFRN_OFFSET            0x1EC

#define GMAC_EFRN_RESETVALUE        _U_(0x00000000)

#define GMAC_EFRN_RUD_Pos           0

#define GMAC_EFRN_RUD_Msk           (_U_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos)

#define GMAC_EFRN_RUD(value)        (GMAC_EFRN_RUD_Msk & ((value) << GMAC_EFRN_RUD_Pos))

#define GMAC_EFRN_MASK              _U_(0x3FFFFFFF)

/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) (R/  32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:32;

  } bit;

  uint32_t reg;

} GMAC_PEFTSL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_PEFTSL_OFFSET          0x1F0

#define GMAC_PEFTSL_RESETVALUE      _U_(0x00000000)

#define GMAC_PEFTSL_RUD_Pos         0

#define GMAC_PEFTSL_RUD_Msk         (_U_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos)

#define GMAC_PEFTSL_RUD(value)      (GMAC_PEFTSL_RUD_Msk & ((value) << GMAC_PEFTSL_RUD_Pos))

#define GMAC_PEFTSL_MASK            _U_(0xFFFFFFFF)

/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) (R/  32) PTP Peer Event Frame Transmitted Nanoseconds -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:30;

    uint32_t :2;

  } bit;

  uint32_t reg;

} GMAC_PEFTN_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_PEFTN_OFFSET           0x1F4

#define GMAC_PEFTN_RESETVALUE       _U_(0x00000000)

#define GMAC_PEFTN_RUD_Pos          0

#define GMAC_PEFTN_RUD_Msk          (_U_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos)

#define GMAC_PEFTN_RUD(value)       (GMAC_PEFTN_RUD_Msk & ((value) << GMAC_PEFTN_RUD_Pos))

#define GMAC_PEFTN_MASK             _U_(0x3FFFFFFF)

/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) (R/  32) PTP Peer Event Frame Received Seconds Low Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:32;

  } bit;

  uint32_t reg;

} GMAC_PEFRSL_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_PEFRSL_OFFSET          0x1F8

#define GMAC_PEFRSL_RESETVALUE      _U_(0x00000000)

#define GMAC_PEFRSL_RUD_Pos         0

#define GMAC_PEFRSL_RUD_Msk         (_U_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos)

#define GMAC_PEFRSL_RUD(value)      (GMAC_PEFRSL_RUD_Msk & ((value) << GMAC_PEFRSL_RUD_Pos))

#define GMAC_PEFRSL_MASK            _U_(0xFFFFFFFF)

/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) (R/  32) PTP Peer Event Frame Received Nanoseconds -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RUD:30;

    uint32_t :2;

  } bit;

  uint32_t reg;

} GMAC_PEFRN_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_PEFRN_OFFSET           0x1FC

#define GMAC_PEFRN_RESETVALUE       _U_(0x00000000)

#define GMAC_PEFRN_RUD_Pos          0

#define GMAC_PEFRN_RUD_Msk          (_U_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos)

#define GMAC_PEFRN_RUD(value)       (GMAC_PEFRN_RUD_Msk & ((value) << GMAC_PEFRN_RUD_Pos))

#define GMAC_PEFRN_MASK             _U_(0x3FFFFFFF)

/* -------- GMAC_RLPITR : (GMAC Offset: 0x270) (R/  32) Receive LPI transition Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RLPITR:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_RLPITR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_RLPITR_OFFSET          0x270

#define GMAC_RLPITR_RESETVALUE      _U_(0x00000000)

#define GMAC_RLPITR_RLPITR_Pos      0

#define GMAC_RLPITR_RLPITR_Msk      (_U_(0xFFFF) << GMAC_RLPITR_RLPITR_Pos)

#define GMAC_RLPITR_RLPITR(value)   (GMAC_RLPITR_RLPITR_Msk & ((value) << GMAC_RLPITR_RLPITR_Pos))

#define GMAC_RLPITR_MASK            _U_(0x0000FFFF)

/* -------- GMAC_RLPITI : (GMAC Offset: 0x274) (R/  32) Receive LPI Time Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t RLPITI:24;

    uint32_t :8;

  } bit;

  uint32_t reg;

} GMAC_RLPITI_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_RLPITI_OFFSET          0x274

#define GMAC_RLPITI_RESETVALUE      _U_(0x00000000)

#define GMAC_RLPITI_RLPITI_Pos      0

#define GMAC_RLPITI_RLPITI_Msk      (_U_(0xFFFFFF) << GMAC_RLPITI_RLPITI_Pos)

#define GMAC_RLPITI_RLPITI(value)   (GMAC_RLPITI_RLPITI_Msk & ((value) << GMAC_RLPITI_RLPITI_Pos))

#define GMAC_RLPITI_MASK            _U_(0x00FFFFFF)

/* -------- GMAC_TLPITR : (GMAC Offset: 0x278) (R/  32) Receive LPI transition Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TLPITR:16;

    uint32_t :16;

  } bit;

  uint32_t reg;

} GMAC_TLPITR_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TLPITR_OFFSET          0x278

#define GMAC_TLPITR_RESETVALUE      _U_(0x00000000)

#define GMAC_TLPITR_TLPITR_Pos      0

#define GMAC_TLPITR_TLPITR_Msk      (_U_(0xFFFF) << GMAC_TLPITR_TLPITR_Pos)

#define GMAC_TLPITR_TLPITR(value)   (GMAC_TLPITR_TLPITR_Msk & ((value) << GMAC_TLPITR_TLPITR_Pos))

#define GMAC_TLPITR_MASK            _U_(0x0000FFFF)

/* -------- GMAC_TLPITI : (GMAC Offset: 0x27C) (R/  32) Receive LPI Time Register -------- */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef union {

  struct {

    uint32_t TLPITI:24;

    uint32_t :8;

  } bit;

  uint32_t reg;

} GMAC_TLPITI_Type;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#define GMAC_TLPITI_OFFSET          0x27C

#define GMAC_TLPITI_RESETVALUE      _U_(0x00000000)

#define GMAC_TLPITI_TLPITI_Pos      0

#define GMAC_TLPITI_TLPITI_Msk      (_U_(0xFFFFFF) << GMAC_TLPITI_TLPITI_Pos)

#define GMAC_TLPITI_TLPITI(value)   (GMAC_TLPITI_TLPITI_Msk & ((value) << GMAC_TLPITI_TLPITI_Pos))

#define GMAC_TLPITI_MASK            _U_(0x00FFFFFF)

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __IO GMAC_SAB_Type             SAB;

  __IO GMAC_SAT_Type             SAT;

} GmacSa;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __IO GMAC_NCR_Type             NCR;

  __IO GMAC_NCFGR_Type           NCFGR;

  __I  GMAC_NSR_Type             NSR;

  __IO GMAC_UR_Type              UR;

  __IO GMAC_DCFGR_Type           DCFGR;

  __IO GMAC_TSR_Type             TSR;

  __IO GMAC_RBQB_Type            RBQB;

  __IO GMAC_TBQB_Type            TBQB;

  __IO GMAC_RSR_Type             RSR;

  __IO GMAC_ISR_Type             ISR;

  __O  GMAC_IER_Type             IER;

  __O  GMAC_IDR_Type             IDR;

  __I  GMAC_IMR_Type             IMR;

  __IO GMAC_MAN_Type             MAN;

  __I  GMAC_RPQ_Type             RPQ;

  __IO GMAC_TPQ_Type             TPQ;

  __IO GMAC_TPSF_Type            TPSF;

  __IO GMAC_RPSF_Type            RPSF;

  __IO GMAC_RJFML_Type           RJFML;

       RoReg8                    Reserved1[0x34];

  __IO GMAC_HRB_Type             HRB;

  __IO GMAC_HRT_Type             HRT;

       GmacSa                    Sa[4];

  __IO GMAC_TIDM_Type            TIDM[4];

  __IO GMAC_WOL_Type             WOL;

  __IO GMAC_IPGS_Type            IPGS;

  __IO GMAC_SVLAN_Type           SVLAN;

  __IO GMAC_TPFCP_Type           TPFCP;

  __IO GMAC_SAMB1_Type           SAMB1;

  __IO GMAC_SAMT1_Type           SAMT1;

       RoReg8                    Reserved2[0xC];

  __IO GMAC_NSC_Type             NSC;

  __IO GMAC_SCL_Type             SCL;

  __IO GMAC_SCH_Type             SCH;

  __I  GMAC_EFTSH_Type           EFTSH;

  __I  GMAC_EFRSH_Type           EFRSH;

  __I  GMAC_PEFTSH_Type          PEFTSH;

  __I  GMAC_PEFRSH_Type          PEFRSH;

       RoReg8                    Reserved3[0x8];

  __I  GMAC_OTLO_Type            OTLO;

  __I  GMAC_OTHI_Type            OTHI;

  __I  GMAC_FT_Type              FT;

  __I  GMAC_BCFT_Type            BCFT;

  __I  GMAC_MFT_Type             MFT;

  __I  GMAC_PFT_Type             PFT;

  __I  GMAC_BFT64_Type           BFT64;

  __I  GMAC_TBFT127_Type         TBFT127;

  __I  GMAC_TBFT255_Type         TBFT255;

  __I  GMAC_TBFT511_Type         TBFT511;

  __I  GMAC_TBFT1023_Type        TBFT1023;

  __I  GMAC_TBFT1518_Type        TBFT1518;

  __I  GMAC_GTBFT1518_Type       GTBFT1518;

  __I  GMAC_TUR_Type             TUR;

  __I  GMAC_SCF_Type             SCF;

  __I  GMAC_MCF_Type             MCF;

  __I  GMAC_EC_Type              EC;

  __I  GMAC_LC_Type              LC;

  __I  GMAC_DTF_Type             DTF;

  __I  GMAC_CSE_Type             CSE;

  __I  GMAC_ORLO_Type            ORLO;

  __I  GMAC_ORHI_Type            ORHI;

  __I  GMAC_FR_Type              FR;

  __I  GMAC_BCFR_Type            BCFR;

  __I  GMAC_MFR_Type             MFR;

  __I  GMAC_PFR_Type             PFR;

  __I  GMAC_BFR64_Type           BFR64;

  __I  GMAC_TBFR127_Type         TBFR127;

  __I  GMAC_TBFR255_Type         TBFR255;

  __I  GMAC_TBFR511_Type         TBFR511;

  __I  GMAC_TBFR1023_Type        TBFR1023;

  __I  GMAC_TBFR1518_Type        TBFR1518;

  __I  GMAC_TMXBFR_Type          TMXBFR;

  __I  GMAC_UFR_Type             UFR;

  __I  GMAC_OFR_Type             OFR;

  __I  GMAC_JR_Type              JR;

  __I  GMAC_FCSE_Type            FCSE;

  __I  GMAC_LFFE_Type            LFFE;

  __I  GMAC_RSE_Type             RSE;

  __I  GMAC_AE_Type              AE;

  __I  GMAC_RRE_Type             RRE;

  __I  GMAC_ROE_Type             ROE;

  __I  GMAC_IHCE_Type            IHCE;

  __I  GMAC_TCE_Type             TCE;

  __I  GMAC_UCE_Type             UCE;

       RoReg8                    Reserved4[0x8];

  __IO GMAC_TISUBN_Type          TISUBN;

  __IO GMAC_TSH_Type             TSH;

       RoReg8                    Reserved5[0x4];

  __IO GMAC_TSSSL_Type           TSSSL;

  __IO GMAC_TSSN_Type            TSSN;

  __IO GMAC_TSL_Type             TSL;

  __IO GMAC_TN_Type              TN;

  __O  GMAC_TA_Type              TA;

  __IO GMAC_TI_Type              TI;

  __I  GMAC_EFTSL_Type           EFTSL;

  __I  GMAC_EFTN_Type            EFTN;

  __I  GMAC_EFRSL_Type           EFRSL;

  __I  GMAC_EFRN_Type            EFRN;

  __I  GMAC_PEFTSL_Type          PEFTSL;

  __I  GMAC_PEFTN_Type           PEFTN;

  __I  GMAC_PEFRSL_Type          PEFRSL;

  __I  GMAC_PEFRN_Type           PEFRN;

       RoReg8                    Reserved6[0x70];

  __I  GMAC_RLPITR_Type          RLPITR;

  __I  GMAC_RLPITI_Type          RLPITI;

  __I  GMAC_TLPITR_Type          TLPITR;

  __I  GMAC_TLPITI_Type          TLPITI;

} Gmac;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#endif /* _SAME54_GMAC_COMPONENT_ */