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SAME54P20A Test Project
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GMAC hardware registers. More...
#include <gmac.h>
Data Fields | |
| __IO GMAC_NCR_Type | NCR |
| Offset: 0x000 (R/W 32) Network Control Register. | |
| __IO GMAC_NCFGR_Type | NCFGR |
| Offset: 0x004 (R/W 32) Network Configuration Register. | |
| __I GMAC_NSR_Type | NSR |
| Offset: 0x008 (R/ 32) Network Status Register. | |
| __IO GMAC_UR_Type | UR |
| Offset: 0x00C (R/W 32) User Register. | |
| __IO GMAC_DCFGR_Type | DCFGR |
| Offset: 0x010 (R/W 32) DMA Configuration Register. | |
| __IO GMAC_TSR_Type | TSR |
| Offset: 0x014 (R/W 32) Transmit Status Register. | |
| __IO GMAC_RBQB_Type | RBQB |
| Offset: 0x018 (R/W 32) Receive Buffer Queue Base Address. | |
| __IO GMAC_TBQB_Type | TBQB |
| Offset: 0x01C (R/W 32) Transmit Buffer Queue Base Address. | |
| __IO GMAC_RSR_Type | RSR |
| Offset: 0x020 (R/W 32) Receive Status Register. | |
| __IO GMAC_ISR_Type | ISR |
| Offset: 0x024 (R/W 32) Interrupt Status Register. | |
| __O GMAC_IER_Type | IER |
| Offset: 0x028 ( /W 32) Interrupt Enable Register. | |
| __O GMAC_IDR_Type | IDR |
| Offset: 0x02C ( /W 32) Interrupt Disable Register. | |
| __I GMAC_IMR_Type | IMR |
| Offset: 0x030 (R/ 32) Interrupt Mask Register. | |
| __IO GMAC_MAN_Type | MAN |
| Offset: 0x034 (R/W 32) PHY Maintenance Register. | |
| __I GMAC_RPQ_Type | RPQ |
| Offset: 0x038 (R/ 32) Received Pause Quantum Register. | |
| __IO GMAC_TPQ_Type | TPQ |
| Offset: 0x03C (R/W 32) Transmit Pause Quantum Register. | |
| __IO GMAC_TPSF_Type | TPSF |
| Offset: 0x040 (R/W 32) TX partial store and forward Register. | |
| __IO GMAC_RPSF_Type | RPSF |
| Offset: 0x044 (R/W 32) RX partial store and forward Register. | |
| __IO GMAC_RJFML_Type | RJFML |
| Offset: 0x048 (R/W 32) RX Jumbo Frame Max Length Register. | |
| RoReg8 | Reserved1 [0x34] |
| __IO GMAC_HRB_Type | HRB |
| Offset: 0x080 (R/W 32) Hash Register Bottom [31:0]. | |
| __IO GMAC_HRT_Type | HRT |
| Offset: 0x084 (R/W 32) Hash Register Top [63:32]. | |
| GmacSa | Sa [4] |
| Offset: 0x088 GmacSa groups. | |
| __IO GMAC_TIDM_Type | TIDM [4] |
| Offset: 0x0A8 (R/W 32) Type ID Match Register. | |
| __IO GMAC_WOL_Type | WOL |
| Offset: 0x0B8 (R/W 32) Wake on LAN. | |
| __IO GMAC_IPGS_Type | IPGS |
| Offset: 0x0BC (R/W 32) IPG Stretch Register. | |
| __IO GMAC_SVLAN_Type | SVLAN |
| Offset: 0x0C0 (R/W 32) Stacked VLAN Register. | |
| __IO GMAC_TPFCP_Type | TPFCP |
| Offset: 0x0C4 (R/W 32) Transmit PFC Pause Register. | |
| __IO GMAC_SAMB1_Type | SAMB1 |
| Offset: 0x0C8 (R/W 32) Specific Address 1 Mask Bottom [31:0] Register. | |
| __IO GMAC_SAMT1_Type | SAMT1 |
| Offset: 0x0CC (R/W 32) Specific Address 1 Mask Top [47:32] Register. | |
| RoReg8 | Reserved2 [0xC] |
| __IO GMAC_NSC_Type | NSC |
| Offset: 0x0DC (R/W 32) Tsu timer comparison nanoseconds Register. | |
| __IO GMAC_SCL_Type | SCL |
| Offset: 0x0E0 (R/W 32) Tsu timer second comparison Register. | |
| __IO GMAC_SCH_Type | SCH |
| Offset: 0x0E4 (R/W 32) Tsu timer second comparison Register. | |
| __I GMAC_EFTSH_Type | EFTSH |
| Offset: 0x0E8 (R/ 32) PTP Event Frame Transmitted Seconds High Register. | |
| __I GMAC_EFRSH_Type | EFRSH |
| Offset: 0x0EC (R/ 32) PTP Event Frame Received Seconds High Register. | |
| __I GMAC_PEFTSH_Type | PEFTSH |
| Offset: 0x0F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register. | |
| __I GMAC_PEFRSH_Type | PEFRSH |
| Offset: 0x0F4 (R/ 32) PTP Peer Event Frame Received Seconds High Register. | |
| RoReg8 | Reserved3 [0x8] |
| __I GMAC_OTLO_Type | OTLO |
| Offset: 0x100 (R/ 32) Octets Transmitted [31:0] Register. | |
| __I GMAC_OTHI_Type | OTHI |
| Offset: 0x104 (R/ 32) Octets Transmitted [47:32] Register. | |
| __I GMAC_FT_Type | FT |
| Offset: 0x108 (R/ 32) Frames Transmitted Register. | |
| __I GMAC_BCFT_Type | BCFT |
| Offset: 0x10C (R/ 32) Broadcast Frames Transmitted Register. | |
| __I GMAC_MFT_Type | MFT |
| Offset: 0x110 (R/ 32) Multicast Frames Transmitted Register. | |
| __I GMAC_PFT_Type | PFT |
| Offset: 0x114 (R/ 32) Pause Frames Transmitted Register. | |
| __I GMAC_BFT64_Type | BFT64 |
| Offset: 0x118 (R/ 32) 64 Byte Frames Transmitted Register. | |
| __I GMAC_TBFT127_Type | TBFT127 |
| Offset: 0x11C (R/ 32) 65 to 127 Byte Frames Transmitted Register. | |
| __I GMAC_TBFT255_Type | TBFT255 |
| Offset: 0x120 (R/ 32) 128 to 255 Byte Frames Transmitted Register. | |
| __I GMAC_TBFT511_Type | TBFT511 |
| Offset: 0x124 (R/ 32) 256 to 511 Byte Frames Transmitted Register. | |
| __I GMAC_TBFT1023_Type | TBFT1023 |
| Offset: 0x128 (R/ 32) 512 to 1023 Byte Frames Transmitted Register. | |
| __I GMAC_TBFT1518_Type | TBFT1518 |
| Offset: 0x12C (R/ 32) 1024 to 1518 Byte Frames Transmitted Register. | |
| __I GMAC_GTBFT1518_Type | GTBFT1518 |
| Offset: 0x130 (R/ 32) Greater Than 1518 Byte Frames Transmitted Register. | |
| __I GMAC_TUR_Type | TUR |
| Offset: 0x134 (R/ 32) Transmit Underruns Register. | |
| __I GMAC_SCF_Type | SCF |
| Offset: 0x138 (R/ 32) Single Collision Frames Register. | |
| __I GMAC_MCF_Type | MCF |
| Offset: 0x13C (R/ 32) Multiple Collision Frames Register. | |
| __I GMAC_EC_Type | EC |
| Offset: 0x140 (R/ 32) Excessive Collisions Register. | |
| __I GMAC_LC_Type | LC |
| Offset: 0x144 (R/ 32) Late Collisions Register. | |
| __I GMAC_DTF_Type | DTF |
| Offset: 0x148 (R/ 32) Deferred Transmission Frames Register. | |
| __I GMAC_CSE_Type | CSE |
| Offset: 0x14C (R/ 32) Carrier Sense Errors Register. | |
| __I GMAC_ORLO_Type | ORLO |
| Offset: 0x150 (R/ 32) Octets Received [31:0] Received. | |
| __I GMAC_ORHI_Type | ORHI |
| Offset: 0x154 (R/ 32) Octets Received [47:32] Received. | |
| __I GMAC_FR_Type | FR |
| Offset: 0x158 (R/ 32) Frames Received Register. | |
| __I GMAC_BCFR_Type | BCFR |
| Offset: 0x15C (R/ 32) Broadcast Frames Received Register. | |
| __I GMAC_MFR_Type | MFR |
| Offset: 0x160 (R/ 32) Multicast Frames Received Register. | |
| __I GMAC_PFR_Type | PFR |
| Offset: 0x164 (R/ 32) Pause Frames Received Register. | |
| __I GMAC_BFR64_Type | BFR64 |
| Offset: 0x168 (R/ 32) 64 Byte Frames Received Register. | |
| __I GMAC_TBFR127_Type | TBFR127 |
| Offset: 0x16C (R/ 32) 65 to 127 Byte Frames Received Register. | |
| __I GMAC_TBFR255_Type | TBFR255 |
| Offset: 0x170 (R/ 32) 128 to 255 Byte Frames Received Register. | |
| __I GMAC_TBFR511_Type | TBFR511 |
| Offset: 0x174 (R/ 32) 256 to 511Byte Frames Received Register. | |
| __I GMAC_TBFR1023_Type | TBFR1023 |
| Offset: 0x178 (R/ 32) 512 to 1023 Byte Frames Received Register. | |
| __I GMAC_TBFR1518_Type | TBFR1518 |
| Offset: 0x17C (R/ 32) 1024 to 1518 Byte Frames Received Register. | |
| __I GMAC_TMXBFR_Type | TMXBFR |
| Offset: 0x180 (R/ 32) 1519 to Maximum Byte Frames Received Register. | |
| __I GMAC_UFR_Type | UFR |
| Offset: 0x184 (R/ 32) Undersize Frames Received Register. | |
| __I GMAC_OFR_Type | OFR |
| Offset: 0x188 (R/ 32) Oversize Frames Received Register. | |
| __I GMAC_JR_Type | JR |
| Offset: 0x18C (R/ 32) Jabbers Received Register. | |
| __I GMAC_FCSE_Type | FCSE |
| Offset: 0x190 (R/ 32) Frame Check Sequence Errors Register. | |
| __I GMAC_LFFE_Type | LFFE |
| Offset: 0x194 (R/ 32) Length Field Frame Errors Register. | |
| __I GMAC_RSE_Type | RSE |
| Offset: 0x198 (R/ 32) Receive Symbol Errors Register. | |
| __I GMAC_AE_Type | AE |
| Offset: 0x19C (R/ 32) Alignment Errors Register. | |
| __I GMAC_RRE_Type | RRE |
| Offset: 0x1A0 (R/ 32) Receive Resource Errors Register. | |
| __I GMAC_ROE_Type | ROE |
| Offset: 0x1A4 (R/ 32) Receive Overrun Register. | |
| __I GMAC_IHCE_Type | IHCE |
| Offset: 0x1A8 (R/ 32) IP Header Checksum Errors Register. | |
| __I GMAC_TCE_Type | TCE |
| Offset: 0x1AC (R/ 32) TCP Checksum Errors Register. | |
| __I GMAC_UCE_Type | UCE |
| Offset: 0x1B0 (R/ 32) UDP Checksum Errors Register. | |
| RoReg8 | Reserved4 [0x8] |
| __IO GMAC_TISUBN_Type | TISUBN |
| Offset: 0x1BC (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register. | |
| __IO GMAC_TSH_Type | TSH |
| Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High [15:0] Register. | |
| RoReg8 | Reserved5 [0x4] |
| __IO GMAC_TSSSL_Type | TSSSL |
| Offset: 0x1C8 (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register. | |
| __IO GMAC_TSSN_Type | TSSN |
| Offset: 0x1CC (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register. | |
| __IO GMAC_TSL_Type | TSL |
| Offset: 0x1D0 (R/W 32) 1588 Timer Seconds [31:0] Register. | |
| __IO GMAC_TN_Type | TN |
| Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register. | |
| __O GMAC_TA_Type | TA |
| Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register. | |
| __IO GMAC_TI_Type | TI |
| Offset: 0x1DC (R/W 32) 1588 Timer Increment Register. | |
| __I GMAC_EFTSL_Type | EFTSL |
| Offset: 0x1E0 (R/ 32) PTP Event Frame Transmitted Seconds Low Register. | |
| __I GMAC_EFTN_Type | EFTN |
| Offset: 0x1E4 (R/ 32) PTP Event Frame Transmitted Nanoseconds. | |
| __I GMAC_EFRSL_Type | EFRSL |
| Offset: 0x1E8 (R/ 32) PTP Event Frame Received Seconds Low Register. | |
| __I GMAC_EFRN_Type | EFRN |
| Offset: 0x1EC (R/ 32) PTP Event Frame Received Nanoseconds. | |
| __I GMAC_PEFTSL_Type | PEFTSL |
| Offset: 0x1F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register. | |
| __I GMAC_PEFTN_Type | PEFTN |
| Offset: 0x1F4 (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds. | |
| __I GMAC_PEFRSL_Type | PEFRSL |
| Offset: 0x1F8 (R/ 32) PTP Peer Event Frame Received Seconds Low Register. | |
| __I GMAC_PEFRN_Type | PEFRN |
| Offset: 0x1FC (R/ 32) PTP Peer Event Frame Received Nanoseconds. | |
| RoReg8 | Reserved6 [0x70] |
| __I GMAC_RLPITR_Type | RLPITR |
| Offset: 0x270 (R/ 32) Receive LPI transition Register. | |
| __I GMAC_RLPITI_Type | RLPITI |
| Offset: 0x274 (R/ 32) Receive LPI Time Register. | |
| __I GMAC_TLPITR_Type | TLPITR |
| Offset: 0x278 (R/ 32) Receive LPI transition Register. | |
| __I GMAC_TLPITI_Type | TLPITI |
| Offset: 0x27C (R/ 32) Receive LPI Time Register. | |
1.8.20