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clocks verified... dfll48m, dpll at 120mhz, osc32k

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stable
penguin 3 years ago
parent 0596887e45
commit 67d34c3b27
7 changed files with 103 additions and 22 deletions
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8
test/same54p20a_test/.igloo/target/same54p20a/Makefile
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@ -86,7 +86,7 @@ SUB_DIRS+= \
src \
ESF/mcu/src \
ESF/modules/core \
ESF/modules/usart
ESF/modules/usart_sync
OBJS+= \
ESF/mcu/src/startup_same54.o \
@ -95,7 +95,7 @@ ESF/modules/core/core.o \
ESF/modules/core/event.o \
ESF/modules/core/memory.o \
ESF/modules/core/clocks.o \
ESF/modules/usart/usart.o \
ESF/modules/usart_sync/usart_sync.o \
src/main.o
OBJS_AS_ARGS+= \
@ -105,7 +105,7 @@ $(QUOTE)ESF/modules/core/core.o$(QUOTE) \
$(QUOTE)ESF/modules/core/clocks.o$(QUOTE) \
$(QUOTE)ESF/modules/core/event.o$(QUOTE) \
$(QUOTE)ESF/modules/core/memory.o$(QUOTE) \
$(QUOTE)ESF/modules/usart/usart.o$(QUOTE) \
$(QUOTE)ESF/modules/usart_sync/usart_sync.o$(QUOTE) \
$(QUOTE)src/main.o$(QUOTE)
DIR_INCLUDES+= \
@ -113,7 +113,7 @@ DIR_INCLUDES+= \
-I$(QUOTE)../../../ESF/common/inc/cmsis$(QUOTE) \
-I$(QUOTE)../../../ESF/modules$(QUOTE) \
-I$(QUOTE)../../../ESF/modules/core$(QUOTE) \
-I$(QUOTE)../../../ESF/modules/usart$(QUOTE) \
-I$(QUOTE)../../../ESF/modules/usart_sync$(QUOTE) \
-I$(QUOTE)../../../ESF/mcu/inc$(QUOTE) \
-I$(QUOTE)../../../cfg$(QUOTE) \
-I$(QUOTE)../../../inc$(QUOTE)

21
test/same54p20a_test/ESF/modules/core/clocks.c
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@ -300,6 +300,10 @@ void clock_dpll_init(void)
OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = CORE_CONF_CLK_DPLL0_REFCLK;
OSCCTRL->Dpll[0].DPLLCTRLB.bit.WUF = CORE_CONF_CLK_DPLL0_WUF;
OSCCTRL->Dpll[0].DPLLCTRLB.bit.FILTER = CORE_CONF_CLK_DPLL0_FILTER;
CRITICAL_SECTION_LEAVE();
CRITICAL_SECTION_ENTER();
OSCCTRL->Dpll[0].DPLLCTRLA.reg = 0;
OSCCTRL->Dpll[0].DPLLCTRLA.bit.RUNSTDBY = CORE_CONF_CLK_DPLL0_RUNSTDBY;
OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = CORE_CONF_CLK_DPLL0_ENABLE;
CRITICAL_SECTION_LEAVE();
@ -328,6 +332,10 @@ void clock_dpll_init(void)
OSCCTRL->Dpll[1].DPLLCTRLB.bit.REFCLK = CORE_CONF_CLK_DPLL1_REFCLK;
OSCCTRL->Dpll[1].DPLLCTRLB.bit.WUF = CORE_CONF_CLK_DPLL1_WUF;
OSCCTRL->Dpll[1].DPLLCTRLB.bit.FILTER = CORE_CONF_CLK_DPLL1_FILTER;
CRITICAL_SECTION_LEAVE();
CRITICAL_SECTION_ENTER();
OSCCTRL->Dpll[1].DPLLCTRLA.reg = 0;
OSCCTRL->Dpll[1].DPLLCTRLA.bit.RUNSTDBY = CORE_CONF_CLK_DPLL1_RUNSTDBY;
OSCCTRL->Dpll[1].DPLLCTRLA.bit.ENABLE = CORE_CONF_CLK_DPLL1_ENABLE;
CRITICAL_SECTION_LEAVE();
@ -388,6 +396,11 @@ void clock_dfll_init(void)
// wait for ctrlb sync
while(OSCCTRL->DFLLSYNC.bit.DFLLCTRLB);
CRITICAL_SECTION_ENTER();
OSCCTRL->DFLLCTRLA.bit.RUNSTDBY = CORE_CONF_CLK_DFLL_RUNSTDBY;
OSCCTRL->DFLLCTRLA.bit.ENABLE = CORE_CONF_CLK_DFLL_ENABLE;
CRITICAL_SECTION_LEAVE();
while(OSCCTRL->DFLLSYNC.bit.ENABLE);
#if CORE_CONF_CLK_DFLL_OVERWRITE_CAL == 1
CRITICAL_SECTION_ENTER();
// set calib for dfll48m
@ -408,14 +421,20 @@ void clock_dfll_init(void)
CRITICAL_SECTION_ENTER();
// write dfll ctrlb
OSCCTRL->DFLLCTRLB.bit.WAITLOCK = CORE_CONF_CLK_DFLL_WAITLOCK;
OSCCTRL->DFLLCTRLB.bit.BPLCKC = CORE_CONF_CLK_DFLL_BPLKC;
OSCCTRL->DFLLCTRLB.bit.QLDIS = CORE_CONF_CLK_DFLL_QLDIS;
OSCCTRL->DFLLCTRLB.bit.CCDIS = CORE_CONF_CLK_DFLL_CCDIS;
OSCCTRL->DFLLCTRLB.bit.USBCRM = CORE_CONF_CLK_DFLL_USBCRM;
OSCCTRL->DFLLCTRLB.bit.LLAW = CORE_CONF_CLK_DFLL_LLAW;
OSCCTRL->DFLLCTRLB.bit.STABLE = CORE_CONF_CLK_DFLL_STABLE_FCALIB;
OSCCTRL->DFLLCTRLB.bit.MODE = CORE_CONF_CLK_DFLL_MODE;
CRITICAL_SECTION_LEAVE();
while(OSCCTRL->DFLLSYNC.bit.DFLLCTRLB);
if (OSCCTRL->DFLLCTRLB.bit.MODE)
{
while(OSCCTRL->STATUS.reg != (OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC));
volatile uint32_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC;
while((OSCCTRL->STATUS.reg & status_mask) != status_mask);
}
else
{

1
test/same54p20a_test/ESF/modules/core/clocks.h
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@ -4,6 +4,7 @@
#include "core.h"
// XOSC32K Definitions
#define CORE_CONF_CLK_XOSC32KCTRL_CGM_LP_MODE (0x0)
#define CORE_CONF_CLK_XOSC32KCTRL_CGM_STD_MODE (0x1)
#define CORE_CONF_CLK_XOSC32KCTRL_CGM_HS_MODE (0x2)

4
test/same54p20a_test/ESF/modules/core/core.c
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@ -12,6 +12,10 @@ void mcu_init(void)
// osc init
clock_osc_init();
clock_dfll_init();
clock_dpll_init();
// master clock init
clock_mclk_init();

2
test/same54p20a_test/ESF/modules/usart/usart.c → test/same54p20a_test/ESF/modules/usart_sync/usart_sync.c
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@ -1,4 +1,4 @@
#include "usart.h"
#include "usart_sync.h"
void usart_init(void)
{

0
test/same54p20a_test/ESF/modules/usart/usart.h → test/same54p20a_test/ESF/modules/usart_sync/usart_sync.h
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89
test/same54p20a_test/cfg/conf_core.h
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@ -38,38 +38,58 @@
#define CORE_CONF_CLK_XOSC1_FREQUENCY 12000000
// XOSC32K Config
#define CORE_CONF_CLK_XOSC32K_ENABLE (0)
#define CORE_CONF_CLK_XOSC32K_ENABLE (1)
#define CORE_CONF_CLK_XOSC32K_CGM CORE_CONF_CLK_XOSC32KCTRL_CGM_STD_MODE
#define CORE_CONF_CLK_XOSC32K_WRTLOCK (0)
#define CORE_CONF_CLK_XOSC32K_STARTUP_TIME CORE_CONF_CLK_XOSC32KCTRL_STARTUP_62592us
#define CORE_CONF_CLK_XOSC32K_ONDEMAND (0)
#define CORE_CONF_CLK_XOSC32K_ONDEMAND (1)
#define CORE_CONF_CLK_XOSC32K_RUNSTDBY (0)
#define CORE_CONF_CLK_XOSC32K_EN1K (0)
#define CORE_CONF_CLK_XOSC32K_EN32K (0)
#define CORE_CONF_CLK_XOSC32K_XTALEN (0)
#define CORE_CONF_CLK_XOSC32K_EN32K (1)
#define CORE_CONF_CLK_XOSC32K_XTALEN (1)
#define CORE_CONF_CLK_XOSC32K_CFDPRESC (0)
#define CORE_CONF_CLK_XOSC32K_CFDEN (0)
#define CORE_CONF_CLK_XOSC32K_SWBACK (0)
#define CORE_CONF_CLK_XOSC32K_WRTLOCK (0)
// DFLL Config
#define CORE_CONF_CLK_DFLL_ENABLE (0)
#define CORE_CONF_CLK_DFLL_RUNSTDBY (0)
#define CORE_CONF_CLK_DFLL_ENABLE (1)
#define CORE_CONF_CLK_DFLL_ONDEMAND (0)
#define CORE_CONF_CLK_DFLL_RUNSTDBY (0)
#define CORE_CONF_CLK_DFLL_WAITLOCK (0)
#define CORE_CONF_CLK_DFLL_BPLKC (0)
#define CORE_CONF_CLK_DFLL_QLDIS (0)
#define CORE_CONF_CLK_DFLL_CCDIS (0)
#define CORE_CONF_CLK_DFLL_USBCRM (0)
#define CORE_CONF_CLK_DFLL_CCDIS (1)
#define CORE_CONF_CLK_DFLL_USBCRM (1)
#define CORE_CONF_CLK_DFLL_LLAW (0)
#define CORE_CONF_CLK_DFLL_STABLE_FCALIB CORE_CONF_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED
#define CORE_CONF_CLK_DFLL_MODE CORE_CONF_CLK_DFLLCTRL_MODE_OPEN_LOOP
/**
* CORE_CONF_CLK_DFLL_MODE Options
* - CORE_CONF_CLK_DFLLCTRL_MODE_OPEN_LOOP: 0x00
* - CORE_CONF_CLK_DFLLCTRL_MODE_CLOSED_LOOP: 0x01
*/
#define CORE_CONF_CLK_DFLL_MODE CORE_CONF_CLK_DFLLCTRL_MODE_CLOSED_LOOP
#define CORE_CONF_CLK_DFLL_DIFF_VAL 0
#define CORE_CONF_CLK_DFLL_COARSE_VAL 31
#define CORE_CONF_CLK_DFLL_COARSE_VAL (0x1f / 4)
#define CORE_CONF_CLK_DFLL_FINE_VAL 128
#define CORE_CONF_CLK_DFLL_CSTEP_VAL 1
#define CORE_CONF_CLK_DFLL_FSTEP_VAL 1
#define CORE_CONF_CLK_DFLL_MUL_VAL 1
#define CORE_CONF_CLK_DFLL_GCLK_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CORE_CONF_CLK_DFLL_MUL_VAL (48000000)
/**
* CORE_CONF_CLK_DFLL_GCLK_SRC Options
* - Generic clock generator: 0
* - Generic clock generator: 1
* - Generic clock generator: 2
* - Generic clock generator: 3
* - Generic clock generator: 4
* - Generic clock generator: 5
* - Generic clock generator: 6
* - Generic clock generator: 7
* - Generic clock generator: 8
* - Generic clock generator: 9
* - Generic clock generator: 10
* - Generic clock generator: 11
*/
#define CORE_CONF_CLK_DFLL_GCLK_SRC 3
#define CORE_CONF_CLK_DFLL_OVERWRITE_CAL 0
// DPLL0 Config
@ -81,7 +101,7 @@
#define CORE_CONF_CLK_DPLL0_DIV_VAL (5)
#define CORE_CONF_CLK_DPLL0_DCOEN 0
#define CORE_CONF_CLK_DPLL0_DCOFILTER CORE_CONF_CLK_DPLLCTRL_DCOFILTER_3210KHZ
#define CORE_CONF_CLK_DPLL0_LBYPASS 0
#define CORE_CONF_CLK_DPLL0_LBYPASS 1
#define CORE_CONF_CLK_DPLL0_LTIME 0
#define CORE_CONF_CLK_DPLL0_WUF 0
#define CORE_CONF_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
@ -111,6 +131,43 @@
#define CORE_CONF_CLK_DPLL0_FILTER 0x0
// DPLL1 Config
#define CORE_CONF_CLK_DPLL1_ENABLE (0)
#define CORE_CONF_CLK_DPLL1_ONDEMAND (0)
#define CORE_CONF_CLK_DPLL1_RUNSTDBY (0)
#define CORE_CONF_CLK_DPLL1_LDRFRAC_VAL 0
#define CORE_CONF_CLK_DPLL1_LDR_VAL (0)
#define CORE_CONF_CLK_DPLL1_DIV_VAL (0)
#define CORE_CONF_CLK_DPLL1_DCOEN 0
#define CORE_CONF_CLK_DPLL1_DCOFILTER CORE_CONF_CLK_DPLLCTRL_DCOFILTER_3210KHZ
#define CORE_CONF_CLK_DPLL1_LBYPASS 0
#define CORE_CONF_CLK_DPLL1_LTIME 0
#define CORE_CONF_CLK_DPLL1_WUF 0
#define CORE_CONF_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
#define CORE_CONF_CLK_DPLL1_REFCLK CORE_CONF_CLK_DPLLCTRL_REFCLK_XOSC0
/**
* pg. 732 of the datasheet
* FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor
* 0x0 | 92.7 kHz | 0.76
* 0x1 | 131 kHz | 1.08
* 0x2 | 46.4 kHz | 0.38
* 0x3 | 65.6 kHz | 0.54
* 0x4 | 131 kHz | 0.56
* 0x5 | 185 kHz | 0.79
* 0x6 | 65.6 kHz | 0.28
* 0x7 | 92.7 kHz | 0.39
* 0x8 | 46.4 kHz | 1.49
* 0x9 | 65.6 kHz | 2.11
* 0xA | 23.2 kHz | 0.75
* 0xB | 32.8 kHz | 1.06
* 0xC | 65.6 kHz | 1.07
* 0xD | 92.7 kHz | 1.51
* 0xE | 32.8 kHz | 0.53
* 0xF | 46.4 kHz | 0.75
*
* When in doubt, leave this at its default.
*/
#define CORE_CONF_CLK_DPLL1_FILTER 0x0
// GCLK Generators Config
#define CORE_CONF_GCLK_0_ENABLE 1
#define CORE_CONF_GCLK_0_RUN_IN_STANDBY 1
@ -139,9 +196,9 @@
#define CORE_CONF_GCLK_2_OUTPUT_OFF_VALUE 0
#define CORE_CONF_GCLK_2_IDC 0
#define CORE_CONF_GCLK_3_ENABLE 0
#define CORE_CONF_GCLK_3_ENABLE 1
#define CORE_CONF_GCLK_3_RUN_IN_STANDBY 0
#define CORE_CONF_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
#define CORE_CONF_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K
#define CORE_CONF_GCLK_3_DIV_VAL 1
#define CORE_CONF_GCLK_3_DIVSEL 0
#define CORE_CONF_GCLK_3_OUTPUT_ENABLE 0

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