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283 lines
9.8 KiB
C
283 lines
9.8 KiB
C
#ifndef _CONF_CLOCKS_H_
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#define _CONF_CLOCKS_H_
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#include "clocks.h"
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#define CORE_CONF_MCLK_NVM_WAIT_STATE 0x5
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#define CORE_CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
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// DMA Config
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#define CORE_CONF_DMA_ENABLE (0)
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// Cache Config
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#define CORE_CONF_CMCC_ENABLE (0)
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// Event Port Configs
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#define CORE_CONF_PORT_EVCTRL_0_ENABLE (0)
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#define CORE_CONF_PORT_EVCTRL_1_ENABLE (0)
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#define CORE_CONF_PORT_EVCTRL_2_ENABLE (0)
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// XOSC0 Config
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#define CORE_CONF_CLK_XOSC0_ENABLE (1)
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#define CORE_CONF_CLK_XOSC0_XTALEN (1)
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#define CORE_CONF_CLK_XOSC0_RUNSTDBY (0)
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#define CORE_CONF_CLK_XOSC0_ONDEMAND (0)
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#define CORE_CONF_CLK_XOSC0_LOWBUFGAIN (0)
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#define CORE_CONF_CLK_XOSC0_ENALC (1)
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#define CORE_CONF_CLK_XOSC0_CFDEN (1)
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#define CORE_CONF_CLK_XOSC0_SWBEN (0)
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#define CORE_CONF_CLK_XOSC0_STARTUP_TIME CORE_CONF_CLK_XOSCCTRL_STARTUP_31us
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#define CORE_CONF_CLK_XOSC0_FREQUENCY 12000000
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// XOSC1 Config
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#define CORE_CONF_CLK_XOSC1_ENABLE (0)
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#define CORE_CONF_CLK_XOSC1_XTALEN (0)
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#define CORE_CONF_CLK_XOSC1_RUNSTDBY (0)
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#define CORE_CONF_CLK_XOSC1_ONDEMAND (0)
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#define CORE_CONF_CLK_XOSC1_LOWBUFGAIN (0)
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#define CORE_CONF_CLK_XOSC1_ENALC (0)
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#define CORE_CONF_CLK_XOSC1_CFDEN (0)
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#define CORE_CONF_CLK_XOSC1_SWBEN (0)
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#define CORE_CONF_CLK_XOSC1_STARTUP_TIME CORE_CONF_CLK_XOSCCTRL_STARTUP_31us
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#define CORE_CONF_CLK_XOSC1_FREQUENCY 12000000
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// XOSC32K Config
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#define CORE_CONF_CLK_XOSC32K_ENABLE (1)
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#define CORE_CONF_CLK_XOSC32K_CGM CORE_CONF_CLK_XOSC32KCTRL_CGM_STD_MODE
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#define CORE_CONF_CLK_XOSC32K_STARTUP_TIME CORE_CONF_CLK_XOSC32KCTRL_STARTUP_62592us
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#define CORE_CONF_CLK_XOSC32K_ONDEMAND (1)
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#define CORE_CONF_CLK_XOSC32K_RUNSTDBY (0)
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#define CORE_CONF_CLK_XOSC32K_EN1K (0)
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#define CORE_CONF_CLK_XOSC32K_EN32K (1)
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#define CORE_CONF_CLK_XOSC32K_XTALEN (1)
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#define CORE_CONF_CLK_XOSC32K_CFDPRESC (0)
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#define CORE_CONF_CLK_XOSC32K_CFDEN (0)
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#define CORE_CONF_CLK_XOSC32K_SWBACK (0)
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#define CORE_CONF_CLK_XOSC32K_WRTLOCK (0)
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// DFLL Config
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#define CORE_CONF_CLK_DFLL_ENABLE (1)
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#define CORE_CONF_CLK_DFLL_ONDEMAND (0)
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#define CORE_CONF_CLK_DFLL_RUNSTDBY (0)
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#define CORE_CONF_CLK_DFLL_WAITLOCK (0)
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#define CORE_CONF_CLK_DFLL_BPLKC (0)
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#define CORE_CONF_CLK_DFLL_QLDIS (0)
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#define CORE_CONF_CLK_DFLL_CCDIS (1)
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#define CORE_CONF_CLK_DFLL_USBCRM (1)
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#define CORE_CONF_CLK_DFLL_LLAW (0)
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#define CORE_CONF_CLK_DFLL_STABLE_FCALIB CORE_CONF_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED
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/**
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* CORE_CONF_CLK_DFLL_MODE Options
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* - CORE_CONF_CLK_DFLLCTRL_MODE_OPEN_LOOP: 0x00
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* - CORE_CONF_CLK_DFLLCTRL_MODE_CLOSED_LOOP: 0x01
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*/
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#define CORE_CONF_CLK_DFLL_MODE CORE_CONF_CLK_DFLLCTRL_MODE_CLOSED_LOOP
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#define CORE_CONF_CLK_DFLL_DIFF_VAL 0
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#define CORE_CONF_CLK_DFLL_COARSE_VAL (0x1f / 4)
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#define CORE_CONF_CLK_DFLL_FINE_VAL 128
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#define CORE_CONF_CLK_DFLL_CSTEP_VAL 1
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#define CORE_CONF_CLK_DFLL_FSTEP_VAL 1
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#define CORE_CONF_CLK_DFLL_MUL_VAL (48000000)
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/**
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* CORE_CONF_CLK_DFLL_GCLK_SRC Options
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* - Generic clock generator: 0
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* - Generic clock generator: 1
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* - Generic clock generator: 2
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* - Generic clock generator: 3
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* - Generic clock generator: 4
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* - Generic clock generator: 5
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* - Generic clock generator: 6
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* - Generic clock generator: 7
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* - Generic clock generator: 8
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* - Generic clock generator: 9
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* - Generic clock generator: 10
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* - Generic clock generator: 11
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*/
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#define CORE_CONF_CLK_DFLL_GCLK_SRC 3
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#define CORE_CONF_CLK_DFLL_OVERWRITE_CAL 0
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// DPLL0 Config
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#define CORE_CONF_CLK_DPLL0_ENABLE (1)
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#define CORE_CONF_CLK_DPLL0_ONDEMAND (0)
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#define CORE_CONF_CLK_DPLL0_RUNSTDBY (0)
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#define CORE_CONF_CLK_DPLL0_LDRFRAC_VAL 0
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#define CORE_CONF_CLK_DPLL0_LDR_VAL (119)
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#define CORE_CONF_CLK_DPLL0_DIV_VAL (5)
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#define CORE_CONF_CLK_DPLL0_DCOEN 0
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#define CORE_CONF_CLK_DPLL0_DCOFILTER CORE_CONF_CLK_DPLLCTRL_DCOFILTER_3210KHZ
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#define CORE_CONF_CLK_DPLL0_LBYPASS 1
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#define CORE_CONF_CLK_DPLL0_LTIME 0
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#define CORE_CONF_CLK_DPLL0_WUF 0
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#define CORE_CONF_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_CLK_DPLL0_REFCLK CORE_CONF_CLK_DPLLCTRL_REFCLK_XOSC0
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/**
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* pg. 732 of the datasheet
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* FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor
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* 0x0 | 92.7 kHz | 0.76
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* 0x1 | 131 kHz | 1.08
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* 0x2 | 46.4 kHz | 0.38
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* 0x3 | 65.6 kHz | 0.54
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* 0x4 | 131 kHz | 0.56
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* 0x5 | 185 kHz | 0.79
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* 0x6 | 65.6 kHz | 0.28
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* 0x7 | 92.7 kHz | 0.39
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* 0x8 | 46.4 kHz | 1.49
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* 0x9 | 65.6 kHz | 2.11
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* 0xA | 23.2 kHz | 0.75
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* 0xB | 32.8 kHz | 1.06
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* 0xC | 65.6 kHz | 1.07
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* 0xD | 92.7 kHz | 1.51
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* 0xE | 32.8 kHz | 0.53
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* 0xF | 46.4 kHz | 0.75
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*
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* When in doubt, leave this at its default.
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*/
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#define CORE_CONF_CLK_DPLL0_FILTER 0x0
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// DPLL1 Config
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#define CORE_CONF_CLK_DPLL1_ENABLE (0)
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#define CORE_CONF_CLK_DPLL1_ONDEMAND (0)
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#define CORE_CONF_CLK_DPLL1_RUNSTDBY (0)
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#define CORE_CONF_CLK_DPLL1_LDRFRAC_VAL 0
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#define CORE_CONF_CLK_DPLL1_LDR_VAL (0)
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#define CORE_CONF_CLK_DPLL1_DIV_VAL (0)
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#define CORE_CONF_CLK_DPLL1_DCOEN 0
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#define CORE_CONF_CLK_DPLL1_DCOFILTER CORE_CONF_CLK_DPLLCTRL_DCOFILTER_3210KHZ
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#define CORE_CONF_CLK_DPLL1_LBYPASS 0
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#define CORE_CONF_CLK_DPLL1_LTIME 0
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#define CORE_CONF_CLK_DPLL1_WUF 0
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#define CORE_CONF_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_CLK_DPLL1_REFCLK CORE_CONF_CLK_DPLLCTRL_REFCLK_XOSC0
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/**
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* pg. 732 of the datasheet
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* FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor
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* 0x0 | 92.7 kHz | 0.76
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* 0x1 | 131 kHz | 1.08
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* 0x2 | 46.4 kHz | 0.38
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* 0x3 | 65.6 kHz | 0.54
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* 0x4 | 131 kHz | 0.56
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* 0x5 | 185 kHz | 0.79
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* 0x6 | 65.6 kHz | 0.28
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* 0x7 | 92.7 kHz | 0.39
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* 0x8 | 46.4 kHz | 1.49
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* 0x9 | 65.6 kHz | 2.11
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* 0xA | 23.2 kHz | 0.75
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* 0xB | 32.8 kHz | 1.06
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* 0xC | 65.6 kHz | 1.07
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* 0xD | 92.7 kHz | 1.51
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* 0xE | 32.8 kHz | 0.53
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* 0xF | 46.4 kHz | 0.75
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*
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* When in doubt, leave this at its default.
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*/
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#define CORE_CONF_CLK_DPLL1_FILTER 0x0
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// GCLK Generators Config
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#define CORE_CONF_GCLK_0_ENABLE 1
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#define CORE_CONF_GCLK_0_RUN_IN_STANDBY 1
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#define CORE_CONF_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_GCLK_0_DIV_VAL 1
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#define CORE_CONF_GCLK_0_DIVSEL 0
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#define CORE_CONF_GCLK_0_OUTPUT_ENABLE 1
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#define CORE_CONF_GCLK_0_OUTPUT_OFF_VALUE 1
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#define CORE_CONF_GCLK_0_IDC 1
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#define CORE_CONF_GCLK_1_ENABLE 0
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#define CORE_CONF_GCLK_1_RUN_IN_STANDBY 0
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#define CORE_CONF_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_GCLK_1_DIV_VAL 1
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#define CORE_CONF_GCLK_1_DIVSEL 0
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#define CORE_CONF_GCLK_1_OUTPUT_ENABLE 0
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#define CORE_CONF_GCLK_1_OUTPUT_OFF_VALUE 0
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#define CORE_CONF_GCLK_1_IDC 0
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#define CORE_CONF_GCLK_2_ENABLE 0
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#define CORE_CONF_GCLK_2_RUN_IN_STANDBY 0
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#define CORE_CONF_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_GCLK_2_DIV_VAL 1
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#define CORE_CONF_GCLK_2_DIVSEL 0
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#define CORE_CONF_GCLK_2_OUTPUT_ENABLE 0
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#define CORE_CONF_GCLK_2_OUTPUT_OFF_VALUE 0
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#define CORE_CONF_GCLK_2_IDC 0
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#define CORE_CONF_GCLK_3_ENABLE 1
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#define CORE_CONF_GCLK_3_RUN_IN_STANDBY 0
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#define CORE_CONF_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K
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#define CORE_CONF_GCLK_3_DIV_VAL 1
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#define CORE_CONF_GCLK_3_DIVSEL 0
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#define CORE_CONF_GCLK_3_OUTPUT_ENABLE 0
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#define CORE_CONF_GCLK_3_OUTPUT_OFF_VALUE 0
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#define CORE_CONF_GCLK_3_IDC 0
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#define CORE_CONF_GCLK_4_ENABLE 0
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#define CORE_CONF_GCLK_4_RUN_IN_STANDBY 0
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#define CORE_CONF_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_GCLK_4_DIV_VAL 1
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#define CORE_CONF_GCLK_4_DIVSEL 1
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#define CORE_CONF_GCLK_4_OUTPUT_ENABLE 0
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#define CORE_CONF_GCLK_4_OUTPUT_OFF_VALUE 0
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#define CORE_CONF_GCLK_4_IDC 0
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#define CORE_CONF_GCLK_5_ENABLE 0
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#define CORE_CONF_GCLK_5_RUN_IN_STANDBY 0
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#define CORE_CONF_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_GCLK_5_DIV_VAL 1
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#define CORE_CONF_GCLK_5_DIVSEL 0
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#define CORE_CONF_GCLK_5_OUTPUT_ENABLE 0
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#define CORE_CONF_GCLK_5_OUTPUT_OFF_VALUE 0
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#define CORE_CONF_GCLK_5_IDC 0
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#define CORE_CONF_GCLK_6_ENABLE 0
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#define CORE_CONF_GCLK_6_RUN_IN_STANDBY 0
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#define CORE_CONF_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_GCLK_6_DIV_VAL 1
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#define CORE_CONF_GCLK_6_DIVSEL 0
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#define CORE_CONF_GCLK_6_OUTPUT_ENABLE 0
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#define CORE_CONF_GCLK_6_OUTPUT_OFF_VALUE 0
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#define CORE_CONF_GCLK_6_IDC 0
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#define CORE_CONF_GCLK_7_ENABLE 0
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#define CORE_CONF_GCLK_7_RUN_IN_STANDBY 0
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#define CORE_CONF_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_GCLK_7_DIV_VAL 1
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#define CORE_CONF_GCLK_7_DIVSEL 0
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#define CORE_CONF_GCLK_7_OUTPUT_ENABLE 0
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#define CORE_CONF_GCLK_7_OUTPUT_OFF_VALUE 0
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#define CORE_CONF_GCLK_7_IDC 0
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#define CORE_CONF_GCLK_8_ENABLE 0
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#define CORE_CONF_GCLK_8_RUN_IN_STANDBY 0
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#define CORE_CONF_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_GCLK_8_DIV_VAL 1
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#define CORE_CONF_GCLK_8_DIVSEL 0
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#define CORE_CONF_GCLK_8_OUTPUT_ENABLE 0
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#define CORE_CONF_GCLK_8_OUTPUT_OFF_VALUE 0
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#define CORE_CONF_GCLK_8_IDC 0
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#define CORE_CONF_GCLK_9_ENABLE 0
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#define CORE_CONF_GCLK_9_RUN_IN_STANDBY 0
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#define CORE_CONF_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_GCLK_9_DIV_VAL 1
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#define CORE_CONF_GCLK_9_DIVSEL 0
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#define CORE_CONF_GCLK_9_OUTPUT_ENABLE 0
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#define CORE_CONF_GCLK_9_OUTPUT_OFF_VALUE 0
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#define CORE_CONF_GCLK_9_IDC 0
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#define CORE_CONF_GCLK_10_ENABLE 0
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#define CORE_CONF_GCLK_10_RUN_IN_STANDBY 0
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#define CORE_CONF_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_GCLK_10_DIV_VAL 1
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#define CORE_CONF_GCLK_10_DIVSEL 0
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#define CORE_CONF_GCLK_10_OUTPUT_ENABLE 0
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#define CORE_CONF_GCLK_10_OUTPUT_OFF_VALUE 0
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#define CORE_CONF_GCLK_10_IDC 0
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#define CORE_CONF_GCLK_11_ENABLE 0
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#define CORE_CONF_GCLK_11_RUN_IN_STANDBY 0
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#define CORE_CONF_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
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#define CORE_CONF_GCLK_11_DIV_VAL 1
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#define CORE_CONF_GCLK_11_DIVSEL 0
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#define CORE_CONF_GCLK_11_OUTPUT_ENABLE 0
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#define CORE_CONF_GCLK_11_OUTPUT_OFF_VALUE 0
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#define CORE_CONF_GCLK_11_IDC 0
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#endif
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