added new testing proj
parent
60bf20d4c7
commit
31295af44a
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/* Auto-generated config file hpl_sercom_config.h */
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#ifndef HPL_SERCOM_CONFIG_H
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#define HPL_SERCOM_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include <peripheral_clk_config.h>
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#ifndef CONF_SERCOM_0_USART_ENABLE
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#define CONF_SERCOM_0_USART_ENABLE 1
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#endif
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// <h> Basic Configuration
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// <q> Receive buffer enable
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// <i> Enable input buffer in SERCOM module
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// <id> usart_rx_enable
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#ifndef CONF_SERCOM_0_USART_RXEN
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#define CONF_SERCOM_0_USART_RXEN 1
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#endif
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// <q> Transmitt buffer enable
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// <i> Enable output buffer in SERCOM module
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// <id> usart_tx_enable
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#ifndef CONF_SERCOM_0_USART_TXEN
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#define CONF_SERCOM_0_USART_TXEN 1
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#endif
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// <o> Frame parity
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// <0x0=>No parity
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// <0x1=>Even parity
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// <0x2=>Odd parity
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// <i> Parity bit mode for USART frame
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// <id> usart_parity
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#ifndef CONF_SERCOM_0_USART_PARITY
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#define CONF_SERCOM_0_USART_PARITY 0x0
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#endif
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// <o> Character Size
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// <0x0=>8 bits
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// <0x1=>9 bits
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// <0x5=>5 bits
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// <0x6=>6 bits
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// <0x7=>7 bits
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// <i> Data character size in USART frame
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// <id> usart_character_size
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#ifndef CONF_SERCOM_0_USART_CHSIZE
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#define CONF_SERCOM_0_USART_CHSIZE 0x0
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#endif
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// <o> Stop Bit
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// <0=>One stop bit
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// <1=>Two stop bits
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// <i> Number of stop bits in USART frame
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// <id> usart_stop_bit
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#ifndef CONF_SERCOM_0_USART_SBMODE
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#define CONF_SERCOM_0_USART_SBMODE 0
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#endif
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// <o> Baud rate <1-6250000>
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// <i> USART baud rate setting
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// <id> usart_baud_rate
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#ifndef CONF_SERCOM_0_USART_BAUD
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#define CONF_SERCOM_0_USART_BAUD 9600
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#endif
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// </h>
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// <e> Advanced configuration
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// <id> usart_advanced
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#ifndef CONF_SERCOM_0_USART_ADVANCED_CONFIG
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#define CONF_SERCOM_0_USART_ADVANCED_CONFIG 0
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#endif
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// <q> Run in stand-by
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// <i> Keep the module running in standby sleep mode
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// <id> usart_arch_runstdby
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#ifndef CONF_SERCOM_0_USART_RUNSTDBY
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#define CONF_SERCOM_0_USART_RUNSTDBY 0
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#endif
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// <q> Immediate Buffer Overflow Notification
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// <i> Controls when the BUFOVF status bit is asserted
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// <id> usart_arch_ibon
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#ifndef CONF_SERCOM_0_USART_IBON
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#define CONF_SERCOM_0_USART_IBON 0
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#endif
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// <q> Start of Frame Detection Enable
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// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
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// <id> usart_arch_sfde
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#ifndef CONF_SERCOM_0_USART_SFDE
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#define CONF_SERCOM_0_USART_SFDE 0
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#endif
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// <q> Collision Detection Enable
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// <i> Collision detection enable
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// <id> usart_arch_cloden
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#ifndef CONF_SERCOM_0_USART_CLODEN
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#define CONF_SERCOM_0_USART_CLODEN 0
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#endif
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// <o> Operating Mode
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// <0x0=>USART with external clock
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// <0x1=>USART with internal clock
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// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
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// <id> usart_arch_clock_mode
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#ifndef CONF_SERCOM_0_USART_MODE
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#define CONF_SERCOM_0_USART_MODE 0x1
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#endif
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// <o> Sample Rate
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// <0x0=>16x arithmetic
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// <0x1=>16x fractional
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// <0x2=>8x arithmetic
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// <0x3=>8x fractional
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// <0x4=>3x arithmetic
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// <i> How many over-sampling bits used when sampling data state
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// <id> usart_arch_sampr
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#ifndef CONF_SERCOM_0_USART_SAMPR
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#define CONF_SERCOM_0_USART_SAMPR 0x0
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#endif
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// <o> Sample Adjustment
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// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
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// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
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// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
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// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
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// <i> Adjust which samples to use for data sampling in asynchronous mode
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// <id> usart_arch_sampa
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#ifndef CONF_SERCOM_0_USART_SAMPA
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#define CONF_SERCOM_0_USART_SAMPA 0x0
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#endif
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// <o> Fractional Part <0-7>
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// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
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// <id> usart_arch_fractional
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#ifndef CONF_SERCOM_0_USART_FRACTIONAL
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#define CONF_SERCOM_0_USART_FRACTIONAL 0x0
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#endif
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// <o> Data Order
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// <0=>MSB is transmitted first
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// <1=>LSB is transmitted first
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// <i> Data order of the data bits in the frame
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// <id> usart_arch_dord
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#ifndef CONF_SERCOM_0_USART_DORD
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#define CONF_SERCOM_0_USART_DORD 1
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#endif
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// Does not do anything in UART mode
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#define CONF_SERCOM_0_USART_CPOL 0
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// <o> Encoding Format
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// <0=>No encoding
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// <1=>IrDA encoded
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// <id> usart_arch_enc
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#ifndef CONF_SERCOM_0_USART_ENC
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#define CONF_SERCOM_0_USART_ENC 0
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#endif
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// <o> LIN Slave Enable
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// <i> Break Character Detection and Auto-Baud/LIN Slave Enable.
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// <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
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// <0=>Disable
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// <1=>Enable
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// <id> usart_arch_lin_slave_enable
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#ifndef CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE
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#define CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE 0
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#endif
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// <o> Debug Stop Mode
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// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
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// <0=>Keep running
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// <1=>Halt
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// <id> usart_arch_dbgstop
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#ifndef CONF_SERCOM_0_USART_DEBUG_STOP_MODE
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#define CONF_SERCOM_0_USART_DEBUG_STOP_MODE 0
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#endif
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// </e>
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#ifndef CONF_SERCOM_0_USART_INACK
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#define CONF_SERCOM_0_USART_INACK 0x0
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#endif
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#ifndef CONF_SERCOM_0_USART_DSNACK
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#define CONF_SERCOM_0_USART_DSNACK 0x0
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#endif
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#ifndef CONF_SERCOM_0_USART_MAXITER
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#define CONF_SERCOM_0_USART_MAXITER 0x7
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#endif
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#ifndef CONF_SERCOM_0_USART_GTIME
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#define CONF_SERCOM_0_USART_GTIME 0x2
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#endif
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#define CONF_SERCOM_0_USART_RXINV 0x0
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#define CONF_SERCOM_0_USART_TXINV 0x0
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#ifndef CONF_SERCOM_0_USART_CMODE
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#define CONF_SERCOM_0_USART_CMODE 0
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#endif
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#ifndef CONF_SERCOM_0_USART_RXPO
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#define CONF_SERCOM_0_USART_RXPO 1 /* RX is on PIN_PA05 */
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#endif
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#ifndef CONF_SERCOM_0_USART_TXPO
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#define CONF_SERCOM_0_USART_TXPO 0 /* TX is on PIN_PA04 */
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#endif
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/* Set correct parity settings in register interface based on PARITY setting */
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#if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 1
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#if CONF_SERCOM_0_USART_PARITY == 0
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#define CONF_SERCOM_0_USART_PMODE 0
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#define CONF_SERCOM_0_USART_FORM 4
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#else
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#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1
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#define CONF_SERCOM_0_USART_FORM 5
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#endif
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#else /* #if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 0 */
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#if CONF_SERCOM_0_USART_PARITY == 0
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#define CONF_SERCOM_0_USART_PMODE 0
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#define CONF_SERCOM_0_USART_FORM 0
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#else
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#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1
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#define CONF_SERCOM_0_USART_FORM 1
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#endif
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#endif
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// Calculate BAUD register value in UART mode
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#if CONF_SERCOM_0_USART_SAMPR == 0
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#ifndef CONF_SERCOM_0_USART_BAUD_RATE
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#define CONF_SERCOM_0_USART_BAUD_RATE \
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65536 - ((65536 * 16.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)
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#endif
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#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
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#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
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#endif
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#elif CONF_SERCOM_0_USART_SAMPR == 1
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#ifndef CONF_SERCOM_0_USART_BAUD_RATE
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#define CONF_SERCOM_0_USART_BAUD_RATE \
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((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 16)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8)
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#endif
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#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
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#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
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#endif
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#elif CONF_SERCOM_0_USART_SAMPR == 2
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#ifndef CONF_SERCOM_0_USART_BAUD_RATE
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#define CONF_SERCOM_0_USART_BAUD_RATE \
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65536 - ((65536 * 8.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)
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#endif
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#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
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#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
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#endif
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#elif CONF_SERCOM_0_USART_SAMPR == 3
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#ifndef CONF_SERCOM_0_USART_BAUD_RATE
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#define CONF_SERCOM_0_USART_BAUD_RATE \
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((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 8)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8)
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#endif
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#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
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#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
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#endif
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#elif CONF_SERCOM_0_USART_SAMPR == 4
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#ifndef CONF_SERCOM_0_USART_BAUD_RATE
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#define CONF_SERCOM_0_USART_BAUD_RATE \
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65536 - ((65536 * 3.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)
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#endif
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#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
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#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
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#endif
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#endif
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// <<< end of configuration section >>>
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#endif // HPL_SERCOM_CONFIG_H
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@ -1,137 +0,0 @@
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/* Auto-generated config file peripheral_clk_config.h */
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#ifndef PERIPHERAL_CLK_CONFIG_H
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#define PERIPHERAL_CLK_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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/**
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* \def CONF_CPU_FREQUENCY
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* \brief CPU's Clock frequency
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*/
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#ifndef CONF_CPU_FREQUENCY
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#define CONF_CPU_FREQUENCY 119997440
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#endif
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// <y> Core Clock Source
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// <id> core_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for CORE.
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#ifndef CONF_GCLK_SERCOM0_CORE_SRC
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#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#endif
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// <y> Slow Clock Source
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// <id> slow_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the slow clock source.
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#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
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#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
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#endif
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/**
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* \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
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* \brief SERCOM0's Core Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
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#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 119997440
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#endif
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/**
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* \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
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* \brief SERCOM0's Slow Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
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#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768
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#endif
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// <y> TC Clock Source
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// <id> tc_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for TC.
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#ifndef CONF_GCLK_TC0_SRC
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#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#endif
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/**
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* \def CONF_GCLK_TC0_FREQUENCY
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* \brief TC0's Clock frequency
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*/
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#ifndef CONF_GCLK_TC0_FREQUENCY
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#define CONF_GCLK_TC0_FREQUENCY 119997440
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#endif
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// <<< end of configuration section >>>
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#endif // PERIPHERAL_CLK_CONFIG_H
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@ -1,61 +0,0 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
|
||||
#include "driver_init.h"
|
||||
#include <peripheral_clk_config.h>
|
||||
#include <utils.h>
|
||||
#include <hal_init.h>
|
||||
|
||||
struct timer_descriptor TIMER_0;
|
||||
|
||||
struct usart_sync_descriptor USART_0;
|
||||
|
||||
void USART_0_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0);
|
||||
|
||||
gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1);
|
||||
}
|
||||
|
||||
void USART_0_CLOCK_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK);
|
||||
}
|
||||
|
||||
void USART_0_init(void)
|
||||
{
|
||||
USART_0_CLOCK_init();
|
||||
usart_sync_init(&USART_0, SERCOM0, (void *)NULL);
|
||||
USART_0_PORT_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Timer initialization function
|
||||
*
|
||||
* Enables Timer peripheral, clocks and initializes Timer driver
|
||||
*/
|
||||
static void TIMER_0_init(void)
|
||||
{
|
||||
hri_mclk_set_APBAMASK_TC0_bit(MCLK);
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
timer_init(&TIMER_0, TC0, _tc_get_timer());
|
||||
}
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
init_mcu();
|
||||
|
||||
USART_0_init();
|
||||
|
||||
TIMER_0_init();
|
||||
}
|
||||
@ -1,50 +0,0 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
|
||||
#include "driver_examples.h"
|
||||
#include "driver_init.h"
|
||||
#include "utils.h"
|
||||
|
||||
/**
|
||||
* Example of using USART_0 to write "Hello World" using the IO abstraction.
|
||||
*/
|
||||
void USART_0_example(void)
|
||||
{
|
||||
struct io_descriptor *io;
|
||||
usart_sync_get_io_descriptor(&USART_0, &io);
|
||||
usart_sync_enable(&USART_0);
|
||||
|
||||
io_write(io, (uint8_t *)"Hello World!", 12);
|
||||
}
|
||||
|
||||
static struct timer_task TIMER_0_task1, TIMER_0_task2;
|
||||
|
||||
/**
|
||||
* Example of using TIMER_0.
|
||||
*/
|
||||
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
|
||||
{
|
||||
}
|
||||
|
||||
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
|
||||
{
|
||||
}
|
||||
|
||||
void TIMER_0_example(void)
|
||||
{
|
||||
TIMER_0_task1.interval = 100;
|
||||
TIMER_0_task1.cb = TIMER_0_task1_cb;
|
||||
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
|
||||
TIMER_0_task2.interval = 200;
|
||||
TIMER_0_task2.cb = TIMER_0_task2_cb;
|
||||
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
|
||||
|
||||
timer_add_task(&TIMER_0, &TIMER_0_task1);
|
||||
timer_add_task(&TIMER_0, &TIMER_0_task2);
|
||||
timer_start(&TIMER_0);
|
||||
}
|
||||
@ -1,58 +0,0 @@
|
||||
The USART Synchronous Driver
|
||||
============================
|
||||
|
||||
The universal synchronous and asynchronous receiver and transmitter
|
||||
(USART) is usually used to transfer data from one device to the other.
|
||||
|
||||
User can set action for flow control pins by function usart_set_flow_control,
|
||||
if the flow control is enabled. All the available states are defined in union
|
||||
usart_flow_control_state.
|
||||
|
||||
Note that user can set state of flow control pins only if automatic support of
|
||||
the flow control is not supported by the hardware.
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* Initialization/de-initialization
|
||||
* Enabling/disabling
|
||||
* Control of the following settings:
|
||||
|
||||
* Baudrate
|
||||
* UART or USRT communication mode
|
||||
* Character size
|
||||
* Data order
|
||||
* Flow control
|
||||
* Data transfer: transmission, reception
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
They are commonly used in a terminal application or low-speed communication
|
||||
between devices.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
USART capable hardware.
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
|
||||
Write buffer should not be changed while data is being sent.
|
||||
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
* The driver does not support 9-bit character size.
|
||||
* The "USART with ISO7816" mode can be only used in ISO7816 capable devices.
|
||||
And the SCK pin can't be set directly. Application can use a GCLK output PIN
|
||||
to generate SCK. For example to communicate with a SMARTCARD with ISO7816
|
||||
(F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be
|
||||
config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification.
|
||||
|
||||
Known issues and workarounds
|
||||
----------------------------
|
||||
|
||||
N/A
|
||||
@ -1,247 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief USART related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_SYNC_USART_H_INCLUDED
|
||||
#define _HAL_SYNC_USART_H_INCLUDED
|
||||
|
||||
#include "hal_io.h"
|
||||
#include <hpl_usart_sync.h>
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_usart_sync
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Synchronous USART descriptor
|
||||
*/
|
||||
struct usart_sync_descriptor {
|
||||
struct io_descriptor io;
|
||||
struct _usart_sync_device device;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize USART interface
|
||||
*
|
||||
* This function initializes the given I/O descriptor to be used
|
||||
* as USART interface descriptor.
|
||||
* It checks if the given hardware is not initialized and
|
||||
* if the given hardware is permitted to be initialized.
|
||||
*
|
||||
* \param[out] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
* \param[in] func The pointer to as set of functions pointers
|
||||
*
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize USART interface
|
||||
*
|
||||
* This function deinitializes the given I/O descriptor.
|
||||
* It checks if the given hardware is initialized and
|
||||
* if the given hardware is permitted to be deinitialized.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return De-initialization status.
|
||||
*/
|
||||
int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Enable USART interface
|
||||
*
|
||||
* Enables the USART interface
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return Enabling status.
|
||||
*/
|
||||
int32_t usart_sync_enable(struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Disable USART interface
|
||||
*
|
||||
* Disables the USART interface
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return Disabling status.
|
||||
*/
|
||||
int32_t usart_sync_disable(struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Retrieve I/O descriptor
|
||||
*
|
||||
* This function retrieves the I/O descriptor of the given USART descriptor.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[out] io An I/O descriptor to retrieve
|
||||
*
|
||||
* \return The status of the I/O descriptor retrieving.
|
||||
*/
|
||||
int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io);
|
||||
|
||||
/**
|
||||
* \brief Specify action for flow control pins
|
||||
*
|
||||
* This function sets the action (or state) for the flow control pins
|
||||
* if the flow control is enabled.
|
||||
* It sets the state of flow control pins only if the automatic support of
|
||||
* the flow control is not supported by the hardware.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] state A state to set the flow control pins
|
||||
*
|
||||
* \return The status of flow control action setup.
|
||||
*/
|
||||
int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr,
|
||||
const union usart_flow_control_state state);
|
||||
|
||||
/**
|
||||
* \brief Set USART baud rate
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] baud_rate A baud rate to set
|
||||
*
|
||||
* \return The status of baud rate setting.
|
||||
*/
|
||||
int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate);
|
||||
|
||||
/**
|
||||
* \brief Set USART data order
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] data_order A data order to set
|
||||
*
|
||||
* \return The status of data order setting.
|
||||
*/
|
||||
int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order);
|
||||
|
||||
/**
|
||||
* \brief Set USART mode
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] mode A mode to set
|
||||
*
|
||||
* \return The status of mode setting.
|
||||
*/
|
||||
int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set USART parity
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] parity A parity to set
|
||||
*
|
||||
* \return The status of parity setting.
|
||||
*/
|
||||
int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity);
|
||||
|
||||
/**
|
||||
* \brief Set USART stop bits
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] stop_bits Stop bits to set
|
||||
*
|
||||
* \return The status of stop bits setting.
|
||||
*/
|
||||
int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits);
|
||||
|
||||
/**
|
||||
* \brief Set USART character size
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] size A character size to set
|
||||
*
|
||||
* \return The status of character size setting.
|
||||
*/
|
||||
int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the state of flow control pins
|
||||
*
|
||||
* This function retrieves the of flow control pins
|
||||
* if the flow control is enabled.
|
||||
* Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
|
||||
* if the flow control is done by the hardware
|
||||
* and the pins state cannot be read out.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[out] state The state of flow control pins
|
||||
*
|
||||
* \return The status of flow control state reading.
|
||||
*/
|
||||
int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr,
|
||||
union usart_flow_control_state *const state);
|
||||
|
||||
/**
|
||||
* \brief Check if the USART transmitter is empty
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return The status of USART TX empty checking.
|
||||
* \retval 0 The USART transmitter is not empty
|
||||
* \retval 1 The USART transmitter is empty
|
||||
*/
|
||||
int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Check if the USART receiver is not empty
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return The status of USART RX empty checking.
|
||||
* \retval 1 The USART receiver is not empty
|
||||
* \retval 0 The USART receiver is empty
|
||||
*/
|
||||
int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t usart_sync_get_version(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HAL_SYNC_USART_H_INCLUDED */
|
||||
@ -1,276 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I/O USART related functionality implementation.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hal_usart_sync.h"
|
||||
#include <utils_assert.h>
|
||||
#include <utils.h>
|
||||
|
||||
/**
|
||||
* \brief Driver version
|
||||
*/
|
||||
#define DRIVER_VERSION 0x00000001u
|
||||
|
||||
static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
|
||||
static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief Initialize usart interface
|
||||
*/
|
||||
int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func)
|
||||
{
|
||||
int32_t init_status;
|
||||
ASSERT(descr && hw);
|
||||
init_status = _usart_sync_init(&descr->device, hw);
|
||||
if (init_status) {
|
||||
return init_status;
|
||||
}
|
||||
|
||||
descr->io.read = usart_sync_read;
|
||||
descr->io.write = usart_sync_write;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Uninitialize usart interface
|
||||
*/
|
||||
int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_deinit(&descr->device);
|
||||
|
||||
descr->io.read = NULL;
|
||||
descr->io.write = NULL;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Enable usart interface
|
||||
*/
|
||||
int32_t usart_sync_enable(struct usart_sync_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_enable(&descr->device);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable usart interface
|
||||
*/
|
||||
int32_t usart_sync_disable(struct usart_sync_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_disable(&descr->device);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve I/O descriptor
|
||||
*/
|
||||
int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io)
|
||||
{
|
||||
ASSERT(descr && io);
|
||||
|
||||
*io = &descr->io;
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Specify action for flow control pins
|
||||
*/
|
||||
int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr,
|
||||
const union usart_flow_control_state state)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_flow_control_state(&descr->device, state);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart baud rate
|
||||
*/
|
||||
int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_baud_rate(&descr->device, baud_rate);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart data order
|
||||
*/
|
||||
int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_data_order(&descr->device, data_order);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart mode
|
||||
*/
|
||||
int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_mode(&descr->device, mode);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart parity
|
||||
*/
|
||||
int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_parity(&descr->device, parity);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart stop bits
|
||||
*/
|
||||
int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_stop_bits(&descr->device, stop_bits);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set usart character size
|
||||
*/
|
||||
int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size)
|
||||
{
|
||||
ASSERT(descr);
|
||||
_usart_sync_set_character_size(&descr->device, size);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the state of flow control pins
|
||||
*/
|
||||
int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr,
|
||||
union usart_flow_control_state *const state)
|
||||
{
|
||||
ASSERT(descr && state);
|
||||
*state = _usart_sync_get_flow_control_state(&descr->device);
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Check if the usart transmitter is empty
|
||||
*/
|
||||
int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
return _usart_sync_is_ready_to_send(&descr->device);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Check if the usart receiver is not empty
|
||||
*/
|
||||
int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr)
|
||||
{
|
||||
ASSERT(descr);
|
||||
return _usart_sync_is_byte_received(&descr->device);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*/
|
||||
uint32_t usart_sync_get_version(void)
|
||||
{
|
||||
return DRIVER_VERSION;
|
||||
}
|
||||
|
||||
/*
|
||||
* \internal Write the given data to usart interface
|
||||
*
|
||||
* \param[in] descr The pointer to an io descriptor
|
||||
* \param[in] buf Data to write to usart
|
||||
* \param[in] length The number of bytes to write
|
||||
*
|
||||
* \return The number of bytes written.
|
||||
*/
|
||||
static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
|
||||
{
|
||||
uint32_t offset = 0;
|
||||
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
|
||||
|
||||
ASSERT(io_descr && buf && length);
|
||||
while (!_usart_sync_is_ready_to_send(&descr->device))
|
||||
;
|
||||
do {
|
||||
_usart_sync_write_byte(&descr->device, buf[offset]);
|
||||
while (!_usart_sync_is_ready_to_send(&descr->device))
|
||||
;
|
||||
} while (++offset < length);
|
||||
while (!_usart_sync_is_transmit_done(&descr->device))
|
||||
;
|
||||
return (int32_t)offset;
|
||||
}
|
||||
|
||||
/*
|
||||
* \internal Read data from usart interface
|
||||
*
|
||||
* \param[in] descr The pointer to an io descriptor
|
||||
* \param[in] buf A buffer to read data to
|
||||
* \param[in] length The size of a buffer
|
||||
*
|
||||
* \return The number of bytes read.
|
||||
*/
|
||||
static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
|
||||
{
|
||||
uint32_t offset = 0;
|
||||
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
|
||||
|
||||
ASSERT(io_descr && buf && length);
|
||||
do {
|
||||
while (!_usart_sync_is_byte_received(&descr->device))
|
||||
;
|
||||
buf[offset] = _usart_sync_read_byte(&descr->device);
|
||||
} while (++offset < length);
|
||||
|
||||
return (int32_t)offset;
|
||||
}
|
||||
@ -1,6 +0,0 @@
|
||||
/*
|
||||
* project.h
|
||||
*
|
||||
* Created: 4/19/2020 6:56:39 PM
|
||||
* Author: Penguin
|
||||
*/
|
||||
@ -1,6 +0,0 @@
|
||||
<environment>
|
||||
<configurations/>
|
||||
<device-packs>
|
||||
<device-pack device="ATSAME54P20A" name="SAME54_DFP" vendor="Atmel" version="1.1.134"/>
|
||||
</device-packs>
|
||||
</environment>
|
||||
@ -1,233 +0,0 @@
|
||||
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
|
||||
<vendor>Atmel</vendor>
|
||||
<name>My Project</name>
|
||||
<description>Project generated by Atmel Start</description>
|
||||
<url>http://start.atmel.com/</url>
|
||||
<releases>
|
||||
<release version="1.0.1">Initial version</release>
|
||||
</releases>
|
||||
<taxonomy>
|
||||
<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
|
||||
</taxonomy>
|
||||
<generators>
|
||||
<generator id="AtmelStart">
|
||||
<description>Atmel Start</description>
|
||||
<select Dname="ATSAME54P20A" Dvendor="Atmel:3"/>
|
||||
<command>http://start.atmel.com/</command>
|
||||
<files>
|
||||
<file category="generator" name="atmel_start_config.atstart"/>
|
||||
<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
|
||||
</files>
|
||||
</generator>
|
||||
</generators>
|
||||
<conditions>
|
||||
<condition id="CMSIS Device Startup">
|
||||
<description>Dependency on CMSIS core and Device Startup components</description>
|
||||
<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
|
||||
<require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/>
|
||||
</condition>
|
||||
<condition id="ARMCC, GCC, IAR">
|
||||
<require Dname="ATSAME54P20A"/>
|
||||
<accept Tcompiler="ARMCC"/>
|
||||
<accept Tcompiler="GCC"/>
|
||||
<accept Tcompiler="IAR"/>
|
||||
</condition>
|
||||
<condition id="GCC">
|
||||
<require Dname="ATSAME54P20A"/>
|
||||
<accept Tcompiler="GCC"/>
|
||||
</condition>
|
||||
</conditions>
|
||||
<components generator="AtmelStart">
|
||||
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
|
||||
<description>Atmel Start Framework</description>
|
||||
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
|
||||
<files>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/ext_irq.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/quad_spi_sync.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/timer.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_ext_irq.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_i2c_m_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_qspi_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ext_irq.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_qspi_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_time_measure.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_sync.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_qspi_sync.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_decrement_macro.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_recursion_macro.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
|
||||
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_can_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gmac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_i2s_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_icm_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pcc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pdec_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_qspi_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ramecc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdhc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e54.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_timer.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_calendar.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_pwm.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_ext_irq.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_timer.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m4.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/eic/hpl_eic.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/qspi/hpl_qspi.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/rtc/hpl_rtc.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/rtc/hpl_rtc_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/systick/hpl_systick.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc_base.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_eic_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_qspi_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_rtc_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_systick_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tc_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/eic"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/qspi"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/rtc"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/systick"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
|
||||
</files>
|
||||
</component>
|
||||
</components>
|
||||
</package>
|
||||
@ -1,865 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,266 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,935 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h
|
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||
* @version V5.0.7
|
||||
* @date 19. June 2018
|
||||
******************************************************************************/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2018 IAR Systems
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__
|
||||
#define __CMSIS_ICCARM_H__
|
||||
|
||||
#ifndef __ICCARM__
|
||||
#error This file should only be compiled by ICCARM
|
||||
#endif
|
||||
|
||||
#pragma system_include
|
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||
|
||||
#if (__VER__ >= 8000000)
|
||||
#define __ICCARM_V8 1
|
||||
#else
|
||||
#define __ICCARM_V8 0
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGNED
|
||||
#if __ICCARM_V8
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#elif (__VER__ >= 7080000)
|
||||
/* Needs IAR language extensions */
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#else
|
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/
|
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||
/* Macros already defined */
|
||||
#else
|
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||
#if __ARM_ARCH == 6
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif __ARM_ARCH == 7
|
||||
#if __ARM_FEATURE_DSP
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#else
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#endif /* __ARM_ARCH */
|
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||
#endif
|
||||
|
||||
/* Alternativ core deduction for older ICCARM's */
|
||||
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#else
|
||||
#error "Unknown target."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#else
|
||||
#define __IAR_M0_FAMILY 0
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if __ICCARM_V8
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#else
|
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_STRUCT
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_UNION
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE _Pragma("inline=forced")
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint16_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||
{
|
||||
*(__packed uint16_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint32_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||
{
|
||||
*(__packed uint32_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__packed struct __iar_u32 { uint32_t v; };
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||
#endif
|
||||
|
||||
#ifndef __USED
|
||||
#if __ICCARM_V8
|
||||
#define __USED __attribute__((used))
|
||||
#else
|
||||
#define __USED _Pragma("__root")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#if __ICCARM_V8
|
||||
#define __WEAK __attribute__((weak))
|
||||
#else
|
||||
#define __WEAK _Pragma("__weak")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||
#endif
|
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||
|
||||
#if defined(__CLZ)
|
||||
#undef __CLZ
|
||||
#endif
|
||||
#if defined(__REVSH)
|
||||
#undef __REVSH
|
||||
#endif
|
||||
#if defined(__RBIT)
|
||||
#undef __RBIT
|
||||
#endif
|
||||
#if defined(__SSAT)
|
||||
#undef __SSAT
|
||||
#endif
|
||||
#if defined(__USAT)
|
||||
#undef __USAT
|
||||
#endif
|
||||
|
||||
#include "iccarm_builtin.h"
|
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||
#define __disable_irq __iar_builtin_disable_interrupt
|
||||
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||
#define __enable_irq __iar_builtin_enable_interrupt
|
||||
#define __arm_rsr __iar_builtin_rsr
|
||||
#define __arm_wsr __iar_builtin_wsr
|
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR"))
|
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||
#else
|
||||
#define __get_FPSCR() ( 0 )
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||
#define __get_MSP() (__arm_rsr("MSP"))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U)
|
||||
#else
|
||||
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||
#endif
|
||||
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||
#define __get_PSP() (__arm_rsr("PSP"))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U)
|
||||
#else
|
||||
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||
#endif
|
||||
|
||||
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||
|
||||
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||
#endif
|
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __TZ_get_PSPLIM_NS() (0U)
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
#define __DSB __iar_builtin_DSB
|
||||
#define __ISB __iar_builtin_ISB
|
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB
|
||||
#define __LDREXH __iar_builtin_LDREXH
|
||||
#define __LDREXW __iar_builtin_LDREX
|
||||
|
||||
#define __RBIT __iar_builtin_RBIT
|
||||
#define __REV __iar_builtin_REV
|
||||
#define __REV16 __iar_builtin_REV16
|
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val)
|
||||
{
|
||||
return (int16_t) __iar_builtin_REVSH(val);
|
||||
}
|
||||
|
||||
#define __ROR __iar_builtin_ROR
|
||||
#define __RRX __iar_builtin_RRX
|
||||
|
||||
#define __SEV __iar_builtin_SEV
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __SSAT __iar_builtin_SSAT
|
||||
#endif
|
||||
|
||||
#define __STREXB __iar_builtin_STREXB
|
||||
#define __STREXH __iar_builtin_STREXH
|
||||
#define __STREXW __iar_builtin_STREX
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __USAT __iar_builtin_USAT
|
||||
#endif
|
||||
|
||||
#define __WFE __iar_builtin_WFE
|
||||
#define __WFI __iar_builtin_WFI
|
||||
|
||||
#if __ARM_MEDIA__
|
||||
#define __SADD8 __iar_builtin_SADD8
|
||||
#define __QADD8 __iar_builtin_QADD8
|
||||
#define __SHADD8 __iar_builtin_SHADD8
|
||||
#define __UADD8 __iar_builtin_UADD8
|
||||
#define __UQADD8 __iar_builtin_UQADD8
|
||||
#define __UHADD8 __iar_builtin_UHADD8
|
||||
#define __SSUB8 __iar_builtin_SSUB8
|
||||
#define __QSUB8 __iar_builtin_QSUB8
|
||||
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||
#define __USUB8 __iar_builtin_USUB8
|
||||
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||
#define __SADD16 __iar_builtin_SADD16
|
||||
#define __QADD16 __iar_builtin_QADD16
|
||||
#define __SHADD16 __iar_builtin_SHADD16
|
||||
#define __UADD16 __iar_builtin_UADD16
|
||||
#define __UQADD16 __iar_builtin_UQADD16
|
||||
#define __UHADD16 __iar_builtin_UHADD16
|
||||
#define __SSUB16 __iar_builtin_SSUB16
|
||||
#define __QSUB16 __iar_builtin_QSUB16
|
||||
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||
#define __USUB16 __iar_builtin_USUB16
|
||||
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||
#define __SASX __iar_builtin_SASX
|
||||
#define __QASX __iar_builtin_QASX
|
||||
#define __SHASX __iar_builtin_SHASX
|
||||
#define __UASX __iar_builtin_UASX
|
||||
#define __UQASX __iar_builtin_UQASX
|
||||
#define __UHASX __iar_builtin_UHASX
|
||||
#define __SSAX __iar_builtin_SSAX
|
||||
#define __QSAX __iar_builtin_QSAX
|
||||
#define __SHSAX __iar_builtin_SHSAX
|
||||
#define __USAX __iar_builtin_USAX
|
||||
#define __UQSAX __iar_builtin_UQSAX
|
||||
#define __UHSAX __iar_builtin_UHSAX
|
||||
#define __USAD8 __iar_builtin_USAD8
|
||||
#define __USADA8 __iar_builtin_USADA8
|
||||
#define __SSAT16 __iar_builtin_SSAT16
|
||||
#define __USAT16 __iar_builtin_USAT16
|
||||
#define __UXTB16 __iar_builtin_UXTB16
|
||||
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||
#define __SXTB16 __iar_builtin_SXTB16
|
||||
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||
#define __SMUAD __iar_builtin_SMUAD
|
||||
#define __SMUADX __iar_builtin_SMUADX
|
||||
#define __SMMLA __iar_builtin_SMMLA
|
||||
#define __SMLAD __iar_builtin_SMLAD
|
||||
#define __SMLADX __iar_builtin_SMLADX
|
||||
#define __SMLALD __iar_builtin_SMLALD
|
||||
#define __SMLALDX __iar_builtin_SMLALDX
|
||||
#define __SMUSD __iar_builtin_SMUSD
|
||||
#define __SMUSDX __iar_builtin_SMUSDX
|
||||
#define __SMLSD __iar_builtin_SMLSD
|
||||
#define __SMLSDX __iar_builtin_SMLSDX
|
||||
#define __SMLSLD __iar_builtin_SMLSLD
|
||||
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||
#define __SEL __iar_builtin_SEL
|
||||
#define __QADD __iar_builtin_QADD
|
||||
#define __QSUB __iar_builtin_QSUB
|
||||
#define __PKHBT __iar_builtin_PKHBT
|
||||
#define __PKHTB __iar_builtin_PKHTB
|
||||
#endif
|
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#define __CLZ __cmsis_iar_clz_not_active
|
||||
#define __SSAT __cmsis_iar_ssat_not_active
|
||||
#define __USAT __cmsis_iar_usat_not_active
|
||||
#define __RBIT __cmsis_iar_rbit_not_active
|
||||
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||
#endif
|
||||
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||
#endif
|
||||
|
||||
#ifdef __INTRINSICS_INCLUDED
|
||||
#error intrinsics.h is already included previously!
|
||||
#endif
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#undef __CLZ
|
||||
#undef __SSAT
|
||||
#undef __USAT
|
||||
#undef __RBIT
|
||||
#undef __get_APSR
|
||||
|
||||
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0U) { return 32U; }
|
||||
|
||||
uint32_t count = 0U;
|
||||
uint32_t mask = 0x80000000U;
|
||||
|
||||
while ((data & mask) == 0U)
|
||||
{
|
||||
count += 1U;
|
||||
mask = mask >> 1U;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||
{
|
||||
uint8_t sc = 31U;
|
||||
uint32_t r = v;
|
||||
for (v >>= 1U; v; v >>= 1U)
|
||||
{
|
||||
r <<= 1U;
|
||||
r |= v & 1U;
|
||||
sc--;
|
||||
}
|
||||
return (r << sc);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm("MRS %0,APSR" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#undef __get_FPSCR
|
||||
#undef __set_FPSCR
|
||||
#define __get_FPSCR() (0)
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
#pragma diag_suppress=Pe177
|
||||
|
||||
#define __enable_irq __enable_interrupt
|
||||
#define __disable_irq __disable_interrupt
|
||||
#define __NOP __no_operation
|
||||
|
||||
#define __get_xPSR __get_PSR
|
||||
|
||||
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||
{
|
||||
return __LDREX((unsigned long *)ptr);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||
{
|
||||
return __STREX(value, (unsigned long *)ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||
return(result);
|
||||
}
|
||||
|
||||
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||
}
|
||||
|
||||
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||
}
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
|
||||
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
|
||||
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#undef __IAR_FT
|
||||
#undef __IAR_M0_FAMILY
|
||||
#undef __ICCARM_V8
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
#pragma diag_default=Pe177
|
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */
|
||||
@ -1,39 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,949 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V5.0.5
|
||||
* @date 28. May 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,976 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm1.h
|
||||
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||
* @version V1.0.0
|
||||
* @date 23. July 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM1_H_GENERIC
|
||||
#define __CORE_CM1_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M1
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM1 definitions */
|
||||
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM1_H_DEPENDANT
|
||||
#define __CORE_CM1_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM1_REV
|
||||
#define __CM1_REV 0x0100U
|
||||
#warning "__CM1_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M1 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[2U];
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M1 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,270 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if non-shareable) or 010b (if shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -1,333 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,70 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
@ -1,196 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
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<head>
|
||||
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
|
||||
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
|
||||
<title>Overview</title>
|
||||
<title>CMSIS-Core (Cortex-M): Overview</title>
|
||||
<link href="tabs.css" rel="stylesheet" type="text/css"/>
|
||||
<link href="cmsis.css" rel="stylesheet" type="text/css" />
|
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<script type="text/javascript" src="jquery.js"></script>
|
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<script type="text/javascript" src="dynsections.js"></script>
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<script type="text/javascript" src="printComponentTabs.js"></script>
|
||||
<link href="navtree.css" rel="stylesheet" type="text/css"/>
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<script type="text/javascript" src="resize.js"></script>
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<script type="text/javascript" src="navtree.js"></script>
|
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$(document).ready(initResizable);
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$(window).load(resizeHeight);
|
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<link href="search/search.css" rel="stylesheet" type="text/css"/>
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<script type="text/javascript" src="search/search.js"></script>
|
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<script type="text/javascript">
|
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$(document).ready(function() { searchBox.OnSelectItem(0); });
|
||||
</script>
|
||||
</head>
|
||||
<body>
|
||||
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
|
||||
<div id="titlearea">
|
||||
<table cellspacing="0" cellpadding="0">
|
||||
<tbody>
|
||||
<tr style="height: 46px;">
|
||||
<td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
|
||||
<td style="padding-left: 0.5em;">
|
||||
<div id="projectname">CMSIS-Core (Cortex-M)
|
||||
 <span id="projectnumber">Version 5.1.2</span>
|
||||
</div>
|
||||
<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<!-- end header part -->
|
||||
<div id="CMSISnav" class="tabs1">
|
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<ul class="tablist">
|
||||
<script type="text/javascript">
|
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|
||||
writeComponentTabs.call(this);
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//-->
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|
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var searchBox = new SearchBox("searchBox", "search",false,'Search');
|
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</script>
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<div id="navrow1" class="tabs">
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<ul class="tablist">
|
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<li class="current"><a href="index.html"><span>Main Page</span></a></li>
|
||||
<li><a href="pages.html"><span>Usage and Description</span></a></li>
|
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<li><a href="modules.html"><span>Reference</span></a></li>
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<div id="MSearchBox" class="MSearchBoxInactive">
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<span class="left">
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<img id="MSearchSelect" src="search/mag_sel.png"
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onmouseover="return searchBox.OnSearchSelectShow()"
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alt=""/>
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<input type="text" id="MSearchField" value="Search" accesskey="S"
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onfocus="searchBox.OnSearchFieldFocus(true)"
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onblur="searchBox.OnSearchFieldFocus(false)"
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onkeyup="searchBox.OnSearchFieldChange(event)"/>
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<a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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</span>
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</div>
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</li>
|
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</ul>
|
||||
</div>
|
||||
</div><!-- top -->
|
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<div id="side-nav" class="ui-resizable side-nav-resizable">
|
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<div id="nav-tree">
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<div id="nav-tree-contents">
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<div id="nav-sync" class="sync"></div>
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</div>
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<div id="splitbar" style="-moz-user-select:none;"
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class="ui-resizable-handle">
|
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</div>
|
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</div>
|
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<script type="text/javascript">
|
||||
$(document).ready(function(){initNavTree('index.html','');});
|
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</script>
|
||||
<div id="doc-content">
|
||||
<!-- window showing the filter options -->
|
||||
<div id="MSearchSelectWindow"
|
||||
onmouseover="return searchBox.OnSearchSelectShow()"
|
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onmouseout="return searchBox.OnSearchSelectHide()"
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onkeydown="return searchBox.OnSearchSelectKey(event)">
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<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div>
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</div>
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|
||||
<div class="header">
|
||||
<div class="headertitle">
|
||||
<div class="title">Overview </div> </div>
|
||||
</div><!--header-->
|
||||
<div class="contents">
|
||||
<div class="textblock"><p>CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p>
|
||||
<ul>
|
||||
<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
|
||||
<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
|
||||
<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
|
||||
<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
|
||||
<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
|
||||
<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
|
||||
</ul>
|
||||
<p>The following sections provide details about the CMSIS-Core (Cortex-M):</p>
|
||||
<ul>
|
||||
<li><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li>
|
||||
<li><a class="el" href="using_TrustZone_pg.html">Using TrustZone® for Armv8-M</a> describes how to use the security extensions available in the Armv8-M architecture.</li>
|
||||
<li><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.</li>
|
||||
<li><a class="el" href="coreMISRA_Exceptions_pg.html">MISRA-C Deviations</a> describes the violations to the MISRA standard.</li>
|
||||
<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
|
||||
<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
|
||||
</ul>
|
||||
<hr/>
|
||||
<h2>CMSIS-Core (Cortex-M) in ARM::CMSIS Pack </h2>
|
||||
<p>Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories: </p>
|
||||
<table class="doxtable">
|
||||
<tr>
|
||||
<th>File/Folder </th><th>Content </th></tr>
|
||||
<tr>
|
||||
<td><b>CMSIS\Documentation\Core</b> </td><td>This documentation </td></tr>
|
||||
<tr>
|
||||
<td><b>CMSIS\Core\Include</b> </td><td>CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) </td></tr>
|
||||
<tr>
|
||||
<td><b>Device</b> </td><td><a class="el" href="using_ARM_pg.html">Arm reference implementations</a> of Cortex-M devices </td></tr>
|
||||
<tr>
|
||||
<td><b>Device\_Template_Vendor</b> </td><td><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> for extension by silicon vendors </td></tr>
|
||||
</table>
|
||||
<hr/>
|
||||
<h1><a class="anchor" id="ref_v6-v8M"></a>
|
||||
Processor Support</h1>
|
||||
<p>CMSIS supports the complete range of <a href="http://www.arm.com/products/processors/cortex-m/index.php" target="_blank"><b>Cortex-M processors</b></a> (with exception of Cortex-M1) and the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M architecture</b></a> including security extensions.</p>
|
||||
<h2><a class="anchor" id="ref_man_sec"></a>
|
||||
Cortex-M Reference Manuals</h2>
|
||||
<p>The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:</p>
|
||||
<ul>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (ARMv7-M architecture)</li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
|
||||
</ul>
|
||||
<p>The <b>Cortex-M23</b> and <b>Cortex-M33</b> are described with Technical Reference Manuals that are available here:</p>
|
||||
<ul>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (Armv8-M baseline architecture)</li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (Armv8-M mainline architecture)</li>
|
||||
</ul>
|
||||
<h2><a class="anchor" id="ARMv8M"></a>
|
||||
Armv8-M Architecture</h2>
|
||||
<p>Armv8-M introduces two profiles <b>baseline</b> (for power and area constrained applications) and <b>mainline</b> (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.</p>
|
||||
<p>The Armv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.</p>
|
||||
<hr/>
|
||||
<h1><a class="anchor" id="tested_tools_sec"></a>
|
||||
Tested and Verified Toolchains</h1>
|
||||
<p>The <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> supplied by Arm have been tested and verified with the following toolchains:</p>
|
||||
<ul>
|
||||
<li>Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)</li>
|
||||
<li>Arm: Arm Compiler 6.9</li>
|
||||
<li>Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)</li>
|
||||
<li>GNU: GNU Tools for Arm Embedded 6.3.1 20170620</li>
|
||||
<li>IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183</li>
|
||||
</ul>
|
||||
<hr/>
|
||||
</div></div><!-- contents -->
|
||||
</div><!-- doc-content -->
|
||||
<!-- start footer part -->
|
||||
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
|
||||
<ul>
|
||||
<li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved.
|
||||
<!--
|
||||
<a href="http://www.doxygen.org/index.html">
|
||||
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6
|
||||
-->
|
||||
</li>
|
||||
</ul>
|
||||
</div>
|
||||
</body>
|
||||
</html>
|
||||
@ -1,243 +0,0 @@
|
||||
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
ifdef SystemRoot
|
||||
SHELL = cmd.exe
|
||||
MK_DIR = mkdir
|
||||
else
|
||||
ifeq ($(shell uname), Linux)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
|
||||
ifeq ($(shell uname | cut -d _ -f 1), CYGWIN)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
|
||||
ifeq ($(shell uname | cut -d _ -f 1), MINGW32)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
|
||||
ifeq ($(shell uname | cut -d _ -f 1), MINGW64)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
endif
|
||||
|
||||
# List the subdirectories for creating object files
|
||||
SUB_DIRS += \
|
||||
\
|
||||
hpl/pm \
|
||||
hpl/tc \
|
||||
hpl/osc32kctrl \
|
||||
hpl/ramecc \
|
||||
hpl/dmac \
|
||||
hal/src \
|
||||
armcc/arm_addon/armcc \
|
||||
hpl/mclk \
|
||||
hpl/qspi \
|
||||
hpl/eic \
|
||||
hpl/sercom \
|
||||
examples \
|
||||
hpl/gclk \
|
||||
hpl/oscctrl \
|
||||
hal/utils/src \
|
||||
hpl/rtc \
|
||||
armcc/arm_addon/armcc/arm \
|
||||
hpl/systick \
|
||||
hpl/core \
|
||||
hpl/cmcc
|
||||
|
||||
# List the object files
|
||||
OBJS += \
|
||||
hal/src/hal_io.o \
|
||||
hpl/qspi/hpl_qspi.o \
|
||||
armcc/arm_addon/armcc/system_same54.o \
|
||||
hpl/eic/hpl_eic.o \
|
||||
hpl/core/hpl_core_m4.o \
|
||||
hpl/systick/hpl_systick.o \
|
||||
hal/src/hal_timer.o \
|
||||
hal/src/hal_i2c_m_sync.o \
|
||||
hal/src/hal_delay.o \
|
||||
hpl/pm/hpl_pm.o \
|
||||
hpl/core/hpl_init.o \
|
||||
hpl/ramecc/hpl_ramecc.o \
|
||||
hal/utils/src/utils_list.o \
|
||||
hal/utils/src/utils_assert.o \
|
||||
hpl/dmac/hpl_dmac.o \
|
||||
hpl/oscctrl/hpl_oscctrl.o \
|
||||
hal/src/hal_usart_sync.o \
|
||||
hpl/mclk/hpl_mclk.o \
|
||||
hpl/sercom/hpl_sercom.o \
|
||||
hpl/gclk/hpl_gclk.o \
|
||||
hal/src/hal_init.o \
|
||||
main.o \
|
||||
hpl/osc32kctrl/hpl_osc32kctrl.o \
|
||||
hpl/rtc/hpl_rtc.o \
|
||||
examples/driver_examples.o \
|
||||
driver_init.o \
|
||||
hal/src/hal_ext_irq.o \
|
||||
hal/src/hal_atomic.o \
|
||||
hal/src/hal_gpio.o \
|
||||
hal/src/hal_qspi_sync.o \
|
||||
hal/utils/src/utils_event.o \
|
||||
hal/src/hal_sleep.o \
|
||||
hal/src/hal_cache.o \
|
||||
atmel_start.o \
|
||||
hpl/tc/hpl_tc.o \
|
||||
hpl/cmcc/hpl_cmcc.o \
|
||||
armcc/arm_addon/armcc/arm/startup_same54.o
|
||||
|
||||
OBJS_AS_ARGS += \
|
||||
"hal/src/hal_io.o" \
|
||||
"hpl/qspi/hpl_qspi.o" \
|
||||
"armcc/arm_addon/armcc/system_same54.o" \
|
||||
"hpl/eic/hpl_eic.o" \
|
||||
"hpl/core/hpl_core_m4.o" \
|
||||
"hpl/systick/hpl_systick.o" \
|
||||
"hal/src/hal_timer.o" \
|
||||
"hal/src/hal_i2c_m_sync.o" \
|
||||
"hal/src/hal_delay.o" \
|
||||
"hpl/pm/hpl_pm.o" \
|
||||
"hpl/core/hpl_init.o" \
|
||||
"hpl/ramecc/hpl_ramecc.o" \
|
||||
"hal/utils/src/utils_list.o" \
|
||||
"hal/utils/src/utils_assert.o" \
|
||||
"hpl/dmac/hpl_dmac.o" \
|
||||
"hpl/oscctrl/hpl_oscctrl.o" \
|
||||
"hal/src/hal_usart_sync.o" \
|
||||
"hpl/mclk/hpl_mclk.o" \
|
||||
"hpl/sercom/hpl_sercom.o" \
|
||||
"hpl/gclk/hpl_gclk.o" \
|
||||
"hal/src/hal_init.o" \
|
||||
"main.o" \
|
||||
"hpl/osc32kctrl/hpl_osc32kctrl.o" \
|
||||
"hpl/rtc/hpl_rtc.o" \
|
||||
"examples/driver_examples.o" \
|
||||
"driver_init.o" \
|
||||
"hal/src/hal_ext_irq.o" \
|
||||
"hal/src/hal_atomic.o" \
|
||||
"hal/src/hal_gpio.o" \
|
||||
"hal/src/hal_qspi_sync.o" \
|
||||
"hal/utils/src/utils_event.o" \
|
||||
"hal/src/hal_sleep.o" \
|
||||
"hal/src/hal_cache.o" \
|
||||
"atmel_start.o" \
|
||||
"hpl/tc/hpl_tc.o" \
|
||||
"hpl/cmcc/hpl_cmcc.o" \
|
||||
"armcc/arm_addon/armcc/arm/startup_same54.o"
|
||||
|
||||
# List the dependency files
|
||||
DEPS := $(OBJS:%.o=%.d)
|
||||
|
||||
DEPS_AS_ARGS += \
|
||||
"hal/utils/src/utils_event.d" \
|
||||
"hal/src/hal_io.d" \
|
||||
"armcc/arm_addon/armcc/system_same54.d" \
|
||||
"hpl/ramecc/hpl_ramecc.d" \
|
||||
"hpl/qspi/hpl_qspi.d" \
|
||||
"hpl/core/hpl_core_m4.d" \
|
||||
"hpl/eic/hpl_eic.d" \
|
||||
"hal/src/hal_i2c_m_sync.d" \
|
||||
"hal/src/hal_timer.d" \
|
||||
"hal/utils/src/utils_list.d" \
|
||||
"hpl/cmcc/hpl_cmcc.d" \
|
||||
"hpl/dmac/hpl_dmac.d" \
|
||||
"hal/utils/src/utils_assert.d" \
|
||||
"hal/src/hal_delay.d" \
|
||||
"hpl/core/hpl_init.d" \
|
||||
"hpl/pm/hpl_pm.d" \
|
||||
"hpl/gclk/hpl_gclk.d" \
|
||||
"hpl/sercom/hpl_sercom.d" \
|
||||
"hal/src/hal_init.d" \
|
||||
"hal/src/hal_usart_sync.d" \
|
||||
"hpl/mclk/hpl_mclk.d" \
|
||||
"driver_init.d" \
|
||||
"hpl/systick/hpl_systick.d" \
|
||||
"hpl/osc32kctrl/hpl_osc32kctrl.d" \
|
||||
"main.d" \
|
||||
"examples/driver_examples.d" \
|
||||
"hpl/rtc/hpl_rtc.d" \
|
||||
"hal/src/hal_qspi_sync.d" \
|
||||
"hal/src/hal_cache.d" \
|
||||
"hal/src/hal_sleep.d" \
|
||||
"hal/src/hal_ext_irq.d" \
|
||||
"hal/src/hal_gpio.d" \
|
||||
"hal/src/hal_atomic.d" \
|
||||
"hpl/tc/hpl_tc.d" \
|
||||
"hpl/oscctrl/hpl_oscctrl.d" \
|
||||
"armcc/arm_addon/armcc/arm/startup_same54.d" \
|
||||
"atmel_start.d"
|
||||
|
||||
OUTPUT_FILE_NAME :=AtmelStart
|
||||
QUOTE := "
|
||||
OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf
|
||||
OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf
|
||||
|
||||
vpath %.c ../
|
||||
vpath %.s ../
|
||||
vpath %.S ../
|
||||
|
||||
# All Target
|
||||
all: $(SUB_DIRS) $(OUTPUT_FILE_PATH)
|
||||
|
||||
# Linker target
|
||||
|
||||
$(OUTPUT_FILE_PATH): $(OBJS)
|
||||
@echo Building target: $@
|
||||
@echo Invoking: ARMCC Linker
|
||||
$(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \
|
||||
--strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \
|
||||
--info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \
|
||||
-o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M4 \
|
||||
$(OBJS_AS_ARGS)
|
||||
|
||||
@echo Finished building target: $@
|
||||
|
||||
# Compiler target(s)
|
||||
|
||||
|
||||
|
||||
|
||||
%.o: %.c
|
||||
@echo Building file: $<
|
||||
@echo ARMCC Compiler
|
||||
$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \
|
||||
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/qspi" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
|
||||
--depend "$@" -o "$@" "$<"
|
||||
|
||||
@echo Finished building: $<
|
||||
|
||||
%.o: %.s
|
||||
@echo Building file: $<
|
||||
@echo ARMCC Assembler
|
||||
$(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M4 --pd "D__SAME54P20A__ SETA 1" \
|
||||
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/qspi" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
|
||||
--depend "$(@:%.o=%.d)" -o "$@" "$<"
|
||||
|
||||
@echo Finished building: $<
|
||||
|
||||
%.o: %.S
|
||||
@echo Building file: $<
|
||||
@echo ARMCC Preprocessing Assembler
|
||||
$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \
|
||||
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/qspi" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
|
||||
--depend "$@" -o "$@" "$<"
|
||||
|
||||
@echo Finished building: $<
|
||||
|
||||
# Detect changes in the dependent files and recompile the respective object files.
|
||||
ifneq ($(MAKECMDGOALS),clean)
|
||||
ifneq ($(strip $(DEPS)),)
|
||||
-include $(DEPS)
|
||||
endif
|
||||
endif
|
||||
|
||||
$(SUB_DIRS):
|
||||
$(MK_DIR) "$@"
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS_AS_ARGS)
|
||||
rm -f $(OUTPUT_FILE_PATH)
|
||||
rm -f $(DEPS_AS_ARGS)
|
||||
rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf
|
||||
@ -1,588 +0,0 @@
|
||||
;/*****************************************************************************
|
||||
; * @file startup_SAME54.s
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for
|
||||
; * Atmel SAME54 Device Series
|
||||
; * @version V1.0.0
|
||||
; * @date 16. January 2017
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2017 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000200
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD PM_Handler ; 0 Power Manager
|
||||
DCD MCLK_Handler ; 1 Main Clock
|
||||
DCD OSCCTRL_0_Handler ; 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0
|
||||
DCD OSCCTRL_1_Handler ; 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1
|
||||
DCD OSCCTRL_2_Handler ; 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY
|
||||
DCD OSCCTRL_3_Handler ; 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0
|
||||
DCD OSCCTRL_4_Handler ; 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1
|
||||
DCD OSC32KCTRL_Handler ; 7 32kHz Oscillators Control
|
||||
DCD SUPC_0_Handler ; 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY
|
||||
DCD SUPC_1_Handler ; 9 SUPC_BOD12DET, SUPC_BOD33DET
|
||||
DCD WDT_Handler ; 10 Watchdog Timer
|
||||
DCD RTC_Handler ; 11 Real-Time Counter
|
||||
DCD EIC_0_Handler ; 12 EIC_EXTINT_0
|
||||
DCD EIC_1_Handler ; 13 EIC_EXTINT_1
|
||||
DCD EIC_2_Handler ; 14 EIC_EXTINT_2
|
||||
DCD EIC_3_Handler ; 15 EIC_EXTINT_3
|
||||
DCD EIC_4_Handler ; 16 EIC_EXTINT_4
|
||||
DCD EIC_5_Handler ; 17 EIC_EXTINT_5
|
||||
DCD EIC_6_Handler ; 18 EIC_EXTINT_6
|
||||
DCD EIC_7_Handler ; 19 EIC_EXTINT_7
|
||||
DCD EIC_8_Handler ; 20 EIC_EXTINT_8
|
||||
DCD EIC_9_Handler ; 21 EIC_EXTINT_9
|
||||
DCD EIC_10_Handler ; 22 EIC_EXTINT_10
|
||||
DCD EIC_11_Handler ; 23 EIC_EXTINT_11
|
||||
DCD EIC_12_Handler ; 24 EIC_EXTINT_12
|
||||
DCD EIC_13_Handler ; 25 EIC_EXTINT_13
|
||||
DCD EIC_14_Handler ; 26 EIC_EXTINT_14
|
||||
DCD EIC_15_Handler ; 27 EIC_EXTINT_15
|
||||
DCD FREQM_Handler ; 28 Frequency Meter
|
||||
DCD NVMCTRL_0_Handler ; 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7
|
||||
DCD NVMCTRL_1_Handler ; 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9
|
||||
DCD DMAC_0_Handler ; 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0
|
||||
DCD DMAC_1_Handler ; 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1
|
||||
DCD DMAC_2_Handler ; 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2
|
||||
DCD DMAC_3_Handler ; 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3
|
||||
DCD DMAC_4_Handler ; 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9
|
||||
DCD EVSYS_0_Handler ; 36 EVSYS_EVD_0, EVSYS_OVR_0
|
||||
DCD EVSYS_1_Handler ; 37 EVSYS_EVD_1, EVSYS_OVR_1
|
||||
DCD EVSYS_2_Handler ; 38 EVSYS_EVD_2, EVSYS_OVR_2
|
||||
DCD EVSYS_3_Handler ; 39 EVSYS_EVD_3, EVSYS_OVR_3
|
||||
DCD EVSYS_4_Handler ; 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9
|
||||
DCD PAC_Handler ; 41 Peripheral Access Controller
|
||||
DCD TAL_0_Handler ; 42 TAL_BRK
|
||||
DCD TAL_1_Handler ; 43 TAL_IPS_0, TAL_IPS_1
|
||||
DCD 0 ; 44 Reserved
|
||||
DCD RAMECC_Handler ; 45 RAM ECC
|
||||
DCD SERCOM0_0_Handler ; 46 SERCOM0_0
|
||||
DCD SERCOM0_1_Handler ; 47 SERCOM0_1
|
||||
DCD SERCOM0_2_Handler ; 48 SERCOM0_2
|
||||
DCD SERCOM0_3_Handler ; 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6
|
||||
DCD SERCOM1_0_Handler ; 50 SERCOM1_0
|
||||
DCD SERCOM1_1_Handler ; 51 SERCOM1_1
|
||||
DCD SERCOM1_2_Handler ; 52 SERCOM1_2
|
||||
DCD SERCOM1_3_Handler ; 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6
|
||||
DCD SERCOM2_0_Handler ; 54 SERCOM2_0
|
||||
DCD SERCOM2_1_Handler ; 55 SERCOM2_1
|
||||
DCD SERCOM2_2_Handler ; 56 SERCOM2_2
|
||||
DCD SERCOM2_3_Handler ; 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6
|
||||
DCD SERCOM3_0_Handler ; 58 SERCOM3_0
|
||||
DCD SERCOM3_1_Handler ; 59 SERCOM3_1
|
||||
DCD SERCOM3_2_Handler ; 60 SERCOM3_2
|
||||
DCD SERCOM3_3_Handler ; 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6
|
||||
DCD SERCOM4_0_Handler ; 62 SERCOM4_0
|
||||
DCD SERCOM4_1_Handler ; 63 SERCOM4_1
|
||||
DCD SERCOM4_2_Handler ; 64 SERCOM4_2
|
||||
DCD SERCOM4_3_Handler ; 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6
|
||||
DCD SERCOM5_0_Handler ; 66 SERCOM5_0
|
||||
DCD SERCOM5_1_Handler ; 67 SERCOM5_1
|
||||
DCD SERCOM5_2_Handler ; 68 SERCOM5_2
|
||||
DCD SERCOM5_3_Handler ; 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6
|
||||
DCD SERCOM6_0_Handler ; 70 SERCOM6_0
|
||||
DCD SERCOM6_1_Handler ; 71 SERCOM6_1
|
||||
DCD SERCOM6_2_Handler ; 72 SERCOM6_2
|
||||
DCD SERCOM6_3_Handler ; 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6
|
||||
DCD SERCOM7_0_Handler ; 74 SERCOM7_0
|
||||
DCD SERCOM7_1_Handler ; 75 SERCOM7_1
|
||||
DCD SERCOM7_2_Handler ; 76 SERCOM7_2
|
||||
DCD SERCOM7_3_Handler ; 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6
|
||||
DCD CAN0_Handler ; 78 Control Area Network 0
|
||||
DCD CAN1_Handler ; 79 Control Area Network 1
|
||||
DCD USB_0_Handler ; 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP
|
||||
DCD USB_1_Handler ; 81 USB_SOF_HSOF
|
||||
DCD USB_2_Handler ; 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7
|
||||
DCD USB_3_Handler ; 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7
|
||||
DCD GMAC_Handler ; 84 Ethernet MAC
|
||||
DCD TCC0_0_Handler ; 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A
|
||||
DCD TCC0_1_Handler ; 86 TCC0_MC_0
|
||||
DCD TCC0_2_Handler ; 87 TCC0_MC_1
|
||||
DCD TCC0_3_Handler ; 88 TCC0_MC_2
|
||||
DCD TCC0_4_Handler ; 89 TCC0_MC_3
|
||||
DCD TCC0_5_Handler ; 90 TCC0_MC_4
|
||||
DCD TCC0_6_Handler ; 91 TCC0_MC_5
|
||||
DCD TCC1_0_Handler ; 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A
|
||||
DCD TCC1_1_Handler ; 93 TCC1_MC_0
|
||||
DCD TCC1_2_Handler ; 94 TCC1_MC_1
|
||||
DCD TCC1_3_Handler ; 95 TCC1_MC_2
|
||||
DCD TCC1_4_Handler ; 96 TCC1_MC_3
|
||||
DCD TCC2_0_Handler ; 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A
|
||||
DCD TCC2_1_Handler ; 98 TCC2_MC_0
|
||||
DCD TCC2_2_Handler ; 99 TCC2_MC_1
|
||||
DCD TCC2_3_Handler ; 100 TCC2_MC_2
|
||||
DCD TCC3_0_Handler ; 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A
|
||||
DCD TCC3_1_Handler ; 102 TCC3_MC_0
|
||||
DCD TCC3_2_Handler ; 103 TCC3_MC_1
|
||||
DCD TCC4_0_Handler ; 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A
|
||||
DCD TCC4_1_Handler ; 105 TCC4_MC_0
|
||||
DCD TCC4_2_Handler ; 106 TCC4_MC_1
|
||||
DCD TC0_Handler ; 107 Basic Timer Counter 0
|
||||
DCD TC1_Handler ; 108 Basic Timer Counter 1
|
||||
DCD TC2_Handler ; 109 Basic Timer Counter 2
|
||||
DCD TC3_Handler ; 110 Basic Timer Counter 3
|
||||
DCD TC4_Handler ; 111 Basic Timer Counter 4
|
||||
DCD TC5_Handler ; 112 Basic Timer Counter 5
|
||||
DCD TC6_Handler ; 113 Basic Timer Counter 6
|
||||
DCD TC7_Handler ; 114 Basic Timer Counter 7
|
||||
DCD PDEC_0_Handler ; 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A
|
||||
DCD PDEC_1_Handler ; 116 PDEC_MC_0
|
||||
DCD PDEC_2_Handler ; 117 PDEC_MC_1
|
||||
DCD ADC0_0_Handler ; 118 ADC0_OVERRUN, ADC0_WINMON
|
||||
DCD ADC0_1_Handler ; 119 ADC0_RESRDY
|
||||
DCD ADC1_0_Handler ; 120 ADC1_OVERRUN, ADC1_WINMON
|
||||
DCD ADC1_1_Handler ; 121 ADC1_RESRDY
|
||||
DCD AC_Handler ; 122 Analog Comparators
|
||||
DCD DAC_0_Handler ; 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1
|
||||
DCD DAC_1_Handler ; 124 DAC_EMPTY_0
|
||||
DCD DAC_2_Handler ; 125 DAC_EMPTY_1
|
||||
DCD DAC_3_Handler ; 126 DAC_RESRDY_0
|
||||
DCD DAC_4_Handler ; 127 DAC_RESRDY_1
|
||||
DCD I2S_Handler ; 128 Inter-IC Sound Interface
|
||||
DCD PCC_Handler ; 129 Parallel Capture Controller
|
||||
DCD AES_Handler ; 130 Advanced Encryption Standard
|
||||
DCD TRNG_Handler ; 131 True Random Generator
|
||||
DCD ICM_Handler ; 132 Integrity Check Monitor
|
||||
DCD PUKCC_Handler ; 133 PUblic-Key Cryptography Controller
|
||||
DCD QSPI_Handler ; 134 Quad SPI interface
|
||||
DCD SDHC0_Handler ; 135 SD/MMC Host Controller 0
|
||||
DCD SDHC1_Handler ; 136 SD/MMC Host Controller 1
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT MCLK_Handler [WEAK]
|
||||
EXPORT OSCCTRL_0_Handler [WEAK]
|
||||
EXPORT OSCCTRL_1_Handler [WEAK]
|
||||
EXPORT OSCCTRL_2_Handler [WEAK]
|
||||
EXPORT OSCCTRL_3_Handler [WEAK]
|
||||
EXPORT OSCCTRL_4_Handler [WEAK]
|
||||
EXPORT OSC32KCTRL_Handler [WEAK]
|
||||
EXPORT SUPC_0_Handler [WEAK]
|
||||
EXPORT SUPC_1_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT EIC_0_Handler [WEAK]
|
||||
EXPORT EIC_1_Handler [WEAK]
|
||||
EXPORT EIC_2_Handler [WEAK]
|
||||
EXPORT EIC_3_Handler [WEAK]
|
||||
EXPORT EIC_4_Handler [WEAK]
|
||||
EXPORT EIC_5_Handler [WEAK]
|
||||
EXPORT EIC_6_Handler [WEAK]
|
||||
EXPORT EIC_7_Handler [WEAK]
|
||||
EXPORT EIC_8_Handler [WEAK]
|
||||
EXPORT EIC_9_Handler [WEAK]
|
||||
EXPORT EIC_10_Handler [WEAK]
|
||||
EXPORT EIC_11_Handler [WEAK]
|
||||
EXPORT EIC_12_Handler [WEAK]
|
||||
EXPORT EIC_13_Handler [WEAK]
|
||||
EXPORT EIC_14_Handler [WEAK]
|
||||
EXPORT EIC_15_Handler [WEAK]
|
||||
EXPORT FREQM_Handler [WEAK]
|
||||
EXPORT NVMCTRL_0_Handler [WEAK]
|
||||
EXPORT NVMCTRL_1_Handler [WEAK]
|
||||
EXPORT DMAC_0_Handler [WEAK]
|
||||
EXPORT DMAC_1_Handler [WEAK]
|
||||
EXPORT DMAC_2_Handler [WEAK]
|
||||
EXPORT DMAC_3_Handler [WEAK]
|
||||
EXPORT DMAC_4_Handler [WEAK]
|
||||
EXPORT EVSYS_0_Handler [WEAK]
|
||||
EXPORT EVSYS_1_Handler [WEAK]
|
||||
EXPORT EVSYS_2_Handler [WEAK]
|
||||
EXPORT EVSYS_3_Handler [WEAK]
|
||||
EXPORT EVSYS_4_Handler [WEAK]
|
||||
EXPORT PAC_Handler [WEAK]
|
||||
EXPORT TAL_0_Handler [WEAK]
|
||||
EXPORT TAL_1_Handler [WEAK]
|
||||
EXPORT RAMECC_Handler [WEAK]
|
||||
EXPORT SERCOM0_0_Handler [WEAK]
|
||||
EXPORT SERCOM0_1_Handler [WEAK]
|
||||
EXPORT SERCOM0_2_Handler [WEAK]
|
||||
EXPORT SERCOM0_3_Handler [WEAK]
|
||||
EXPORT SERCOM1_0_Handler [WEAK]
|
||||
EXPORT SERCOM1_1_Handler [WEAK]
|
||||
EXPORT SERCOM1_2_Handler [WEAK]
|
||||
EXPORT SERCOM1_3_Handler [WEAK]
|
||||
EXPORT SERCOM2_0_Handler [WEAK]
|
||||
EXPORT SERCOM2_1_Handler [WEAK]
|
||||
EXPORT SERCOM2_2_Handler [WEAK]
|
||||
EXPORT SERCOM2_3_Handler [WEAK]
|
||||
EXPORT SERCOM3_0_Handler [WEAK]
|
||||
EXPORT SERCOM3_1_Handler [WEAK]
|
||||
EXPORT SERCOM3_2_Handler [WEAK]
|
||||
EXPORT SERCOM3_3_Handler [WEAK]
|
||||
EXPORT SERCOM4_0_Handler [WEAK]
|
||||
EXPORT SERCOM4_1_Handler [WEAK]
|
||||
EXPORT SERCOM4_2_Handler [WEAK]
|
||||
EXPORT SERCOM4_3_Handler [WEAK]
|
||||
EXPORT SERCOM5_0_Handler [WEAK]
|
||||
EXPORT SERCOM5_1_Handler [WEAK]
|
||||
EXPORT SERCOM5_2_Handler [WEAK]
|
||||
EXPORT SERCOM5_3_Handler [WEAK]
|
||||
EXPORT SERCOM6_0_Handler [WEAK]
|
||||
EXPORT SERCOM6_1_Handler [WEAK]
|
||||
EXPORT SERCOM6_2_Handler [WEAK]
|
||||
EXPORT SERCOM6_3_Handler [WEAK]
|
||||
EXPORT SERCOM7_0_Handler [WEAK]
|
||||
EXPORT SERCOM7_1_Handler [WEAK]
|
||||
EXPORT SERCOM7_2_Handler [WEAK]
|
||||
EXPORT SERCOM7_3_Handler [WEAK]
|
||||
EXPORT CAN0_Handler [WEAK]
|
||||
EXPORT CAN1_Handler [WEAK]
|
||||
EXPORT USB_0_Handler [WEAK]
|
||||
EXPORT USB_1_Handler [WEAK]
|
||||
EXPORT USB_2_Handler [WEAK]
|
||||
EXPORT USB_3_Handler [WEAK]
|
||||
EXPORT GMAC_Handler [WEAK]
|
||||
EXPORT TCC0_0_Handler [WEAK]
|
||||
EXPORT TCC0_1_Handler [WEAK]
|
||||
EXPORT TCC0_2_Handler [WEAK]
|
||||
EXPORT TCC0_3_Handler [WEAK]
|
||||
EXPORT TCC0_4_Handler [WEAK]
|
||||
EXPORT TCC0_5_Handler [WEAK]
|
||||
EXPORT TCC0_6_Handler [WEAK]
|
||||
EXPORT TCC1_0_Handler [WEAK]
|
||||
EXPORT TCC1_1_Handler [WEAK]
|
||||
EXPORT TCC1_2_Handler [WEAK]
|
||||
EXPORT TCC1_3_Handler [WEAK]
|
||||
EXPORT TCC1_4_Handler [WEAK]
|
||||
EXPORT TCC2_0_Handler [WEAK]
|
||||
EXPORT TCC2_1_Handler [WEAK]
|
||||
EXPORT TCC2_2_Handler [WEAK]
|
||||
EXPORT TCC2_3_Handler [WEAK]
|
||||
EXPORT TCC3_0_Handler [WEAK]
|
||||
EXPORT TCC3_1_Handler [WEAK]
|
||||
EXPORT TCC3_2_Handler [WEAK]
|
||||
EXPORT TCC4_0_Handler [WEAK]
|
||||
EXPORT TCC4_1_Handler [WEAK]
|
||||
EXPORT TCC4_2_Handler [WEAK]
|
||||
EXPORT TC0_Handler [WEAK]
|
||||
EXPORT TC1_Handler [WEAK]
|
||||
EXPORT TC2_Handler [WEAK]
|
||||
EXPORT TC3_Handler [WEAK]
|
||||
EXPORT TC4_Handler [WEAK]
|
||||
EXPORT TC5_Handler [WEAK]
|
||||
EXPORT TC6_Handler [WEAK]
|
||||
EXPORT TC7_Handler [WEAK]
|
||||
EXPORT PDEC_0_Handler [WEAK]
|
||||
EXPORT PDEC_1_Handler [WEAK]
|
||||
EXPORT PDEC_2_Handler [WEAK]
|
||||
EXPORT ADC0_0_Handler [WEAK]
|
||||
EXPORT ADC0_1_Handler [WEAK]
|
||||
EXPORT ADC1_0_Handler [WEAK]
|
||||
EXPORT ADC1_1_Handler [WEAK]
|
||||
EXPORT AC_Handler [WEAK]
|
||||
EXPORT DAC_0_Handler [WEAK]
|
||||
EXPORT DAC_1_Handler [WEAK]
|
||||
EXPORT DAC_2_Handler [WEAK]
|
||||
EXPORT DAC_3_Handler [WEAK]
|
||||
EXPORT DAC_4_Handler [WEAK]
|
||||
EXPORT I2S_Handler [WEAK]
|
||||
EXPORT PCC_Handler [WEAK]
|
||||
EXPORT AES_Handler [WEAK]
|
||||
EXPORT TRNG_Handler [WEAK]
|
||||
EXPORT ICM_Handler [WEAK]
|
||||
EXPORT PUKCC_Handler [WEAK]
|
||||
EXPORT QSPI_Handler [WEAK]
|
||||
EXPORT SDHC0_Handler [WEAK]
|
||||
EXPORT SDHC1_Handler [WEAK]
|
||||
|
||||
PM_Handler
|
||||
MCLK_Handler
|
||||
OSCCTRL_0_Handler
|
||||
OSCCTRL_1_Handler
|
||||
OSCCTRL_2_Handler
|
||||
OSCCTRL_3_Handler
|
||||
OSCCTRL_4_Handler
|
||||
OSC32KCTRL_Handler
|
||||
SUPC_0_Handler
|
||||
SUPC_1_Handler
|
||||
WDT_Handler
|
||||
RTC_Handler
|
||||
EIC_0_Handler
|
||||
EIC_1_Handler
|
||||
EIC_2_Handler
|
||||
EIC_3_Handler
|
||||
EIC_4_Handler
|
||||
EIC_5_Handler
|
||||
EIC_6_Handler
|
||||
EIC_7_Handler
|
||||
EIC_8_Handler
|
||||
EIC_9_Handler
|
||||
EIC_10_Handler
|
||||
EIC_11_Handler
|
||||
EIC_12_Handler
|
||||
EIC_13_Handler
|
||||
EIC_14_Handler
|
||||
EIC_15_Handler
|
||||
FREQM_Handler
|
||||
NVMCTRL_0_Handler
|
||||
NVMCTRL_1_Handler
|
||||
DMAC_0_Handler
|
||||
DMAC_1_Handler
|
||||
DMAC_2_Handler
|
||||
DMAC_3_Handler
|
||||
DMAC_4_Handler
|
||||
EVSYS_0_Handler
|
||||
EVSYS_1_Handler
|
||||
EVSYS_2_Handler
|
||||
EVSYS_3_Handler
|
||||
EVSYS_4_Handler
|
||||
PAC_Handler
|
||||
TAL_0_Handler
|
||||
TAL_1_Handler
|
||||
RAMECC_Handler
|
||||
SERCOM0_0_Handler
|
||||
SERCOM0_1_Handler
|
||||
SERCOM0_2_Handler
|
||||
SERCOM0_3_Handler
|
||||
SERCOM1_0_Handler
|
||||
SERCOM1_1_Handler
|
||||
SERCOM1_2_Handler
|
||||
SERCOM1_3_Handler
|
||||
SERCOM2_0_Handler
|
||||
SERCOM2_1_Handler
|
||||
SERCOM2_2_Handler
|
||||
SERCOM2_3_Handler
|
||||
SERCOM3_0_Handler
|
||||
SERCOM3_1_Handler
|
||||
SERCOM3_2_Handler
|
||||
SERCOM3_3_Handler
|
||||
SERCOM4_0_Handler
|
||||
SERCOM4_1_Handler
|
||||
SERCOM4_2_Handler
|
||||
SERCOM4_3_Handler
|
||||
SERCOM5_0_Handler
|
||||
SERCOM5_1_Handler
|
||||
SERCOM5_2_Handler
|
||||
SERCOM5_3_Handler
|
||||
SERCOM6_0_Handler
|
||||
SERCOM6_1_Handler
|
||||
SERCOM6_2_Handler
|
||||
SERCOM6_3_Handler
|
||||
SERCOM7_0_Handler
|
||||
SERCOM7_1_Handler
|
||||
SERCOM7_2_Handler
|
||||
SERCOM7_3_Handler
|
||||
CAN0_Handler
|
||||
CAN1_Handler
|
||||
USB_0_Handler
|
||||
USB_1_Handler
|
||||
USB_2_Handler
|
||||
USB_3_Handler
|
||||
GMAC_Handler
|
||||
TCC0_0_Handler
|
||||
TCC0_1_Handler
|
||||
TCC0_2_Handler
|
||||
TCC0_3_Handler
|
||||
TCC0_4_Handler
|
||||
TCC0_5_Handler
|
||||
TCC0_6_Handler
|
||||
TCC1_0_Handler
|
||||
TCC1_1_Handler
|
||||
TCC1_2_Handler
|
||||
TCC1_3_Handler
|
||||
TCC1_4_Handler
|
||||
TCC2_0_Handler
|
||||
TCC2_1_Handler
|
||||
TCC2_2_Handler
|
||||
TCC2_3_Handler
|
||||
TCC3_0_Handler
|
||||
TCC3_1_Handler
|
||||
TCC3_2_Handler
|
||||
TCC4_0_Handler
|
||||
TCC4_1_Handler
|
||||
TCC4_2_Handler
|
||||
TC0_Handler
|
||||
TC1_Handler
|
||||
TC2_Handler
|
||||
TC3_Handler
|
||||
TC4_Handler
|
||||
TC5_Handler
|
||||
TC6_Handler
|
||||
TC7_Handler
|
||||
PDEC_0_Handler
|
||||
PDEC_1_Handler
|
||||
PDEC_2_Handler
|
||||
ADC0_0_Handler
|
||||
ADC0_1_Handler
|
||||
ADC1_0_Handler
|
||||
ADC1_1_Handler
|
||||
AC_Handler
|
||||
DAC_0_Handler
|
||||
DAC_1_Handler
|
||||
DAC_2_Handler
|
||||
DAC_3_Handler
|
||||
DAC_4_Handler
|
||||
I2S_Handler
|
||||
PCC_Handler
|
||||
AES_Handler
|
||||
TRNG_Handler
|
||||
ICM_Handler
|
||||
PUKCC_Handler
|
||||
QSPI_Handler
|
||||
SDHC0_Handler
|
||||
SDHC1_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@ -1,70 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2016 Atmel Corporation,
|
||||
* a wholly owned subsidiary of Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same54.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (48000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if __FPU_USED
|
||||
/* Enable FPU */
|
||||
SCB->CPACR |= (0xFu << 20);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
@ -1,9 +0,0 @@
|
||||
#include <atmel_start.h>
|
||||
|
||||
/**
|
||||
* Initializes MCU, drivers and middleware in the project
|
||||
**/
|
||||
void atmel_start_init(void)
|
||||
{
|
||||
system_init();
|
||||
}
|
||||
@ -1,18 +0,0 @@
|
||||
#ifndef ATMEL_START_H_INCLUDED
|
||||
#define ATMEL_START_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "driver_init.h"
|
||||
|
||||
/**
|
||||
* Initializes MCU, drivers and middleware in the project
|
||||
**/
|
||||
void atmel_start_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@ -1,35 +0,0 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef ATMEL_START_PINS_H_INCLUDED
|
||||
#define ATMEL_START_PINS_H_INCLUDED
|
||||
|
||||
#include <hal_gpio.h>
|
||||
|
||||
// SAME54 has 14 pin functions
|
||||
|
||||
#define GPIO_PIN_FUNCTION_A 0
|
||||
#define GPIO_PIN_FUNCTION_B 1
|
||||
#define GPIO_PIN_FUNCTION_C 2
|
||||
#define GPIO_PIN_FUNCTION_D 3
|
||||
#define GPIO_PIN_FUNCTION_E 4
|
||||
#define GPIO_PIN_FUNCTION_F 5
|
||||
#define GPIO_PIN_FUNCTION_G 6
|
||||
#define GPIO_PIN_FUNCTION_H 7
|
||||
#define GPIO_PIN_FUNCTION_I 8
|
||||
#define GPIO_PIN_FUNCTION_J 9
|
||||
#define GPIO_PIN_FUNCTION_K 10
|
||||
#define GPIO_PIN_FUNCTION_L 11
|
||||
#define GPIO_PIN_FUNCTION_M 12
|
||||
#define GPIO_PIN_FUNCTION_N 13
|
||||
|
||||
#define PA04 GPIO(GPIO_PORTA, 4)
|
||||
#define PA05 GPIO(GPIO_PORTA, 5)
|
||||
#define PA16 GPIO(GPIO_PORTA, 16)
|
||||
#define PA17 GPIO(GPIO_PORTA, 17)
|
||||
|
||||
#endif // ATMEL_START_PINS_H_INCLUDED
|
||||
@ -1,54 +0,0 @@
|
||||
/* Auto-generated config file hpl_cmcc_config.h */
|
||||
#ifndef HPL_CMCC_CONFIG_H
|
||||
#define HPL_CMCC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Basic Configuration
|
||||
|
||||
// <q> Cache enable
|
||||
//<i> Defines the cache should be enabled or not.
|
||||
// <id> cmcc_enable
|
||||
#ifndef CONF_CMCC_ENABLE
|
||||
#define CONF_CMCC_ENABLE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Cache Size
|
||||
//<i> Defines the cache memory size to be configured.
|
||||
// <0x0=>1 KB
|
||||
// <0x1=>2 KB
|
||||
// <0x2=>4 KB
|
||||
// <id> cache_size
|
||||
#ifndef CONF_CMCC_CACHE_SIZE
|
||||
#define CONF_CMCC_CACHE_SIZE 0x2
|
||||
#endif
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> cmcc_advanced_configuration
|
||||
// <q> Data cache disable
|
||||
//<i> Defines the data cache should be disabled or not.
|
||||
// <id> cmcc_data_cache_disable
|
||||
#ifndef CONF_CMCC_DATA_CACHE_DISABLE
|
||||
#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
|
||||
#endif
|
||||
|
||||
// <q> Instruction cache disable
|
||||
//<i> Defines the Instruction cache should be disabled or not.
|
||||
// <id> cmcc_inst_cache_disable
|
||||
#ifndef CONF_CMCC_INST_CACHE_DISABLE
|
||||
#define CONF_CMCC_INST_CACHE_DISABLE 0x0
|
||||
#endif
|
||||
|
||||
// <q> Clock Gating disable
|
||||
//<i> Defines the clock gating should be disabled or not.
|
||||
// <id> cmcc_clock_gating_disable
|
||||
#ifndef CONF_CMCC_CLK_GATING_DISABLE
|
||||
#define CONF_CMCC_CLK_GATING_DISABLE 0x0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_CMCC_CONFIG_H
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,920 +0,0 @@
|
||||
/* Auto-generated config file hpl_gclk_config.h */
|
||||
#ifndef HPL_GCLK_CONFIG_H
|
||||
#define HPL_GCLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> Generic clock generator 0 configuration
|
||||
// <i> Indicates whether generic clock 0 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_0
|
||||
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_0_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 0 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 0
|
||||
// <id> gclk_gen_0_oscillator
|
||||
#ifndef CONF_GCLK_GEN_0_SOURCE
|
||||
#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_0_runstdby
|
||||
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_0_div_sel
|
||||
#ifndef CONF_GCLK_GEN_0_DIVSEL
|
||||
#define CONF_GCLK_GEN_0_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_0_oe
|
||||
#ifndef CONF_GCLK_GEN_0_OE
|
||||
#define CONF_GCLK_GEN_0_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_0_oov
|
||||
#ifndef CONF_GCLK_GEN_0_OOV
|
||||
#define CONF_GCLK_GEN_0_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_0_idc
|
||||
#ifndef CONF_GCLK_GEN_0_IDC
|
||||
#define CONF_GCLK_GEN_0_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_0_enable
|
||||
#ifndef CONF_GCLK_GEN_0_GENEN
|
||||
#define CONF_GCLK_GEN_0_GENEN 1
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_0_div
|
||||
#ifndef CONF_GCLK_GEN_0_DIV
|
||||
#define CONF_GCLK_GEN_0_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 1 configuration
|
||||
// <i> Indicates whether generic clock 1 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_1
|
||||
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_1_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 1 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 1
|
||||
// <id> gclk_gen_1_oscillator
|
||||
#ifndef CONF_GCLK_GEN_1_SOURCE
|
||||
#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_1_runstdby
|
||||
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_1_div_sel
|
||||
#ifndef CONF_GCLK_GEN_1_DIVSEL
|
||||
#define CONF_GCLK_GEN_1_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_1_oe
|
||||
#ifndef CONF_GCLK_GEN_1_OE
|
||||
#define CONF_GCLK_GEN_1_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_1_oov
|
||||
#ifndef CONF_GCLK_GEN_1_OOV
|
||||
#define CONF_GCLK_GEN_1_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_1_idc
|
||||
#ifndef CONF_GCLK_GEN_1_IDC
|
||||
#define CONF_GCLK_GEN_1_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_1_enable
|
||||
#ifndef CONF_GCLK_GEN_1_GENEN
|
||||
#define CONF_GCLK_GEN_1_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_1_div
|
||||
#ifndef CONF_GCLK_GEN_1_DIV
|
||||
#define CONF_GCLK_GEN_1_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 2 configuration
|
||||
// <i> Indicates whether generic clock 2 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_2
|
||||
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_2_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 2 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 2
|
||||
// <id> gclk_gen_2_oscillator
|
||||
#ifndef CONF_GCLK_GEN_2_SOURCE
|
||||
#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_2_runstdby
|
||||
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_2_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_2_div_sel
|
||||
#ifndef CONF_GCLK_GEN_2_DIVSEL
|
||||
#define CONF_GCLK_GEN_2_DIVSEL 1
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_2_oe
|
||||
#ifndef CONF_GCLK_GEN_2_OE
|
||||
#define CONF_GCLK_GEN_2_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_2_oov
|
||||
#ifndef CONF_GCLK_GEN_2_OOV
|
||||
#define CONF_GCLK_GEN_2_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_2_idc
|
||||
#ifndef CONF_GCLK_GEN_2_IDC
|
||||
#define CONF_GCLK_GEN_2_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_2_enable
|
||||
#ifndef CONF_GCLK_GEN_2_GENEN
|
||||
#define CONF_GCLK_GEN_2_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_2_div
|
||||
#ifndef CONF_GCLK_GEN_2_DIV
|
||||
#define CONF_GCLK_GEN_2_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 3 configuration
|
||||
// <i> Indicates whether generic clock 3 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_3
|
||||
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_3_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 3 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 3
|
||||
// <id> gclk_gen_3_oscillator
|
||||
#ifndef CONF_GCLK_GEN_3_SOURCE
|
||||
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_3_runstdby
|
||||
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_3_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_3_div_sel
|
||||
#ifndef CONF_GCLK_GEN_3_DIVSEL
|
||||
#define CONF_GCLK_GEN_3_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_3_oe
|
||||
#ifndef CONF_GCLK_GEN_3_OE
|
||||
#define CONF_GCLK_GEN_3_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_3_oov
|
||||
#ifndef CONF_GCLK_GEN_3_OOV
|
||||
#define CONF_GCLK_GEN_3_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_3_idc
|
||||
#ifndef CONF_GCLK_GEN_3_IDC
|
||||
#define CONF_GCLK_GEN_3_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_3_enable
|
||||
#ifndef CONF_GCLK_GEN_3_GENEN
|
||||
#define CONF_GCLK_GEN_3_GENEN 1
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_3_div
|
||||
#ifndef CONF_GCLK_GEN_3_DIV
|
||||
#define CONF_GCLK_GEN_3_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 4 configuration
|
||||
// <i> Indicates whether generic clock 4 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_4
|
||||
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_4_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 4 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 4
|
||||
// <id> gclk_gen_4_oscillator
|
||||
#ifndef CONF_GCLK_GEN_4_SOURCE
|
||||
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_4_runstdby
|
||||
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_4_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_4_div_sel
|
||||
#ifndef CONF_GCLK_GEN_4_DIVSEL
|
||||
#define CONF_GCLK_GEN_4_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_4_oe
|
||||
#ifndef CONF_GCLK_GEN_4_OE
|
||||
#define CONF_GCLK_GEN_4_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_4_oov
|
||||
#ifndef CONF_GCLK_GEN_4_OOV
|
||||
#define CONF_GCLK_GEN_4_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_4_idc
|
||||
#ifndef CONF_GCLK_GEN_4_IDC
|
||||
#define CONF_GCLK_GEN_4_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_4_enable
|
||||
#ifndef CONF_GCLK_GEN_4_GENEN
|
||||
#define CONF_GCLK_GEN_4_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_4_div
|
||||
#ifndef CONF_GCLK_GEN_4_DIV
|
||||
#define CONF_GCLK_GEN_4_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 5 configuration
|
||||
// <i> Indicates whether generic clock 5 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_5
|
||||
#ifndef CONF_GCLK_GENERATOR_5_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_5_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 5 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 5
|
||||
// <id> gclk_gen_5_oscillator
|
||||
#ifndef CONF_GCLK_GEN_5_SOURCE
|
||||
#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_5_runstdby
|
||||
#ifndef CONF_GCLK_GEN_5_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_5_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_5_div_sel
|
||||
#ifndef CONF_GCLK_GEN_5_DIVSEL
|
||||
#define CONF_GCLK_GEN_5_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_5_oe
|
||||
#ifndef CONF_GCLK_GEN_5_OE
|
||||
#define CONF_GCLK_GEN_5_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_5_oov
|
||||
#ifndef CONF_GCLK_GEN_5_OOV
|
||||
#define CONF_GCLK_GEN_5_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_5_idc
|
||||
#ifndef CONF_GCLK_GEN_5_IDC
|
||||
#define CONF_GCLK_GEN_5_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_5_enable
|
||||
#ifndef CONF_GCLK_GEN_5_GENEN
|
||||
#define CONF_GCLK_GEN_5_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 5 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_5_div
|
||||
#ifndef CONF_GCLK_GEN_5_DIV
|
||||
#define CONF_GCLK_GEN_5_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 6 configuration
|
||||
// <i> Indicates whether generic clock 6 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_6
|
||||
#ifndef CONF_GCLK_GENERATOR_6_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_6_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 6 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 6
|
||||
// <id> gclk_gen_6_oscillator
|
||||
#ifndef CONF_GCLK_GEN_6_SOURCE
|
||||
#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_6_runstdby
|
||||
#ifndef CONF_GCLK_GEN_6_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_6_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_6_div_sel
|
||||
#ifndef CONF_GCLK_GEN_6_DIVSEL
|
||||
#define CONF_GCLK_GEN_6_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_6_oe
|
||||
#ifndef CONF_GCLK_GEN_6_OE
|
||||
#define CONF_GCLK_GEN_6_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_6_oov
|
||||
#ifndef CONF_GCLK_GEN_6_OOV
|
||||
#define CONF_GCLK_GEN_6_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_6_idc
|
||||
#ifndef CONF_GCLK_GEN_6_IDC
|
||||
#define CONF_GCLK_GEN_6_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_6_enable
|
||||
#ifndef CONF_GCLK_GEN_6_GENEN
|
||||
#define CONF_GCLK_GEN_6_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 6 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_6_div
|
||||
#ifndef CONF_GCLK_GEN_6_DIV
|
||||
#define CONF_GCLK_GEN_6_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 7 configuration
|
||||
// <i> Indicates whether generic clock 7 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_7
|
||||
#ifndef CONF_GCLK_GENERATOR_7_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_7_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 7 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 7
|
||||
// <id> gclk_gen_7_oscillator
|
||||
#ifndef CONF_GCLK_GEN_7_SOURCE
|
||||
#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_7_runstdby
|
||||
#ifndef CONF_GCLK_GEN_7_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_7_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_7_div_sel
|
||||
#ifndef CONF_GCLK_GEN_7_DIVSEL
|
||||
#define CONF_GCLK_GEN_7_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_7_oe
|
||||
#ifndef CONF_GCLK_GEN_7_OE
|
||||
#define CONF_GCLK_GEN_7_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_7_oov
|
||||
#ifndef CONF_GCLK_GEN_7_OOV
|
||||
#define CONF_GCLK_GEN_7_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_7_idc
|
||||
#ifndef CONF_GCLK_GEN_7_IDC
|
||||
#define CONF_GCLK_GEN_7_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_7_enable
|
||||
#ifndef CONF_GCLK_GEN_7_GENEN
|
||||
#define CONF_GCLK_GEN_7_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 7 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_7_div
|
||||
#ifndef CONF_GCLK_GEN_7_DIV
|
||||
#define CONF_GCLK_GEN_7_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 8 configuration
|
||||
// <i> Indicates whether generic clock 8 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_8
|
||||
#ifndef CONF_GCLK_GENERATOR_8_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_8_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 8 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 8
|
||||
// <id> gclk_gen_8_oscillator
|
||||
#ifndef CONF_GCLK_GEN_8_SOURCE
|
||||
#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_8_runstdby
|
||||
#ifndef CONF_GCLK_GEN_8_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_8_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_8_div_sel
|
||||
#ifndef CONF_GCLK_GEN_8_DIVSEL
|
||||
#define CONF_GCLK_GEN_8_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_8_oe
|
||||
#ifndef CONF_GCLK_GEN_8_OE
|
||||
#define CONF_GCLK_GEN_8_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_8_oov
|
||||
#ifndef CONF_GCLK_GEN_8_OOV
|
||||
#define CONF_GCLK_GEN_8_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_8_idc
|
||||
#ifndef CONF_GCLK_GEN_8_IDC
|
||||
#define CONF_GCLK_GEN_8_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_8_enable
|
||||
#ifndef CONF_GCLK_GEN_8_GENEN
|
||||
#define CONF_GCLK_GEN_8_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 8 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_8_div
|
||||
#ifndef CONF_GCLK_GEN_8_DIV
|
||||
#define CONF_GCLK_GEN_8_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 9 configuration
|
||||
// <i> Indicates whether generic clock 9 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_9
|
||||
#ifndef CONF_GCLK_GENERATOR_9_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_9_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 9 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 9
|
||||
// <id> gclk_gen_9_oscillator
|
||||
#ifndef CONF_GCLK_GEN_9_SOURCE
|
||||
#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_9_runstdby
|
||||
#ifndef CONF_GCLK_GEN_9_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_9_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_9_div_sel
|
||||
#ifndef CONF_GCLK_GEN_9_DIVSEL
|
||||
#define CONF_GCLK_GEN_9_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_9_oe
|
||||
#ifndef CONF_GCLK_GEN_9_OE
|
||||
#define CONF_GCLK_GEN_9_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_9_oov
|
||||
#ifndef CONF_GCLK_GEN_9_OOV
|
||||
#define CONF_GCLK_GEN_9_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_9_idc
|
||||
#ifndef CONF_GCLK_GEN_9_IDC
|
||||
#define CONF_GCLK_GEN_9_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_9_enable
|
||||
#ifndef CONF_GCLK_GEN_9_GENEN
|
||||
#define CONF_GCLK_GEN_9_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 9 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_9_div
|
||||
#ifndef CONF_GCLK_GEN_9_DIV
|
||||
#define CONF_GCLK_GEN_9_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 10 configuration
|
||||
// <i> Indicates whether generic clock 10 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_10
|
||||
#ifndef CONF_GCLK_GENERATOR_10_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_10_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 10 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 10
|
||||
// <id> gclk_gen_10_oscillator
|
||||
#ifndef CONF_GCLK_GEN_10_SOURCE
|
||||
#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_10_runstdby
|
||||
#ifndef CONF_GCLK_GEN_10_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_10_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_10_div_sel
|
||||
#ifndef CONF_GCLK_GEN_10_DIVSEL
|
||||
#define CONF_GCLK_GEN_10_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_10_oe
|
||||
#ifndef CONF_GCLK_GEN_10_OE
|
||||
#define CONF_GCLK_GEN_10_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_10_oov
|
||||
#ifndef CONF_GCLK_GEN_10_OOV
|
||||
#define CONF_GCLK_GEN_10_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_10_idc
|
||||
#ifndef CONF_GCLK_GEN_10_IDC
|
||||
#define CONF_GCLK_GEN_10_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_10_enable
|
||||
#ifndef CONF_GCLK_GEN_10_GENEN
|
||||
#define CONF_GCLK_GEN_10_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 10 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_10_div
|
||||
#ifndef CONF_GCLK_GEN_10_DIV
|
||||
#define CONF_GCLK_GEN_10_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> Generic clock generator 11 configuration
|
||||
// <i> Indicates whether generic clock 11 configuration is enabled or not
|
||||
// <id> enable_gclk_gen_11
|
||||
#ifndef CONF_GCLK_GENERATOR_11_CONFIG
|
||||
#define CONF_GCLK_GENERATOR_11_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> Generic Clock Generator Control
|
||||
// <y> Generic clock generator 11 source
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
|
||||
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
|
||||
// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
|
||||
// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
|
||||
// <i> This defines the clock source for generic clock generator 11
|
||||
// <id> gclk_gen_11_oscillator
|
||||
#ifndef CONF_GCLK_GEN_11_SOURCE
|
||||
#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> gclk_arch_gen_11_runstdby
|
||||
#ifndef CONF_GCLK_GEN_11_RUNSTDBY
|
||||
#define CONF_GCLK_GEN_11_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Divide Selection
|
||||
// <i> Indicates whether Divide Selection is enabled or not
|
||||
//<id> gclk_gen_11_div_sel
|
||||
#ifndef CONF_GCLK_GEN_11_DIVSEL
|
||||
#define CONF_GCLK_GEN_11_DIVSEL 0
|
||||
#endif
|
||||
|
||||
// <q> Output Enable
|
||||
// <i> Indicates whether Output Enable is enabled or not
|
||||
// <id> gclk_arch_gen_11_oe
|
||||
#ifndef CONF_GCLK_GEN_11_OE
|
||||
#define CONF_GCLK_GEN_11_OE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Off Value
|
||||
// <i> Indicates whether Output Off Value is enabled or not
|
||||
// <id> gclk_arch_gen_11_oov
|
||||
#ifndef CONF_GCLK_GEN_11_OOV
|
||||
#define CONF_GCLK_GEN_11_OOV 0
|
||||
#endif
|
||||
|
||||
// <q> Improve Duty Cycle
|
||||
// <i> Indicates whether Improve Duty Cycle is enabled or not
|
||||
// <id> gclk_arch_gen_11_idc
|
||||
#ifndef CONF_GCLK_GEN_11_IDC
|
||||
#define CONF_GCLK_GEN_11_IDC 0
|
||||
#endif
|
||||
|
||||
// <q> Generic Clock Generator Enable
|
||||
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
||||
// <id> gclk_arch_gen_11_enable
|
||||
#ifndef CONF_GCLK_GEN_11_GENEN
|
||||
#define CONF_GCLK_GEN_11_GENEN 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
//<h> Generic Clock Generator Division
|
||||
//<o> Generic clock generator 11 division <0x0000-0xFFFF>
|
||||
// <id> gclk_gen_11_div
|
||||
#ifndef CONF_GCLK_GEN_11_DIV
|
||||
#define CONF_GCLK_GEN_11_DIV 1
|
||||
#endif
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_GCLK_CONFIG_H
|
||||
@ -1,104 +0,0 @@
|
||||
/* Auto-generated config file hpl_mclk_config.h */
|
||||
#ifndef HPL_MCLK_CONFIG_H
|
||||
#define HPL_MCLK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// <e> System Configuration
|
||||
// <i> Indicates whether configuration for system is enabled or not
|
||||
// <id> enable_cpu_clock
|
||||
#ifndef CONF_SYSTEM_CONFIG
|
||||
#define CONF_SYSTEM_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> Basic settings
|
||||
// <y> CPU Clock source
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <i> This defines the clock source for the CPU
|
||||
// <id> cpu_clock_source
|
||||
#ifndef CONF_CPU_SRC
|
||||
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#endif
|
||||
|
||||
// <y> CPU Clock Division Factor
|
||||
// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
|
||||
// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
|
||||
// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
|
||||
// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
|
||||
// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
|
||||
// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
|
||||
// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
|
||||
// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
|
||||
// <i> Prescalar for CPU clock
|
||||
// <id> cpu_div
|
||||
#ifndef CONF_MCLK_CPUDIV
|
||||
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
|
||||
#endif
|
||||
// <y> Low Power Clock Division
|
||||
// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
|
||||
// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
|
||||
// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
|
||||
// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
|
||||
// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
|
||||
// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
|
||||
// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
|
||||
// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
|
||||
// <id> mclk_arch_lpdiv
|
||||
#ifndef CONF_MCLK_LPDIV
|
||||
#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
|
||||
#endif
|
||||
|
||||
// <y> Backup Clock Division
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
|
||||
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
|
||||
// <id> mclk_arch_bupdiv
|
||||
#ifndef CONF_MCLK_BUPDIV
|
||||
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
|
||||
#endif
|
||||
// <y> High-Speed Clock Division
|
||||
// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
|
||||
// <id> mclk_arch_hsdiv
|
||||
#ifndef CONF_MCLK_HSDIV
|
||||
#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <h> NVM Settings
|
||||
// <o> NVM Wait States
|
||||
// <i> These bits select the number of wait states for a read operation.
|
||||
// <0=> 0
|
||||
// <1=> 1
|
||||
// <2=> 2
|
||||
// <3=> 3
|
||||
// <4=> 4
|
||||
// <5=> 5
|
||||
// <6=> 6
|
||||
// <7=> 7
|
||||
// <8=> 8
|
||||
// <9=> 9
|
||||
// <10=> 10
|
||||
// <11=> 11
|
||||
// <12=> 12
|
||||
// <13=> 13
|
||||
// <14=> 14
|
||||
// <15=> 15
|
||||
// <id> nvm_wait_states
|
||||
#ifndef CONF_NVM_WAIT_STATE
|
||||
#define CONF_NVM_WAIT_STATE 5
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_MCLK_CONFIG_H
|
||||
@ -1,165 +0,0 @@
|
||||
/* Auto-generated config file hpl_osc32kctrl_config.h */
|
||||
#ifndef HPL_OSC32KCTRL_CONFIG_H
|
||||
#define HPL_OSC32KCTRL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> RTC Source configuration
|
||||
// <id> enable_rtc_source
|
||||
#ifndef CONF_RTCCTRL_CONFIG
|
||||
#define CONF_RTCCTRL_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <h> RTC source control
|
||||
// <y> RTC Clock Source Selection
|
||||
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <i> This defines the clock source for RTC
|
||||
// <id> rtc_source_oscillator
|
||||
#ifndef CONF_RTCCTRL_SRC
|
||||
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
|
||||
#endif
|
||||
|
||||
// <q> Use 1 kHz output
|
||||
// <id> rtc_1khz_selection
|
||||
#ifndef CONF_RTCCTRL_1KHZ
|
||||
|
||||
#define CONF_RTCCTRL_1KHZ 0
|
||||
|
||||
#endif
|
||||
|
||||
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
|
||||
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
|
||||
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
|
||||
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
|
||||
#else
|
||||
#error unexpected CONF_RTCCTRL_SRC
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> 32kHz External Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for External 32K Osc is enabled or not
|
||||
// <id> enable_xosc32k
|
||||
#ifndef CONF_XOSC32K_CONFIG
|
||||
#define CONF_XOSC32K_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> 32kHz External Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
|
||||
// <id> xosc32k_arch_enable
|
||||
#ifndef CONF_XOSC32K_ENABLE
|
||||
#define CONF_XOSC32K_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>62592us
|
||||
// <0x1=>125092us
|
||||
// <0x2=>500092us
|
||||
// <0x3=>1000092us
|
||||
// <0x4=>2000092us
|
||||
// <0x5=>4000092us
|
||||
// <0x6=>8000092us
|
||||
// <id> xosc32k_arch_startup
|
||||
#ifndef CONF_XOSC32K_STARTUP
|
||||
#define CONF_XOSC32K_STARTUP 0x3
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc32k_arch_ondemand
|
||||
#ifndef CONF_XOSC32K_ONDEMAND
|
||||
#define CONF_XOSC32K_ONDEMAND 1
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc32k_arch_runstdby
|
||||
#ifndef CONF_XOSC32K_RUNSTDBY
|
||||
#define CONF_XOSC32K_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> 1kHz Output Enable
|
||||
// <i> Indicates whether 1kHz Output is enabled or not
|
||||
// <id> xosc32k_arch_en1k
|
||||
#ifndef CONF_XOSC32K_EN1K
|
||||
#define CONF_XOSC32K_EN1K 0
|
||||
#endif
|
||||
|
||||
// <q> 32kHz Output Enable
|
||||
// <i> Indicates whether 32kHz Output is enabled or not
|
||||
// <id> xosc32k_arch_en32k
|
||||
#ifndef CONF_XOSC32K_EN32K
|
||||
#define CONF_XOSC32K_EN32K 1
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc32k_arch_swben
|
||||
#ifndef CONF_XOSC32K_SWBEN
|
||||
#define CONF_XOSC32K_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc32k_arch_cfden
|
||||
#ifndef CONF_XOSC32K_CFDEN
|
||||
#define CONF_XOSC32K_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector Event Out
|
||||
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
|
||||
// <id> xosc32k_arch_cfdeo
|
||||
#ifndef CONF_XOSC32K_CFDEO
|
||||
#define CONF_XOSC32K_CFDEO 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN32/XOUT32 Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc32k_arch_xtalen
|
||||
#ifndef CONF_XOSC32K_XTALEN
|
||||
#define CONF_XOSC32K_XTALEN 1
|
||||
#endif
|
||||
|
||||
// <o> Control Gain Mode
|
||||
// <0x0=>Low Power mode
|
||||
// <0x1=>Standard mode
|
||||
// <0x2=>High Speed mode
|
||||
// <id> xosc32k_arch_cgm
|
||||
#ifndef CONF_XOSC32K_CGM
|
||||
#define CONF_XOSC32K_CGM 0x1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for OSCULP32K is enabled or not
|
||||
// <id> enable_osculp32k
|
||||
#ifndef CONF_OSCULP32K_CONFIG
|
||||
#define CONF_OSCULP32K_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <h> 32kHz Ultra Low Power Internal Oscillator Control
|
||||
|
||||
// <q> Oscillator Calibration Control
|
||||
// <i> Indicates whether Oscillator Calibration is enabled or not
|
||||
// <id> osculp32k_calib_enable
|
||||
#ifndef CONF_OSCULP32K_CALIB_ENABLE
|
||||
#define CONF_OSCULP32K_CALIB_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Oscillator Calibration <0x0-0x3F>
|
||||
// <id> osculp32k_calib
|
||||
#ifndef CONF_OSCULP32K_CALIB
|
||||
#define CONF_OSCULP32K_CALIB 0x0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_OSC32KCTRL_CONFIG_H
|
||||
@ -1,640 +0,0 @@
|
||||
/* Auto-generated config file hpl_oscctrl_config.h */
|
||||
#ifndef HPL_OSCCTRL_CONFIG_H
|
||||
#define HPL_OSCCTRL_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for XOSC0 is enabled or not
|
||||
// <id> enable_xosc0
|
||||
#ifndef CONF_XOSC0_CONFIG
|
||||
#define CONF_XOSC0_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <o> Frequency <8000000-48000000>
|
||||
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||
// <id> xosc0_frequency
|
||||
#ifndef CONF_XOSC_FREQUENCY
|
||||
#define CONF_XOSC0_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <h> External Multipurpose Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
|
||||
// <id> xosc0_arch_enable
|
||||
#ifndef CONF_XOSC0_ENABLE
|
||||
#define CONF_XOSC0_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>31us
|
||||
// <0x1=>61us
|
||||
// <0x2=>122us
|
||||
// <0x3=>244us
|
||||
// <0x4=>488us
|
||||
// <0x5=>977us
|
||||
// <0x6=>1953us
|
||||
// <0x7=>3906us
|
||||
// <0x8=>7813us
|
||||
// <0x9=>15625us
|
||||
// <0xA=>31250us
|
||||
// <0xB=>62500us
|
||||
// <0xC=>125000us
|
||||
// <0xD=>250000us
|
||||
// <0xE=>500000us
|
||||
// <0xF=>1000000us
|
||||
// <id> xosc0_arch_startup
|
||||
#ifndef CONF_XOSC0_STARTUP
|
||||
#define CONF_XOSC0_STARTUP 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc0_arch_swben
|
||||
#ifndef CONF_XOSC0_SWBEN
|
||||
#define CONF_XOSC0_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc0_arch_cfden
|
||||
#ifndef CONF_XOSC0_CFDEN
|
||||
#define CONF_XOSC0_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Automatic Loop Control Enable
|
||||
// <i> Indicates whether Automatic Loop Control is enabled or not
|
||||
// <id> xosc0_arch_enalc
|
||||
#ifndef CONF_XOSC0_ENALC
|
||||
#define CONF_XOSC0_ENALC 0
|
||||
#endif
|
||||
|
||||
// <q> Low Buffer Gain Enable
|
||||
// <i> Indicates whether Low Buffer Gain is enabled or not
|
||||
// <id> xosc0_arch_lowbufgain
|
||||
#ifndef CONF_XOSC0_LOWBUFGAIN
|
||||
#define CONF_XOSC0_LOWBUFGAIN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc0_arch_ondemand
|
||||
#ifndef CONF_XOSC0_ONDEMAND
|
||||
#define CONF_XOSC0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc0_arch_runstdby
|
||||
#ifndef CONF_XOSC0_RUNSTDBY
|
||||
#define CONF_XOSC0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN/XOUT Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc0_arch_xtalen
|
||||
#ifndef CONF_XOSC0_XTALEN
|
||||
#define CONF_XOSC0_XTALEN 0
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
#if CONF_XOSC0_FREQUENCY >= 32000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x0
|
||||
#define CONF_XOSC0_IMULT 0x7
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 24000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x1
|
||||
#define CONF_XOSC0_IMULT 0x6
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 16000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x2
|
||||
#define CONF_XOSC0_IMULT 0x5
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#elif CONF_XOSC0_FREQUENCY >= 8000000
|
||||
#define CONF_XOSC0_CFDPRESC 0x3
|
||||
#define CONF_XOSC0_IMULT 0x4
|
||||
#define CONF_XOSC0_IPTAT 0x3
|
||||
#endif
|
||||
|
||||
// <e> External Multipurpose Crystal Oscillator Configuration
|
||||
// <i> Indicates whether configuration for XOSC1 is enabled or not
|
||||
// <id> enable_xosc1
|
||||
#ifndef CONF_XOSC1_CONFIG
|
||||
#define CONF_XOSC1_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <o> Frequency <8000000-48000000>
|
||||
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
|
||||
// <id> xosc1_frequency
|
||||
#ifndef CONF_XOSC_FREQUENCY
|
||||
#define CONF_XOSC1_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <h> External Multipurpose Crystal Oscillator Control
|
||||
// <q> Oscillator enable
|
||||
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
|
||||
// <id> xosc1_arch_enable
|
||||
#ifndef CONF_XOSC1_ENABLE
|
||||
#define CONF_XOSC1_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Start-Up Time
|
||||
// <0x0=>31us
|
||||
// <0x1=>61us
|
||||
// <0x2=>122us
|
||||
// <0x3=>244us
|
||||
// <0x4=>488us
|
||||
// <0x5=>977us
|
||||
// <0x6=>1953us
|
||||
// <0x7=>3906us
|
||||
// <0x8=>7813us
|
||||
// <0x9=>15625us
|
||||
// <0xA=>31250us
|
||||
// <0xB=>62500us
|
||||
// <0xC=>125000us
|
||||
// <0xD=>250000us
|
||||
// <0xE=>500000us
|
||||
// <0xF=>1000000us
|
||||
// <id> xosc1_arch_startup
|
||||
#ifndef CONF_XOSC1_STARTUP
|
||||
#define CONF_XOSC1_STARTUP 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Switch Back
|
||||
// <i> Indicates whether Clock Switch Back is enabled or not
|
||||
// <id> xosc1_arch_swben
|
||||
#ifndef CONF_XOSC1_SWBEN
|
||||
#define CONF_XOSC1_SWBEN 0
|
||||
#endif
|
||||
|
||||
// <q> Clock Failure Detector
|
||||
// <i> Indicates whether Clock Failure Detector is enabled or not
|
||||
// <id> xosc1_arch_cfden
|
||||
#ifndef CONF_XOSC1_CFDEN
|
||||
#define CONF_XOSC1_CFDEN 0
|
||||
#endif
|
||||
|
||||
// <q> Automatic Loop Control Enable
|
||||
// <i> Indicates whether Automatic Loop Control is enabled or not
|
||||
// <id> xosc1_arch_enalc
|
||||
#ifndef CONF_XOSC1_ENALC
|
||||
#define CONF_XOSC1_ENALC 0
|
||||
#endif
|
||||
|
||||
// <q> Low Buffer Gain Enable
|
||||
// <i> Indicates whether Low Buffer Gain is enabled or not
|
||||
// <id> xosc1_arch_lowbufgain
|
||||
#ifndef CONF_XOSC1_LOWBUFGAIN
|
||||
#define CONF_XOSC1_LOWBUFGAIN 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> xosc1_arch_ondemand
|
||||
#ifndef CONF_XOSC1_ONDEMAND
|
||||
#define CONF_XOSC1_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> xosc1_arch_runstdby
|
||||
#ifndef CONF_XOSC1_RUNSTDBY
|
||||
#define CONF_XOSC1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Crystal connected to XIN/XOUT Enable
|
||||
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
|
||||
// <id> xosc1_arch_xtalen
|
||||
#ifndef CONF_XOSC1_XTALEN
|
||||
#define CONF_XOSC1_XTALEN 1
|
||||
#endif
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
#if CONF_XOSC1_FREQUENCY >= 32000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x0
|
||||
#define CONF_XOSC1_IMULT 0x7
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 24000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x1
|
||||
#define CONF_XOSC1_IMULT 0x6
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 16000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x2
|
||||
#define CONF_XOSC1_IMULT 0x5
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#elif CONF_XOSC1_FREQUENCY >= 8000000
|
||||
#define CONF_XOSC1_CFDPRESC 0x3
|
||||
#define CONF_XOSC1_IMULT 0x4
|
||||
#define CONF_XOSC1_IPTAT 0x3
|
||||
#endif
|
||||
|
||||
// <e> DFLL Configuration
|
||||
// <i> Indicates whether configuration for DFLL is enabled or not
|
||||
// <id> enable_dfll
|
||||
#ifndef CONF_DFLL_CONFIG
|
||||
#define CONF_DFLL_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source
|
||||
// <id> dfll_ref_clock
|
||||
#ifndef CONF_DFLL_GCLK
|
||||
#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
|
||||
#endif
|
||||
|
||||
// <h> Digital Frequency Locked Loop Control
|
||||
// <q> DFLL Enable
|
||||
// <i> Indicates whether DFLL is enabled or not
|
||||
// <id> dfll_arch_enable
|
||||
#ifndef CONF_DFLL_ENABLE
|
||||
#define CONF_DFLL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> dfll_arch_ondemand
|
||||
#ifndef CONF_DFLL_ONDEMAND
|
||||
#define CONF_DFLL_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> dfll_arch_runstdby
|
||||
#ifndef CONF_DFLL_RUNSTDBY
|
||||
#define CONF_DFLL_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> USB Clock Recovery Mode
|
||||
// <i> Indicates whether USB Clock Recovery Mode is enabled or not
|
||||
// <id> dfll_arch_usbcrm
|
||||
#ifndef CONF_DFLL_USBCRM
|
||||
#define CONF_DFLL_USBCRM 0
|
||||
#endif
|
||||
|
||||
// <q> Wait Lock
|
||||
// <i> Indicates whether Wait Lock is enabled or not
|
||||
// <id> dfll_arch_waitlock
|
||||
#ifndef CONF_DFLL_WAITLOCK
|
||||
#define CONF_DFLL_WAITLOCK 1
|
||||
#endif
|
||||
|
||||
// <q> Bypass Coarse Lock
|
||||
// <i> Indicates whether Bypass Coarse Lock is enabled or not
|
||||
// <id> dfll_arch_bplckc
|
||||
#ifndef CONF_DFLL_BPLCKC
|
||||
#define CONF_DFLL_BPLCKC 0
|
||||
#endif
|
||||
|
||||
// <q> Quick Lock Disable
|
||||
// <i> Indicates whether Quick Lock Disable is enabled or not
|
||||
// <id> dfll_arch_qldis
|
||||
#ifndef CONF_DFLL_QLDIS
|
||||
#define CONF_DFLL_QLDIS 0
|
||||
#endif
|
||||
|
||||
// <q> Chill Cycle Disable
|
||||
// <i> Indicates whether Chill Cycle Disable is enabled or not
|
||||
// <id> dfll_arch_ccdis
|
||||
#ifndef CONF_DFLL_CCDIS
|
||||
#define CONF_DFLL_CCDIS 0
|
||||
#endif
|
||||
|
||||
// <q> Lose Lock After Wake
|
||||
// <i> Indicates whether Lose Lock After Wake is enabled or not
|
||||
// <id> dfll_arch_llaw
|
||||
#ifndef CONF_DFLL_LLAW
|
||||
#define CONF_DFLL_LLAW 0
|
||||
#endif
|
||||
|
||||
// <q> Stable DFLL Frequency
|
||||
// <i> Indicates whether Stable DFLL Frequency is enabled or not
|
||||
// <id> dfll_arch_stable
|
||||
#ifndef CONF_DFLL_STABLE
|
||||
#define CONF_DFLL_STABLE 0
|
||||
#endif
|
||||
|
||||
// <o> Operating Mode Selection
|
||||
// <0=>Open Loop Mode
|
||||
// <1=>Closed Loop Mode
|
||||
// <id> dfll_mode
|
||||
#ifndef CONF_DFLL_MODE
|
||||
#define CONF_DFLL_MODE 0x0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Maximum Step <0x0-0x1F>
|
||||
// <id> dfll_arch_cstep
|
||||
#ifndef CONF_DFLL_CSTEP
|
||||
#define CONF_DFLL_CSTEP 0x1
|
||||
#endif
|
||||
|
||||
// <o> Fine Maximum Step <0x0-0xFF>
|
||||
// <id> dfll_arch_fstep
|
||||
#ifndef CONF_DFLL_FSTEP
|
||||
#define CONF_DFLL_FSTEP 0x1
|
||||
#endif
|
||||
|
||||
// <o> DFLL Multiply Factor <0x0-0xFFFF>
|
||||
// <id> dfll_mul
|
||||
#ifndef CONF_DFLL_MUL
|
||||
#define CONF_DFLL_MUL 0x0
|
||||
#endif
|
||||
|
||||
// <e> DFLL Calibration Overwrite
|
||||
// <i> Indicates whether Overwrite Calibration value of DFLL
|
||||
// <id> dfll_arch_calibration
|
||||
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
|
||||
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
|
||||
#endif
|
||||
|
||||
// <o> Coarse Value <0x0-0x3F>
|
||||
// <id> dfll_arch_coarse
|
||||
#ifndef CONF_DFLL_COARSE
|
||||
#define CONF_DFLL_COARSE (0x1f / 4)
|
||||
#endif
|
||||
|
||||
// <o> Fine Value <0x0-0xFF>
|
||||
// <id> dfll_arch_fine
|
||||
#ifndef CONF_DFLL_FINE
|
||||
#define CONF_DFLL_FINE (0x80)
|
||||
#endif
|
||||
|
||||
//</e>
|
||||
|
||||
//</h>
|
||||
|
||||
//</e>
|
||||
|
||||
// <e> FDPLL0 Configuration
|
||||
// <i> Indicates whether configuration for FDPLL0 is enabled or not
|
||||
// <id> enable_fdpll0
|
||||
#ifndef CONF_FDPLL0_CONFIG
|
||||
#define CONF_FDPLL0_CONFIG 1
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source.
|
||||
// <id> fdpll0_ref_clock
|
||||
#ifndef CONF_FDPLL0_GCLK
|
||||
#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <h> Digital Phase Locked Loop Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
|
||||
// <id> fdpll0_arch_enable
|
||||
#ifndef CONF_FDPLL0_ENABLE
|
||||
#define CONF_FDPLL0_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> fdpll0_arch_ondemand
|
||||
#ifndef CONF_FDPLL0_ONDEMAND
|
||||
#define CONF_FDPLL0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> fdpll0_arch_runstdby
|
||||
#ifndef CONF_FDPLL0_RUNSTDBY
|
||||
#define CONF_FDPLL0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
|
||||
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll0_ldrfrac
|
||||
#ifndef CONF_FDPLL0_LDRFRAC
|
||||
#define CONF_FDPLL0_LDRFRAC 0x1
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
|
||||
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll0_ldr
|
||||
#ifndef CONF_FDPLL0_LDR
|
||||
#define CONF_FDPLL0_LDR 0xe4d
|
||||
#endif
|
||||
|
||||
// <o> Clock Divider <0x0-0x7FF>
|
||||
// <i> This Clock divider is only for XOSC clock input to DPLL
|
||||
// <id> fdpll0_clock_div
|
||||
#ifndef CONF_FDPLL0_DIV
|
||||
#define CONF_FDPLL0_DIV 0x0
|
||||
#endif
|
||||
|
||||
// <q> DCO Filter Enable
|
||||
// <i> Indicates whether DCO Filter Enable is enabled or not
|
||||
// <id> fdpll0_arch_dcoen
|
||||
#ifndef CONF_FDPLL0_DCOEN
|
||||
#define CONF_FDPLL0_DCOEN 0
|
||||
#endif
|
||||
|
||||
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
|
||||
// <id> fdpll0_clock_dcofilter
|
||||
#ifndef CONF_FDPLL0_DCOFILTER
|
||||
#define CONF_FDPLL0_DCOFILTER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Lock Bypass
|
||||
// <i> Indicates whether Lock Bypass is enabled or not
|
||||
// <id> fdpll0_arch_lbypass
|
||||
#ifndef CONF_FDPLL0_LBYPASS
|
||||
#define CONF_FDPLL0_LBYPASS 1
|
||||
#endif
|
||||
|
||||
// <o> Lock Time
|
||||
// <0x0=>No time-out, automatic lock
|
||||
// <0x4=>The Time-out if no lock within 800 us
|
||||
// <0x5=>The Time-out if no lock within 900 us
|
||||
// <0x6=>The Time-out if no lock within 1 ms
|
||||
// <0x7=>The Time-out if no lock within 11 ms
|
||||
// <id> fdpll0_arch_ltime
|
||||
#ifndef CONF_FDPLL0_LTIME
|
||||
#define CONF_FDPLL0_LTIME 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0x0=>GCLK clock reference
|
||||
// <0x1=>XOSC32K clock reference
|
||||
// <0x2=>XOSC0 clock reference
|
||||
// <0x3=>XOSC1 clock reference
|
||||
// <id> fdpll0_arch_refclk
|
||||
#ifndef CONF_FDPLL0_REFCLK
|
||||
#define CONF_FDPLL0_REFCLK 0x1
|
||||
#endif
|
||||
|
||||
// <q> Wake Up Fast
|
||||
// <i> Indicates whether Wake Up Fast is enabled or not
|
||||
// <id> fdpll0_arch_wuf
|
||||
#ifndef CONF_FDPLL0_WUF
|
||||
#define CONF_FDPLL0_WUF 0
|
||||
#endif
|
||||
|
||||
// <o> Proportional Integral Filter Selection <0x0-0xF>
|
||||
// <id> fdpll0_arch_filter
|
||||
#ifndef CONF_FDPLL0_FILTER
|
||||
#define CONF_FDPLL0_FILTER 0x0
|
||||
#endif
|
||||
|
||||
//</h>
|
||||
//</e>
|
||||
// <e> FDPLL1 Configuration
|
||||
// <i> Indicates whether configuration for FDPLL1 is enabled or not
|
||||
// <id> enable_fdpll1
|
||||
#ifndef CONF_FDPLL1_CONFIG
|
||||
#define CONF_FDPLL1_CONFIG 0
|
||||
#endif
|
||||
|
||||
// <y> Reference Clock Source
|
||||
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
||||
// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
|
||||
// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
// <i> Select the clock source.
|
||||
// <id> fdpll1_ref_clock
|
||||
#ifndef CONF_FDPLL1_GCLK
|
||||
#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K
|
||||
#endif
|
||||
|
||||
// <h> Digital Phase Locked Loop Control
|
||||
// <q> Enable
|
||||
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
|
||||
// <id> fdpll1_arch_enable
|
||||
#ifndef CONF_FDPLL1_ENABLE
|
||||
#define CONF_FDPLL1_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> On Demand Control
|
||||
// <i> Indicates whether On Demand Control is enabled or not
|
||||
// <id> fdpll1_arch_ondemand
|
||||
#ifndef CONF_FDPLL1_ONDEMAND
|
||||
#define CONF_FDPLL1_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// <q> Run in Standby
|
||||
// <i> Indicates whether Run in Standby is enabled or not
|
||||
// <id> fdpll1_arch_runstdby
|
||||
#ifndef CONF_FDPLL1_RUNSTDBY
|
||||
#define CONF_FDPLL1_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
|
||||
// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll1_ldrfrac
|
||||
#ifndef CONF_FDPLL1_LDRFRAC
|
||||
#define CONF_FDPLL1_LDRFRAC 0xd
|
||||
#endif
|
||||
|
||||
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
|
||||
// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
|
||||
// <id> fdpll1_ldr
|
||||
#ifndef CONF_FDPLL1_LDR
|
||||
#define CONF_FDPLL1_LDR 0x5b7
|
||||
#endif
|
||||
|
||||
// <o> Clock Divider <0x0-0x7FF>
|
||||
// <i> This Clock divider is only for XOSC clock input to DPLL
|
||||
// <id> fdpll1_clock_div
|
||||
#ifndef CONF_FDPLL1_DIV
|
||||
#define CONF_FDPLL1_DIV 0x0
|
||||
#endif
|
||||
|
||||
// <q> DCO Filter Enable
|
||||
// <i> Indicates whether DCO Filter Enable is enabled or not
|
||||
// <id> fdpll1_arch_dcoen
|
||||
#ifndef CONF_FDPLL1_DCOEN
|
||||
#define CONF_FDPLL1_DCOEN 0
|
||||
#endif
|
||||
|
||||
// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
|
||||
// <id> fdpll1_clock_dcofilter
|
||||
#ifndef CONF_FDPLL1_DCOFILTER
|
||||
#define CONF_FDPLL1_DCOFILTER 0x0
|
||||
#endif
|
||||
|
||||
// <q> Lock Bypass
|
||||
// <i> Indicates whether Lock Bypass is enabled or not
|
||||
// <id> fdpll1_arch_lbypass
|
||||
#ifndef CONF_FDPLL1_LBYPASS
|
||||
#define CONF_FDPLL1_LBYPASS 0
|
||||
#endif
|
||||
|
||||
// <o> Lock Time
|
||||
// <0x0=>No time-out, automatic lock
|
||||
// <0x4=>The Time-out if no lock within 800 us
|
||||
// <0x5=>The Time-out if no lock within 900 us
|
||||
// <0x6=>The Time-out if no lock within 1 ms
|
||||
// <0x7=>The Time-out if no lock within 11 ms
|
||||
// <id> fdpll1_arch_ltime
|
||||
#ifndef CONF_FDPLL1_LTIME
|
||||
#define CONF_FDPLL1_LTIME 0x0
|
||||
#endif
|
||||
|
||||
// <o> Reference Clock Selection
|
||||
// <0x0=>GCLK clock reference
|
||||
// <0x1=>XOSC32K clock reference
|
||||
// <0x2=>XOSC0 clock reference
|
||||
// <0x3=>XOSC1 clock reference
|
||||
// <id> fdpll1_arch_refclk
|
||||
#ifndef CONF_FDPLL1_REFCLK
|
||||
#define CONF_FDPLL1_REFCLK 0x1
|
||||
#endif
|
||||
|
||||
// <q> Wake Up Fast
|
||||
// <i> Indicates whether Wake Up Fast is enabled or not
|
||||
// <id> fdpll1_arch_wuf
|
||||
#ifndef CONF_FDPLL1_WUF
|
||||
#define CONF_FDPLL1_WUF 0
|
||||
#endif
|
||||
|
||||
// <o> Proportional Integral Filter Selection <0x0-0xF>
|
||||
// <id> fdpll1_arch_filter
|
||||
#ifndef CONF_FDPLL1_FILTER
|
||||
#define CONF_FDPLL1_FILTER 0x0
|
||||
#endif
|
||||
|
||||
//</h>
|
||||
//</e>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_OSCCTRL_CONFIG_H
|
||||
@ -1,522 +0,0 @@
|
||||
/* Auto-generated config file hpl_port_config.h */
|
||||
#ifndef HPL_PORT_CONFIG_H
|
||||
#define HPL_PORT_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <e> PORT Input Event 0 configuration
|
||||
// <id> enable_port_input_event_0
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_0
|
||||
#define CONF_PORT_EVCTRL_PORT_0 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 0 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
|
||||
// <id> porta_input_event_enable_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_0
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_0
|
||||
#define CONF_PORTA_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 0
|
||||
// <id> porta_event_action_0
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_0
|
||||
#define CONF_PORTA_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
|
||||
// <id> portb_input_event_enable_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_0
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_0
|
||||
#define CONF_PORTB_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 0
|
||||
// <id> portb_event_action_0
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_0
|
||||
#define CONF_PORTB_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled
|
||||
// <id> portc_input_event_enable_0
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_0
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_0
|
||||
#define CONF_PORTC_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 0
|
||||
// <id> portc_event_action_0
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_0
|
||||
#define CONF_PORTC_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 0 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 0 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled
|
||||
// <id> portd_input_event_enable_0
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_0
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 0 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_0
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_0
|
||||
#define CONF_PORTD_EVCTRL_PID_0 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 0 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 0
|
||||
// <id> portd_event_action_0
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_0
|
||||
#define CONF_PORTD_EVCTRL_EVACT_0 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 1 configuration
|
||||
// <id> enable_port_input_event_1
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_1
|
||||
#define CONF_PORT_EVCTRL_PORT_1 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 1 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
|
||||
// <id> porta_input_event_enable_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_1
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_1
|
||||
#define CONF_PORTA_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 1
|
||||
// <id> porta_event_action_1
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_1
|
||||
#define CONF_PORTA_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
|
||||
// <id> portb_input_event_enable_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_1
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_1
|
||||
#define CONF_PORTB_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 1
|
||||
// <id> portb_event_action_1
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_1
|
||||
#define CONF_PORTB_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled
|
||||
// <id> portc_input_event_enable_1
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_1
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_1
|
||||
#define CONF_PORTC_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 1
|
||||
// <id> portc_event_action_1
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_1
|
||||
#define CONF_PORTC_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 1 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 1 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled
|
||||
// <id> portd_input_event_enable_1
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_1
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 1 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_1
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_1
|
||||
#define CONF_PORTD_EVCTRL_PID_1 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 1 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 1
|
||||
// <id> portd_event_action_1
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_1
|
||||
#define CONF_PORTD_EVCTRL_EVACT_1 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 2 configuration
|
||||
// <id> enable_port_input_event_2
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_2
|
||||
#define CONF_PORT_EVCTRL_PORT_2 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 2 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
|
||||
// <id> porta_input_event_enable_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_2
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_2
|
||||
#define CONF_PORTA_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 2
|
||||
// <id> porta_event_action_2
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_2
|
||||
#define CONF_PORTA_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
|
||||
// <id> portb_input_event_enable_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_2
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_2
|
||||
#define CONF_PORTB_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 2
|
||||
// <id> portb_event_action_2
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_2
|
||||
#define CONF_PORTB_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled
|
||||
// <id> portc_input_event_enable_2
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_2
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_2
|
||||
#define CONF_PORTC_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 2
|
||||
// <id> portc_event_action_2
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_2
|
||||
#define CONF_PORTC_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 2 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 2 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled
|
||||
// <id> portd_input_event_enable_2
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_2
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 2 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_2
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_2
|
||||
#define CONF_PORTD_EVCTRL_PID_2 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 2 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 2
|
||||
// <id> portd_event_action_2
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_2
|
||||
#define CONF_PORTD_EVCTRL_EVACT_2 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> PORT Input Event 3 configuration
|
||||
// <id> enable_port_input_event_3
|
||||
#ifndef CONF_PORT_EVCTRL_PORT_3
|
||||
#define CONF_PORT_EVCTRL_PORT_3 0
|
||||
#endif
|
||||
|
||||
// <h> PORT Input Event 3 configuration on PORT A
|
||||
|
||||
// <q> PORTA Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
|
||||
// <id> porta_input_event_enable_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port A on which the event action will be performed
|
||||
// <id> porta_event_pin_identifier_3
|
||||
#ifndef CONF_PORTA_EVCTRL_PID_3
|
||||
#define CONF_PORTA_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTA Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT A will perform on event input 3
|
||||
// <id> porta_event_action_3
|
||||
#ifndef CONF_PORTA_EVCTRL_EVACT_3
|
||||
#define CONF_PORTA_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT B
|
||||
|
||||
// <q> PORTB Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
|
||||
// <id> portb_input_event_enable_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port B on which the event action will be performed
|
||||
// <id> portb_event_pin_identifier_3
|
||||
#ifndef CONF_PORTB_EVCTRL_PID_3
|
||||
#define CONF_PORTB_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTB Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT B will perform on event input 3
|
||||
// <id> portb_event_action_3
|
||||
#ifndef CONF_PORTB_EVCTRL_EVACT_3
|
||||
#define CONF_PORTB_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT C
|
||||
|
||||
// <q> PORTC Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled
|
||||
// <id> portc_input_event_enable_3
|
||||
#ifndef CONF_PORTC_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTC_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port C on which the event action will be performed
|
||||
// <id> portc_event_pin_identifier_3
|
||||
#ifndef CONF_PORTC_EVCTRL_PID_3
|
||||
#define CONF_PORTC_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTC Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT C will perform on event input 3
|
||||
// <id> portc_event_action_3
|
||||
#ifndef CONF_PORTC_EVCTRL_EVACT_3
|
||||
#define CONF_PORTC_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// <h> PORT Input Event 3 configuration on PORT D
|
||||
|
||||
// <q> PORTD Input Event 3 Enable
|
||||
// <i> The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled
|
||||
// <id> portd_input_event_enable_3
|
||||
#ifndef CONF_PORTD_EVCTRL_PORTEI_3
|
||||
#define CONF_PORTD_EVCTRL_PORTEI_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 3 Pin Identifier <0x00-0x1F>
|
||||
// <i> These bits define the I/O pin from port D on which the event action will be performed
|
||||
// <id> portd_event_pin_identifier_3
|
||||
#ifndef CONF_PORTD_EVCTRL_PID_3
|
||||
#define CONF_PORTD_EVCTRL_PID_3 0x0
|
||||
#endif
|
||||
|
||||
// <o> PORTD Event 3 Action
|
||||
// <0=> Output register of pin will be set to level of event
|
||||
// <1=> Set output register of pin on event
|
||||
// <2=> Clear output register of pin on event
|
||||
// <3=> Toggle output register of pin on event
|
||||
// <i> These bits define the event action the PORT D will perform on event input 3
|
||||
// <id> portd_event_action_3
|
||||
#ifndef CONF_PORTD_EVCTRL_EVACT_3
|
||||
#define CONF_PORTD_EVCTRL_EVACT_3 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
#define CONF_PORTA_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
|
||||
#define CONF_PORTB_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
|
||||
#define CONF_PORTC_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3))
|
||||
#define CONF_PORTD_EVCTRL \
|
||||
(0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
|
||||
| PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \
|
||||
| CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \
|
||||
| PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
|
||||
| PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \
|
||||
| CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3))
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_PORT_CONFIG_H
|
||||
@ -1,84 +0,0 @@
|
||||
/* Auto-generated config file hpl_qspi_config.h */
|
||||
#ifndef HPL_QSPI_CONFIG_H
|
||||
#define HPL_QSPI_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#include <peripheral_clk_config.h>
|
||||
|
||||
// <h> Basic settings
|
||||
|
||||
#ifndef CONF_CONF_QSPI_ENABLE
|
||||
#define CONF_CONF_QSPI_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o> Baud rate <1-150000000>
|
||||
// <i> The SPI data transfer rate. Note: (fqspi_clock / baudrate) < 255
|
||||
// <id> qspi_baud_rate
|
||||
#ifndef CONF_QSPI_BAUD
|
||||
#define CONF_QSPI_BAUD 375000
|
||||
#endif
|
||||
|
||||
// <o> Clock Polarity
|
||||
// <0x0=>The inactive state value of SPCK is logic level zero.
|
||||
// <0x1=>The inactive state value of SPCK is logic level one.
|
||||
// <i> Determines the inactive state value of the serial clock (SPCK).
|
||||
// <id> qspi_cpol
|
||||
#ifndef CONF_QSPI_CPOL
|
||||
#define CONF_QSPI_CPOL 0x0
|
||||
#endif
|
||||
|
||||
// <o> Clock Phase
|
||||
// <0x0=>Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
|
||||
// <0x1=>Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
|
||||
// <i> Determines which edge of SPCK causes data to change and which edge causes data to be captured.
|
||||
// <id> qspi_cpha
|
||||
#ifndef CONF_QSPI_CPHA
|
||||
#define CONF_QSPI_CPHA 0x0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <e> Advanced Configuration
|
||||
// <id> qspi_advanced
|
||||
#ifndef CONF_QSPI_ADVANCED
|
||||
#define CONF_QSPI_ADVANCED 0
|
||||
#endif
|
||||
|
||||
// <o> Delay Before QSCK (ns) <0-255000>
|
||||
// <i> This field defines the delay from QCS falling edge (activation) to the first valid QSCK transition (in ns).
|
||||
// <id> qspi_dlybs
|
||||
#ifndef CONF_QSPI_DLY_BS
|
||||
#define CONF_QSPI_DLY_BS 0
|
||||
#endif
|
||||
|
||||
// <o> Minimum Inactive QCS Delay (ns) <0-8160000>
|
||||
// <i> This field defines the minimum delay between the deactivation and the activation of QCS (in ns).
|
||||
// <id> qspi_dlycs
|
||||
#ifndef CONF_QSPI_DLY_CS
|
||||
#define CONF_QSPI_DLY_CS 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
/* Calculate baud register value from requested baudrate value */
|
||||
#ifndef CONF_QSPI_BAUD_RATE
|
||||
#define CONF_QSPI_BAUD_RATE ((CONF_CPU_FREQUENCY / CONF_QSPI_BAUD) - 1)
|
||||
#if CONF_QSPI_BAUD > CONF_CPU_FREQUENCY || CONF_QSPI_BAUD_RATE > 255
|
||||
#warning Invalid baudrate, please check.
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Calculates the value of the CSR DLYCS field given the desired delay (in ns) */
|
||||
#ifndef CONF_QSPI_DLYCS
|
||||
#define CONF_QSPI_DLYCS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_CS) / 1000)
|
||||
#endif
|
||||
|
||||
/* Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
|
||||
#ifndef CONF_QSPI_DLYBS
|
||||
#define CONF_QSPI_DLYBS (((CONF_CPU_FREQUENCY / 1000000) * CONF_QSPI_DLY_BS) / 1000)
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_QSPI_CONFIG_H
|
||||
@ -1,341 +0,0 @@
|
||||
/* Auto-generated config file hpl_rtc_config.h */
|
||||
#ifndef HPL_RTC_CONFIG_H
|
||||
#define HPL_RTC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Basic settings
|
||||
|
||||
#ifndef CONF_RTC_ENABLE
|
||||
#define CONF_RTC_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <q> Force reset RTC on initialization
|
||||
// <i> Force RTC to reset on initialization.
|
||||
// <i> Note that the previous power down data in RTC is lost if it's enabled.
|
||||
// <id> rtc_arch_init_reset
|
||||
#ifndef CONF_RTC_INIT_RESET
|
||||
#define CONF_RTC_INIT_RESET 1
|
||||
#endif
|
||||
|
||||
// <o> Prescaler configuration
|
||||
// <0x0=>OFF(Peripheral clock divided by 1)
|
||||
// <0x1=>Peripheral clock divided by 1
|
||||
// <0x2=>Peripheral clock divided by 2
|
||||
// <0x3=>Peripheral clock divided by 4
|
||||
// <0x4=>Peripheral clock divided by 8
|
||||
// <0x5=>Peripheral clock divided by 16
|
||||
// <0x6=>Peripheral clock divided by 32
|
||||
// <0x7=>Peripheral clock divided by 64
|
||||
// <0x8=>Peripheral clock divided by 128
|
||||
// <0x9=>Peripheral clock divided by 256
|
||||
// <0xA=>Peripheral clock divided by 512
|
||||
// <0xB=>Peripheral clock divided by 1024
|
||||
// <i> These bits define the RTC clock relative to the peripheral clock
|
||||
// <id> rtc_arch_prescaler
|
||||
#ifndef CONF_RTC_PRESCALER
|
||||
#define CONF_RTC_PRESCALER 0x0
|
||||
|
||||
#endif
|
||||
|
||||
// <o> Compare Value <1-4294967295>
|
||||
// <i> These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value),
|
||||
// <i> by default 1K clock input, 1 prescaler, 1 compare value, the ticks period equals to 1ms.
|
||||
// <id> rtc_arch_comp_val
|
||||
|
||||
#ifndef CONF_RTC_COMP_VAL
|
||||
|
||||
#define CONF_RTC_COMP_VAL 32
|
||||
|
||||
#endif
|
||||
|
||||
// <e> RTC Tamper Input 0 settings
|
||||
// <id> tamper_input_0_settings
|
||||
#ifndef CONF_TAMPER_INPUT_0_SETTINGS
|
||||
#define CONF_TAMPER_INPUT_0_SETTINGS 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Level Settings
|
||||
// <i> Indicates Tamper input 0 level
|
||||
// <id> tamper_level_0
|
||||
#ifndef CONF_RTC_TAMP_LVL_0
|
||||
#define CONF_RTC_TAMP_LVL_0 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Input Action
|
||||
// <0x0=>OFF(Disabled)
|
||||
// <0x1=>Wake and Set Tamper Flag
|
||||
// <0x2=>Capture Timestamp and Set Tamper Flag
|
||||
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
|
||||
// <i> These bits define the RTC Tamper Input Action to be performed
|
||||
// <id> rtc_tamper_input_action_0
|
||||
#ifndef CONF_RTC_TAMPER_INACT_0
|
||||
#define CONF_RTC_TAMPER_INACT_0 0
|
||||
#endif
|
||||
|
||||
// <q> Debounce Enable for Tamper Input
|
||||
// <i> Indicates Debounce should be enabled for Tamper input 0
|
||||
// <id> tamper_debounce_enable_0
|
||||
#ifndef CONF_RTC_TAMP_DEBNC_0
|
||||
#define CONF_RTC_TAMP_DEBNC_0 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> RTC Tamper Input 1 settings
|
||||
// <id> tamper_input_1_settings
|
||||
#ifndef CONF_TAMPER_INPUT_1_SETTINGS
|
||||
#define CONF_TAMPER_INPUT_1_SETTINGS 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Level Settings
|
||||
// <i> Indicates Tamper input 1 level
|
||||
// <id> tamper_level_1
|
||||
#ifndef CONF_RTC_TAMP_LVL_1
|
||||
#define CONF_RTC_TAMP_LVL_1 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Input Action
|
||||
// <0x0=>OFF(Disabled)
|
||||
// <0x1=>Wake and Set Tamper Flag
|
||||
// <0x2=>Capture Timestamp and Set Tamper Flag
|
||||
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
|
||||
// <i> These bits define the RTC Tamper Input Action to be performed
|
||||
// <id> rtc_tamper_input_action_1
|
||||
#ifndef CONF_RTC_TAMPER_INACT_1
|
||||
#define CONF_RTC_TAMPER_INACT_1 0
|
||||
#endif
|
||||
|
||||
// <q> Debounce Enable for Tamper Input
|
||||
// <i> Indicates Debounce should be enabled for Tamper input 1
|
||||
// <id> tamper_debounce_enable_1
|
||||
#ifndef CONF_RTC_TAMP_DEBNC_1
|
||||
#define CONF_RTC_TAMP_DEBNC_1 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> RTC Tamper Input 2 settings
|
||||
// <id> tamper_input_2_settings
|
||||
#ifndef CONF_TAMPER_INPUT_2_SETTINGS
|
||||
#define CONF_TAMPER_INPUT_2_SETTINGS 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Level Settings
|
||||
// <i> Indicates Tamper input 2 level
|
||||
// <id> tamper_level_2
|
||||
#ifndef CONF_RTC_TAMP_LVL_2
|
||||
#define CONF_RTC_TAMP_LVL_2 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Input Action
|
||||
// <0x0=>OFF(Disabled)
|
||||
// <0x1=>Wake and Set Tamper Flag
|
||||
// <0x2=>Capture Timestamp and Set Tamper Flag
|
||||
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
|
||||
// <i> These bits define the RTC Tamper Input Action to be performed
|
||||
// <id> rtc_tamper_input_action_2
|
||||
#ifndef CONF_RTC_TAMPER_INACT_2
|
||||
#define CONF_RTC_TAMPER_INACT_2 0
|
||||
#endif
|
||||
|
||||
// <q> Debounce Enable for Tamper Input
|
||||
// <i> Indicates Debounce should be enabled for Tamper input 2
|
||||
// <id> tamper_debounce_enable_2
|
||||
#ifndef CONF_RTC_TAMP_DEBNC_2
|
||||
#define CONF_RTC_TAMP_DEBNC_2 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> RTC Tamper Input 3 settings
|
||||
// <id> tamper_input_3_settings
|
||||
#ifndef CONF_TAMPER_INPUT_3_SETTINGS
|
||||
#define CONF_TAMPER_INPUT_3_SETTINGS 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Level Settings
|
||||
// <i> Indicates Tamper input 3 level
|
||||
// <id> tamper_level_3
|
||||
#ifndef CONF_RTC_TAMP_LVL_3
|
||||
#define CONF_RTC_TAMP_LVL_3 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Input Action
|
||||
// <0x0=>OFF(Disabled)
|
||||
// <0x1=>Wake and Set Tamper Flag
|
||||
// <0x2=>Capture Timestamp and Set Tamper Flag
|
||||
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
|
||||
// <i> These bits define the RTC Tamper Input Action to be performed
|
||||
// <id> rtc_tamper_input_action_3
|
||||
#ifndef CONF_RTC_TAMPER_INACT_3
|
||||
#define CONF_RTC_TAMPER_INACT_3 0
|
||||
#endif
|
||||
|
||||
// <q> Debounce Enable for Tamper Input
|
||||
// <i> Indicates Debounce should be enabled for Tamper input 3
|
||||
// <id> tamper_debounce_enable_3
|
||||
#ifndef CONF_RTC_TAMP_DEBNC_3
|
||||
#define CONF_RTC_TAMP_DEBNC_3 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> RTC Tamper Input 4 settings
|
||||
// <id> tamper_input_4_settings
|
||||
#ifndef CONF_TAMPER_INPUT_4_SETTINGS
|
||||
#define CONF_TAMPER_INPUT_4_SETTINGS 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Level Settings
|
||||
// <i> Indicates Tamper input 4 level
|
||||
// <id> tamper_level_4
|
||||
#ifndef CONF_RTC_TAMP_LVL_4
|
||||
#define CONF_RTC_TAMP_LVL_4 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Input Action
|
||||
// <0x0=>OFF(Disabled)
|
||||
// <0x1=>Wake and Set Tamper Flag
|
||||
// <0x2=>Capture Timestamp and Set Tamper Flag
|
||||
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
|
||||
// <i> These bits define the RTC Tamper Input Action to be performed
|
||||
// <id> rtc_tamper_input_action_4
|
||||
#ifndef CONF_RTC_TAMPER_INACT_4
|
||||
#define CONF_RTC_TAMPER_INACT_4 0
|
||||
#endif
|
||||
|
||||
// <q> Debounce Enable for Tamper Input
|
||||
// <i> Indicates Debounce should be enabled for Tamper input 4
|
||||
// <id> tamper_debounce_enable_4
|
||||
#ifndef CONF_RTC_TAMP_DEBNC_4
|
||||
#define CONF_RTC_TAMP_DEBNC_4 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o> RTC Tamper Active Layer Frequency Prescalar
|
||||
// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2
|
||||
// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4
|
||||
// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8
|
||||
// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16
|
||||
// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32
|
||||
// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64
|
||||
// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128
|
||||
// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256
|
||||
// <i> These bits define the RTC Tamper Active Layer Frequecny Prescalar
|
||||
// <id> rtc_tamper_active_layer_frequency_prescalar
|
||||
#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES
|
||||
#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0
|
||||
#endif
|
||||
|
||||
// <o> RTC Tamper Debounce Frequency Prescalar
|
||||
// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2
|
||||
// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4
|
||||
// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8
|
||||
// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16
|
||||
// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32
|
||||
// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64
|
||||
// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128
|
||||
// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256
|
||||
// <i> These bits define the RTC Debounce Frequency Prescalar
|
||||
// <id> rtc_tamper_debounce_frequency_prescalar
|
||||
#ifndef CONF_RTC_TAMP_DEBF_PRES
|
||||
#define CONF_RTC_TAMP_DEBF_PRES 0
|
||||
#endif
|
||||
|
||||
// <e> Event control
|
||||
// <id> rtc_event_control
|
||||
#ifndef CONF_RTC_EVENT_CONTROL_ENABLE
|
||||
#define CONF_RTC_EVENT_CONTROL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> Periodic Interval 0 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated
|
||||
// <id> rtc_pereo0
|
||||
#ifndef CONF_RTC_PEREO0
|
||||
#define CONF_RTC_PEREO0 0
|
||||
#endif
|
||||
// <q> Periodic Interval 1 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated
|
||||
// <id> rtc_pereo1
|
||||
#ifndef CONF_RTC_PEREO1
|
||||
#define CONF_RTC_PEREO1 0
|
||||
#endif
|
||||
// <q> Periodic Interval 2 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated
|
||||
// <id> rtc_pereo2
|
||||
#ifndef CONF_RTC_PEREO2
|
||||
#define CONF_RTC_PEREO2 0
|
||||
#endif
|
||||
// <q> Periodic Interval 3 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated
|
||||
// <id> rtc_pereo3
|
||||
#ifndef CONF_RTC_PEREO3
|
||||
#define CONF_RTC_PEREO3 0
|
||||
#endif
|
||||
// <q> Periodic Interval 4 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated
|
||||
// <id> rtc_pereo4
|
||||
#ifndef CONF_RTC_PEREO4
|
||||
#define CONF_RTC_PEREO4 0
|
||||
#endif
|
||||
// <q> Periodic Interval 5 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated
|
||||
// <id> rtc_pereo5
|
||||
#ifndef CONF_RTC_PEREO5
|
||||
#define CONF_RTC_PEREO5 0
|
||||
#endif
|
||||
// <q> Periodic Interval 6 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated
|
||||
// <id> rtc_pereo6
|
||||
#ifndef CONF_RTC_PEREO6
|
||||
#define CONF_RTC_PEREO6 0
|
||||
#endif
|
||||
// <q> Periodic Interval 7 Event Output
|
||||
// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated
|
||||
// <id> rtc_pereo7
|
||||
#ifndef CONF_RTC_PEREO7
|
||||
#define CONF_RTC_PEREO7 0
|
||||
#endif
|
||||
|
||||
// <q> Compare 0 Event Output
|
||||
// <i> This bit indicates whether Compare O event is enabled and will be generated
|
||||
// <id> rtc_cmpeo0
|
||||
#ifndef CONF_RTC_COMPE0
|
||||
#define CONF_RTC_COMPE0 0
|
||||
#endif
|
||||
|
||||
// <q> Compare 1 Event Output
|
||||
// <i> This bit indicates whether Compare 1 event is enabled and will be generated
|
||||
// <id> rtc_cmpeo1
|
||||
#ifndef CONF_RTC_COMPE1
|
||||
#define CONF_RTC_COMPE1 0
|
||||
#endif
|
||||
// <q> Overflow Event Output
|
||||
// <i> This bit indicates whether Overflow event is enabled and will be generated
|
||||
// <id> rtc_ovfeo
|
||||
#ifndef CONF_RTC_OVFEO
|
||||
#define CONF_RTC_OVFEO 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Event Output
|
||||
// <i> This bit indicates whether Tamper event output is enabled and will be generated
|
||||
// <id> rtc_tampereo
|
||||
#ifndef CONF_RTC_TAMPEREO
|
||||
#define CONF_RTC_TAMPEREO 0
|
||||
#endif
|
||||
|
||||
// <q> Tamper Event Input
|
||||
// <i> This bit indicates whether Tamper event input is enabled and will be generated
|
||||
// <id> rtc_tampevei
|
||||
#ifndef CONF_RTC_TAMPEVEI
|
||||
#define CONF_RTC_TAMPEVEI 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_RTC_CONFIG_H
|
||||
@ -1,18 +0,0 @@
|
||||
/* Auto-generated config file hpl_systick_config.h */
|
||||
#ifndef HPL_SYSTICK_CONFIG_H
|
||||
#define HPL_SYSTICK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Advanced settings
|
||||
// <q> SysTick exception request
|
||||
// <i> Indicates whether the generation of SysTick exception is enabled or not
|
||||
// <id> systick_arch_tickint
|
||||
#ifndef CONF_SYSTICK_TICKINT
|
||||
#define CONF_SYSTICK_TICKINT 0
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_SYSTICK_CONFIG_H
|
||||
@ -1,180 +0,0 @@
|
||||
/* Auto-generated config file hpl_tc_config.h */
|
||||
#ifndef HPL_TC_CONFIG_H
|
||||
#define HPL_TC_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
#ifndef CONF_TC0_ENABLE
|
||||
#define CONF_TC0_ENABLE 1
|
||||
#endif
|
||||
|
||||
#include "peripheral_clk_config.h"
|
||||
|
||||
// <h> Basic configuration
|
||||
|
||||
// <o> Prescaler
|
||||
// <0x0=> No division
|
||||
// <0x1=> Divide by 2
|
||||
// <0x2=> Divide by 4
|
||||
// <0x3=> Divide by 8
|
||||
// <0x4=> Divide by 16
|
||||
// <0x5=> Divide by 64
|
||||
// <0x6=> Divide by 256
|
||||
// <0x7=> Divide by 1024
|
||||
// <i> This defines the prescaler value
|
||||
// <id> timer_prescaler
|
||||
#ifndef CONF_TC0_PRESCALER
|
||||
#define CONF_TC0_PRESCALER 0x3
|
||||
#endif
|
||||
|
||||
// <o> Length of one timer tick in uS <0-4294967295>
|
||||
// <id> timer_tick
|
||||
#ifndef CONF_TC0_TIMER_TICK
|
||||
#define CONF_TC0_TIMER_TICK 1000
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <e> Advanced configuration
|
||||
// <id> timer_advanced_configuration
|
||||
#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE
|
||||
#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <y> Prescaler and Counter Synchronization Selection
|
||||
// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
|
||||
// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
|
||||
// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
|
||||
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
|
||||
// <id> tc_arch_presync
|
||||
#ifndef CONF_TC0_PRESCSYNC
|
||||
#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
|
||||
#endif
|
||||
|
||||
// <q> Run in standby
|
||||
// <i> Indicates whether the module will continue to run in standby sleep mode
|
||||
// <id> tc_arch_runstdby
|
||||
#ifndef CONF_TC0_RUNSTDBY
|
||||
#define CONF_TC0_RUNSTDBY 0
|
||||
#endif
|
||||
|
||||
// <q> Run in debug mode
|
||||
// <i> Indicates whether the module will run in debug mode
|
||||
// <id> tc_arch_dbgrun
|
||||
#ifndef CONF_TC0_DBGRUN
|
||||
#define CONF_TC0_DBGRUN 0
|
||||
#endif
|
||||
|
||||
// <q> Run on demand
|
||||
// <i> Run if requested by some other peripheral in the device
|
||||
// <id> tc_arch_ondemand
|
||||
#ifndef CONF_TC0_ONDEMAND
|
||||
#define CONF_TC0_ONDEMAND 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e> Event control
|
||||
// <id> timer_event_control
|
||||
#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
|
||||
#define CONF_TC0_EVENT_CONTROL_ENABLE 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Match or Capture on Channel 0
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_mceo0
|
||||
#ifndef CONF_TC0_MCEO0
|
||||
#define CONF_TC0_MCEO0 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Match or Capture on Channel 1
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_mceo1
|
||||
#ifndef CONF_TC0_MCEO1
|
||||
#define CONF_TC0_MCEO1 0
|
||||
#endif
|
||||
|
||||
// <q> Output Event On Timer Tick
|
||||
// <i> Enable output of event on timer tick
|
||||
// <id> tc_arch_ovfeo
|
||||
#ifndef CONF_TC0_OVFEO
|
||||
#define CONF_TC0_OVFEO 0
|
||||
#endif
|
||||
|
||||
// <q> Event Input
|
||||
// <i> Enable asynchronous input events
|
||||
// <id> tc_arch_tcei
|
||||
#ifndef CONF_TC0_TCEI
|
||||
#define CONF_TC0_TCEI 0
|
||||
#endif
|
||||
|
||||
// <q> Inverted Event Input
|
||||
// <i> Invert the asynchronous input events
|
||||
// <id> tc_arch_tcinv
|
||||
#ifndef CONF_TC0_TCINV
|
||||
#define CONF_TC0_TCINV 0
|
||||
#endif
|
||||
|
||||
// <o> Event action
|
||||
// <0=> Event action disabled
|
||||
// <1=> Start, restart or re-trigger TC on event
|
||||
// <2=> Count on event
|
||||
// <3=> Start on event
|
||||
// <4=> Time stamp capture
|
||||
// <5=> Period captured in CC0, pulse width in CC1
|
||||
// <6=> Period captured in CC1, pulse width in CC0
|
||||
// <7=> Pulse width capture
|
||||
// <i> Event which will be performed on an event
|
||||
//<id> tc_arch_evact
|
||||
#ifndef CONF_TC0_EVACT
|
||||
#define CONF_TC0_EVACT 0
|
||||
#endif
|
||||
// </e>
|
||||
|
||||
// Default values which the driver needs in order to work correctly
|
||||
|
||||
// Mode set to 32-bit
|
||||
#ifndef CONF_TC0_MODE
|
||||
#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val
|
||||
#endif
|
||||
|
||||
// CC 1 register set to 0
|
||||
#ifndef CONF_TC0_CC1
|
||||
#define CONF_TC0_CC1 0
|
||||
#endif
|
||||
|
||||
#ifndef CONF_TC0_ALOCK
|
||||
#define CONF_TC0_ALOCK 0
|
||||
#endif
|
||||
|
||||
// Not used in 32-bit mode
|
||||
#define CONF_TC0_PER 0
|
||||
|
||||
// Calculating correct top value based on requested tick interval.
|
||||
#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER)
|
||||
|
||||
// Prescaler set to 64
|
||||
#if CONF_TC0_PRESCALER > 0x4
|
||||
#undef CONF_TC0_PRESCALE
|
||||
#define CONF_TC0_PRESCALE 64
|
||||
#endif
|
||||
|
||||
// Prescaler set to 256
|
||||
#if CONF_TC0_PRESCALER > 0x5
|
||||
#undef CONF_TC0_PRESCALE
|
||||
#define CONF_TC0_PRESCALE 256
|
||||
#endif
|
||||
|
||||
// Prescaler set to 1024
|
||||
#if CONF_TC0_PRESCALER > 0x6
|
||||
#undef CONF_TC0_PRESCALE
|
||||
#define CONF_TC0_PRESCALE 1024
|
||||
#endif
|
||||
|
||||
#ifndef CONF_TC0_CC0
|
||||
#define CONF_TC0_CC0 \
|
||||
(uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE)))
|
||||
#endif
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_TC_CONFIG_H
|
||||
@ -1,159 +0,0 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
|
||||
#include "driver_init.h"
|
||||
#include <peripheral_clk_config.h>
|
||||
#include <utils.h>
|
||||
#include <hal_init.h>
|
||||
|
||||
#include <hpl_rtc_base.h>
|
||||
|
||||
struct timer_descriptor TIMER_0;
|
||||
struct timer_descriptor TIMER_1;
|
||||
|
||||
struct qspi_sync_descriptor QUAD_SPI_0;
|
||||
|
||||
struct usart_sync_descriptor USART_0;
|
||||
|
||||
struct i2c_m_sync_desc I2C_0;
|
||||
|
||||
void EXTERNAL_IRQ_0_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_mclk_set_APBAMASK_EIC_bit(MCLK);
|
||||
|
||||
ext_irq_init();
|
||||
}
|
||||
|
||||
void QUAD_SPI_0_PORT_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void QUAD_SPI_0_CLOCK_init(void)
|
||||
{
|
||||
hri_mclk_set_AHBMASK_QSPI_bit(MCLK);
|
||||
hri_mclk_set_AHBMASK_QSPI_2X_bit(MCLK);
|
||||
hri_mclk_set_APBCMASK_QSPI_bit(MCLK);
|
||||
}
|
||||
|
||||
void QUAD_SPI_0_init(void)
|
||||
{
|
||||
QUAD_SPI_0_CLOCK_init();
|
||||
qspi_sync_init(&QUAD_SPI_0, QSPI);
|
||||
QUAD_SPI_0_PORT_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Timer initialization function
|
||||
*
|
||||
* Enables Timer peripheral, clocks and initializes Timer driver
|
||||
*/
|
||||
static void TIMER_0_init(void)
|
||||
{
|
||||
hri_mclk_set_APBAMASK_RTC_bit(MCLK);
|
||||
timer_init(&TIMER_0, RTC, _rtc_get_timer());
|
||||
}
|
||||
|
||||
void USART_0_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0);
|
||||
|
||||
gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1);
|
||||
}
|
||||
|
||||
void USART_0_CLOCK_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK);
|
||||
}
|
||||
|
||||
void USART_0_init(void)
|
||||
{
|
||||
USART_0_CLOCK_init();
|
||||
usart_sync_init(&USART_0, SERCOM0, (void *)NULL);
|
||||
USART_0_PORT_init();
|
||||
}
|
||||
|
||||
void I2C_0_PORT_init(void)
|
||||
{
|
||||
|
||||
gpio_set_pin_pull_mode(PA16,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(PA16, PINMUX_PA16C_SERCOM1_PAD0);
|
||||
|
||||
gpio_set_pin_pull_mode(PA17,
|
||||
// <y> Pull configuration
|
||||
// <id> pad_pull_config
|
||||
// <GPIO_PULL_OFF"> Off
|
||||
// <GPIO_PULL_UP"> Pull-up
|
||||
// <GPIO_PULL_DOWN"> Pull-down
|
||||
GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(PA17, PINMUX_PA17C_SERCOM1_PAD1);
|
||||
}
|
||||
|
||||
void I2C_0_CLOCK_init(void)
|
||||
{
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK);
|
||||
}
|
||||
|
||||
void I2C_0_init(void)
|
||||
{
|
||||
I2C_0_CLOCK_init();
|
||||
i2c_m_sync_init(&I2C_0, SERCOM1);
|
||||
I2C_0_PORT_init();
|
||||
}
|
||||
|
||||
void delay_driver_init(void)
|
||||
{
|
||||
delay_init(SysTick);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Timer initialization function
|
||||
*
|
||||
* Enables Timer peripheral, clocks and initializes Timer driver
|
||||
*/
|
||||
static void TIMER_1_init(void)
|
||||
{
|
||||
hri_mclk_set_APBAMASK_TC0_bit(MCLK);
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
|
||||
|
||||
timer_init(&TIMER_1, TC0, _tc_get_timer());
|
||||
}
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
init_mcu();
|
||||
|
||||
EXTERNAL_IRQ_0_init();
|
||||
|
||||
QUAD_SPI_0_init();
|
||||
|
||||
TIMER_0_init();
|
||||
|
||||
USART_0_init();
|
||||
|
||||
I2C_0_init();
|
||||
|
||||
delay_driver_init();
|
||||
|
||||
TIMER_1_init();
|
||||
}
|
||||
@ -1,70 +0,0 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef DRIVER_INIT_INCLUDED
|
||||
#define DRIVER_INIT_INCLUDED
|
||||
|
||||
#include "atmel_start_pins.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <hal_atomic.h>
|
||||
#include <hal_delay.h>
|
||||
#include <hal_gpio.h>
|
||||
#include <hal_init.h>
|
||||
#include <hal_io.h>
|
||||
#include <hal_sleep.h>
|
||||
|
||||
#include <hal_ext_irq.h>
|
||||
|
||||
#include <hal_qspi_sync.h>
|
||||
|
||||
#include <hal_timer.h>
|
||||
|
||||
#include <hal_usart_sync.h>
|
||||
|
||||
#include <hal_i2c_m_sync.h>
|
||||
|
||||
#include <hal_delay.h>
|
||||
#include <hal_timer.h>
|
||||
#include <hpl_tc_base.h>
|
||||
|
||||
extern struct qspi_sync_descriptor QUAD_SPI_0;
|
||||
extern struct timer_descriptor TIMER_0;
|
||||
|
||||
extern struct usart_sync_descriptor USART_0;
|
||||
|
||||
extern struct i2c_m_sync_desc I2C_0;
|
||||
|
||||
extern struct timer_descriptor TIMER_1;
|
||||
|
||||
void QUAD_SPI_0_PORT_init(void);
|
||||
void QUAD_SPI_0_CLOCK_init(void);
|
||||
void QUAD_SPI_0_init(void);
|
||||
|
||||
void USART_0_PORT_init(void);
|
||||
void USART_0_CLOCK_init(void);
|
||||
void USART_0_init(void);
|
||||
|
||||
void I2C_0_CLOCK_init(void);
|
||||
void I2C_0_init(void);
|
||||
void I2C_0_PORT_init(void);
|
||||
|
||||
void delay_driver_init(void);
|
||||
|
||||
/**
|
||||
* \brief Perform system initialization, initialize pins and clocks for
|
||||
* peripherals
|
||||
*/
|
||||
void system_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif // DRIVER_INIT_INCLUDED
|
||||
@ -1,121 +0,0 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
|
||||
#include "driver_examples.h"
|
||||
#include "driver_init.h"
|
||||
#include "utils.h"
|
||||
|
||||
/**
|
||||
* Example of using EXTERNAL_IRQ_0
|
||||
*/
|
||||
void EXTERNAL_IRQ_0_example(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using QUAD_SPI_0 to get N25Q256A status value,
|
||||
* and check bit 0 which indicate embedded operation is busy or not.
|
||||
*/
|
||||
void QUAD_SPI_0_example(void)
|
||||
{
|
||||
uint8_t status = 0xFF;
|
||||
struct _qspi_command cmd = {
|
||||
.inst_frame.bits.inst_en = 1,
|
||||
.inst_frame.bits.data_en = 1,
|
||||
.inst_frame.bits.tfr_type = QSPI_READ_ACCESS,
|
||||
.instruction = 0x05,
|
||||
.buf_len = 1,
|
||||
.rx_buf = &status,
|
||||
};
|
||||
|
||||
qspi_sync_enable(&QUAD_SPI_0);
|
||||
while (status & (1 << 0)) {
|
||||
qspi_sync_serial_run_command(&QUAD_SPI_0, &cmd);
|
||||
}
|
||||
qspi_sync_deinit(&QUAD_SPI_0);
|
||||
}
|
||||
|
||||
static struct timer_task TIMER_0_task1, TIMER_0_task2;
|
||||
/**
|
||||
* Example of using TIMER_0.
|
||||
*/
|
||||
static void TIMER_0_task1_cb(const struct timer_task *const timer_task)
|
||||
{
|
||||
}
|
||||
|
||||
static void TIMER_0_task2_cb(const struct timer_task *const timer_task)
|
||||
{
|
||||
}
|
||||
|
||||
void TIMER_0_example(void)
|
||||
{
|
||||
TIMER_0_task1.interval = 100;
|
||||
TIMER_0_task1.cb = TIMER_0_task1_cb;
|
||||
TIMER_0_task1.mode = TIMER_TASK_REPEAT;
|
||||
TIMER_0_task2.interval = 200;
|
||||
TIMER_0_task2.cb = TIMER_0_task2_cb;
|
||||
TIMER_0_task2.mode = TIMER_TASK_REPEAT;
|
||||
|
||||
timer_add_task(&TIMER_0, &TIMER_0_task1);
|
||||
timer_add_task(&TIMER_0, &TIMER_0_task2);
|
||||
timer_start(&TIMER_0);
|
||||
}
|
||||
|
||||
/**
|
||||
* Example of using USART_0 to write "Hello World" using the IO abstraction.
|
||||
*/
|
||||
void USART_0_example(void)
|
||||
{
|
||||
struct io_descriptor *io;
|
||||
usart_sync_get_io_descriptor(&USART_0, &io);
|
||||
usart_sync_enable(&USART_0);
|
||||
|
||||
io_write(io, (uint8_t *)"Hello World!", 12);
|
||||
}
|
||||
|
||||
void I2C_0_example(void)
|
||||
{
|
||||
struct io_descriptor *I2C_0_io;
|
||||
|
||||
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
|
||||
i2c_m_sync_enable(&I2C_0);
|
||||
i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
|
||||
io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
|
||||
}
|
||||
|
||||
void delay_example(void)
|
||||
{
|
||||
delay_ms(5000);
|
||||
}
|
||||
|
||||
static struct timer_task TIMER_1_task1, TIMER_1_task2;
|
||||
|
||||
/**
|
||||
* Example of using TIMER_1.
|
||||
*/
|
||||
static void TIMER_1_task1_cb(const struct timer_task *const timer_task)
|
||||
{
|
||||
}
|
||||
|
||||
static void TIMER_1_task2_cb(const struct timer_task *const timer_task)
|
||||
{
|
||||
}
|
||||
|
||||
void TIMER_1_example(void)
|
||||
{
|
||||
TIMER_1_task1.interval = 100;
|
||||
TIMER_1_task1.cb = TIMER_1_task1_cb;
|
||||
TIMER_1_task1.mode = TIMER_TASK_REPEAT;
|
||||
TIMER_1_task2.interval = 200;
|
||||
TIMER_1_task2.cb = TIMER_1_task2_cb;
|
||||
TIMER_1_task2.mode = TIMER_TASK_REPEAT;
|
||||
|
||||
timer_add_task(&TIMER_1, &TIMER_1_task1);
|
||||
timer_add_task(&TIMER_1, &TIMER_1_task2);
|
||||
timer_start(&TIMER_1);
|
||||
}
|
||||
@ -1,32 +0,0 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef DRIVER_EXAMPLES_H_INCLUDED
|
||||
#define DRIVER_EXAMPLES_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void EXTERNAL_IRQ_0_example(void);
|
||||
|
||||
void QUAD_SPI_0_example(void);
|
||||
|
||||
void TIMER_0_example(void);
|
||||
|
||||
void USART_0_example(void);
|
||||
|
||||
void I2C_0_example(void);
|
||||
|
||||
void delay_example(void);
|
||||
|
||||
void TIMER_1_example(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif // DRIVER_EXAMPLES_H_INCLUDED
|
||||
@ -1,289 +0,0 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
ifdef SystemRoot
|
||||
SHELL = cmd.exe
|
||||
MK_DIR = mkdir
|
||||
else
|
||||
ifeq ($(shell uname), Linux)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
|
||||
ifeq ($(shell uname | cut -d _ -f 1), CYGWIN)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
|
||||
ifeq ($(shell uname | cut -d _ -f 1), MINGW32)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
|
||||
ifeq ($(shell uname | cut -d _ -f 1), MINGW64)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
|
||||
ifeq ($(shell uname | cut -d _ -f 1), DARWIN)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
endif
|
||||
|
||||
# List the subdirectories for creating object files
|
||||
SUB_DIRS += \
|
||||
\
|
||||
hpl/pm \
|
||||
hpl/tc \
|
||||
hpl/osc32kctrl \
|
||||
hpl/ramecc \
|
||||
hpl/dmac \
|
||||
hal/src \
|
||||
gcc \
|
||||
hpl/mclk \
|
||||
hpl/qspi \
|
||||
hpl/eic \
|
||||
hpl/sercom \
|
||||
examples \
|
||||
hpl/gclk \
|
||||
hpl/oscctrl \
|
||||
hal/utils/src \
|
||||
gcc/gcc \
|
||||
hpl/rtc \
|
||||
hpl/systick \
|
||||
hpl/core \
|
||||
hpl/cmcc
|
||||
|
||||
# List the object files
|
||||
OBJS += \
|
||||
hal/src/hal_io.o \
|
||||
hpl/qspi/hpl_qspi.o \
|
||||
hpl/eic/hpl_eic.o \
|
||||
hpl/core/hpl_core_m4.o \
|
||||
hal/utils/src/utils_syscalls.o \
|
||||
hpl/systick/hpl_systick.o \
|
||||
hal/src/hal_timer.o \
|
||||
hal/src/hal_i2c_m_sync.o \
|
||||
hal/src/hal_delay.o \
|
||||
hpl/pm/hpl_pm.o \
|
||||
hpl/core/hpl_init.o \
|
||||
hpl/ramecc/hpl_ramecc.o \
|
||||
hal/utils/src/utils_list.o \
|
||||
hal/utils/src/utils_assert.o \
|
||||
hpl/dmac/hpl_dmac.o \
|
||||
hpl/oscctrl/hpl_oscctrl.o \
|
||||
hal/src/hal_usart_sync.o \
|
||||
hpl/mclk/hpl_mclk.o \
|
||||
hpl/sercom/hpl_sercom.o \
|
||||
hpl/gclk/hpl_gclk.o \
|
||||
hal/src/hal_init.o \
|
||||
gcc/gcc/startup_same54.o \
|
||||
main.o \
|
||||
hpl/osc32kctrl/hpl_osc32kctrl.o \
|
||||
hpl/rtc/hpl_rtc.o \
|
||||
examples/driver_examples.o \
|
||||
driver_init.o \
|
||||
hal/src/hal_ext_irq.o \
|
||||
hal/src/hal_atomic.o \
|
||||
hal/src/hal_gpio.o \
|
||||
hal/src/hal_qspi_sync.o \
|
||||
hal/utils/src/utils_event.o \
|
||||
hal/src/hal_sleep.o \
|
||||
hal/src/hal_cache.o \
|
||||
gcc/system_same54.o \
|
||||
atmel_start.o \
|
||||
hpl/tc/hpl_tc.o \
|
||||
hpl/cmcc/hpl_cmcc.o
|
||||
|
||||
OBJS_AS_ARGS += \
|
||||
"hal/src/hal_io.o" \
|
||||
"hpl/qspi/hpl_qspi.o" \
|
||||
"hpl/eic/hpl_eic.o" \
|
||||
"hpl/core/hpl_core_m4.o" \
|
||||
"hal/utils/src/utils_syscalls.o" \
|
||||
"hpl/systick/hpl_systick.o" \
|
||||
"hal/src/hal_timer.o" \
|
||||
"hal/src/hal_i2c_m_sync.o" \
|
||||
"hal/src/hal_delay.o" \
|
||||
"hpl/pm/hpl_pm.o" \
|
||||
"hpl/core/hpl_init.o" \
|
||||
"hpl/ramecc/hpl_ramecc.o" \
|
||||
"hal/utils/src/utils_list.o" \
|
||||
"hal/utils/src/utils_assert.o" \
|
||||
"hpl/dmac/hpl_dmac.o" \
|
||||
"hpl/oscctrl/hpl_oscctrl.o" \
|
||||
"hal/src/hal_usart_sync.o" \
|
||||
"hpl/mclk/hpl_mclk.o" \
|
||||
"hpl/sercom/hpl_sercom.o" \
|
||||
"hpl/gclk/hpl_gclk.o" \
|
||||
"hal/src/hal_init.o" \
|
||||
"gcc/gcc/startup_same54.o" \
|
||||
"main.o" \
|
||||
"hpl/osc32kctrl/hpl_osc32kctrl.o" \
|
||||
"hpl/rtc/hpl_rtc.o" \
|
||||
"examples/driver_examples.o" \
|
||||
"driver_init.o" \
|
||||
"hal/src/hal_ext_irq.o" \
|
||||
"hal/src/hal_atomic.o" \
|
||||
"hal/src/hal_gpio.o" \
|
||||
"hal/src/hal_qspi_sync.o" \
|
||||
"hal/utils/src/utils_event.o" \
|
||||
"hal/src/hal_sleep.o" \
|
||||
"hal/src/hal_cache.o" \
|
||||
"gcc/system_same54.o" \
|
||||
"atmel_start.o" \
|
||||
"hpl/tc/hpl_tc.o" \
|
||||
"hpl/cmcc/hpl_cmcc.o"
|
||||
|
||||
# List the directories containing header files
|
||||
DIR_INCLUDES += \
|
||||
-I"../" \
|
||||
-I"../config" \
|
||||
-I"../examples" \
|
||||
-I"../hal/include" \
|
||||
-I"../hal/utils/include" \
|
||||
-I"../hpl/cmcc" \
|
||||
-I"../hpl/core" \
|
||||
-I"../hpl/dmac" \
|
||||
-I"../hpl/eic" \
|
||||
-I"../hpl/gclk" \
|
||||
-I"../hpl/mclk" \
|
||||
-I"../hpl/osc32kctrl" \
|
||||
-I"../hpl/oscctrl" \
|
||||
-I"../hpl/pm" \
|
||||
-I"../hpl/port" \
|
||||
-I"../hpl/qspi" \
|
||||
-I"../hpl/ramecc" \
|
||||
-I"../hpl/rtc" \
|
||||
-I"../hpl/sercom" \
|
||||
-I"../hpl/systick" \
|
||||
-I"../hpl/tc" \
|
||||
-I"../hri" \
|
||||
-I"../" \
|
||||
-I"../CMSIS/Core/Include" \
|
||||
-I"../include"
|
||||
|
||||
# List the dependency files
|
||||
DEPS := $(OBJS:%.o=%.d)
|
||||
|
||||
DEPS_AS_ARGS += \
|
||||
"hal/utils/src/utils_event.d" \
|
||||
"hal/src/hal_io.d" \
|
||||
"hpl/ramecc/hpl_ramecc.d" \
|
||||
"hpl/qspi/hpl_qspi.d" \
|
||||
"hpl/core/hpl_core_m4.d" \
|
||||
"hpl/eic/hpl_eic.d" \
|
||||
"hal/utils/src/utils_syscalls.d" \
|
||||
"hal/src/hal_i2c_m_sync.d" \
|
||||
"hal/src/hal_timer.d" \
|
||||
"hal/utils/src/utils_list.d" \
|
||||
"hpl/cmcc/hpl_cmcc.d" \
|
||||
"hpl/dmac/hpl_dmac.d" \
|
||||
"hal/utils/src/utils_assert.d" \
|
||||
"hal/src/hal_delay.d" \
|
||||
"hpl/core/hpl_init.d" \
|
||||
"hpl/pm/hpl_pm.d" \
|
||||
"hpl/gclk/hpl_gclk.d" \
|
||||
"hpl/sercom/hpl_sercom.d" \
|
||||
"gcc/gcc/startup_same54.d" \
|
||||
"hal/src/hal_init.d" \
|
||||
"hal/src/hal_usart_sync.d" \
|
||||
"hpl/mclk/hpl_mclk.d" \
|
||||
"driver_init.d" \
|
||||
"hpl/systick/hpl_systick.d" \
|
||||
"hpl/osc32kctrl/hpl_osc32kctrl.d" \
|
||||
"main.d" \
|
||||
"examples/driver_examples.d" \
|
||||
"hpl/rtc/hpl_rtc.d" \
|
||||
"hal/src/hal_qspi_sync.d" \
|
||||
"hal/src/hal_cache.d" \
|
||||
"hal/src/hal_sleep.d" \
|
||||
"hal/src/hal_ext_irq.d" \
|
||||
"hal/src/hal_gpio.d" \
|
||||
"hal/src/hal_atomic.d" \
|
||||
"hpl/tc/hpl_tc.d" \
|
||||
"hpl/oscctrl/hpl_oscctrl.d" \
|
||||
"gcc/system_same54.d" \
|
||||
"atmel_start.d"
|
||||
|
||||
OUTPUT_FILE_NAME :=AtmelStart
|
||||
QUOTE := "
|
||||
OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf
|
||||
OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf
|
||||
|
||||
vpath %.c ../
|
||||
vpath %.s ../
|
||||
vpath %.S ../
|
||||
|
||||
# All Target
|
||||
all: $(SUB_DIRS) $(OUTPUT_FILE_PATH)
|
||||
|
||||
# Linker target
|
||||
|
||||
$(OUTPUT_FILE_PATH): $(OBJS)
|
||||
@echo Building target: $@
|
||||
@echo Invoking: ARM/GNU Linker
|
||||
$(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \
|
||||
-Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m4 \
|
||||
\
|
||||
-T"../gcc/gcc/same54p20a_flash.ld" \
|
||||
-L"../gcc/gcc"
|
||||
@echo Finished building target: $@
|
||||
|
||||
"arm-none-eabi-objcopy" -O binary "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).bin"
|
||||
"arm-none-eabi-objcopy" -O ihex -R .eeprom -R .fuse -R .lock -R .signature \
|
||||
"$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).hex"
|
||||
"arm-none-eabi-objcopy" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma \
|
||||
.eeprom=0 --no-change-warnings -O binary "$(OUTPUT_FILE_NAME).elf" \
|
||||
"$(OUTPUT_FILE_NAME).eep" || exit 0
|
||||
"arm-none-eabi-objdump" -h -S "$(OUTPUT_FILE_NAME).elf" > "$(OUTPUT_FILE_NAME).lss"
|
||||
"arm-none-eabi-size" "$(OUTPUT_FILE_NAME).elf"
|
||||
|
||||
|
||||
|
||||
# Compiler targets
|
||||
|
||||
|
||||
|
||||
|
||||
%.o: %.c
|
||||
@echo Building file: $<
|
||||
@echo ARM/GNU C Compiler
|
||||
$(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
|
||||
-D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \
|
||||
$(DIR_INCLUDES) \
|
||||
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
%.o: %.s
|
||||
@echo Building file: $<
|
||||
@echo ARM/GNU Assembler
|
||||
$(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
|
||||
-D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \
|
||||
$(DIR_INCLUDES) \
|
||||
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
%.o: %.S
|
||||
@echo Building file: $<
|
||||
@echo ARM/GNU Preprocessing Assembler
|
||||
$(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \
|
||||
-D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \
|
||||
$(DIR_INCLUDES) \
|
||||
-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
|
||||
@echo Finished building: $<
|
||||
|
||||
# Detect changes in the dependent files and recompile the respective object files.
|
||||
ifneq ($(MAKECMDGOALS),clean)
|
||||
ifneq ($(strip $(DEPS)),)
|
||||
-include $(DEPS)
|
||||
endif
|
||||
endif
|
||||
|
||||
$(SUB_DIRS):
|
||||
$(MK_DIR) "$@"
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS_AS_ARGS)
|
||||
rm -f $(OUTPUT_FILE_PATH)
|
||||
rm -f $(DEPS_AS_ARGS)
|
||||
rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \
|
||||
$(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \
|
||||
$(OUTPUT_FILE_NAME).srec
|
||||
@ -1,163 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME54P20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
@ -1,162 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME54P20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
@ -1,678 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief gcc starttup file for SAME54
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same54.h"
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
extern uint32_t _efixed;
|
||||
extern uint32_t _etext;
|
||||
extern uint32_t _srelocate;
|
||||
extern uint32_t _erelocate;
|
||||
extern uint32_t _szero;
|
||||
extern uint32_t _ezero;
|
||||
extern uint32_t _sstack;
|
||||
extern uint32_t _estack;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Default empty handler */
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M4 core handlers */
|
||||
void NonMaskableInt_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void MemManagement_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void BusFault_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void UsageFault_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void SVCall_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void DebugMonitor_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void MCLK_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void OSCCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
void OSCCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
void OSCCTRL_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF,
|
||||
OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS,
|
||||
OSCCTRL_DFLLRDY */
|
||||
void OSCCTRL_3_Handler(void) __attribute__((
|
||||
weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
void OSCCTRL_4_Handler(void) __attribute__((
|
||||
weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
void OSC32KCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void SUPC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY,
|
||||
SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY
|
||||
*/
|
||||
void SUPC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void EIC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
|
||||
void EIC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
|
||||
void EIC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
|
||||
void EIC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
|
||||
void EIC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
|
||||
void EIC_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
|
||||
void EIC_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
|
||||
void EIC_7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
|
||||
void EIC_8_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
|
||||
void EIC_9_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
|
||||
void EIC_10_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
|
||||
void EIC_11_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
|
||||
void EIC_12_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
|
||||
void EIC_13_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
|
||||
void EIC_14_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
|
||||
void EIC_15_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
|
||||
void FREQM_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void NVMCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2,
|
||||
NVMCTRL_3, NVMCTRL_4, NVMCTRL_5,
|
||||
NVMCTRL_6, NVMCTRL_7 */
|
||||
void NVMCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
void DMAC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
void DMAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
void DMAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
void DMAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
void DMAC_4_Handler(void)
|
||||
__attribute__((weak,
|
||||
alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14,
|
||||
DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19,
|
||||
DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24,
|
||||
DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29,
|
||||
DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6,
|
||||
DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11,
|
||||
DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15,
|
||||
DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19,
|
||||
DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23,
|
||||
DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27,
|
||||
DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31,
|
||||
DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8,
|
||||
DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13,
|
||||
DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18,
|
||||
DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23,
|
||||
DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28,
|
||||
DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5,
|
||||
DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
void EVSYS_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
void EVSYS_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
void EVSYS_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
void EVSYS_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
void EVSYS_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4,
|
||||
EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7,
|
||||
EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10,
|
||||
EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5,
|
||||
EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8,
|
||||
EVSYS_OVR_9 */
|
||||
void PAC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void RAMECC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void SERCOM0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
|
||||
void SERCOM0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
|
||||
void SERCOM0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
|
||||
void SERCOM0_3_Handler(void)
|
||||
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
void SERCOM1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
|
||||
void SERCOM1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
|
||||
void SERCOM1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
|
||||
void SERCOM1_3_Handler(void)
|
||||
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
void SERCOM2_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
|
||||
void SERCOM2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
|
||||
void SERCOM2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
|
||||
void SERCOM2_3_Handler(void)
|
||||
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
void SERCOM3_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
|
||||
void SERCOM3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
|
||||
void SERCOM3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
|
||||
void SERCOM3_3_Handler(void)
|
||||
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
void SERCOM4_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
|
||||
void SERCOM4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
|
||||
void SERCOM4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
|
||||
void SERCOM4_3_Handler(void)
|
||||
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
void SERCOM5_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
|
||||
void SERCOM5_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
|
||||
void SERCOM5_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
|
||||
void SERCOM5_3_Handler(void)
|
||||
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
void SERCOM6_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
|
||||
void SERCOM6_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
|
||||
void SERCOM6_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
|
||||
void SERCOM6_3_Handler(void)
|
||||
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
void SERCOM7_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
|
||||
void SERCOM7_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
|
||||
void SERCOM7_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
|
||||
void SERCOM7_3_Handler(void)
|
||||
__attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
void CAN0_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
void CAN1_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
void USB_0_Handler(void)
|
||||
__attribute__((weak,
|
||||
alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN,
|
||||
USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1,
|
||||
USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4,
|
||||
USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7,
|
||||
USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2,
|
||||
USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5,
|
||||
USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1,
|
||||
USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6,
|
||||
USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1,
|
||||
USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4,
|
||||
USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7,
|
||||
USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2,
|
||||
USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5,
|
||||
USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
void USB_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
|
||||
void USB_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2,
|
||||
USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5,
|
||||
USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
void USB_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2,
|
||||
USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5,
|
||||
USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
void GMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void TCC0_0_Handler(void)
|
||||
__attribute__((weak,
|
||||
alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A,
|
||||
TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
void TCC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
|
||||
void TCC0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
|
||||
void TCC0_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
|
||||
void TCC0_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
|
||||
void TCC0_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
|
||||
void TCC0_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
|
||||
void TCC1_0_Handler(void)
|
||||
__attribute__((weak,
|
||||
alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A,
|
||||
TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
void TCC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
|
||||
void TCC1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
|
||||
void TCC1_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
|
||||
void TCC1_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
|
||||
void TCC2_0_Handler(void)
|
||||
__attribute__((weak,
|
||||
alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A,
|
||||
TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
void TCC2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
|
||||
void TCC2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
|
||||
void TCC2_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
void TCC3_0_Handler(void)
|
||||
__attribute__((weak,
|
||||
alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A,
|
||||
TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
void TCC3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
|
||||
void TCC3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
void TCC4_0_Handler(void)
|
||||
__attribute__((weak,
|
||||
alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A,
|
||||
TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
void TCC4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
|
||||
void TCC4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
|
||||
#endif
|
||||
void TC0_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void TC1_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void TC2_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_TC4
|
||||
void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void PDEC_0_Handler(void)
|
||||
__attribute__((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
void PDEC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
|
||||
void PDEC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
|
||||
void ADC0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
|
||||
void ADC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
|
||||
void ADC1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
|
||||
void ADC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
|
||||
void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void DAC_0_Handler(void)
|
||||
__attribute__((weak,
|
||||
alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
void DAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
|
||||
void DAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
|
||||
void DAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
|
||||
void DAC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void PCC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void AES_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
void TRNG_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_ICM
|
||||
void ICM_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
void PUKCC_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void QSPI_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_SDHC0
|
||||
void SDHC0_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
void SDHC1_Handler(void) __attribute__((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__((section(".vectors"))) const DeviceVectors exception_table
|
||||
= {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
.pvStack = (void *)(&_estack),
|
||||
|
||||
.pfnReset_Handler = (void *)Reset_Handler,
|
||||
.pfnNonMaskableInt_Handler = (void *)NonMaskableInt_Handler,
|
||||
.pfnHardFault_Handler = (void *)HardFault_Handler,
|
||||
.pfnMemManagement_Handler = (void *)MemManagement_Handler,
|
||||
.pfnBusFault_Handler = (void *)BusFault_Handler,
|
||||
.pfnUsageFault_Handler = (void *)UsageFault_Handler,
|
||||
.pvReservedM9 = (void *)(0UL), /* Reserved */
|
||||
.pvReservedM8 = (void *)(0UL), /* Reserved */
|
||||
.pvReservedM7 = (void *)(0UL), /* Reserved */
|
||||
.pvReservedM6 = (void *)(0UL), /* Reserved */
|
||||
.pfnSVCall_Handler = (void *)SVCall_Handler,
|
||||
.pfnDebugMonitor_Handler = (void *)DebugMonitor_Handler,
|
||||
.pvReservedM3 = (void *)(0UL), /* Reserved */
|
||||
.pfnPendSV_Handler = (void *)PendSV_Handler,
|
||||
.pfnSysTick_Handler = (void *)SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
.pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */
|
||||
.pfnMCLK_Handler = (void *)MCLK_Handler, /* 1 Main Clock */
|
||||
.pfnOSCCTRL_0_Handler = (void *)OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
.pfnOSCCTRL_1_Handler = (void *)OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
.pfnOSCCTRL_2_Handler
|
||||
= (void *)OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS,
|
||||
OSCCTRL_DFLLRDY */
|
||||
.pfnOSCCTRL_3_Handler = (void *)
|
||||
OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
.pfnOSCCTRL_4_Handler = (void *)
|
||||
OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
.pfnOSC32KCTRL_Handler = (void *)OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
|
||||
.pfnSUPC_0_Handler = (void *)SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY,
|
||||
SUPC_VCORERDY, SUPC_VREGRDY */
|
||||
.pfnSUPC_1_Handler = (void *)SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
.pfnWDT_Handler = (void *)WDT_Handler, /* 10 Watchdog Timer */
|
||||
.pfnRTC_Handler = (void *)RTC_Handler, /* 11 Real-Time Counter */
|
||||
.pfnEIC_0_Handler = (void *)EIC_0_Handler, /* 12 EIC_EXTINT_0 */
|
||||
.pfnEIC_1_Handler = (void *)EIC_1_Handler, /* 13 EIC_EXTINT_1 */
|
||||
.pfnEIC_2_Handler = (void *)EIC_2_Handler, /* 14 EIC_EXTINT_2 */
|
||||
.pfnEIC_3_Handler = (void *)EIC_3_Handler, /* 15 EIC_EXTINT_3 */
|
||||
.pfnEIC_4_Handler = (void *)EIC_4_Handler, /* 16 EIC_EXTINT_4 */
|
||||
.pfnEIC_5_Handler = (void *)EIC_5_Handler, /* 17 EIC_EXTINT_5 */
|
||||
.pfnEIC_6_Handler = (void *)EIC_6_Handler, /* 18 EIC_EXTINT_6 */
|
||||
.pfnEIC_7_Handler = (void *)EIC_7_Handler, /* 19 EIC_EXTINT_7 */
|
||||
.pfnEIC_8_Handler = (void *)EIC_8_Handler, /* 20 EIC_EXTINT_8 */
|
||||
.pfnEIC_9_Handler = (void *)EIC_9_Handler, /* 21 EIC_EXTINT_9 */
|
||||
.pfnEIC_10_Handler = (void *)EIC_10_Handler, /* 22 EIC_EXTINT_10 */
|
||||
.pfnEIC_11_Handler = (void *)EIC_11_Handler, /* 23 EIC_EXTINT_11 */
|
||||
.pfnEIC_12_Handler = (void *)EIC_12_Handler, /* 24 EIC_EXTINT_12 */
|
||||
.pfnEIC_13_Handler = (void *)EIC_13_Handler, /* 25 EIC_EXTINT_13 */
|
||||
.pfnEIC_14_Handler = (void *)EIC_14_Handler, /* 26 EIC_EXTINT_14 */
|
||||
.pfnEIC_15_Handler = (void *)EIC_15_Handler, /* 27 EIC_EXTINT_15 */
|
||||
.pfnFREQM_Handler = (void *)FREQM_Handler, /* 28 Frequency Meter */
|
||||
.pfnNVMCTRL_0_Handler = (void *)
|
||||
NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6,
|
||||
NVMCTRL_7 */
|
||||
.pfnNVMCTRL_1_Handler = (void *)NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
.pfnDMAC_0_Handler = (void *)DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
.pfnDMAC_1_Handler = (void *)DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
.pfnDMAC_2_Handler = (void *)DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
.pfnDMAC_3_Handler = (void *)DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
.pfnDMAC_4_Handler = (void *)DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13,
|
||||
DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17,
|
||||
DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21,
|
||||
DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25,
|
||||
DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29,
|
||||
DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5,
|
||||
DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9,
|
||||
DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13,
|
||||
DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17,
|
||||
DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21,
|
||||
DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25,
|
||||
DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29,
|
||||
DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5,
|
||||
DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9,
|
||||
DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13,
|
||||
DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17,
|
||||
DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21,
|
||||
DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25,
|
||||
DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29,
|
||||
DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5,
|
||||
DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
.pfnEVSYS_0_Handler = (void *)EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
.pfnEVSYS_1_Handler = (void *)EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
.pfnEVSYS_2_Handler = (void *)EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
.pfnEVSYS_3_Handler = (void *)EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
.pfnEVSYS_4_Handler = (void *)EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5,
|
||||
EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9,
|
||||
EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5,
|
||||
EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
|
||||
.pfnPAC_Handler = (void *)PAC_Handler, /* 41 Peripheral Access Controller */
|
||||
.pvReserved42 = (void *)(0UL), /* 42 Reserved */
|
||||
.pvReserved43 = (void *)(0UL), /* 43 Reserved */
|
||||
.pvReserved44 = (void *)(0UL), /* 44 Reserved */
|
||||
.pfnRAMECC_Handler = (void *)RAMECC_Handler, /* 45 RAM ECC */
|
||||
.pfnSERCOM0_0_Handler = (void *)SERCOM0_0_Handler, /* 46 SERCOM0_0 */
|
||||
.pfnSERCOM0_1_Handler = (void *)SERCOM0_1_Handler, /* 47 SERCOM0_1 */
|
||||
.pfnSERCOM0_2_Handler = (void *)SERCOM0_2_Handler, /* 48 SERCOM0_2 */
|
||||
.pfnSERCOM0_3_Handler = (void *)SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
.pfnSERCOM1_0_Handler = (void *)SERCOM1_0_Handler, /* 50 SERCOM1_0 */
|
||||
.pfnSERCOM1_1_Handler = (void *)SERCOM1_1_Handler, /* 51 SERCOM1_1 */
|
||||
.pfnSERCOM1_2_Handler = (void *)SERCOM1_2_Handler, /* 52 SERCOM1_2 */
|
||||
.pfnSERCOM1_3_Handler = (void *)SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
.pfnSERCOM2_0_Handler = (void *)SERCOM2_0_Handler, /* 54 SERCOM2_0 */
|
||||
.pfnSERCOM2_1_Handler = (void *)SERCOM2_1_Handler, /* 55 SERCOM2_1 */
|
||||
.pfnSERCOM2_2_Handler = (void *)SERCOM2_2_Handler, /* 56 SERCOM2_2 */
|
||||
.pfnSERCOM2_3_Handler = (void *)SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
.pfnSERCOM3_0_Handler = (void *)SERCOM3_0_Handler, /* 58 SERCOM3_0 */
|
||||
.pfnSERCOM3_1_Handler = (void *)SERCOM3_1_Handler, /* 59 SERCOM3_1 */
|
||||
.pfnSERCOM3_2_Handler = (void *)SERCOM3_2_Handler, /* 60 SERCOM3_2 */
|
||||
.pfnSERCOM3_3_Handler = (void *)SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
.pfnSERCOM4_0_Handler = (void *)SERCOM4_0_Handler, /* 62 SERCOM4_0 */
|
||||
.pfnSERCOM4_1_Handler = (void *)SERCOM4_1_Handler, /* 63 SERCOM4_1 */
|
||||
.pfnSERCOM4_2_Handler = (void *)SERCOM4_2_Handler, /* 64 SERCOM4_2 */
|
||||
.pfnSERCOM4_3_Handler = (void *)SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#else
|
||||
.pvReserved62 = (void *)(0UL), /* 62 Reserved */
|
||||
.pvReserved63 = (void *)(0UL), /* 63 Reserved */
|
||||
.pvReserved64 = (void *)(0UL), /* 64 Reserved */
|
||||
.pvReserved65 = (void *)(0UL), /* 65 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
.pfnSERCOM5_0_Handler = (void *)SERCOM5_0_Handler, /* 66 SERCOM5_0 */
|
||||
.pfnSERCOM5_1_Handler = (void *)SERCOM5_1_Handler, /* 67 SERCOM5_1 */
|
||||
.pfnSERCOM5_2_Handler = (void *)SERCOM5_2_Handler, /* 68 SERCOM5_2 */
|
||||
.pfnSERCOM5_3_Handler = (void *)SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#else
|
||||
.pvReserved66 = (void *)(0UL), /* 66 Reserved */
|
||||
.pvReserved67 = (void *)(0UL), /* 67 Reserved */
|
||||
.pvReserved68 = (void *)(0UL), /* 68 Reserved */
|
||||
.pvReserved69 = (void *)(0UL), /* 69 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
.pfnSERCOM6_0_Handler = (void *)SERCOM6_0_Handler, /* 70 SERCOM6_0 */
|
||||
.pfnSERCOM6_1_Handler = (void *)SERCOM6_1_Handler, /* 71 SERCOM6_1 */
|
||||
.pfnSERCOM6_2_Handler = (void *)SERCOM6_2_Handler, /* 72 SERCOM6_2 */
|
||||
.pfnSERCOM6_3_Handler = (void *)SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#else
|
||||
.pvReserved70 = (void *)(0UL), /* 70 Reserved */
|
||||
.pvReserved71 = (void *)(0UL), /* 71 Reserved */
|
||||
.pvReserved72 = (void *)(0UL), /* 72 Reserved */
|
||||
.pvReserved73 = (void *)(0UL), /* 73 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
.pfnSERCOM7_0_Handler = (void *)SERCOM7_0_Handler, /* 74 SERCOM7_0 */
|
||||
.pfnSERCOM7_1_Handler = (void *)SERCOM7_1_Handler, /* 75 SERCOM7_1 */
|
||||
.pfnSERCOM7_2_Handler = (void *)SERCOM7_2_Handler, /* 76 SERCOM7_2 */
|
||||
.pfnSERCOM7_3_Handler = (void *)SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#else
|
||||
.pvReserved74 = (void *)(0UL), /* 74 Reserved */
|
||||
.pvReserved75 = (void *)(0UL), /* 75 Reserved */
|
||||
.pvReserved76 = (void *)(0UL), /* 76 Reserved */
|
||||
.pvReserved77 = (void *)(0UL), /* 77 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
.pfnCAN0_Handler = (void *)CAN0_Handler, /* 78 Control Area Network 0 */
|
||||
#else
|
||||
.pvReserved78 = (void *)(0UL), /* 78 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
.pfnCAN1_Handler = (void *)CAN1_Handler, /* 79 Control Area Network 1 */
|
||||
#else
|
||||
.pvReserved79 = (void *)(0UL), /* 79 Reserved */
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
.pfnUSB_0_Handler = (void *)
|
||||
USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF,
|
||||
USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3,
|
||||
USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7,
|
||||
USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3,
|
||||
USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7,
|
||||
USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5,
|
||||
USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1,
|
||||
USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5,
|
||||
USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1,
|
||||
USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5,
|
||||
USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
.pfnUSB_1_Handler = (void *)USB_1_Handler, /* 81 USB_SOF_HSOF */
|
||||
.pfnUSB_2_Handler = (void *)USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3,
|
||||
USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
.pfnUSB_3_Handler = (void *)USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3,
|
||||
USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#else
|
||||
.pvReserved80 = (void *)(0UL), /* 80 Reserved */
|
||||
.pvReserved81 = (void *)(0UL), /* 81 Reserved */
|
||||
.pvReserved82 = (void *)(0UL), /* 82 Reserved */
|
||||
.pvReserved83 = (void *)(0UL), /* 83 Reserved */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
.pfnGMAC_Handler = (void *)GMAC_Handler, /* 84 Ethernet MAC */
|
||||
#else
|
||||
.pvReserved84 = (void *)(0UL), /* 84 Reserved */
|
||||
#endif
|
||||
.pfnTCC0_0_Handler = (void *)
|
||||
TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A,
|
||||
TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
.pfnTCC0_1_Handler = (void *)TCC0_1_Handler, /* 86 TCC0_MC_0 */
|
||||
.pfnTCC0_2_Handler = (void *)TCC0_2_Handler, /* 87 TCC0_MC_1 */
|
||||
.pfnTCC0_3_Handler = (void *)TCC0_3_Handler, /* 88 TCC0_MC_2 */
|
||||
.pfnTCC0_4_Handler = (void *)TCC0_4_Handler, /* 89 TCC0_MC_3 */
|
||||
.pfnTCC0_5_Handler = (void *)TCC0_5_Handler, /* 90 TCC0_MC_4 */
|
||||
.pfnTCC0_6_Handler = (void *)TCC0_6_Handler, /* 91 TCC0_MC_5 */
|
||||
.pfnTCC1_0_Handler = (void *)
|
||||
TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A,
|
||||
TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
.pfnTCC1_1_Handler = (void *)TCC1_1_Handler, /* 93 TCC1_MC_0 */
|
||||
.pfnTCC1_2_Handler = (void *)TCC1_2_Handler, /* 94 TCC1_MC_1 */
|
||||
.pfnTCC1_3_Handler = (void *)TCC1_3_Handler, /* 95 TCC1_MC_2 */
|
||||
.pfnTCC1_4_Handler = (void *)TCC1_4_Handler, /* 96 TCC1_MC_3 */
|
||||
.pfnTCC2_0_Handler = (void *)
|
||||
TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A,
|
||||
TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
.pfnTCC2_1_Handler = (void *)TCC2_1_Handler, /* 98 TCC2_MC_0 */
|
||||
.pfnTCC2_2_Handler = (void *)TCC2_2_Handler, /* 99 TCC2_MC_1 */
|
||||
.pfnTCC2_3_Handler = (void *)TCC2_3_Handler, /* 100 TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
.pfnTCC3_0_Handler
|
||||
= (void *)TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A,
|
||||
TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
.pfnTCC3_1_Handler = (void *)TCC3_1_Handler, /* 102 TCC3_MC_0 */
|
||||
.pfnTCC3_2_Handler = (void *)TCC3_2_Handler, /* 103 TCC3_MC_1 */
|
||||
#else
|
||||
.pvReserved101 = (void *)(0UL), /* 101 Reserved */
|
||||
.pvReserved102 = (void *)(0UL), /* 102 Reserved */
|
||||
.pvReserved103 = (void *)(0UL), /* 103 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
.pfnTCC4_0_Handler
|
||||
= (void *)TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A,
|
||||
TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
.pfnTCC4_1_Handler = (void *)TCC4_1_Handler, /* 105 TCC4_MC_0 */
|
||||
.pfnTCC4_2_Handler = (void *)TCC4_2_Handler, /* 106 TCC4_MC_1 */
|
||||
#else
|
||||
.pvReserved104 = (void *)(0UL), /* 104 Reserved */
|
||||
.pvReserved105 = (void *)(0UL), /* 105 Reserved */
|
||||
.pvReserved106 = (void *)(0UL), /* 106 Reserved */
|
||||
#endif
|
||||
.pfnTC0_Handler = (void *)TC0_Handler, /* 107 Basic Timer Counter 0 */
|
||||
.pfnTC1_Handler = (void *)TC1_Handler, /* 108 Basic Timer Counter 1 */
|
||||
.pfnTC2_Handler = (void *)TC2_Handler, /* 109 Basic Timer Counter 2 */
|
||||
.pfnTC3_Handler = (void *)TC3_Handler, /* 110 Basic Timer Counter 3 */
|
||||
#ifdef ID_TC4
|
||||
.pfnTC4_Handler = (void *)TC4_Handler, /* 111 Basic Timer Counter 4 */
|
||||
#else
|
||||
.pvReserved111 = (void *)(0UL), /* 111 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
.pfnTC5_Handler = (void *)TC5_Handler, /* 112 Basic Timer Counter 5 */
|
||||
#else
|
||||
.pvReserved112 = (void *)(0UL), /* 112 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
.pfnTC6_Handler = (void *)TC6_Handler, /* 113 Basic Timer Counter 6 */
|
||||
#else
|
||||
.pvReserved113 = (void *)(0UL), /* 113 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
.pfnTC7_Handler = (void *)TC7_Handler, /* 114 Basic Timer Counter 7 */
|
||||
#else
|
||||
.pvReserved114 = (void *)(0UL), /* 114 Reserved */
|
||||
#endif
|
||||
.pfnPDEC_0_Handler = (void *)PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
.pfnPDEC_1_Handler = (void *)PDEC_1_Handler, /* 116 PDEC_MC_0 */
|
||||
.pfnPDEC_2_Handler = (void *)PDEC_2_Handler, /* 117 PDEC_MC_1 */
|
||||
.pfnADC0_0_Handler = (void *)ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */
|
||||
.pfnADC0_1_Handler = (void *)ADC0_1_Handler, /* 119 ADC0_RESRDY */
|
||||
.pfnADC1_0_Handler = (void *)ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */
|
||||
.pfnADC1_1_Handler = (void *)ADC1_1_Handler, /* 121 ADC1_RESRDY */
|
||||
.pfnAC_Handler = (void *)AC_Handler, /* 122 Analog Comparators */
|
||||
.pfnDAC_0_Handler
|
||||
= (void *)DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
.pfnDAC_1_Handler = (void *)DAC_1_Handler, /* 124 DAC_EMPTY_0 */
|
||||
.pfnDAC_2_Handler = (void *)DAC_2_Handler, /* 125 DAC_EMPTY_1 */
|
||||
.pfnDAC_3_Handler = (void *)DAC_3_Handler, /* 126 DAC_RESRDY_0 */
|
||||
.pfnDAC_4_Handler = (void *)DAC_4_Handler, /* 127 DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
.pfnI2S_Handler = (void *)I2S_Handler, /* 128 Inter-IC Sound Interface */
|
||||
#else
|
||||
.pvReserved128 = (void *)(0UL), /* 128 Reserved */
|
||||
#endif
|
||||
.pfnPCC_Handler = (void *)PCC_Handler, /* 129 Parallel Capture Controller */
|
||||
.pfnAES_Handler = (void *)AES_Handler, /* 130 Advanced Encryption Standard */
|
||||
.pfnTRNG_Handler = (void *)TRNG_Handler, /* 131 True Random Generator */
|
||||
#ifdef ID_ICM
|
||||
.pfnICM_Handler = (void *)ICM_Handler, /* 132 Integrity Check Monitor */
|
||||
#else
|
||||
.pvReserved132 = (void *)(0UL), /* 132 Reserved */
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
.pfnPUKCC_Handler = (void *)PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
|
||||
#else
|
||||
.pvReserved133 = (void *)(0UL), /* 133 Reserved */
|
||||
#endif
|
||||
.pfnQSPI_Handler = (void *)QSPI_Handler, /* 134 Quad SPI interface */
|
||||
#ifdef ID_SDHC0
|
||||
.pfnSDHC0_Handler = (void *)SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */
|
||||
#else
|
||||
.pvReserved135 = (void *)(0UL), /* 135 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
.pfnSDHC1_Handler = (void *)SDHC1_Handler /* 136 SD/MMC Host Controller 1 */
|
||||
#else
|
||||
.pvReserved136 = (void *)(0UL) /* 136 Reserved */
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *)&_sfixed;
|
||||
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
#if __FPU_USED
|
||||
/* Enable FPU */
|
||||
SCB->CPACR |= (0xFu << 20);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Branch to main function */
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
@ -1,64 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same54.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (48000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
@ -1,43 +0,0 @@
|
||||
The Quad SPI Synchronous Driver
|
||||
=================================
|
||||
|
||||
The Quad SPI Interface (QSPI) is a synchronous serial data link that provides
|
||||
communication with external devices in master mode.
|
||||
|
||||
The driver can be used for SPI serial memory middleware which support flash
|
||||
earse, program and read.
|
||||
|
||||
|
||||
Features
|
||||
--------
|
||||
|
||||
* Initialization/de-initialization
|
||||
* Enabling/disabling
|
||||
* Execute command in Serial Memory Mode
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
They are commonly used in an application for using serial flash memory operating
|
||||
in single-bit SPI, Dual SPI and Quad SPI.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
|
||||
Serial NOR flash with Multiple I/O hardware
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
|
||||
N/A
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
N.A
|
||||
|
||||
Known issues and workarounds
|
||||
----------------------------
|
||||
|
||||
N/A
|
||||
|
||||
@ -1,52 +0,0 @@
|
||||
============================
|
||||
The Timer driver (bare-bone)
|
||||
============================
|
||||
|
||||
The Timer driver provides means for delayed and periodical function invocation.
|
||||
|
||||
A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has
|
||||
been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a
|
||||
configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically
|
||||
changes execution delays and periods for all tasks in the timers task queue.
|
||||
|
||||
A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue
|
||||
and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on
|
||||
the period set in the task configuration.
|
||||
In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to
|
||||
reuse the memory of expired task in the callback.
|
||||
|
||||
Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available.
|
||||
|
||||
Features
|
||||
--------
|
||||
* Initialization and de-initialization
|
||||
* Starting and stopping
|
||||
* Timer tasks - periodical invocation of functions
|
||||
* Changing and obtaining of the period of a timer
|
||||
|
||||
Applications
|
||||
------------
|
||||
* Delayed and periodical function execution for middle-ware stacks and applications.
|
||||
|
||||
Dependencies
|
||||
------------
|
||||
* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt.
|
||||
|
||||
Concurrency
|
||||
-----------
|
||||
The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during
|
||||
the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed
|
||||
until the task adding or removing is complete.
|
||||
|
||||
The task queue is not protected from the access by interrupts not used by the driver. Due to this
|
||||
it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes
|
||||
the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver.
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts.
|
||||
* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task.
|
||||
|
||||
Knows issues and workarounds
|
||||
----------------------------
|
||||
Not applicable
|
||||
@ -1,120 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Critical sections related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_ATOMIC_H_INCLUDED
|
||||
#define _HAL_ATOMIC_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_atomic
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Type for the register holding global interrupt enable flag
|
||||
*/
|
||||
typedef uint32_t hal_atomic_t;
|
||||
|
||||
/**
|
||||
* \brief Helper macro for entering critical sections
|
||||
*
|
||||
* This macro is recommended to be used instead of a direct call
|
||||
* hal_enterCritical() function to enter critical
|
||||
* sections. No semicolon is required after the macro.
|
||||
*
|
||||
* \section atomic_usage Usage Example
|
||||
* \code
|
||||
* CRITICAL_SECTION_ENTER()
|
||||
* Critical code
|
||||
* CRITICAL_SECTION_LEAVE()
|
||||
* \endcode
|
||||
*/
|
||||
#define CRITICAL_SECTION_ENTER() \
|
||||
{ \
|
||||
volatile hal_atomic_t __atomic; \
|
||||
atomic_enter_critical(&__atomic);
|
||||
|
||||
/**
|
||||
* \brief Helper macro for leaving critical sections
|
||||
*
|
||||
* This macro is recommended to be used instead of a direct call
|
||||
* hal_leaveCritical() function to leave critical
|
||||
* sections. No semicolon is required after the macro.
|
||||
*/
|
||||
#define CRITICAL_SECTION_LEAVE() \
|
||||
atomic_leave_critical(&__atomic); \
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Disable interrupts, enter critical section
|
||||
*
|
||||
* Disables global interrupts. Supports nested critical sections,
|
||||
* so that global interrupts are only re-enabled
|
||||
* upon leaving the outermost nested critical section.
|
||||
*
|
||||
* \param[out] atomic The pointer to a variable to store the value of global
|
||||
* interrupt enable flag
|
||||
*/
|
||||
void atomic_enter_critical(hal_atomic_t volatile *atomic);
|
||||
|
||||
/**
|
||||
* \brief Exit atomic section
|
||||
*
|
||||
* Enables global interrupts. Supports nested critical sections,
|
||||
* so that global interrupts are only re-enabled
|
||||
* upon leaving the outermost nested critical section.
|
||||
*
|
||||
* \param[in] atomic The pointer to a variable, which stores the latest stored
|
||||
* value of the global interrupt enable flag
|
||||
*/
|
||||
void atomic_leave_critical(hal_atomic_t volatile *atomic);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t atomic_get_version(void);
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_ATOMIC_H_INCLUDED */
|
||||
@ -1,96 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL cache functionality implementation.
|
||||
*
|
||||
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef HAL_CACHE_H_
|
||||
#define HAL_CACHE_H_
|
||||
|
||||
#include <hpl_cmcc.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Enable cache module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_enable(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Disable cache module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_disable(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Initialize cache module
|
||||
*
|
||||
* This function initialize cache module configuration.
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_init(void);
|
||||
|
||||
/**
|
||||
* \brief Configure cache module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
* \param[in] cache configuration structure pointer
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
|
||||
|
||||
/**
|
||||
* \brief Invalidate entire cache entries
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of cache module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t cache_invalidate_all(const void *hw);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_CACHE_H_ */
|
||||
@ -1,89 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL delay related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include <hpl_irq.h>
|
||||
#include <hpl_reset.h>
|
||||
#include <hpl_sleep.h>
|
||||
|
||||
#ifndef _HAL_DELAY_H_INCLUDED
|
||||
#define _HAL_DELAY_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_delay Delay Driver
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize Delay driver
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*/
|
||||
void delay_init(void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Perform delay in us
|
||||
*
|
||||
* This function performs delay for the given amount of microseconds.
|
||||
*
|
||||
* \param[in] us The amount delay in us
|
||||
*/
|
||||
void delay_us(const uint16_t us);
|
||||
|
||||
/**
|
||||
* \brief Perform delay in ms
|
||||
*
|
||||
* This function performs delay for the given amount of milliseconds.
|
||||
*
|
||||
* \param[in] ms The amount delay in ms
|
||||
*/
|
||||
void delay_ms(const uint16_t ms);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t delay_get_version(void);
|
||||
|
||||
/**@}*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HAL_DELAY_H_INCLUDED */
|
||||
@ -1,201 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Port
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*/
|
||||
#ifndef _HAL_GPIO_INCLUDED_
|
||||
#define _HAL_GPIO_INCLUDED_
|
||||
|
||||
#include <hpl_gpio.h>
|
||||
#include <utils_assert.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Set gpio pull mode
|
||||
*
|
||||
* Set pin pull mode, non existing pull modes throws an fatal assert
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor
|
||||
* GPIO_PULL_UP = Pull pin high with internal resistor
|
||||
* GPIO_PULL_OFF = Disable pin pull mode
|
||||
*/
|
||||
static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
|
||||
{
|
||||
_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set pin function
|
||||
*
|
||||
* Select which function a pin will be used for
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] function The pin function is given by a 32-bit wide bitfield
|
||||
* found in the header files for the device
|
||||
*
|
||||
*/
|
||||
static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
|
||||
{
|
||||
_gpio_set_pin_function(pin, function);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set port data direction
|
||||
*
|
||||
* Select if the pin data direction is input, output or disabled.
|
||||
* If disabled state is not possible, this function throws an assert.
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to the
|
||||
* corresponding pin
|
||||
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
|
||||
* GPIO_DIRECTION_OUT = Data direction out
|
||||
* GPIO_DIRECTION_OFF = Disables the pin
|
||||
* (low power state)
|
||||
*/
|
||||
static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
|
||||
const enum gpio_direction direction)
|
||||
{
|
||||
_gpio_set_direction(port, mask, direction);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set gpio data direction
|
||||
*
|
||||
* Select if the pin data direction is input, output or disabled.
|
||||
* If disabled state is not possible, this function throws an assert.
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
|
||||
* GPIO_DIRECTION_OUT = Data direction out
|
||||
* GPIO_DIRECTION_OFF = Disables the pin
|
||||
* (low power state)
|
||||
*/
|
||||
static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
|
||||
{
|
||||
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set port level
|
||||
*
|
||||
* Sets output level on the pins defined by the bit mask
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply port level to the corresponding
|
||||
* pin
|
||||
* \param[in] level true = Pin levels set to "high" state
|
||||
* false = Pin levels set to "low" state
|
||||
*/
|
||||
static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
|
||||
{
|
||||
_gpio_set_level(port, mask, level);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set gpio level
|
||||
*
|
||||
* Sets output level on a pin
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
* \param[in] level true = Pin level set to "high" state
|
||||
* false = Pin level set to "low" state
|
||||
*/
|
||||
static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
|
||||
{
|
||||
_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Toggle out level on pins
|
||||
*
|
||||
* Toggle the pin levels on pins defined by bit mask
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means toggle pin level to the corresponding
|
||||
* pin
|
||||
*/
|
||||
static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
|
||||
{
|
||||
_gpio_toggle_level(port, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Toggle output level on pin
|
||||
*
|
||||
* Toggle the pin levels on pins defined by bit mask
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
*/
|
||||
static inline void gpio_toggle_pin_level(const uint8_t pin)
|
||||
{
|
||||
_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get input level on pins
|
||||
*
|
||||
* Read the input level on pins connected to a port
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
*/
|
||||
static inline uint32_t gpio_get_port_level(const enum gpio_port port)
|
||||
{
|
||||
return _gpio_get_level(port);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Get level on pin
|
||||
*
|
||||
* Reads the level on pins connected to a port
|
||||
*
|
||||
* \param[in] pin The pin number for device
|
||||
*/
|
||||
static inline bool gpio_get_pin_level(const uint8_t pin)
|
||||
{
|
||||
return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
|
||||
}
|
||||
/**
|
||||
* \brief Get current driver version
|
||||
*/
|
||||
uint32_t gpio_get_version(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,72 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief HAL initialization related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_INIT_H_INCLUDED
|
||||
#define _HAL_INIT_H_INCLUDED
|
||||
|
||||
#include <hpl_init.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_init Init Driver
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize the hardware abstraction layer
|
||||
*
|
||||
* This function calls the various initialization functions.
|
||||
* Currently the following initialization functions are supported:
|
||||
* - System clock initialization
|
||||
*/
|
||||
static inline void init_mcu(void)
|
||||
{
|
||||
_init_chip();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t init_get_version(void);
|
||||
|
||||
/**@}*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HAL_INIT_H_INCLUDED */
|
||||
@ -1,110 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I/O related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_IO_INCLUDED
|
||||
#define _HAL_IO_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_io I/O Driver
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief I/O descriptor
|
||||
*
|
||||
* The I/O descriptor forward declaration.
|
||||
*/
|
||||
struct io_descriptor;
|
||||
|
||||
/**
|
||||
* \brief I/O write function pointer type
|
||||
*/
|
||||
typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief I/O read function pointer type
|
||||
*/
|
||||
typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief I/O descriptor
|
||||
*/
|
||||
struct io_descriptor {
|
||||
io_write_t write; /*! The write function pointer. */
|
||||
io_read_t read; /*! The read function pointer. */
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief I/O write interface
|
||||
*
|
||||
* This function writes up to \p length of bytes to a given I/O descriptor.
|
||||
* It returns the number of bytes actually write.
|
||||
*
|
||||
* \param[in] descr An I/O descriptor to write
|
||||
* \param[in] buf The buffer pointer to story the write data
|
||||
* \param[in] length The number of bytes to write
|
||||
*
|
||||
* \return The number of bytes written
|
||||
*/
|
||||
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
|
||||
|
||||
/**
|
||||
* \brief I/O read interface
|
||||
*
|
||||
* This function reads up to \p length bytes from a given I/O descriptor, and
|
||||
* stores it in the buffer pointed to by \p buf. It returns the number of bytes
|
||||
* actually read.
|
||||
*
|
||||
* \param[in] descr An I/O descriptor to read
|
||||
* \param[in] buf The buffer pointer to story the read data
|
||||
* \param[in] length The number of bytes to read
|
||||
*
|
||||
* \return The number of bytes actually read. This number can be less than the
|
||||
* requested length. E.g., in a driver that uses ring buffer for
|
||||
* reception, it may depend on the availability of data in the
|
||||
* ring buffer.
|
||||
*/
|
||||
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HAL_IO_INCLUDED */
|
||||
@ -1,122 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Quad QSPI related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_QSPI_INCLUDED
|
||||
#define _HAL_QSPI_INCLUDED
|
||||
|
||||
#include <hpl_qspi_sync.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_quad_spi_sync
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief QSPI descriptor structure
|
||||
*/
|
||||
struct qspi_sync_descriptor {
|
||||
struct _qspi_sync_dev dev;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize QSPI low level driver.
|
||||
*
|
||||
* \param[in] qspi Pointer to the QSPI device instance
|
||||
* \param[in] hw Pointer to the hardware base
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success
|
||||
*/
|
||||
int32_t qspi_sync_init(struct qspi_sync_descriptor *qspi, void *hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize QSPI low level driver.
|
||||
*
|
||||
* \param[in] qspi Pointer to the QSPI device instance
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success
|
||||
*/
|
||||
int32_t qspi_sync_deinit(struct qspi_sync_descriptor *qspi);
|
||||
|
||||
/**
|
||||
* \brief Enable QSPI for access without interrupts
|
||||
*
|
||||
* \param[in] qspi Pointer to the QSPI device instance
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success
|
||||
*/
|
||||
int32_t qspi_sync_enable(struct qspi_sync_descriptor *qspi);
|
||||
|
||||
/**
|
||||
* \brief Disable QSPI for access without interrupts
|
||||
*
|
||||
* Disable QSPI. Deactivate all CS pins if it works as master.
|
||||
*
|
||||
* \param[in] qspi Pointer to the QSPI device instance
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success
|
||||
*/
|
||||
int32_t qspi_sync_disable(struct qspi_sync_descriptor *qspi);
|
||||
|
||||
/** \brief Execute command in Serial Memory Mode.
|
||||
*
|
||||
* \param[in] qspi Pointer to the HAL QSPI instance
|
||||
* \param[in] cmd Pointer to the command structure
|
||||
*
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Success
|
||||
*/
|
||||
int32_t qspi_sync_serial_run_command(struct qspi_sync_descriptor *qspi, const struct _qspi_command *cmd);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t qspi_sync_get_version(void);
|
||||
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_QSPI_INCLUDED */
|
||||
@ -1,74 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Sleep related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_SLEEP_H_INCLUDED
|
||||
#define _HAL_SLEEP_H_INCLUDED
|
||||
|
||||
#include <hpl_sleep.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_helper_sleep
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Set the sleep mode of the device and put the MCU to sleep
|
||||
*
|
||||
* For an overview of which systems are disabled in sleep for the different
|
||||
* sleep modes, see the data sheet.
|
||||
*
|
||||
* \param[in] mode Sleep mode to use
|
||||
*
|
||||
* \return The status of a sleep request
|
||||
* \retval -1 The requested sleep mode was invalid or not available
|
||||
* \retval 0 The operation completed successfully, returned after leaving the
|
||||
* sleep
|
||||
*/
|
||||
int sleep(const uint8_t mode);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t sleep_get_version(void);
|
||||
/**@}*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HAL_SLEEP_H_INCLUDED */
|
||||
@ -1,207 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Timer task functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_TIMER_H_INCLUDED
|
||||
#define _HAL_TIMER_H_INCLUDED
|
||||
|
||||
#include <utils_list.h>
|
||||
#include <hpl_timer.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_timer
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Timer mode type
|
||||
*/
|
||||
enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT };
|
||||
|
||||
/**
|
||||
* \brief Timer task descriptor
|
||||
*
|
||||
* The timer task descriptor forward declaration.
|
||||
*/
|
||||
struct timer_task;
|
||||
|
||||
/**
|
||||
* \brief Timer task callback function type
|
||||
*/
|
||||
typedef void (*timer_cb_t)(const struct timer_task *const timer_task);
|
||||
|
||||
/**
|
||||
* \brief Timer task structure
|
||||
*/
|
||||
struct timer_task {
|
||||
struct list_element elem; /*! List element. */
|
||||
uint32_t time_label; /*! Absolute timer start time. */
|
||||
|
||||
uint32_t interval; /*! Number of timer ticks before calling the task. */
|
||||
timer_cb_t cb; /*! Function pointer to the task. */
|
||||
enum timer_task_mode mode; /*! Task mode: one shot or repeat. */
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Timer structure
|
||||
*/
|
||||
struct timer_descriptor {
|
||||
struct _timer_hpl_interface *func;
|
||||
struct _timer_device device;
|
||||
uint32_t time;
|
||||
struct list_descriptor tasks; /*! Timer tasks list. */
|
||||
volatile uint8_t flags;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize timer
|
||||
*
|
||||
* This function initializes the given timer.
|
||||
* It checks if the given hardware is not initialized and if the given hardware
|
||||
* is permitted to be initialized.
|
||||
*
|
||||
* \param[out] descr A timer descriptor to initialize
|
||||
* \param[in] hw The pointer to the hardware instance
|
||||
* \param[in] func The pointer to a set of function pointers
|
||||
*
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize timer
|
||||
*
|
||||
* This function deinitializes the given timer.
|
||||
* It checks if the given hardware is initialized and if the given hardware is
|
||||
* permitted to be deinitialized.
|
||||
*
|
||||
* \param[in] descr A timer descriptor to deinitialize
|
||||
*
|
||||
* \return De-initialization status.
|
||||
*/
|
||||
int32_t timer_deinit(struct timer_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Start timer
|
||||
*
|
||||
* This function starts the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to start
|
||||
*
|
||||
* \return Timer starting status.
|
||||
*/
|
||||
int32_t timer_start(struct timer_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Stop timer
|
||||
*
|
||||
* This function stops the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to stop
|
||||
*
|
||||
* \return Timer stopping status.
|
||||
*/
|
||||
int32_t timer_stop(struct timer_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Set amount of clock cycles per timer tick
|
||||
*
|
||||
* This function sets the amount of clock cycles per timer tick for the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to stop
|
||||
* \param[in] clock_cycles The amount of clock cycles per tick to set
|
||||
*
|
||||
* \return Setting clock cycles amount status.
|
||||
*/
|
||||
int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the amount of clock cycles in a tick
|
||||
*
|
||||
* This function retrieves how many clock cycles there are in a single timer tick.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to convert ticks to
|
||||
* clock cycles
|
||||
* \param[out] cycles The amount of clock cycles
|
||||
*
|
||||
* \return The status of clock cycles retrieving.
|
||||
*/
|
||||
int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles);
|
||||
|
||||
/**
|
||||
* \brief Add timer task
|
||||
*
|
||||
* This function adds the given timer task to the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to add task to
|
||||
* \param[in] task A task to add
|
||||
*
|
||||
* \return Timer's task adding status.
|
||||
*/
|
||||
int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task);
|
||||
|
||||
/**
|
||||
* \brief Remove timer task
|
||||
*
|
||||
* This function removes the given timer task from the given timer.
|
||||
* It checks if the given hardware is initialized.
|
||||
*
|
||||
* \param[in] descr The timer descriptor of a timer to remove task from
|
||||
* \param[in] task A task to remove
|
||||
*
|
||||
* \return Timer's task removing status.
|
||||
*/
|
||||
int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t timer_get_version(void);
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_TIMER_H_INCLUDED */
|
||||
@ -1,247 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief USART related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HAL_SYNC_USART_H_INCLUDED
|
||||
#define _HAL_SYNC_USART_H_INCLUDED
|
||||
|
||||
#include "hal_io.h"
|
||||
#include <hpl_usart_sync.h>
|
||||
|
||||
/**
|
||||
* \addtogroup doc_driver_hal_usart_sync
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Synchronous USART descriptor
|
||||
*/
|
||||
struct usart_sync_descriptor {
|
||||
struct io_descriptor io;
|
||||
struct _usart_sync_device device;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize USART interface
|
||||
*
|
||||
* This function initializes the given I/O descriptor to be used
|
||||
* as USART interface descriptor.
|
||||
* It checks if the given hardware is not initialized and
|
||||
* if the given hardware is permitted to be initialized.
|
||||
*
|
||||
* \param[out] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
* \param[in] func The pointer to as set of functions pointers
|
||||
*
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize USART interface
|
||||
*
|
||||
* This function deinitializes the given I/O descriptor.
|
||||
* It checks if the given hardware is initialized and
|
||||
* if the given hardware is permitted to be deinitialized.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return De-initialization status.
|
||||
*/
|
||||
int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Enable USART interface
|
||||
*
|
||||
* Enables the USART interface
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return Enabling status.
|
||||
*/
|
||||
int32_t usart_sync_enable(struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Disable USART interface
|
||||
*
|
||||
* Disables the USART interface
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return Disabling status.
|
||||
*/
|
||||
int32_t usart_sync_disable(struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Retrieve I/O descriptor
|
||||
*
|
||||
* This function retrieves the I/O descriptor of the given USART descriptor.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[out] io An I/O descriptor to retrieve
|
||||
*
|
||||
* \return The status of the I/O descriptor retrieving.
|
||||
*/
|
||||
int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io);
|
||||
|
||||
/**
|
||||
* \brief Specify action for flow control pins
|
||||
*
|
||||
* This function sets the action (or state) for the flow control pins
|
||||
* if the flow control is enabled.
|
||||
* It sets the state of flow control pins only if the automatic support of
|
||||
* the flow control is not supported by the hardware.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] state A state to set the flow control pins
|
||||
*
|
||||
* \return The status of flow control action setup.
|
||||
*/
|
||||
int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr,
|
||||
const union usart_flow_control_state state);
|
||||
|
||||
/**
|
||||
* \brief Set USART baud rate
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] baud_rate A baud rate to set
|
||||
*
|
||||
* \return The status of baud rate setting.
|
||||
*/
|
||||
int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate);
|
||||
|
||||
/**
|
||||
* \brief Set USART data order
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] data_order A data order to set
|
||||
*
|
||||
* \return The status of data order setting.
|
||||
*/
|
||||
int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order);
|
||||
|
||||
/**
|
||||
* \brief Set USART mode
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] mode A mode to set
|
||||
*
|
||||
* \return The status of mode setting.
|
||||
*/
|
||||
int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode);
|
||||
|
||||
/**
|
||||
* \brief Set USART parity
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] parity A parity to set
|
||||
*
|
||||
* \return The status of parity setting.
|
||||
*/
|
||||
int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity);
|
||||
|
||||
/**
|
||||
* \brief Set USART stop bits
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] stop_bits Stop bits to set
|
||||
*
|
||||
* \return The status of stop bits setting.
|
||||
*/
|
||||
int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits);
|
||||
|
||||
/**
|
||||
* \brief Set USART character size
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[in] size A character size to set
|
||||
*
|
||||
* \return The status of character size setting.
|
||||
*/
|
||||
int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the state of flow control pins
|
||||
*
|
||||
* This function retrieves the of flow control pins
|
||||
* if the flow control is enabled.
|
||||
* Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
|
||||
* if the flow control is done by the hardware
|
||||
* and the pins state cannot be read out.
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
* \param[out] state The state of flow control pins
|
||||
*
|
||||
* \return The status of flow control state reading.
|
||||
*/
|
||||
int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr,
|
||||
union usart_flow_control_state *const state);
|
||||
|
||||
/**
|
||||
* \brief Check if the USART transmitter is empty
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return The status of USART TX empty checking.
|
||||
* \retval 0 The USART transmitter is not empty
|
||||
* \retval 1 The USART transmitter is empty
|
||||
*/
|
||||
int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Check if the USART receiver is not empty
|
||||
*
|
||||
* \param[in] descr A USART descriptor which is used to communicate via USART
|
||||
*
|
||||
* \return The status of USART RX empty checking.
|
||||
* \retval 1 The USART receiver is not empty
|
||||
* \retval 0 The USART receiver is empty
|
||||
*/
|
||||
int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the current driver version
|
||||
*
|
||||
* \return Current driver version.
|
||||
*/
|
||||
uint32_t usart_sync_get_version(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HAL_SYNC_USART_H_INCLUDED */
|
||||
@ -1,321 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Generic CALENDAR functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_CALENDER_H_INCLUDED
|
||||
#define _HPL_CALENDER_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
#include <utils_list.h>
|
||||
#include "hpl_irq.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Calendar structure
|
||||
*
|
||||
* The Calendar structure forward declaration.
|
||||
*/
|
||||
struct calendar_dev;
|
||||
|
||||
/**
|
||||
* \brief Available mask options for alarms.
|
||||
*
|
||||
* Available mask options for alarms.
|
||||
*/
|
||||
enum calendar_alarm_option {
|
||||
/** Alarm disabled. */
|
||||
CALENDAR_ALARM_MATCH_DISABLED = 0,
|
||||
/** Alarm match on second. */
|
||||
CALENDAR_ALARM_MATCH_SEC,
|
||||
/** Alarm match on second and minute. */
|
||||
CALENDAR_ALARM_MATCH_MIN,
|
||||
/** Alarm match on second, minute, and hour. */
|
||||
CALENDAR_ALARM_MATCH_HOUR,
|
||||
/** Alarm match on second, minute, hour, and day. */
|
||||
CALENDAR_ALARM_MATCH_DAY,
|
||||
/** Alarm match on second, minute, hour, day, and month. */
|
||||
CALENDAR_ALARM_MATCH_MONTH,
|
||||
/** Alarm match on second, minute, hour, day, month and year. */
|
||||
CALENDAR_ALARM_MATCH_YEAR
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Available mode for alarms.
|
||||
*/
|
||||
enum calendar_alarm_mode { ONESHOT = 1, REPEAT };
|
||||
/**
|
||||
* \brief Prototype of callback on alarm match
|
||||
*/
|
||||
typedef void (*calendar_drv_cb_alarm_t)(struct calendar_dev *const dev);
|
||||
|
||||
/**
|
||||
* \brief Prototype of callback on tamper detect
|
||||
*/
|
||||
typedef void (*tamper_drv_cb_t)(struct calendar_dev *const dev);
|
||||
|
||||
/**
|
||||
* \brief Structure of Calendar instance
|
||||
*/
|
||||
struct calendar_dev {
|
||||
/** Pointer to the hardware base */
|
||||
void *hw;
|
||||
/** Alarm match callback */
|
||||
calendar_drv_cb_alarm_t callback;
|
||||
/** Tamper callback */
|
||||
tamper_drv_cb_t callback_tamper;
|
||||
/** IRQ struct */
|
||||
struct _irq_descriptor irq;
|
||||
};
|
||||
/**
|
||||
* \brief Time struct for calendar
|
||||
*/
|
||||
struct calendar_time {
|
||||
/*range from 0 to 59*/
|
||||
uint8_t sec;
|
||||
/*range from 0 to 59*/
|
||||
uint8_t min;
|
||||
/*range from 0 to 23*/
|
||||
uint8_t hour;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Time struct for calendar
|
||||
*/
|
||||
struct calendar_date {
|
||||
/*range from 1 to 28/29/30/31*/
|
||||
uint8_t day;
|
||||
/*range from 1 to 12*/
|
||||
uint8_t month;
|
||||
/*absolute year>= 1970(such as 2000)*/
|
||||
uint16_t year;
|
||||
};
|
||||
|
||||
/** \brief Calendar driver struct
|
||||
*
|
||||
*/
|
||||
struct calendar_descriptor {
|
||||
struct calendar_dev device;
|
||||
struct list_descriptor alarms;
|
||||
/*base date/time = base_year/1/1/0/0/0(year/month/day/hour/min/sec)*/
|
||||
uint32_t base_year;
|
||||
uint8_t flags;
|
||||
};
|
||||
|
||||
/** \brief Date&Time struct for calendar
|
||||
*/
|
||||
struct calendar_date_time {
|
||||
struct calendar_time time;
|
||||
struct calendar_date date;
|
||||
};
|
||||
|
||||
/** \brief struct for alarm time
|
||||
*/
|
||||
struct _calendar_alarm {
|
||||
struct calendar_date_time datetime;
|
||||
uint32_t timestamp;
|
||||
enum calendar_alarm_option option;
|
||||
enum calendar_alarm_mode mode;
|
||||
};
|
||||
|
||||
/** \enum for tamper detection mode
|
||||
*/
|
||||
enum tamper_detection_mode { TAMPER_MODE_OFF = 0U, TAMPER_MODE_WAKE, TAMPER_MODE_CAPTURE, TAMPER_MODE_ACTL };
|
||||
|
||||
/** \enum for tamper detection mode
|
||||
*/
|
||||
enum tamper_id { TAMPID0 = 0U, TAMPID1, TAMPID2, TAMPID3, TAMPID4 };
|
||||
/**
|
||||
* \brief Initialize Calendar instance
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _calendar_init(struct calendar_dev *const dev);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize Calendar instance
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _calendar_deinit(struct calendar_dev *const dev);
|
||||
|
||||
/**
|
||||
* \brief Enable Calendar instance
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _calendar_enable(struct calendar_dev *const dev);
|
||||
|
||||
/**
|
||||
* \brief Disable Calendar instance
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _calendar_disable(struct calendar_dev *const dev);
|
||||
/**
|
||||
* \brief Set time for calendar
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
* \param[in] p_calendar_time Pointer to the time configuration
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _calendar_set_time(struct calendar_dev *const dev, struct calendar_time *const p_calendar_time);
|
||||
|
||||
/**
|
||||
* \brief Set date for calendar
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
* \param[in] p_calendar_date Pointer to the date configuration
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _calendar_set_date(struct calendar_dev *const dev, struct calendar_date *const p_calendar_date);
|
||||
|
||||
/**
|
||||
* \brief Get the time for calendar HAL instance and hardware
|
||||
* Retrieve the time from calendar instance.
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
* \param[in] date_time Pointer to value that will be filled with current time
|
||||
*
|
||||
* \return Return current counter value
|
||||
*/
|
||||
uint32_t _calendar_get_date_time(struct calendar_dev *const dev, struct calendar_date_time *const date_time);
|
||||
|
||||
/**
|
||||
* \brief Set compare value for calendar
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
* \param[in] alarm Pointer to the configuration
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _calendar_set_alarm(struct calendar_dev *const dev, struct _calendar_alarm *const alarm);
|
||||
|
||||
/**
|
||||
* \brief Register callback for calendar alarm
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
* \param[in] callback The pointer to callback function
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback);
|
||||
|
||||
/**
|
||||
* \brief Set calendar IRQ
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
*/
|
||||
void _calendar_set_irq(struct calendar_dev *const dev);
|
||||
|
||||
/**
|
||||
* \brief Register callback for tamper detection
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
* \param[in] callback The pointer to callback function
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _tamper_register_callback(struct calendar_dev *const dev, tamper_drv_cb_t callback_tamper);
|
||||
|
||||
/**
|
||||
* \brief Find tamper is detected on specified pin
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
* \param[in] enum Tamper ID number
|
||||
*
|
||||
* \return true on detection success and false on failure.
|
||||
*/
|
||||
bool _is_tamper_detected(struct calendar_dev *const dev, enum tamper_id tamper_id_pin);
|
||||
|
||||
/**
|
||||
* \brief brief Clear the Tamper ID flag
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
* \param[in] enum Tamper ID number
|
||||
*
|
||||
* \return ERR_NONE
|
||||
*/
|
||||
int32_t _tamper_clear_tampid_flag(struct calendar_dev *const dev, enum tamper_id tamper_id_pin);
|
||||
|
||||
/**
|
||||
* \brief Enable Debounce Asynchronous Feature
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _tamper_enable_debounce_asynchronous(struct calendar_dev *const dev);
|
||||
|
||||
/**
|
||||
* \brief Disable Tamper Debounce Asynchronous Feature
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _tamper_disable_debounce_asynchronous(struct calendar_dev *const dev);
|
||||
|
||||
/**
|
||||
* \brief Enable Tamper Debounce Majority Feature
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _tamper_enable_debounce_majority(struct calendar_dev *const dev);
|
||||
|
||||
/**
|
||||
* \brief Enable Tamper Debounce Majority Feature
|
||||
*
|
||||
* \param[in] dev The pointer to calendar device struct
|
||||
*
|
||||
* \return ERR_NONE on success, or an error code on failure.
|
||||
*/
|
||||
int32_t _tamper_disable_debounce_majority(struct calendar_dev *const dev);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HPL_RTC_H_INCLUDED */
|
||||
@ -1,277 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Generic CMCC(Cortex M Cache Controller) related functionality.
|
||||
*
|
||||
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
|
||||
*/
|
||||
|
||||
#ifndef HPL_CMCC_H_
|
||||
#define HPL_CMCC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/**
|
||||
* \Cache driver MACROS
|
||||
*/
|
||||
#define CMCC_DISABLE 0U
|
||||
#define CMCC_ENABLE 1U
|
||||
#define IS_CMCC_DISABLED 0U
|
||||
#define IS_CMCC_ENABLED 1U
|
||||
#define CMCC_WAY_NOS 4U
|
||||
#define CMCC_LINE_NOS 64U
|
||||
#define CMCC_MONITOR_DISABLE 0U
|
||||
|
||||
/**
|
||||
* \brief Cache size configurations
|
||||
*/
|
||||
enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB };
|
||||
|
||||
/**
|
||||
* \brief Way Numbers
|
||||
*/
|
||||
enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 };
|
||||
|
||||
/**
|
||||
* \brief Cache monitor configurations
|
||||
*/
|
||||
enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT };
|
||||
|
||||
/**
|
||||
* \brief Cache configuration structure
|
||||
*/
|
||||
struct _cache_cfg {
|
||||
enum conf_cache_size cache_size;
|
||||
bool data_cache_disable;
|
||||
bool inst_cache_disable;
|
||||
bool gclk_gate_disable;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Cache enable status
|
||||
*/
|
||||
static inline bool _is_cache_enabled(const void *hw)
|
||||
{
|
||||
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Cache disable status
|
||||
*/
|
||||
static inline bool _is_cache_disabled(const void *hw)
|
||||
{
|
||||
return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Cache enable
|
||||
*/
|
||||
static inline int32_t _cmcc_enable(const void *hw)
|
||||
{
|
||||
int32_t return_value;
|
||||
|
||||
if (_is_cache_disabled(hw)) {
|
||||
hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN);
|
||||
return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE;
|
||||
} else {
|
||||
return_value = ERR_NO_CHANGE;
|
||||
}
|
||||
|
||||
return return_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Cache disable
|
||||
*/
|
||||
static inline int32_t _cmcc_disable(const void *hw)
|
||||
{
|
||||
hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos));
|
||||
while (!(_is_cache_disabled(hw)))
|
||||
;
|
||||
|
||||
return ERR_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Initialize Cache Module
|
||||
*
|
||||
* This function initialize low level cmcc module configuration.
|
||||
*
|
||||
* \return initialize status
|
||||
*/
|
||||
int32_t _cmcc_init(void);
|
||||
|
||||
/**
|
||||
* \brief Configure CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] cache configuration structure pointer
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl);
|
||||
|
||||
/**
|
||||
* \brief Enable data cache in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_data_cache(const void *hw, bool value);
|
||||
|
||||
/**
|
||||
* \brief Enable instruction cache in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_inst_cache(const void *hw, bool value);
|
||||
|
||||
/**
|
||||
* \brief Enable clock gating in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_clock_gating(const void *hw, bool value);
|
||||
|
||||
/**
|
||||
* \brief Configure the cache size in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from cache size configuration enumerator
|
||||
* 0->1K, 1->2K, 2->4K(default)
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size);
|
||||
|
||||
/**
|
||||
* \brief Lock the mentioned WAY in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from "way_num_index" enumerator
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_lock_way(const void *hw, enum way_num_index);
|
||||
|
||||
/**
|
||||
* \brief Unlock the mentioned WAY in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from "way_num_index" enumerator
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_unlock_way(const void *hw, enum way_num_index);
|
||||
|
||||
/**
|
||||
* \brief Invalidate the mentioned cache line in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from "way_num" enumerator (valid arg is 0-3)
|
||||
* \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num);
|
||||
|
||||
/**
|
||||
* \brief Invalidate entire cache entries in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_invalidate_all(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Configure cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
* \param[in] element from cache monitor configurations enumerator
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg);
|
||||
|
||||
/**
|
||||
* \brief Enable cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_enable_monitor(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Disable cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_disable_monitor(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Reset cache monitor in CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _cmcc_reset_monitor(const void *hw);
|
||||
|
||||
/**
|
||||
* \brief Get cache monitor event counter value from CMCC module
|
||||
*
|
||||
* \param[in] pointer pointing to the starting address of CMCC module
|
||||
*
|
||||
* \return event counter value
|
||||
*/
|
||||
uint32_t _cmcc_get_monitor_event_count(const void *hw);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HPL_CMCC_H_ */
|
||||
@ -1,56 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief CPU core related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_CORE_H_INCLUDED
|
||||
#define _HPL_CORE_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Core
|
||||
*
|
||||
* \section hpl_core_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include "hpl_core_port.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_CORE_H_INCLUDED */
|
||||
@ -1,97 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Delay related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_DELAY_H_INCLUDED
|
||||
#define _HPL_DELAY_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Delay
|
||||
*
|
||||
* \section hpl_delay_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifndef _UNIT_TEST_
|
||||
#include <compiler.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
|
||||
/**
|
||||
* \brief Initialize delay functionality
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*/
|
||||
void _delay_init(void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the amount of cycles to delay for the given amount of us
|
||||
*
|
||||
* \param[in] us The amount of us to delay for
|
||||
*
|
||||
* \return The amount of cycles
|
||||
*/
|
||||
uint32_t _get_cycles_for_us(const uint16_t us);
|
||||
|
||||
/**
|
||||
* \brief Retrieve the amount of cycles to delay for the given amount of ms
|
||||
*
|
||||
* \param[in] ms The amount of ms to delay for
|
||||
*
|
||||
* \return The amount of cycles
|
||||
*/
|
||||
uint32_t _get_cycles_for_ms(const uint16_t ms);
|
||||
|
||||
/**
|
||||
* \brief Delay loop to delay n number of cycles
|
||||
*
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
* \param[in] cycles The amount of cycles to delay for
|
||||
*/
|
||||
void _delay_cycles(void *const hw, uint32_t cycles);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_DELAY_H_INCLUDED */
|
||||
@ -1,176 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief DMA related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_DMA_H_INCLUDED
|
||||
#define _HPL_DMA_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL DMA
|
||||
*
|
||||
* \section hpl_dma_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <hpl_irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct _dma_resource;
|
||||
|
||||
/**
|
||||
* \brief DMA callback types
|
||||
*/
|
||||
enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
|
||||
|
||||
/**
|
||||
* \brief DMA interrupt callbacks
|
||||
*/
|
||||
struct _dma_callbacks {
|
||||
void (*transfer_done)(struct _dma_resource *resource);
|
||||
void (*error)(struct _dma_resource *resource);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief DMA resource structure
|
||||
*/
|
||||
struct _dma_resource {
|
||||
struct _dma_callbacks dma_cb;
|
||||
void * back;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize DMA
|
||||
*
|
||||
* This function does low level DMA configuration.
|
||||
*
|
||||
* \return initialize status
|
||||
*/
|
||||
int32_t _dma_init(void);
|
||||
|
||||
/**
|
||||
* \brief Set destination address
|
||||
*
|
||||
* \param[in] channel DMA channel to set destination address for
|
||||
* \param[in] dst Destination address
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst);
|
||||
|
||||
/**
|
||||
* \brief Set source address
|
||||
*
|
||||
* \param[in] channel DMA channel to set source address for
|
||||
* \param[in] src Source address
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_source_address(const uint8_t channel, const void *const src);
|
||||
|
||||
/**
|
||||
* \brief Set next descriptor address
|
||||
*
|
||||
* \param[in] current_channel Current DMA channel to set next descriptor address
|
||||
* \param[in] next_channel Next DMA channel used as next descriptor
|
||||
*
|
||||
* \return setting status
|
||||
*/
|
||||
int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable source address incrementation during DMA transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set source address for
|
||||
* \param[in] enable True to enable, false to disable
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable Destination address incrementation during DMA transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set destination address for
|
||||
* \param[in] enable True to enable, false to disable
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable);
|
||||
/**
|
||||
* \brief Set the amount of data to be transfered per transaction
|
||||
*
|
||||
* \param[in] channel DMA channel to set data amount for
|
||||
* \param[in] amount Data amount
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount);
|
||||
|
||||
/**
|
||||
* \brief Trigger DMA transaction on the given channel
|
||||
*
|
||||
* \param[in] channel DMA channel to trigger transaction on
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger);
|
||||
|
||||
/**
|
||||
* \brief Retrieves DMA resource structure
|
||||
*
|
||||
* \param[out] resource The resource to be retrieved
|
||||
* \param[in] channel DMA channel to retrieve structure for
|
||||
*
|
||||
* \return status of operation
|
||||
*/
|
||||
int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable DMA interrupt
|
||||
*
|
||||
* \param[in] channel DMA channel to enable/disable interrupt for
|
||||
* \param[in] type The type of interrupt to disable/enable if applicable
|
||||
* \param[in] state Enable or disable
|
||||
*/
|
||||
void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HPL_DMA_H_INCLUDED */
|
||||
@ -1,185 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Port related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_GPIO_H_INCLUDED
|
||||
#define _HPL_GPIO_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Port
|
||||
*
|
||||
* \section hpl_port_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/**
|
||||
* \brief Macros for the pin and port group, lower 5
|
||||
* bits stands for pin number in the group, higher 3
|
||||
* bits stands for port group
|
||||
*/
|
||||
#define GPIO_PIN(n) (((n)&0x1Fu) << 0)
|
||||
#define GPIO_PORT(n) ((n) >> 5)
|
||||
#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu))
|
||||
#define GPIO_PIN_FUNCTION_OFF 0xffffffff
|
||||
|
||||
/**
|
||||
* \brief PORT pull mode settings
|
||||
*/
|
||||
enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN };
|
||||
|
||||
/**
|
||||
* \brief PORT direction settins
|
||||
*/
|
||||
enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT };
|
||||
|
||||
/**
|
||||
* \brief PORT group abstraction
|
||||
*/
|
||||
|
||||
enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE };
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Port initialization function
|
||||
*
|
||||
* Port initialization function should setup the port module based
|
||||
* on a static configuration file, this function should normally
|
||||
* not be called directly, but is a part of hal_init()
|
||||
*/
|
||||
void _gpio_init(void);
|
||||
|
||||
/**
|
||||
* \brief Set direction on port with mask
|
||||
*
|
||||
* Set data direction for each pin, or disable the pin
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to the
|
||||
* corresponding pin
|
||||
* \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input
|
||||
* and disable input buffer to disable the pin
|
||||
* GPIO_DIRECTION_IN = set pin direction to input
|
||||
* and enable input buffer to enable the pin
|
||||
* GPIO_DIRECTION_OUT = set pin direction to output
|
||||
* and disable input buffer
|
||||
*/
|
||||
static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
|
||||
const enum gpio_direction direction);
|
||||
|
||||
/**
|
||||
* \brief Set output level on port with mask
|
||||
*
|
||||
* Sets output state on pin to high or low with pin masking
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to
|
||||
* the corresponding pin
|
||||
* \param[in] level true = pin level is set to 1
|
||||
* false = pin level is set to 0
|
||||
*/
|
||||
static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level);
|
||||
|
||||
/**
|
||||
* \brief Change output level to the opposite with mask
|
||||
*
|
||||
* Change pin output level to the opposite with pin masking
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] mask Bit mask where 1 means apply direction setting to
|
||||
* the corresponding pin
|
||||
*/
|
||||
static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask);
|
||||
|
||||
/**
|
||||
* \brief Get input levels on all port pins
|
||||
*
|
||||
* Get input level on all port pins, will read IN register if configured to
|
||||
* input and OUT register if configured as output
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
*/
|
||||
static inline uint32_t _gpio_get_level(const enum gpio_port port);
|
||||
|
||||
/**
|
||||
* \brief Set pin pull mode
|
||||
*
|
||||
* Set pull mode on a single pin
|
||||
*
|
||||
* \notice This function will automatically change pin direction to input
|
||||
*
|
||||
* \param[in] port Ports are grouped into groups of maximum 32 pins,
|
||||
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
|
||||
* \param[in] pin The pin in the group that pull mode should be selected
|
||||
* for
|
||||
* \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled
|
||||
* GPIO_PULL_DOWN = pull resistor on pin will pull pin
|
||||
* level to ground level
|
||||
* GPIO_PULL_UP = pull resistor on pin will pull pin
|
||||
* level to VCC
|
||||
*/
|
||||
static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
|
||||
const enum gpio_pull_mode pull_mode);
|
||||
|
||||
/**
|
||||
* \brief Set gpio function
|
||||
*
|
||||
* Select which function a gpio is used for
|
||||
*
|
||||
* \param[in] gpio The gpio to set function for
|
||||
* \param[in] function The gpio function is given by a 32-bit wide bitfield
|
||||
* found in the header files for the device
|
||||
*
|
||||
*/
|
||||
static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function);
|
||||
|
||||
#include <hpl_gpio_base.h>
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_GPIO_H_INCLUDED */
|
||||
@ -1,205 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED
|
||||
#define _HPL_I2C_M_ASYNC_H_INCLUDED
|
||||
|
||||
#include "hpl_i2c_m_sync.h"
|
||||
#include "hpl_irq.h"
|
||||
#include "utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief i2c master callback names
|
||||
*/
|
||||
enum _i2c_m_async_callback_type {
|
||||
I2C_M_ASYNC_DEVICE_ERROR,
|
||||
I2C_M_ASYNC_DEVICE_TX_COMPLETE,
|
||||
I2C_M_ASYNC_DEVICE_RX_COMPLETE
|
||||
};
|
||||
|
||||
struct _i2c_m_async_device;
|
||||
|
||||
typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev);
|
||||
typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode);
|
||||
|
||||
/**
|
||||
* \brief i2c callback pointers structure
|
||||
*/
|
||||
struct _i2c_m_async_callback {
|
||||
_i2c_error_cb_t error;
|
||||
_i2c_complete_cb_t tx_complete;
|
||||
_i2c_complete_cb_t rx_complete;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c device structure
|
||||
*/
|
||||
struct _i2c_m_async_device {
|
||||
struct _i2c_m_service service;
|
||||
void * hw;
|
||||
struct _i2c_m_async_callback cb;
|
||||
struct _irq_descriptor irq;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize I2C in interrupt mode
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c interrupt device structure
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize I2C in interrupt mode
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Transfer data by I2C
|
||||
*
|
||||
* This function does low level I2C data transfer.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] msg The pointer to i2c msg structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg);
|
||||
|
||||
/**
|
||||
* \brief Set baud rate of I2C
|
||||
*
|
||||
* This function does low level I2C set baud rate.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] clkrate The clock rate(KHz) input to i2c module
|
||||
* \param[in] baudrate The demand baud rate(KHz) of i2c module
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
|
||||
|
||||
/**
|
||||
* \brief Register callback to I2C
|
||||
*
|
||||
* This function does low level I2C callback register.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] cb_type The callback type request
|
||||
* \param[in] func The callback function pointer
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type,
|
||||
FUNC_PTR func);
|
||||
|
||||
/**
|
||||
* \brief Generate stop condition on the I2C bus
|
||||
*
|
||||
* This function will generate a stop condition on the I2C bus
|
||||
*
|
||||
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
|
||||
*
|
||||
* \return Operation status
|
||||
* \retval 0 Operation executed successfully
|
||||
* \retval <0 Operation failed
|
||||
*/
|
||||
int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Returns the number of bytes left or not used in the I2C message buffer
|
||||
*
|
||||
* This function will return the number of bytes left (not written to the bus) or still free
|
||||
* (not received from the bus) in the message buffer, depending on direction of transmission.
|
||||
*
|
||||
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
|
||||
*
|
||||
* \return Number of bytes or error code
|
||||
* \retval >0 Positive number indicating bytes left
|
||||
* \retval 0 Buffer is full/empty depending on direction
|
||||
* \retval <0 Error code
|
||||
*/
|
||||
int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable I2C master interrupt
|
||||
*
|
||||
* param[in] device The pointer to I2C master device instance
|
||||
* param[in] type The type of interrupt to disable/enable if applicable
|
||||
* param[in] state Enable or disable
|
||||
*/
|
||||
void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
|
||||
const bool state);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,185 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_M_SYNC_H_INCLUDED
|
||||
#define _HPL_I2C_M_SYNC_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief i2c flags
|
||||
*/
|
||||
#define I2C_M_RD 0x0001 /* read data, from slave to master */
|
||||
#define I2C_M_BUSY 0x0100
|
||||
#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */
|
||||
#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */
|
||||
#define I2C_M_FAIL 0x1000
|
||||
#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
|
||||
|
||||
/**
|
||||
* \brief i2c Return codes
|
||||
*/
|
||||
#define I2C_OK 0 /* Operation successful */
|
||||
#define I2C_ACK -1 /* Received ACK from device on I2C bus */
|
||||
#define I2C_NACK -2 /* Received NACK from device on I2C bus */
|
||||
#define I2C_ERR_ARBLOST -3 /* Arbitration lost */
|
||||
#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */
|
||||
#define I2C_ERR_BUS -5 /* Bus error */
|
||||
#define I2C_ERR_BUSY -6 /* Device busy */
|
||||
#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */
|
||||
|
||||
/**
|
||||
* \brief i2c I2C Modes
|
||||
*/
|
||||
#define I2C_STANDARD_MODE 0x00
|
||||
#define I2C_FASTMODE 0x01
|
||||
#define I2C_HIGHSPEED_MODE 0x02
|
||||
|
||||
/**
|
||||
* \brief i2c master message structure
|
||||
*/
|
||||
struct _i2c_m_msg {
|
||||
uint16_t addr;
|
||||
volatile uint16_t flags;
|
||||
int32_t len;
|
||||
uint8_t * buffer;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c master service
|
||||
*/
|
||||
struct _i2c_m_service {
|
||||
struct _i2c_m_msg msg;
|
||||
uint16_t mode;
|
||||
uint16_t trise;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c sync master device structure
|
||||
*/
|
||||
struct _i2c_m_sync_device {
|
||||
struct _i2c_m_service service;
|
||||
void * hw;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize I2C
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize I2C
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
/**
|
||||
* \brief Transfer data by I2C
|
||||
*
|
||||
* This function does low level I2C data transfer.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] msg The pointer to i2c msg structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg);
|
||||
|
||||
/**
|
||||
* \brief Set baud rate of I2C
|
||||
*
|
||||
* This function does low level I2C set baud rate.
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device structure
|
||||
* \param[in] clkrate The clock rate(KHz) input to i2c module
|
||||
* \param[in] baudrate The demand baud rate(KHz) of i2c module
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
|
||||
|
||||
/**
|
||||
* \brief Send send condition on the I2C bus
|
||||
*
|
||||
* This function will generate a stop condition on the I2C bus
|
||||
*
|
||||
* \param[in] i2c_dev The pointer to i2c device struct
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,184 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED
|
||||
#define _HPL_I2C_S_ASYNC_H_INCLUDED
|
||||
|
||||
#include "hpl_i2c_s_sync.h"
|
||||
#include "hpl_irq.h"
|
||||
#include "utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief i2c callback types
|
||||
*/
|
||||
enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE };
|
||||
|
||||
/**
|
||||
* \brief Forward declaration of I2C Slave device
|
||||
*/
|
||||
struct _i2c_s_async_device;
|
||||
|
||||
/**
|
||||
* \brief i2c slave callback function type
|
||||
*/
|
||||
typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device);
|
||||
|
||||
/**
|
||||
* \brief i2c slave callback pointers structure
|
||||
*/
|
||||
struct _i2c_s_async_callback {
|
||||
void (*error)(struct _i2c_s_async_device *const device);
|
||||
void (*tx)(struct _i2c_s_async_device *const device);
|
||||
void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief i2c slave device structure
|
||||
*/
|
||||
struct _i2c_s_async_device {
|
||||
void * hw;
|
||||
struct _i2c_s_async_callback cb;
|
||||
struct _irq_descriptor irq;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize asynchronous I2C slave
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] device The pointer to i2c interrupt device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize asynchronous I2C in interrupt mode
|
||||
*
|
||||
* \param[in] device The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if 10-bit addressing mode is on
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Cheking status
|
||||
* \retval 1 10-bit addressing mode is on
|
||||
* \retval 0 10-bit addressing mode is off
|
||||
*/
|
||||
int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set I2C slave address
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] address Address to set
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address);
|
||||
|
||||
/**
|
||||
* \brief Write a byte to the given I2C instance
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] data Data to write
|
||||
*/
|
||||
void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data);
|
||||
|
||||
/**
|
||||
* \brief Retrieve I2C slave status
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
*\return I2C slave status
|
||||
*/
|
||||
i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Abort data transmission
|
||||
*
|
||||
* \param[in] device The pointer to i2c device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable I2C slave interrupt
|
||||
*
|
||||
* param[in] device The pointer to I2C slave device instance
|
||||
* param[in] type The type of interrupt to disable/enable if applicable
|
||||
* param[in] disable Enable or disable
|
||||
*/
|
||||
int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
|
||||
const bool disable);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */
|
||||
@ -1,184 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
|
||||
*
|
||||
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_I2C_S_SYNC_H_INCLUDED
|
||||
#define _HPL_I2C_S_SYNC_H_INCLUDED
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief I2C Slave status type
|
||||
*/
|
||||
typedef uint32_t i2c_s_status_t;
|
||||
|
||||
/**
|
||||
* \brief i2c slave device structure
|
||||
*/
|
||||
struct _i2c_s_sync_device {
|
||||
void *hw;
|
||||
};
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize synchronous I2C slave
|
||||
*
|
||||
* This function does low level I2C configuration.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize synchronous I2C slave
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable I2C module
|
||||
*
|
||||
* This function does low level I2C enable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Disable I2C module
|
||||
*
|
||||
* This function does low level I2C disable.
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if 10-bit addressing mode is on
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Cheking status
|
||||
* \retval 1 10-bit addressing mode is on
|
||||
* \retval 0 10-bit addressing mode is off
|
||||
*/
|
||||
int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set I2C slave address
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] address Address to set
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address);
|
||||
|
||||
/**
|
||||
* \brief Write a byte to the given I2C instance
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
* \param[in] data Data to write
|
||||
*/
|
||||
void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data);
|
||||
|
||||
/**
|
||||
* \brief Retrieve I2C slave status
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
*\return I2C slave status
|
||||
*/
|
||||
i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Clear the Data Ready interrupt flag
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Return 0 for success and negative value for error
|
||||
*/
|
||||
int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Read a byte from the given I2C instance
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Data received via I2C interface.
|
||||
*/
|
||||
uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if I2C is ready to send next byte
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Status of the ready check.
|
||||
* \retval true if the I2C is ready to send next byte
|
||||
* \retval false if the I2C is not ready to send next byte
|
||||
*/
|
||||
bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Check if there is data received by I2C
|
||||
*
|
||||
* \param[in] device The pointer to i2c slave device structure
|
||||
*
|
||||
* \return Status of the data received check.
|
||||
* \retval true if the I2C has received a byte
|
||||
* \retval false if the I2C has not received a byte
|
||||
*/
|
||||
bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */
|
||||
@ -1,124 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Init related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_INIT_H_INCLUDED
|
||||
#define _HPL_INIT_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL Init
|
||||
*
|
||||
* \section hpl_init_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Initializes clock sources
|
||||
*/
|
||||
void _sysctrl_init_sources(void);
|
||||
|
||||
/**
|
||||
* \brief Initializes Power Manager
|
||||
*/
|
||||
void _pm_init(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize generators
|
||||
*/
|
||||
void _gclk_init_generators(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize 32 kHz clock sources
|
||||
*/
|
||||
void _osc32kctrl_init_sources(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock sources
|
||||
*/
|
||||
void _oscctrl_init_sources(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock sources that need input reference clocks
|
||||
*/
|
||||
void _sysctrl_init_referenced_generators(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock sources that need input reference clocks
|
||||
*/
|
||||
void _oscctrl_init_referenced_generators(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize master clock generator
|
||||
*/
|
||||
void _mclk_init(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock generator
|
||||
*/
|
||||
void _lpmcu_misc_regs_init(void);
|
||||
|
||||
/**
|
||||
* \brief Initialize clock generator
|
||||
*/
|
||||
void _pmc_init(void);
|
||||
|
||||
/**
|
||||
* \brief Set performance level
|
||||
*
|
||||
* \param[in] level The performance level to set
|
||||
*/
|
||||
void _set_performance_level(const uint8_t level);
|
||||
|
||||
/**
|
||||
* \brief Initialize the chip
|
||||
*/
|
||||
void _init_chip(void);
|
||||
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_INIT_H_INCLUDED */
|
||||
@ -1,116 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief IRQ related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_IRQ_H_INCLUDED
|
||||
#define _HPL_IRQ_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL IRQ
|
||||
*
|
||||
* \section hpl_irq_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief IRQ descriptor
|
||||
*/
|
||||
struct _irq_descriptor {
|
||||
void (*handler)(void *parameter);
|
||||
void *parameter;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name HPL functions
|
||||
*/
|
||||
//@{
|
||||
/**
|
||||
* \brief Retrieve current IRQ number
|
||||
*
|
||||
* \return The current IRQ number
|
||||
*/
|
||||
uint8_t _irq_get_current(void);
|
||||
|
||||
/**
|
||||
* \brief Disable the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to disable
|
||||
*/
|
||||
void _irq_disable(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Set the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to set
|
||||
*/
|
||||
void _irq_set(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Clear the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to clear
|
||||
*/
|
||||
void _irq_clear(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Enable the given IRQ
|
||||
*
|
||||
* \param[in] n The number of IRQ to enable
|
||||
*/
|
||||
void _irq_enable(uint8_t n);
|
||||
|
||||
/**
|
||||
* \brief Register IRQ handler
|
||||
*
|
||||
* \param[in] number The number registered IRQ
|
||||
* \param[in] irq The pointer to irq handler to register
|
||||
*
|
||||
* \return The status of IRQ handler registering
|
||||
* \retval -1 Passed parameters were invalid
|
||||
* \retval 0 The registering is completed successfully
|
||||
*/
|
||||
void _irq_register(const uint8_t number, struct _irq_descriptor *const irq);
|
||||
//@}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_IRQ_H_INCLUDED */
|
||||
@ -1,37 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Family-dependent missing features expected by HAL
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_MISSING_FEATURES
|
||||
#define _HPL_MISSING_FEATURES
|
||||
|
||||
#endif /* _HPL_MISSING_FEATURES */
|
||||
@ -1,193 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief PWM related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
#ifndef _HPL_PWM_H_INCLUDED
|
||||
#define _HPL_PWM_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL PWM
|
||||
*
|
||||
* \section hpl_pwm_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include "hpl_irq.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief PWM callback types
|
||||
*/
|
||||
enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB };
|
||||
|
||||
/**
|
||||
* \brief PWM pulse-width period
|
||||
*/
|
||||
typedef uint32_t pwm_period_t;
|
||||
|
||||
/**
|
||||
* \brief PWM device structure
|
||||
*
|
||||
* The PWM device structure forward declaration.
|
||||
*/
|
||||
struct _pwm_device;
|
||||
|
||||
/**
|
||||
* \brief PWM interrupt callbacks
|
||||
*/
|
||||
struct _pwm_callback {
|
||||
void (*pwm_period_cb)(struct _pwm_device *device);
|
||||
void (*pwm_error_cb)(struct _pwm_device *device);
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief PWM descriptor device structure
|
||||
*/
|
||||
struct _pwm_device {
|
||||
struct _pwm_callback callback;
|
||||
struct _irq_descriptor irq;
|
||||
void * hw;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief PWM functions, pointers to low-level functions
|
||||
*/
|
||||
struct _pwm_hpl_interface {
|
||||
int32_t (*init)(struct _pwm_device *const device, void *const hw);
|
||||
void (*deinit)(struct _pwm_device *const device);
|
||||
void (*start_pwm)(struct _pwm_device *const device);
|
||||
void (*stop_pwm)(struct _pwm_device *const device);
|
||||
void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
|
||||
bool (*is_pwm_enabled)(const struct _pwm_device *const device);
|
||||
pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device);
|
||||
uint32_t (*pwm_get_duty)(const struct _pwm_device *const device);
|
||||
void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
|
||||
};
|
||||
/**
|
||||
* \brief Initialize TC
|
||||
*
|
||||
* This function does low level TC configuration.
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
* \param[in] hw The pointer to hardware instance
|
||||
*
|
||||
* \return Initialization status.
|
||||
*/
|
||||
int32_t _pwm_init(struct _pwm_device *const device, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize TC
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*/
|
||||
void _pwm_deinit(struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Retrieve offset of the given tc hardware instance
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*
|
||||
* \return The offset of the given tc hardware instance
|
||||
*/
|
||||
uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Start hardware pwm
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*/
|
||||
void _pwm_enable(struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Stop hardware pwm
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*/
|
||||
void _pwm_disable(struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Set pwm parameter
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
* \param[in] period Total period of one PWM cycle.
|
||||
* \param[in] duty_cycle Period of PWM first half during one cycle.
|
||||
*/
|
||||
void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
|
||||
|
||||
/**
|
||||
* \brief Check if pwm is working
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*
|
||||
* \return Check status.
|
||||
* \retval true The given pwm is working
|
||||
* \retval false The given pwm is not working
|
||||
*/
|
||||
bool _pwm_is_enabled(const struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Get pwm waveform period value
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*
|
||||
* \return Period value.
|
||||
*/
|
||||
pwm_period_t _pwm_get_period(const struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Get pwm waveform duty cycle value
|
||||
*
|
||||
* \param[in] device The pointer to PWM device instance
|
||||
*
|
||||
* \return Duty cycle value
|
||||
*/
|
||||
uint32_t _pwm_get_duty(const struct _pwm_device *const device);
|
||||
|
||||
/**
|
||||
* \brief Enable/disable PWM interrupt
|
||||
*
|
||||
* param[in] device The pointer to PWM device instance
|
||||
* param[in] type The type of interrupt to disable/enable if applicable
|
||||
* param[in] disable Enable or disable
|
||||
*/
|
||||
void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/**@}*/
|
||||
#endif /* _HPL_PWM_H_INCLUDED */
|
||||
@ -1,149 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Quad SPI related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_QSPI_H_INCLUDED
|
||||
#define _HPL_QSPI_H_INCLUDED
|
||||
|
||||
#include "compiler.h"
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_qspi HPL QSPI
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief Qspi access modes
|
||||
*/
|
||||
enum qspi_access {
|
||||
/* Read access */
|
||||
QSPI_READ_ACCESS = 0,
|
||||
/* Read memory access */
|
||||
QSPI_READMEM_ACCESS,
|
||||
/* Write access */
|
||||
QSPI_WRITE_ACCESS,
|
||||
/* Write memory access */
|
||||
QSPI_WRITEMEM_ACCESS
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief QSPI command instruction/address/data width
|
||||
*/
|
||||
enum qspi_cmd_width {
|
||||
/** Instruction: Single-bit, Address: Single-bit, Data: Single-bit */
|
||||
QSPI_INST1_ADDR1_DATA1,
|
||||
/** Instruction: Single-bit, Address: Single-bit, Data: Dual-bit */
|
||||
QSPI_INST1_ADDR1_DATA2,
|
||||
/** Instruction: Single-bit, Address: Single-bit, Data: Quad-bit */
|
||||
QSPI_INST1_ADDR1_DATA4,
|
||||
/** Instruction: Single-bit, Address: Dual-bit, Data: Dual-bit */
|
||||
QSPI_INST1_ADDR2_DATA2,
|
||||
/** Instruction: Single-bit, Address: Quad-bit, Data: Quad-bit */
|
||||
QSPI_INST1_ADDR4_DATA4,
|
||||
/** Instruction: Dual-bit, Address: Dual-bit, Data: Dual-bit */
|
||||
QSPI_INST2_ADDR2_DATA2,
|
||||
/** Instruction: Quad-bit, Address: Quad-bit, Data: Quad-bit */
|
||||
QSPI_INST4_ADDR4_DATA4
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief QSPI command option code length in bits
|
||||
*/
|
||||
enum qspi_cmd_opt_len {
|
||||
/** The option code is 1 bit long */
|
||||
QSPI_OPT_1BIT,
|
||||
/** The option code is 2 bits long */
|
||||
QSPI_OPT_2BIT,
|
||||
/** The option code is 4 bits long */
|
||||
QSPI_OPT_4BIT,
|
||||
/** The option code is 8 bits long */
|
||||
QSPI_OPT_8BIT
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Qspi command structure
|
||||
*/
|
||||
struct _qspi_command {
|
||||
union {
|
||||
struct {
|
||||
/* Width of QSPI Addr , inst data */
|
||||
uint32_t width : 3;
|
||||
/* Reserved */
|
||||
uint32_t reserved0 : 1;
|
||||
/* Enable Instruction */
|
||||
uint32_t inst_en : 1;
|
||||
/* Enable Address */
|
||||
uint32_t addr_en : 1;
|
||||
/* Enable Option */
|
||||
uint32_t opt_en : 1;
|
||||
/* Enable Data */
|
||||
uint32_t data_en : 1;
|
||||
/* Option Length */
|
||||
uint32_t opt_len : 2;
|
||||
/* Address Length */
|
||||
uint32_t addr_len : 1;
|
||||
/* Option Length */
|
||||
uint32_t reserved1 : 1;
|
||||
/* Transfer type */
|
||||
uint32_t tfr_type : 2;
|
||||
/* Continuous read mode */
|
||||
uint32_t continues_read : 1;
|
||||
/* Enable Double Data Rate */
|
||||
uint32_t ddr_enable : 1;
|
||||
/* Dummy Cycles Length */
|
||||
uint32_t dummy_cycles : 5;
|
||||
/* Reserved */
|
||||
uint32_t reserved3 : 11;
|
||||
} bits;
|
||||
uint32_t word;
|
||||
} inst_frame;
|
||||
|
||||
uint8_t instruction;
|
||||
uint8_t option;
|
||||
uint32_t address;
|
||||
|
||||
size_t buf_len;
|
||||
const void *tx_buf;
|
||||
void * rx_buf;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_QSPI_H_INCLUDED */
|
||||
@ -1,146 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Quad SPI dma related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_QSPI_DMA_H_INCLUDED
|
||||
#define _HPL_QSPI_DMA_H_INCLUDED
|
||||
|
||||
#include <hpl_qspi.h>
|
||||
#include "hpl_irq.h"
|
||||
#include "hpl_dma.h"
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_qspi_dma HPL QSPI
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** The callback types */
|
||||
enum _qspi_dma_cb_type {
|
||||
/** Callback type for DMA transfer done */
|
||||
QSPI_DMA_CB_XFER_DONE,
|
||||
/** Callback type for DMA errors */
|
||||
QSPI_DMA_CB_ERROR,
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief QSPI DMA callback type
|
||||
*/
|
||||
typedef void (*_qspi_dma_cb_t)(struct _dma_resource *resource);
|
||||
|
||||
/**
|
||||
* \brief The callbacks offered by QSPI driver
|
||||
*/
|
||||
struct _qspi_dma_callbacks {
|
||||
_qspi_dma_cb_t xfer_done;
|
||||
_qspi_dma_cb_t error;
|
||||
};
|
||||
|
||||
/**
|
||||
* QSPI dma driver instance.
|
||||
*/
|
||||
struct _qspi_dma_dev {
|
||||
/** Pointer to private data or hardware base */
|
||||
void *prvt;
|
||||
/**
|
||||
* Pointer to the callback functions so that initialize the driver to
|
||||
* handle interrupts.
|
||||
*/
|
||||
struct _qspi_dma_callbacks cb;
|
||||
/** DMA resource */
|
||||
struct _dma_resource *resource;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize QSPI for access without interrupts
|
||||
* It will load default hardware configuration and software struct.
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_dma_init(struct _qspi_dma_dev *dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize QSPI
|
||||
* Disable, reset the hardware and the software struct.
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_dma_deinit(struct _qspi_dma_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Enable QSPI for access without interrupts
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_dma_enable(struct _qspi_dma_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Disable QSPI for access without interrupts
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_dma_disable(struct _qspi_dma_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Execute command in Serial Memory Mode.
|
||||
*
|
||||
* \param[in] dev The pointer to QSPI device instance
|
||||
* \param[in] cmd The pointer to the command information
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_dma_serial_run_command(struct _qspi_dma_dev *dev, const struct _qspi_command *cmd);
|
||||
|
||||
/**
|
||||
* \brief Register the QSPI device callback
|
||||
* \param[in] dev Pointer to the SPI device instance.
|
||||
* \param[in] type The callback type.
|
||||
* \param[in] cb The callback function to register. NULL to disable callback.
|
||||
* \return Always 0.
|
||||
*/
|
||||
void _qspi_dma_register_callback(struct _qspi_dma_dev *dev, const enum _qspi_dma_cb_type type, _qspi_dma_cb_t cb);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_QSPI_DMA_H_INCLUDED */
|
||||
@ -1,105 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Quad SPI Sync related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_QSPI_SYNC_H_INCLUDED
|
||||
#define _HPL_QSPI_SYNC_H_INCLUDED
|
||||
|
||||
#include <hpl_qspi.h>
|
||||
|
||||
/**
|
||||
* \addtogroup hpl_qspi HPL QSPI
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Quad SPI polling driver instance. */
|
||||
struct _qspi_sync_dev {
|
||||
/** Pointer to private data or hardware base */
|
||||
void *prvt;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize QSPI for access without interrupts
|
||||
* It will load default hardware configuration and software struct.
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \param[in] hw Pointer to the hardware base.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_sync_init(struct _qspi_sync_dev *dev, void *const hw);
|
||||
|
||||
/**
|
||||
* \brief Deinitialize QSPI
|
||||
* Disable, reset the hardware and the software struct.
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_sync_deinit(struct _qspi_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Enable QSPI for access without interrupts
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_sync_enable(struct _qspi_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Disable QSPI for access without interrupts
|
||||
* \param[in, out] dev Pointer to the QSPI device instance.
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_sync_disable(struct _qspi_sync_dev *dev);
|
||||
|
||||
/**
|
||||
* \brief Execute command in Serial Memory Mode.
|
||||
*
|
||||
* \param[in] dev The pointer to QSPI device instance
|
||||
* \param[in] cmd The pointer to the command information
|
||||
* \return Operation status.
|
||||
* \retval ERR_NONE Operation done successfully.
|
||||
*/
|
||||
int32_t _qspi_sync_serial_run_command(struct _qspi_sync_dev *dev, const struct _qspi_command *cmd);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
#endif /* ifndef _HPL_QSPI_SYNC_H_INCLUDED */
|
||||
@ -1,100 +0,0 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief RAMECC related functionality declaration.
|
||||
*
|
||||
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip
|
||||
* software and any derivatives exclusively with Microchip products.
|
||||
* It is your responsibility to comply with third party license terms applicable
|
||||
* to your use of third party software (including open source software) that
|
||||
* may accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
|
||||
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
|
||||
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
|
||||
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
|
||||
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HPL_RAMECC_H_INCLUDED
|
||||
#define _HPL_RAMECC_H_INCLUDED
|
||||
|
||||
/**
|
||||
* \addtogroup HPL RAMECC
|
||||
*
|
||||
* \section hpl_ramecc_rev Revision History
|
||||
* - v1.0.0 Initial Release
|
||||
*
|
||||
*@{
|
||||
*/
|
||||
|
||||
#include <compiler.h>
|
||||
#include <hpl_irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief RAMECC callback type
|
||||
*/
|
||||
typedef void (*ramecc_cb_t)(const uint32_t data);
|
||||
|
||||
/**
|
||||
* \brief RAMECC callback types
|
||||
*/
|
||||
enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB };
|
||||
|
||||
/**
|
||||
* \brief RAMECC interrupt callbacks
|
||||
*/
|
||||
struct _ramecc_callbacks {
|
||||
ramecc_cb_t dual_bit_err;
|
||||
ramecc_cb_t single_bit_err;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief RAMECC device structure
|
||||
*/
|
||||
struct _ramecc_device {
|
||||
struct _ramecc_callbacks ramecc_cb;
|
||||
struct _irq_descriptor irq;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Initialize RAMECC
|
||||
*
|
||||
* This function does low level RAMECC configuration.
|
||||
*
|
||||
* \return initialize status
|
||||
*/
|
||||
int32_t _ramecc_init(void);
|
||||
|
||||
/**
|
||||
* \brief Register RAMECC callback
|
||||
*
|
||||
* \param[in] type The type of callback
|
||||
* \param[in] cb A callback function
|
||||
*/
|
||||
void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HPL_RAMECC_H_INCLUDED */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue